Renesas HD6433690 Old company name in catalogs and other document Datasheet

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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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April 1st, 2010
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User’s Manual
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
H8/3694
Group
16
Hardware Manual
Renesas 16-Bit Single-Chip
Microcomputer
H8 Family/H8/300H Tiny Series
H8/3694N
H8/3694F
H8/3694
H8/3693
H8/3692
H8/3691
H8/3690
HD64N3694G, HD6483694G,
HD64F3694, HD64F3694G,
HD6433694, HD6433694G,
HD6433693, HD6433693G,
HD6433692, HD6433692G,
HD6433691, HD6433691G,
HD6433690, HD6433690G
Rev.5.00 2005.11
Rev.5.00 Nov. 02, 2005 Page ii of xxviii
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
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circuit application examples contained in these materials.
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information contained herein.
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Rev.5.00 Nov. 02, 2005 Page iii of xxviii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev.5.00 Nov. 02, 2005 Page iv of xxviii
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev.5.00 Nov. 02, 2005 Page v of xxviii
Preface
The H8/3694 Group are single-chip microcomputers made up of the high-speed H8/300H CPU
employing Renesas Technology original architecture as their cores, and the peripheral functions
required to configure a system. The H8/300H CPU has an instruction set that is compatible with
the H8/300 CPU.
Target Users: This manual was written for users who will be using the H8/3694 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8/3694 Group to the target users.
Refer to the H8/300H Series Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300H Series Software Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registers.
Example:
Bit order:
The MSB is on the left and the LSB is on the right.
Notes:
When using the on-chip emulator (E7, E8) for H8/3694 program development and debugging, the
following restrictions must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be used.
2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be
provided on the user board.
3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user.
4. Area H'F780 to H'FB7F must on no account be accessed.
Rev.5.00 Nov. 02, 2005 Page vi of xxviii
5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use
by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break
control registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and
P87 are input pins, and P86 is an output pin.
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
H8/3694 Group manuals:
Document Title
Document No.
H8/3694 Group Hardware Manual
This manual
H8/300H Series Software Manual
REJ09B0213
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
Microcomputer Development Environment System H8S, H8/300 Series
Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-Performance Embedded Workshop 3, Tutorial
REJ10B0024
H8S, H8/300 Series High-Performance Embedded Workshop 3, User's
Manual
REJ10B0026
Application notes:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler Package Application Note
TM
Single Power Supply F-ZTAT On-Board Programming
REJ05B0464
ADE-502-055
Rev.5.00 Nov. 02, 2005 Page vii of xxviii
Rev.5.00 Nov. 02, 2005 Page viii of xxviii
Contents
Section 1 Overview................................................................................................1
1.1
1.2
1.3
1.4
Features.................................................................................................................................. 1
Internal Block Diagram.......................................................................................................... 4
Pin Arrangement .................................................................................................................... 6
Pin Functions ......................................................................................................................... 9
Section 2 CPU......................................................................................................13
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Address Space and Memory Map ........................................................................................ 14
Register Configuration......................................................................................................... 17
2.2.1 General Registers.................................................................................................... 18
2.2.2 Program Counter (PC) ............................................................................................ 19
2.2.3 Condition-Code Register (CCR)............................................................................. 19
Data Formats........................................................................................................................ 21
2.3.1 General Register Data Formats ............................................................................... 21
2.3.2 Memory Data Formats ............................................................................................ 23
Instruction Set ...................................................................................................................... 24
2.4.1 Table of Instructions Classified by Function .......................................................... 24
2.4.2 Basic Instruction Formats ....................................................................................... 33
Addressing Modes and Effective Address Calculation........................................................ 34
2.5.1 Addressing Modes .................................................................................................. 34
2.5.2 Effective Address Calculation ................................................................................ 38
Basic Bus Cycle ................................................................................................................... 40
2.6.1 Access to On-Chip Memory (RAM, ROM)............................................................ 40
2.6.2 On-Chip Peripheral Modules .................................................................................. 41
CPU States ........................................................................................................................... 42
Usage Notes ......................................................................................................................... 43
2.8.1 Notes on Data Access to Empty Areas ................................................................... 43
2.8.2 EEPMOV Instruction.............................................................................................. 43
2.8.3 Bit Manipulation Instruction................................................................................... 43
Section 3 Exception Handling .............................................................................49
3.1
3.2
Exception Sources and Vector Address ............................................................................... 49
Register Descriptions ........................................................................................................... 51
3.2.1 Interrupt Edge Select Register 1 (IEGR1) .............................................................. 51
3.2.2 Interrupt Edge Select Register 2 (IEGR2) .............................................................. 52
3.2.3 Interrupt Enable Register 1 (IENR1) ...................................................................... 53
3.2.4 Interrupt Flag Register 1 (IRR1)............................................................................. 54
Rev.5.00 Nov. 02, 2005 Page ix of xxviii
3.3
3.4
3.5
3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 55
Reset Exception Handling.................................................................................................... 56
Interrupt Exception Handling .............................................................................................. 57
3.4.1 External Interrupts .................................................................................................. 57
3.4.2 Internal Interrupts ................................................................................................... 58
3.4.3 Interrupt Handling Sequence .................................................................................. 58
3.4.4 Interrupt Response Time......................................................................................... 60
Usage Notes ......................................................................................................................... 62
3.5.1 Interrupts after Reset............................................................................................... 62
3.5.2 Notes on Stack Area Use ........................................................................................ 62
3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 62
Section 4 Address Break ..................................................................................... 63
4.1
4.2
Register Descriptions........................................................................................................... 63
4.1.1 Address Break Control Register (ABRKCR) ......................................................... 64
4.1.2 Address Break Status Register (ABRKSR) ............................................................ 65
4.1.3 Break Address Registers (BARH, BARL).............................................................. 66
4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 66
Operation ............................................................................................................................. 66
Section 5 Clock Pulse Generators ....................................................................... 69
5.1
5.2
5.3
5.4
System Clock Generator ...................................................................................................... 70
5.1.1 Connecting Crystal Resonator ................................................................................ 70
5.1.2 Connecting Ceramic Resonator .............................................................................. 71
5.1.3 External Clock Input Method ................................................................................. 71
Subclock Generator.............................................................................................................. 72
5.2.1 Connecting 32.768-kHz Crystal Resonator ............................................................ 72
5.2.2 Pin Connection when Not Using Subclock............................................................. 73
Prescalers ............................................................................................................................. 73
5.3.1 Prescaler S .............................................................................................................. 73
5.3.2 Prescaler W............................................................................................................. 73
Usage Notes ......................................................................................................................... 74
5.4.1 Note on Resonators................................................................................................. 74
5.4.2 Notes on Board Design ........................................................................................... 74
Section 6 Power-Down Modes............................................................................ 75
6.1
Register Descriptions........................................................................................................... 75
6.1.1 System Control Register 1 (SYSCR1) .................................................................... 76
6.1.2 System Control Register 2 (SYSCR2) .................................................................... 78
6.1.3 Module Standby Control Register 1 (MSTCR1) .................................................... 79
Rev.5.00 Nov. 02, 2005 Page x of xxviii
6.2
6.3
6.4
6.5
Mode Transitions and States of LSI..................................................................................... 80
6.2.1 Sleep Mode ............................................................................................................. 83
6.2.2 Standby Mode ......................................................................................................... 83
6.2.3 Subsleep Mode........................................................................................................ 83
6.2.4 Subactive Mode ...................................................................................................... 84
Operating Frequency in Active Mode.................................................................................. 84
Direct Transition .................................................................................................................. 85
6.4.1 Direct Transition from Active Mode to Subactive Mode ....................................... 85
6.4.2 Direct Transition from Subactive Mode to Active Mode ....................................... 85
Module Standby Function.................................................................................................... 86
Section 7 ROM ....................................................................................................87
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Block Configuration............................................................................................................. 87
Register Descriptions ........................................................................................................... 88
7.2.1 Flash Memory Control Register 1 (FLMCR1)........................................................ 89
7.2.2 Flash Memory Control Register 2 (FLMCR2)........................................................ 90
7.2.3 Erase Block Register 1 (EBR1) .............................................................................. 91
7.2.4 Flash Memory Power Control Register (FLPWCR) ............................................... 92
7.2.5 Flash Memory Enable Register (FENR) ................................................................. 92
On-Board Programming Modes........................................................................................... 93
7.3.1 Boot Mode .............................................................................................................. 93
7.3.2 Programming/Erasing in User Program Mode........................................................ 96
Flash Memory Programming/Erasing .................................................................................. 98
7.4.1 Program/Program-Verify ........................................................................................ 98
7.4.2 Erase/Erase-Verify................................................................................................ 100
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 101
Program/Erase Protection .................................................................................................. 103
7.5.1 Hardware Protection ............................................................................................. 103
7.5.2 Software Protection............................................................................................... 103
7.5.3 Error Protection..................................................................................................... 103
Programmer Mode ............................................................................................................. 104
Power-Down States for Flash Memory.............................................................................. 104
Section 8 RAM ..................................................................................................107
Section 9 I/O Ports .............................................................................................109
9.1
Port 1.................................................................................................................................. 109
9.1.1 Port Mode Register 1 (PMR1) .............................................................................. 110
9.1.2 Port Control Register 1 (PCR1) ............................................................................ 111
9.1.3 Port Data Register 1 (PDR1)................................................................................. 111
Rev.5.00 Nov. 02, 2005 Page xi of xxviii
9.2
9.3
9.4
9.5
9.6
9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................ 112
9.1.5 Pin Functions ........................................................................................................ 112
Port 2.................................................................................................................................. 114
9.2.1 Port Control Register 2 (PCR2) ............................................................................ 115
9.2.2 Port Data Register 2 (PDR2) ................................................................................ 115
9.2.3 Pin Functions ........................................................................................................ 116
Port 5.................................................................................................................................. 117
9.3.1 Port Mode Register 5 (PMR5) .............................................................................. 118
9.3.2 Port Control Register 5 (PCR5) ............................................................................ 119
9.3.3 Port Data Register 5 (PDR5) ................................................................................ 119
9.3.4 Port Pull-Up Control Register 5 (PUCR5)............................................................ 120
9.3.5 Pin Functions ........................................................................................................ 120
Port 7.................................................................................................................................. 123
9.4.1 Port Control Register 7 (PCR7) ............................................................................ 124
9.4.2 Port Data Register 7 (PDR7) ................................................................................ 124
9.4.3 Pin Functions ........................................................................................................ 125
Port 8.................................................................................................................................. 126
9.5.1 Port Control Register 8 (PCR8) ............................................................................ 126
9.5.2 Port Data Register 8 (PDR8) ................................................................................ 127
9.5.3 Pin Functions ........................................................................................................ 127
Port B ................................................................................................................................. 130
9.6.1 Port Data Register B (PDRB) ............................................................................... 130
Section 10 Timer A ........................................................................................... 131
10.1 Features.............................................................................................................................. 131
10.2 Input/Output Pins............................................................................................................... 132
10.3 Register Descriptions......................................................................................................... 133
10.3.1 Timer Mode Register A (TMA)............................................................................ 133
10.3.2 Timer Counter A (TCA) ....................................................................................... 134
10.4 Operation ........................................................................................................................... 135
10.4.1 Interval Timer Operation ...................................................................................... 135
10.4.2 Clock Time Base Operation.................................................................................. 135
10.4.3 Clock Output......................................................................................................... 135
10.5 Usage Note......................................................................................................................... 135
Section 11 Timer V ........................................................................................... 137
11.1 Features.............................................................................................................................. 137
11.2 Input/Output Pins............................................................................................................... 138
11.3 Register Descriptions......................................................................................................... 139
11.3.1 Timer Counter V (TCNTV).................................................................................. 139
Rev.5.00 Nov. 02, 2005 Page xii of xxviii
11.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 139
11.3.3 Timer Control Register V0 (TCRV0) ................................................................... 140
11.3.4 Timer Control/Status Register V (TCSRV) .......................................................... 142
11.3.5 Timer Control Register V1 (TCRV1) ................................................................... 143
11.4 Operation ........................................................................................................................... 144
11.4.1 Timer V Operation................................................................................................ 144
11.5 Timer V Application Examples ......................................................................................... 148
11.5.1 Pulse Output with Arbitrary Duty Cycle............................................................... 148
11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .............. 149
11.6 Usage Notes ....................................................................................................................... 150
Section 12 Timer W ...........................................................................................153
12.1 Features.............................................................................................................................. 153
12.2 Input/Output Pins ............................................................................................................... 156
12.3 Register Descriptions ......................................................................................................... 156
12.3.1 Timer Mode Register W (TMRW) ....................................................................... 157
12.3.2 Timer Control Register W (TCRW) ..................................................................... 158
12.3.3 Timer Interrupt Enable Register W (TIERW) ...................................................... 159
12.3.4 Timer Status Register W (TSRW) ........................................................................ 160
12.3.5 Timer I/O Control Register 0 (TIOR0) ................................................................. 161
12.3.6 Timer I/O Control Register 1 (TIOR1) ................................................................. 163
12.3.7 Timer Counter (TCNT)......................................................................................... 164
12.3.8 General Registers A to D (GRA to GRD)............................................................. 164
12.4 Operation ........................................................................................................................... 165
12.4.1 Normal Operation ................................................................................................. 165
12.4.2 PWM Operation.................................................................................................... 169
12.5 Operation Timing............................................................................................................... 174
12.5.1 TCNT Count Timing ............................................................................................ 174
12.5.2 Output Compare Output Timing ........................................................................... 174
12.5.3 Input Capture Timing............................................................................................ 175
12.5.4 Timing of Counter Clearing by Compare Match .................................................. 176
12.5.5 Buffer Operation Timing ...................................................................................... 176
12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match.................................. 177
12.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................. 178
12.5.8 Timing of Status Flag Clearing............................................................................. 178
12.6 Usage Notes ....................................................................................................................... 179
Section 13 Watchdog Timer ..............................................................................183
13.1 Features.............................................................................................................................. 183
13.2 Register Descriptions ......................................................................................................... 184
Rev.5.00 Nov. 02, 2005 Page xiii of xxviii
13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 184
13.2.2 Timer Counter WD (TCWD)................................................................................ 185
13.2.3 Timer Mode Register WD (TMWD) .................................................................... 186
13.3 Operation ........................................................................................................................... 187
Section 14 Serial Communication Interface 3 (SCI3)....................................... 189
14.1 Features.............................................................................................................................. 189
14.2 Input/Output Pins............................................................................................................... 191
14.3 Register Descriptions......................................................................................................... 191
14.3.1 Receive Shift Register (RSR) ............................................................................... 192
14.3.2 Receive Data Register (RDR)............................................................................... 192
14.3.3 Transmit Shift Register (TSR) .............................................................................. 192
14.3.4 Transmit Data Register (TDR).............................................................................. 192
14.3.5 Serial Mode Register (SMR) ................................................................................ 193
14.3.6 Serial Control Register 3 (SCR3) ......................................................................... 194
14.3.7 Serial Status Register (SSR) ................................................................................. 196
14.3.8 Bit Rate Register (BRR) ....................................................................................... 198
14.4 Operation in Asynchronous Mode ..................................................................................... 205
14.4.1 Clock..................................................................................................................... 205
14.4.2 SCI3 Initialization................................................................................................. 206
14.4.3 Data Transmission ................................................................................................ 207
14.4.4 Serial Data Reception ........................................................................................... 209
14.5 Operation in Clocked Synchronous Mode ......................................................................... 213
14.5.1 Clock..................................................................................................................... 213
14.5.2 SCI3 Initialization................................................................................................. 213
14.5.3 Serial Data Transmission ...................................................................................... 214
14.5.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 217
14.5.5 Simultaneous Serial Data Transmission and Reception........................................ 219
14.6 Multiprocessor Communication Function.......................................................................... 221
14.6.1 Multiprocessor Serial Data Transmission ............................................................. 222
14.6.2 Multiprocessor Serial Data Reception .................................................................. 224
14.7 Interrupts............................................................................................................................ 228
14.8 Usage Notes ....................................................................................................................... 229
14.8.1 Break Detection and Processing ........................................................................... 229
14.8.2 Mark State and Break Sending ............................................................................. 229
14.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ..................................................................... 229
14.8.4 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode......................................................................................... 230
Rev.5.00 Nov. 02, 2005 Page xiv of xxviii
Section 15 I2C Bus Interface 2 (IIC2) ................................................................231
15.1 Features.............................................................................................................................. 231
15.2 Input/Output Pins ............................................................................................................... 233
15.3 Register Descriptions ......................................................................................................... 233
15.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 234
15.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 236
15.3.3 I2C Bus Mode Register (ICMR)............................................................................ 237
15.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 239
15.3.5 I2C Bus Status Register (ICSR)............................................................................. 241
15.3.6 Slave Address Register (SAR).............................................................................. 244
15.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 245
15.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 245
15.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 245
15.4 Operation ........................................................................................................................... 246
15.4.1 I2C Bus Format...................................................................................................... 246
15.4.2 Master Transmit Operation ................................................................................... 247
15.4.3 Master Receive Operation..................................................................................... 249
15.4.4 Slave Transmit Operation ..................................................................................... 251
15.4.5 Slave Receive Operation....................................................................................... 253
15.4.6 Clocked Synchronous Serial Format..................................................................... 255
15.4.7 Noise Canceler...................................................................................................... 257
15.4.8 Example of Use..................................................................................................... 258
15.5 Interrupt Request................................................................................................................ 262
15.6 Bit Synchronous Circuit..................................................................................................... 263
15.7 Usage Notes ....................................................................................................................... 264
15.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 264
15.7.2 WAIT Setting in I2C Bus Mode Register (ICMR) ................................................ 264
Section 16 A/D Converter..................................................................................265
16.1 Features.............................................................................................................................. 265
16.2 Input/Output Pins ............................................................................................................... 267
16.3 Register Descriptions ......................................................................................................... 268
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 268
16.3.2 A/D Control/Status Register (ADCSR) ................................................................ 269
16.3.3 A/D Control Register (ADCR) ............................................................................. 270
16.4 Operation ........................................................................................................................... 271
16.4.1 Single Mode.......................................................................................................... 271
16.4.2 Scan Mode ............................................................................................................ 271
16.4.3 Input Sampling and A/D Conversion Time .......................................................... 272
16.4.4 External Trigger Input Timing.............................................................................. 273
Rev.5.00 Nov. 02, 2005 Page xv of xxviii
16.5 A/D Conversion Accuracy Definitions .............................................................................. 274
16.6 Usage Notes ....................................................................................................................... 276
16.6.1 Permissible Signal Source Impedance .................................................................. 276
16.6.2 Influences on Absolute Accuracy ......................................................................... 276
Section 17 EEPROM......................................................................................... 277
17.1 Features.............................................................................................................................. 277
17.2 Input/Output Pins............................................................................................................... 279
17.3 Register Description .......................................................................................................... 279
17.3.1 EEPROM Key Register (EKR)............................................................................. 279
17.4 Operation ........................................................................................................................... 280
17.4.1 EEPROM Interface............................................................................................... 280
17.4.2 Bus Format and Timing ........................................................................................ 280
17.4.3 Start Condition...................................................................................................... 280
17.4.4 Stop Condition ...................................................................................................... 281
17.4.5 Acknowledge ........................................................................................................ 281
17.4.6 Slave Addressing .................................................................................................. 281
17.4.7 Write Operations................................................................................................... 283
17.4.8 Acknowledge Polling............................................................................................ 284
17.4.9 Read Operation ..................................................................................................... 285
17.5 Usage Notes ....................................................................................................................... 288
17.5.1 Data Protection at VCC On/Off............................................................................... 288
17.5.2 Write/Erase Endurance ......................................................................................... 288
17.5.3 Noise Suppression Time ....................................................................................... 288
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional).. 289
18.1 Features.............................................................................................................................. 289
18.2 Register Descriptions......................................................................................................... 290
18.2.1 Low-Voltage-Detection Control Register (LVDCR)............................................ 290
18.2.2 Low-Voltage-Detection Status Register (LVDSR)............................................... 292
18.3 Operation ........................................................................................................................... 293
18.3.1 Power-On Reset Circuit ........................................................................................ 293
18.3.2 Low-Voltage Detection Circuit............................................................................. 294
Section 19 Power Supply Circuit ...................................................................... 299
19.1 When Using Internal Power Supply Step-Down Circuit ................................................... 299
19.2 When Not Using Internal Power Supply Step-Down Circuit............................................. 300
Section 20 List of Registers............................................................................... 301
20.1 Register Addresses (Address Order).................................................................................. 302
Rev.5.00 Nov. 02, 2005 Page xvi of xxviii
20.2 Register Bits....................................................................................................................... 307
20.3 Registers States in Each Operating Mode .......................................................................... 311
Section 21 Electrical Characteristics .................................................................315
21.1 Absolute Maximum Ratings .............................................................................................. 315
21.2 Electrical Characteristics
(F-ZTAT™ Version, EEPROM Stacked F-ZTATTM Version).......................................... 315
21.2.1 Power Supply Voltage and Operating Ranges ...................................................... 315
21.2.2 DC Characteristics ................................................................................................ 318
21.2.3 AC Characteristics ................................................................................................ 324
21.2.4 A/D Converter Characteristics .............................................................................. 328
21.2.5 Watchdog Timer Characteristics........................................................................... 329
21.2.6 Flash Memory Characteristics .............................................................................. 330
21.2.7 EEPROM Characteristics...................................................................................... 332
21.2.8 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 333
21.2.9 Power-On Reset Circuit Characteristics (Optional) .............................................. 334
21.3 Electrical Characteristics
(Mask-ROM Version, EEPROM Stacked Mask-ROM Version)....................................... 334
21.3.1 Power Supply Voltage and Operating Ranges ...................................................... 334
21.3.2 DC Characteristics ................................................................................................ 337
21.3.3 AC Characteristics ................................................................................................ 343
21.3.4 A/D Converter Characteristics .............................................................................. 347
21.3.5 Watchdog Timer Characteristics........................................................................... 348
21.3.6 EEPROM Characteristics...................................................................................... 349
21.3.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ................... 350
21.3.8 Power-On Reset Circuit Characteristics (Optional) .............................................. 351
21.4 Operation Timing............................................................................................................... 351
21.5 Output Load Condition ...................................................................................................... 354
Appendix A Instruction Set ...............................................................................355
A.1
A.2
A.3
A.4
Instruction List................................................................................................................... 355
Operation Code Map.......................................................................................................... 370
Number of Execution States .............................................................................................. 373
Combinations of Instructions and Addressing Modes ....................................................... 384
Appendix B I/O Port Block Diagrams ...............................................................385
B.1
B.2
I/O Port Block Diagrams.................................................................................................... 385
Port States in Each Operating State ................................................................................... 401
Appendix C Product Code Lineup.....................................................................402
Rev.5.00 Nov. 02, 2005 Page xvii of xxviii
Appendix D Package Dimensions ..................................................................... 405
Appendix E EEPROM Stacked-Structure Cross-Sectional View ..................... 410
Main Revisions and Additions in this Edition..................................................... 411
Index .................................................................................................................. 415
Rev.5.00 Nov. 02, 2005 Page xviii of xxviii
Figures
Section 1
Figure 1.1
Figure 1.2
Figure 1.3
Overview
Internal Block Diagram of H8/3694 Group of F-ZTATTM and Mask-ROM Versions.. 4
Internal Block Diagram of H8/3694N (EEPROM Stacked Version) ............................ 5
Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions
(FP-64E, FP-64A).......................................................................................................... 6
Figure 1.4 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions
(FP-48F, FP-48B, TNP-48)............................................................................................ 7
Figure 1.5 Pin Arrangement of H8/3694N (EEPROM Stacked Version) (FP-64E)....................... 8
Section 2 CPU
Figure 2.1 Memory Map (1) ......................................................................................................... 14
Figure 2.1 Memory Map (2) ......................................................................................................... 15
Figure 2.1 Memory Map (3) ......................................................................................................... 16
Figure 2.2 CPU Registers ............................................................................................................. 17
Figure 2.3 Usage of General Registers ......................................................................................... 18
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 19
Figure 2.5 General Register Data Formats (1).............................................................................. 21
Figure 2.5 General Register Data Formats (2).............................................................................. 22
Figure 2.6 Memory Data Formats................................................................................................. 23
Figure 2.7 Instruction Formats...................................................................................................... 34
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 37
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 40
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 41
Figure 2.11 CPU Operation States................................................................................................ 42
Figure 2.12 State Transitions ........................................................................................................ 43
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address .. 44
Section 3
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Exception Handling
Reset Sequence............................................................................................................ 58
Stack Status after Exception Handling ........................................................................ 60
Interrupt Sequence....................................................................................................... 61
Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 62
Section 4
Figure 4.1
Figure 4.2
Figure 4.2
Address Break
Block Diagram of Address Break................................................................................ 63
Address Break Interrupt Operation Example (1)......................................................... 67
Address Break Interrupt Operation Example (2)......................................................... 67
Rev.5.00 Nov. 02, 2005 Page xix of xxviii
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69
Figure 5.2 Block Diagram of System Clock Generator ................................................................ 70
Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 70
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 71
Figure 5.6 Example of External Clock Input ................................................................................ 71
Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 72
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72
Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73
Figure 5.11 Example of Incorrect Board Design ........................................................................... 74
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 80
Section 7
Figure 7.1
Figure 7.2
Figure 7.3
Figure 7.4
ROM
Flash Memory Block Configuration............................................................................ 88
Programming/Erasing Flowchart Example in User Program Mode............................ 97
Program/Program-Verify Flowchart ........................................................................... 99
Erase/Erase-Verify Flowchart ................................................................................... 102
Section 9
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
I/O Ports
Port 1 Pin Configuration............................................................................................ 109
Port 2 Pin Configuration............................................................................................ 114
Port 5 Pin Configuration............................................................................................ 117
Port 7 Pin Configuration............................................................................................ 123
Port 8 Pin Configuration............................................................................................ 126
Port B Pin Configuration........................................................................................... 130
Section 10 Timer A
Figure 10.1 Block Diagram of Timer A ..................................................................................... 132
Section 11
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Timer V
Block Diagram of Timer V ..................................................................................... 138
Increment Timing with Internal Clock .................................................................... 145
Increment Timing with External Clock................................................................... 145
OVF Set Timing ...................................................................................................... 145
CMFA and CMFB Set Timing................................................................................ 146
TMOV Output Timing ............................................................................................ 146
Clear Timing by Compare Match............................................................................ 146
Clear Timing by TMRIV Input ............................................................................... 147
Rev.5.00 Nov. 02, 2005 Page xx of xxviii
Figure 11.9 Pulse Output Example ............................................................................................. 148
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 149
Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 150
Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 151
Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 151
Section 12 Timer W
Figure 12.1 Timer W Block Diagram ......................................................................................... 155
Figure 12.2 Free-Running Counter Operation ............................................................................ 166
Figure 12.3 Periodic Counter Operation..................................................................................... 166
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 167
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 167
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 167
Figure 12.7 Input Capture Operating Example........................................................................... 168
Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 169
Figure 12.9 PWM Mode Example (1) ........................................................................................ 170
Figure 12.10 PWM Mode Example (2) ...................................................................................... 170
Figure 12.11 Buffer Operation Example (Output Compare) ...................................................... 171
Figure 12.12 PWM Mode Example
(TOB, TOC, and TOD = 0: initial output values are set to 0) ............................... 172
Figure 12.13 PWM Mode Example
(TOB, TOC, and TOD = 1: initial output values are set to 1) ............................... 173
Figure 12.14 Count Timing for Internal Clock Source ............................................................... 174
Figure 12.15 Count Timing for External Clock Source.............................................................. 174
Figure 12.16 Output Compare Output Timing ........................................................................... 175
Figure 12.17 Input Capture Input Signal Timing........................................................................ 175
Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 176
Figure 12.19 Buffer Operation Timing (Compare Match).......................................................... 176
Figure 12.20 Buffer Operation Timing (Input Capture) ............................................................. 177
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 177
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 178
Figure 12.23 Timing of Status Flag Clearing by CPU................................................................ 178
Figure 12.24 Contention between TCNT Write and Clear ......................................................... 179
Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 180
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW
Occur at the Same Timing ..................................................................................... 181
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of Watchdog Timer ........................................................................ 183
Figure 13.2 Watchdog Timer Operation Example...................................................................... 187
Rev.5.00 Nov. 02, 2005 Page xxi of xxviii
Section 14
Figure 14.1
Figure 14.2
Figure 14.3
Serial Communication Interface 3 (SCI3)
Block Diagram of SCI3........................................................................................... 190
Data Format in Asynchronous Communication ...................................................... 205
Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 205
Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 206
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 207
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 208
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 209
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 211
Figure 14.8 Sample Serial Reception Data Flowchart (2) .......................................................... 212
Figure 14.9 Data Format in Clocked Synchronous Communication .......................................... 213
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode...... 215
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 216
Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 217
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 218
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit
and Receive Operations (Clocked Synchronous Mode) ........................................ 220
Figure 14.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 222
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 223
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 225
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 226
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 227
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 230
Section 15 I2C Bus Interface 2 (IIC2)
Figure 15.1 Block Diagram of I2C Bus Interface 2..................................................................... 232
Figure 15.2 External Circuit Connections of I/O Pins ................................................................ 233
Figure 15.3 I2C Bus Formats ...................................................................................................... 246
Figure 15.4 I2C Bus Timing........................................................................................................ 246
Figure 15.5 Master Transmit Mode Operation Timing (1)......................................................... 248
Figure 15.6 Master Transmit Mode Operation Timing (2)......................................................... 248
Figure 15.7 Master Receive Mode Operation Timing (1) .......................................................... 250
Figure 15.8 Master Receive Mode Operation Timing (2) .......................................................... 251
Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 252
Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 253
Rev.5.00 Nov. 02, 2005 Page xxii of xxviii
Figure 15.11
Figure 15.12
Figure 15.13
Figure 15.14
Figure 15.15
Figure 15.16
Figure 15.17
Figure 15.18
Figure 15.19
Figure 15.20
Figure 15.21
Slave Receive Mode Operation Timing (1)........................................................... 254
Slave Receive Mode Operation Timing (2)........................................................... 254
Clocked Synchronous Serial Transfer Format....................................................... 255
Transmit Mode Operation Timing......................................................................... 256
Receive Mode Operation Timing .......................................................................... 257
Block Diagram of Noise Conceler......................................................................... 257
Sample Flowchart for Master Transmit Mode....................................................... 258
Sample Flowchart for Master Receive Mode ........................................................ 259
Sample Flowchart for Slave Transmit Mode......................................................... 260
Sample Flowchart for Slave Receive Mode .......................................................... 261
The Timing of the Bit Synchronous Circuit .......................................................... 263
Section 16
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Figure 16.6
A/D Converter
Block Diagram of A/D Converter ........................................................................... 266
A/D Conversion Timing .......................................................................................... 272
External Trigger Input Timing ................................................................................ 273
A/D Conversion Accuracy Definitions (1) .............................................................. 275
A/D Conversion Accuracy Definitions (2) .............................................................. 275
Analog Input Circuit Example................................................................................. 276
Section 17
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
EEPROM
Block Diagram of EEPROM ................................................................................... 278
EEPROM Bus Format and Bus Timing .................................................................. 280
Byte Write Operation .............................................................................................. 283
Page Write Operation .............................................................................................. 284
Current Address Read Operation............................................................................. 285
Random Address Read Operation ........................................................................... 286
Sequential Read Operation (when current address read is used)............................. 287
Section 18
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Figure 18.5
Power-On Reset and Low-Voltage Detection Circuits (Optional)
Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 290
Operational Timing of Power-On Reset Circuit...................................................... 294
Operational Timing of LVDR Circuit ..................................................................... 295
Operational Timing of LVDI Circuit....................................................................... 296
Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 297
Section 19 Power Supply Circuit
Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 299
Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 300
Section 21 Electrical Characteristics
Figure 21.1 System Clock Input Timing..................................................................................... 351
Figure 21.2 RES Low Width Timing.......................................................................................... 352
Rev.5.00 Nov. 02, 2005 Page xxiii of xxviii
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
Figure 21.7
Figure 21.8
Input Timing............................................................................................................ 352
I2C Bus Interface Input/Output Timing ................................................................... 352
SCK3 Input Clock Timing ...................................................................................... 353
SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 353
EEPROM Bus Timing............................................................................................. 354
Output Load Circuit ................................................................................................ 354
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 385
Figure B.2 Port 1 Block Diagram (P16 to P14) .......................................................................... 386
Figure B.3 Port 1 Block Diagram (P12, P11) ............................................................................. 387
Figure B.4 Port 1 Block Diagram (P10) ..................................................................................... 388
Figure B.5 Port 2 Block Diagram (P22) ..................................................................................... 389
Figure B.6 Port 2 Block Diagram (P21) ..................................................................................... 390
Figure B.7 Port 2 Block Diagram (P20) ..................................................................................... 391
Figure B.8 Port 5 Block Diagram (P57, P56) ............................................................................. 392
Figure B.9 Port 5 Block Diagram (P55) ..................................................................................... 393
Figure B.10 Port 5 Block Diagram (P54 to P50) ........................................................................ 394
Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 395
Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 396
Figure B.13 Port 7 Block Diagram (P74) ................................................................................... 397
Figure B.14 Port 8 Block Diagram (P87 to P85) ........................................................................ 398
Figure B.15 Port 8 Block Diagram (P84 to P81) ........................................................................ 399
Figure B.16 Port 8 Block Diagram (P80) ................................................................................... 400
Figure B.17 Port B Block Diagram (PB7 to PB0) ...................................................................... 401
Appendix D Package Dimensions
Figure D.1 FP-64E Package Dimensions ................................................................................... 405
Figure D.2 FP-64A Package Dimensions ................................................................................... 406
Figure D.3 FP-48F Package Dimensions.................................................................................... 407
Figure D.4 FP-48B Package Dimensions ................................................................................... 408
Figure D.5 TNP-48 Package Dimensions................................................................................... 409
Appendix E EEPROM Stacked-Structure Cross-Sectional View
Figure E.1 EEPROM Stacked-Structure Cross-Sectional View ................................................. 410
Rev.5.00 Nov. 02, 2005 Page xxiv of xxviii
Tables
Section 1 Overview
Table 1.1
Pin Functions ............................................................................................................ 9
Section 2 CPU
Table 2.1
Operation Notation ................................................................................................. 24
Table 2.2
Data Transfer Instructions....................................................................................... 25
Table 2.3
Arithmetic Operations Instructions (1) ................................................................... 26
Table 2.3
Arithmetic Operations Instructions (2) ................................................................... 27
Table 2.4
Logic Operations Instructions................................................................................. 28
Table 2.5
Shift Instructions..................................................................................................... 28
Table 2.6
Bit Manipulation Instructions (1)............................................................................ 29
Table 2.6
Bit Manipulation Instructions (2)............................................................................ 30
Table 2.7
Branch Instructions ................................................................................................. 31
Table 2.8
System Control Instructions.................................................................................... 32
Table 2.9
Block Data Transfer Instructions ............................................................................ 33
Table 2.10
Addressing Modes .................................................................................................. 35
Table 2.11
Absolute Address Access Ranges ........................................................................... 36
Table 2.12
Effective Address Calculation (1)........................................................................... 38
Table 2.12
Effective Address Calculation (2)........................................................................... 39
Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address .................................................................. 49
Table 3.2
Interrupt Wait States ............................................................................................... 60
Section 4 Address Break
Table 4.1
Access and Data Bus Used ..................................................................................... 65
Section 5 Clock Pulse Generators
Table 5.1
Crystal Resonator Parameters ................................................................................. 71
Section 6 Power-Down Modes
Table 6.1
Operating Frequency and Waiting Time................................................................. 77
Table 6.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 81
Table 6.3
Internal State in Each Operating Mode................................................................... 82
Section 7 ROM
Table 7.1
Setting Programming Modes .................................................................................. 93
Table 7.2
Boot Mode Operation ............................................................................................. 95
Table 7.3
System Clock Frequencies for which Automatic Adjustment
of LSI Bit Rate is Possible ...................................................................................... 96
Table 7.4
Reprogram Data Computation Table .................................................................... 100
Rev.5.00 Nov. 02, 2005 Page xxv of xxviii
Table 7.5
Table 7.6
Table 7.7
Additional-Program Data Computation Table ...................................................... 100
Programming Time ............................................................................................... 100
Flash Memory Operating States............................................................................ 105
Section 10 Timer A
Table 10.1
Pin Configuration.................................................................................................. 132
Section 11 Timer V
Table 11.1
Pin Configuration.................................................................................................. 138
Table 11.2
Clock Signals to Input to TCNTV and Counting Conditions ............................... 141
Section 12 Timer W
Table 12.1
Timer W Functions ............................................................................................... 154
Table 12.2
Pin Configuration.................................................................................................. 156
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.1
Pin Configuration.................................................................................................. 191
Table 14.2
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 199
Table 14.2
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 200
Table 14.2
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 201
Table 14.3
Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 202
Table 14.4
Examples of BBR Setting for Various Bit Rates
(Clocked Synchronous Mode) (1)......................................................................... 203
Table 14.4
Examples of BRR Settings for Various Bit Rates
(Clocked Synchronous Mode) (2)......................................................................... 204
Table 14.5
SSR Status Flags and Receive Data Handling ...................................................... 210
Table 14.6
SCI3 Interrupt Requests........................................................................................ 228
Section 15 I2C Bus Interface 2 (IIC2)
Table 15.1
I2C Bus Interface Pins........................................................................................... 233
Table 15.2
Transfer Rate ........................................................................................................ 235
Table 15.3
Interrupt Requests................................................................................................. 262
Table 15.4
Time for Monitoring SCL..................................................................................... 263
Section 16 A/D Converter
Table 16.1
Pin Configuration.................................................................................................. 267
Table 16.2
Analog Input Channels and Corresponding ADDR Registers .............................. 268
Table 16.3
A/D Conversion Time (Single Mode)................................................................... 273
Section 17 EEPROM
Table 17.1
Pin Configuration.................................................................................................. 279
Table 17.2
Slave Addresses .................................................................................................... 282
Rev.5.00 Nov. 02, 2005 Page xxvi of xxviii
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Table 18.1
LVDCR Settings and Select Functions................................................................. 292
Section 21 Electrical Characteristics
Table 21.1
Absolute Maximum Ratings ................................................................................. 315
Table 21.2
DC Characteristics (1)........................................................................................... 318
Table 21.2
DC Characteristics (2)........................................................................................... 322
Table 21.2
DC Characteristics (3)........................................................................................... 323
Table 21.3
AC Characteristics ................................................................................................ 324
Table 21.4
I2C Bus Interface Timing ...................................................................................... 326
Table 21.5
Serial Communication Interface (SCI) Timing..................................................... 327
Table 21.6
A/D Converter Characteristics .............................................................................. 328
Table 21.7
Watchdog Timer Characteristics........................................................................... 329
Table 21.8
Flash Memory Characteristics .............................................................................. 330
Table 21.9
EEPROM Characteristics...................................................................................... 332
Table 21.10
Power-Supply-Voltage Detection Circuit Characteristics................................. 333
Table 21.11
Power-On Reset Circuit Characteristics............................................................ 334
Table 21.12
DC Characteristics (1)....................................................................................... 337
Table 21.12
DC Characteristics (2)....................................................................................... 341
Table 21.12
DC Characteristics (3)....................................................................................... 342
Table 21.13
AC Characteristics ............................................................................................ 343
Table 21.14
I2C Bus Interface Timing .................................................................................. 345
Table 21.15
Serial Communication Interface (SCI) Timing................................................. 346
Table 21.16
A/D Converter Characteristics .......................................................................... 347
Table 21.17
Watchdog Timer Characteristics....................................................................... 348
Table 21.18
EEPROM Characteristics.................................................................................. 349
Table 21.19
Power-Supply-Voltage Detection Circuit Characteristics................................. 350
Table 21.20
Power-On Reset Circuit Characteristics............................................................ 351
Appendix A
Table A.1
Table A.2
Table A.2
Table A.2
Table A.3
Table A.4
Table A.5
Instruction Set
Instruction Set ....................................................................................................... 357
Operation Code Map (1) ....................................................................................... 370
Operation Code Map (2) ....................................................................................... 371
Operation Code Map (3) ....................................................................................... 372
Number of Cycles in Each Instruction.................................................................. 374
Number of Cycles in Each Instruction.................................................................. 375
Combinations of Instructions and Addressing Modes .......................................... 384
Rev.5.00 Nov. 02, 2005 Page xxvii of xxviii
Rev.5.00 Nov. 02, 2005 Page xxviii of xxviii
Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8/300H central processing unit with an internal 16-bit architecture
 Upward-compatible with H8/300 CPU on an object level
 Sixteen 16-bit general registers
 62 basic instructions
• Various peripheral functions
 Timer A (can be used as a time base for a clock)
 Timer V (8-bit timer)
 Timer W (16-bit timer)
 Watchdog timer
 SCI (Asynchronous or clocked synchronous serial communication interface)
 I2C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips
Electronics)
 10-bit A/D converter
Rev.5.00 Nov. 02, 2005 Page 1 of 418
REJ09B0028-0500
Section 1 Overview
• On-chip memory
Model
Standard
Version
Product Classification
On-Chip
Power-On
Reset and LowVoltage
Detecting
Circuit Version ROM
RAM
Flash memory version
TM
(F-ZTAT version)
H8/3694F HD64F3694 HD64F3694G
32 kbytes
2,048 bytes
Mask ROM version
H8/3694
HD6433694 HD6433694G
32 kbytes
1,024 bytes
H8/3693
HD6433693 HD6433693G
24 kbytes
1,024 bytes
H8/3692
HD6433692 HD6433692G
16 kbytes
512 bytes
H8/3691
HD6433691 HD6433691G
12 kbytes
512 bytes
H8/3690
HD6433690 HD6433690G
8 kbytes
512 bytes
EEPROM
stacked
version
(512 bytes)
Flash
memory
version
H8/3694N 
HD64N3694G
32 kbytes
2,048 bytes

HD6483694G
32 kbytes
1,024 bytes
Mask-ROM
version
Remarks
• General I/O ports
 I/O pins: 29 I/O pins (27 I/O pins for H8/3694N), including 8 large current ports (IOL = 20
mA, @VOL = 1.5 V)
 Input-only pins: 8 input pins (also used for analog input)
• EEPROM interface (only for H8/3694N)
 I2C bus interface (conforms to the I2C bus interface format that is advocated by Philips
Electronics)
• Supports various power-down modes
Note: F-ZTATTM is a trademark of Renesas Technology Corp.
Rev.5.00 Nov. 02, 2005 Page 2 of 418
REJ09B0028-0500
Section 1 Overview
• Compact package
Package
Code
Body Size
Pin Pitch
LQFP-64
FP-64E
10.0 × 10.0 mm
0.5 mm
QFP-64
FP-64A
LQFP-48
FP-48F
LQFP-48
FP-48B
QFN-48
TNP-48
14.0 × 14.0 mm
10.0 × 10.0 mm
7.0 × 7.0 mm
7.0 × 7.0 mm
0.8 mm
0.65 mm
0.5 mm
0.5 mm
Only LQFP-64 (FP-64E) for H8/3694N package
Rev.5.00 Nov. 02, 2005 Page 3 of 418
REJ09B0028-0500
Section 1 Overview
Port 8
Port 7
P74/TMRIV
P75/TMCIV
P76/TMOV
Port 5
P20/SCK3
P21/RXD
P22/TXD
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTRG
P56/SDA
P57/SCL
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
CPU
H8/300H
Port 1
Data bus (lower)
Port 2
P10/TMOW
P11
P12
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
System
clock
generator
Port B
Subclock
generator
OSC1
OSC2
X1
X2
NMI
TEST
RES
VCL
Internal Block Diagram
VSS
VCC
1.2
ROM
RAM
Timer W
SCI3
Timer A
Watchdog
timer
Timer V
IIC2
A/D
converter
POR/LVD
(optional)
Data bus (upper)
Address bus
AVCC
Figure 1.1 Internal Block Diagram of H8/3694 Group of F-ZTATTM
and Mask-ROM Versions
Rev.5.00 Nov. 02, 2005 Page 4 of 418
REJ09B0028-0500
Port 8
Port 7
P74/TMRIV
P75/TMCIV
P76/TMOV
Port 5
SCL
P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTRG
P56/SDA
P57/SCL
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Port 1
2
SDA
I C bus
P20/SCK3
P21/RXD
P22/TXD
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
CPU
H8/300H
Data bus (lower)
Port 2
P10/TMOW
P11
P12
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
System
clock
generator
Port B
Subclock
generator
OSC1
OSC2
X1
X2
NMI
TEST
RES
VCL
VSS
VCC
Section 1 Overview
ROM
RAM
Timer W
SCI3
Timer A
Watchdog
timer
Timer V
IIC2
A/D
converter
POR/LVD
(optional)
Data bus (upper)
Address bus
AVCC
EEPROM
Note: The HD64N3694G is a stacked-structure product in which an EEPROM chip is mounted on the HD64F3694G (F-ZTATTM version).
The HD6483694G is a stacked-structure product in which an EEPROM chip is mounted on the HD6433694G (mask-ROM version).
Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version)
Rev.5.00 Nov. 02, 2005 Page 5 of 418
REJ09B0028-0500
Section 1 Overview
NC
NC
NMI
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P20/SCK3
P21/RXD
P22/TXD
NC
Pin Arrangement
NC
1.3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC
49
32
NC
NC
50
31
NC
P14/IRQ0
51
30
P76/TMOV
P15/IRQ1
52
29
P75/TMCIV
P16/IRQ2
53
28
P74/TMRIV
P17/IRQ3/TRGV
54
27
P57/SCL
PB4/AN4
55
26
P56/SDA
PB5/AN5
56
25
P12
PB6/AN6
57
24
P11
PB7/AN7
58
23
P10/TMOW
PB3/AN3
59
22
P55/WKP5/ADTRG
PB2/AN2
60
21
P54/WKP4
PB1/AN1
61
20
P53/WKP3
PB0/AN0
62
19
P52/WKP2
NC
63
18
NC
NC
64
17
NC
H8/3694 Group
X2
X1
VCL
RES
NC
AVCC
NC
NC
8 9 10 11 12 13 14 15 16
P51/WKP1
7
P50/WKP0
6
VCC
5
OSC1
4
OSC2
3
VSS
2
TEST
1
NC
Top view
Note: Do not connect NC pins (these pins are not connected to the internal circuitry).
Figure 1.3 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions
(FP-64E, FP-64A)
Rev.5.00 Nov. 02, 2005 Page 6 of 418
REJ09B0028-0500
NMI
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P20/SCK3
P21/RXD
P22/TXD
Section 1 Overview
36 35 34 33 32 31 30 29 28 27 26 25
40
21
P57/SCL
PB4/AN4
41
20
P56/SDA
PB5/AN5
42
19
P12
PB6/AN6
43
H8/3694 Group
18
P11
PB7/AN7
44
Top View
17
P10/TMOW
PB3/AN3
45
16
P55/WKP5/ADTRG
PB2/AN2
46
15
P54/WKP4
PB1/AN1
47
14
P53/WKP3
PB0/AN0
48
13
P52/WKP2
4
5
6
7
8
9 10 11 12
P51/WKP1
3
P50/WKP0
2
Vcc
1
OSC1
P74/TMRIV
P17/IRQ3/TRGV
OSC2
22
VSS
39
TEST
P75/TMCIV
P16/IRQ2
RES
23
VCL
P76/TMOV
38
X1
24
P15/IRQ1
X2
37
AVcc
P14/IRQ0
Figure 1.4 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions
(FP-48F, FP-48B, TNP-48)
Rev.5.00 Nov. 02, 2005 Page 7 of 418
REJ09B0028-0500
NC
NC
NMI
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P20/SCK3
P21/RXD
P22/TXD
NC
NC
Section 1 Overview
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52
29
P75/TMCIV
P16/IRQ2
53
28
P74/TMRIV
P17/IRQ3/TRGV
54
27
SCL
PB4/AN4
55
26
SDA
PB5/AN5
56
H8/3694N
25
P12
PB6/AN6
57
Top View
24
P11
PB7/AN7
58
23
P10/TMOW
PB3/AN3
59
22
P55/WKP5/ADTRG
PB2/AN2
60
21
P54/WKP4
PB1/AN1
61
20
P53/WKP3
PB0/AN0
62
19
P52/WKP2
NC
63
18
NC
NC
64
17
NC
8
9 10 11 12 13 14 15 16
NC
7
NC
6
P51/WKP1
5
P50/WKP0
4
Vcc
3
OSC1
2
OSC2
1
VSS
P76/TMOV
P15/IRQ1
TEST
30
RES
51
VCL
NC
P14/IRQ0
X1
31
X2
NC
50
AVcc
32
NC
NC
49
NC
NC
Note: Do not connect NC pins.
Figure 1.5 Pin Arrangement of H8/3694N (EEPROM Stacked Version)
(FP-64E)
Rev.5.00 Nov. 02, 2005 Page 8 of 418
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Section 1 Overview
1.4
Pin Functions
Table 1.1
Pin Functions
Pin No.
FP-48F
FP-48B
TNP-48
I/O
Functions
Type
Symbol
FP-64E
FP-64A
Power
source
pins
VCC
12
10
Input
Power supply pin. Connect this pin to the
system power supply.
VSS
9
7
Input
Ground pin. Connect this pin to the system
power supply (0V).
AVCC
3
1
Input
Analog power supply pin for the A/D converter.
When the A/D converter is not used, connect
this pin to the system power supply.
VCL
6
4
Input
Internal step-down power supply pin. Connect a
capacitor of around 0.1 µF between this pin
and the Vss pin for stabilization.
OSC1
11
9
Input
OSC2
10
8
Output
These pins connect with crystal or ceramic
resonator for the system clock, or can be used
to input an external clock.
Clock
pins
See section 5, Clock Pulse Generators, for a
typical connection.
System
control
These pins connect with a 32.768 kHz crystal
resonator for the subclock. See section 5,
Clock Pulse Generators, for a typical
connection.
X1
5
3
Input
X2
4
2
Output
RES
7
5
Input
Reset pin. The pull-up resistor (typ. 150 kΩ) is
incorporated. When driven low, the chip is
reset.
TEST
8
6
Input
Test pin. Connect this pin to Vss.
35
25
Input
Non-maskable interrupt request input pin. Be
sure to pull-up by a pull-up resistor.
51 to 54
37 to 40 Input
External interrupt request input pins. Can select
the rising or falling edge.
WKP0 to 13, 14,
WKP5
19 to 22
11 to 16 Input
External interrupt request input pins. Can select
the rising or falling edge.
Interrupt NMI
pins
IRQ0 to
IRQ3
Rev.5.00 Nov. 02, 2005 Page 9 of 418
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Section 1 Overview
Pin No.
FP-48F
FP-48B
TNP-48
I/O
Functions
Type
Symbol
FP-64E
FP-64A
Timer A
TMOW
23
17
Output
This is an output pin for divided clocks.
Timer V
TMOV
30
24
Output
This is an output pin for waveforms
generated by the output compare function.
TMCIV
29
23
Input
External event input pin.
TMRIV
28
22
Input
Counter reset input pin.
TRGV
54
40
Input
Counter start trigger input pin.
FTCI
36
26
Input
External event input pin.
I/O
Output compare output/input capture input/
PWM output pin
IIC data I/O pin. Can directly drive a bus by
NMOS open-drain output.
Timer W
FTIOA to 37 to 40 27 to 30
FTIOD
I2C bus
interface
(IIC)
SDA
26*1
20
I/O
SCL
27*1
21
I/O
IIC clock I/O pin. Can directly drive a bus
(EEPROM: by NMOS open-drain output.
Input)
Serial
TXD
communiRXD
cation
interface SCK3
(SCI)
46
36
Output
Transmit data output pin
45
35
Input
Receive data input pin
44
34
I/O
Clock I/O pin
A/D
AN7 to
converter AN0
55 to 62 41 to 48
Input
Analog input pin
ADTRG
22
Input
A/D converter trigger input pin.
PB7 to
PB0
55 to 62 41 to 48
Input
8-bit input port.
P17 to
P14,
P12 to
P10
51 to 54, 37 to 40
23 to 25 17 to 19
I/O
7-bit I/O port.
P22 to
P20
44 to 46 34 to 36
I/O
3-bit I/O port.
P57 to
P50
20, 21,
I/O
13, 14,
19 to 22, 13 to 16,
11, 12
26*2,
2
27*
8-bit I/O port
I/O ports
16
Rev.5.00 Nov. 02, 2005 Page 10 of 418
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Section 1 Overview
Pin No.
FP-64E
FP-64A
FP-48F
FP-48B
TNP-48
I/O
Functions
Type
Symbol
I/O ports
P76 to
P74
28 to 30 22 to 24
I/O
3-bit I/O port
P87 to
P80
36 to 43 26 to 33
I/O
8-bit I/O port.
Notes: 1. These pins are only available for the I2C bus interface in the H8/3694N. Since the I2C
bus is disabled after canceling a reset, the ICE bit in ICCR1 must be set to 1 by using
the program.
2. The P57 and P56 pins are not available in the H8/3694N.
Rev.5.00 Nov. 02, 2005 Page 11 of 418
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Section 1 Overview
Rev.5.00 Nov. 02, 2005 Page 12 of 418
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Section 2 CPU
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.
• Upward-compatible with H8/300 CPUs
 Can execute H8/300 CPUs object programs
 Additional eight 16-bit extended registers
 32-bit transfer and arithmetic and logic instructions are added
 Signed multiply and divide instructions are added.
• General-register architecture
 Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit
registers, or eight 32-bit registers
• Sixty-two basic instructions
 8/16/32-bit data transfer and arithmetic and logic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
 Absolute address [@aa:8, @aa:16, @aa:24]
 Immediate [#xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Memory indirect [@@aa:8]
• 64-kbyte address space
• High-speed operation
 All frequently-used instructions execute in one or two states
 8/16/32-bit register-register add/subtract
: 2 state
 8 × 8-bit register-register multiply : 14 states
 16 ÷ 8-bit register-register divide
: 14 states
 16 × 16-bit register-register multiply : 22 states
 32 ÷ 16-bit register-register divide : 22 states
• Power-down state
 Transition to power-down state by SLEEP instruction
CPU30H2D_000120030300
Rev.5.00 Nov. 02, 2005 Page 13 of 418
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Section 2 CPU
2.1
Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area.
Figures 2.1 show the memory map.
HD6433690, HD6433690G
(Mask ROM version)
HD64F3694, HD64F3694G
(Flash memory version)
H'0000
H'0033
H'0034
H'0000
H'0033
H'0034
Interrupt vector
Interrupt vector
HD6433691, HD6433691G
(Mask ROM version)
H'0000
H'0033
H'0034
On-chip ROM
(8 kbytes)
Interrupt vector
On-chip ROM
(12 kbytes)
H'1FFF
H'2FFF
On-chip ROM
(32 kbytes)
Not used
Not used
H'7FFF
Not used
H'F730
H'F730
Internal I/O register
H'F730
Internal I/O register
H'F74F
H'F74F
Internal I/O register
H'F74F
Not used
H'F780
(1-kbyte work area
for flash memory
programming)
H'FB7F
H'FB80
Not used
Not used
On-chip RAM
(2 kbytes)
(1-kbyte user area)
H'FD80
H'FD80
On-chip RAM
(512 bytes)
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
H'FF7F
H'FF80
H'FF7F
H'FF80
H'FFFF
Figure 2.1 Memory Map (1)
Rev.5.00 Nov. 02, 2005 Page 14 of 418
REJ09B0028-0500
Internal I/O register
Internal I/O register
Internal I/O register
H'FFFF
H'FFFF
Section 2 CPU
HD6433692, HD6433692G
(Mask ROM version)
H'0000
H'0033
H'0034
Interrupt vector
HD6433693, HD6433693G
(Mask ROM version)
H'0000
H'0033
H'0034
HD6433694, HD6433694G
(Mask ROM version)
H'0000
H'0033
H'0034
Interrupt vector
Interrupt vector
On-chip ROM
(16 kbytes)
On-chip ROM
(24 kbytes)
H'3FFF
On-chip ROM
(32 kbytes)
H'5FFF
Not used
H'7FFF
Not used
Not used
H'F730
H'F730
Internal I/O register
H'F74F
H'F730
Internal I/O register
Internal I/O register
H'F74F
H'F74F
Not used
Not used
Not used
H'FB80
H'FB80
On-chip RAM
(1 kbyte)
On-chip RAM
(1 kbyte)
H'FD80
On-chip RAM
(512 bytes)
Internal I/O register
Internal I/O register
Internal I/O register
H'FFFF
H'FF7F
H'FF80
H'FF7F
H'FF80
H'FF7F
H'FF80
H'FFFF
H'FFFF
Figure 2.1 Memory Map (2)
Rev.5.00 Nov. 02, 2005 Page 15 of 418
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Section 2 CPU
HD64N3694G
HD6483694G
(On-chip EEPROM module)
H'0000
H'01FF
User area
(512 bytes)
Not used
H'FF09
Slave address
register
Not used
Figure 2.1 Memory Map (3)
Rev.5.00 Nov. 02, 2005 Page 16 of 418
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Section 2 CPU
2.2
Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition code register (CCR).
General Registers (ERn)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7
E7
R7H
R7L
(SP)
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
[Legend]
SP:
PC:
CCR:
I:
UI:
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit
H:
U:
N:
Z:
V:
C:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Figure 2.2 CPU Registers
Rev.5.00 Nov. 02, 2005 Page 17 of 418
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Section 2 CPU
2.2.1
General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between stack pointer and the stack area.
Free area
SP (ER7)
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
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Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
6
UI
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0
C
Undefined R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
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2.3
Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1
General Register Data Formats
Figure 2.5 shows the data formats in general registers.
Data Type
General Register
Data Format
7
RnH
1-bit data
0
Don't care
7 6 5 4 3 2 1 0
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Lower
0
Don't care
MSB
LSB
Figure 2.5 General Register Data Formats (1)
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Data Type
General
Register
Word data
Rn
Data Format
15
Word data
MSB
En
15
MSB
Longword
data
0
LSB
0
LSB
ERn
31
16 15
MSB
[Legend]
ERn:
General register ER
En:
General register E
Rn:
General register R
RnH:
General register RH
RnL:
General register RL
MSB:
Most significant bit
LSB:
Least significant bit
Figure 2.5 General Register Data Formats (2)
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0
LSB
Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.
Data Type
Address
Data Format
7
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
LSB
Address 2N+3
Figure 2.6 Memory Data Formats
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2.4
Instruction Set
2.4.1
Table of Instructions Classified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined below.
Table 2.1
Operation Notation
Symbol
Description
Rd
General register (destination)*
Rs
General register (source)*
Rn
General register*
ERn
General register (32-bit register or address register)
(EAd)
Destination operand
(EAs)
Source operand
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical XOR
→
Move
¬
NOT (logical complement)
:3/:8/:16/:24
3-, 8-, 16-, or 24-bit length
Note:
*
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
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Table 2.2
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
(EAs) → Rd, Cannot be used in this LSI.
MOVTPE
B
Rs → (EAs) Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the
SUBX or ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3
Arithmetic Operations Instructions (2)
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note:
*
Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.6
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
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Table 2.6
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
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Table 2.7
Branch Instructions
Instruction
Size
Function
Bcc*
—
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA(BT)
Always (true)
Always
BRN(BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC(BHS)
Carry clear
(high or same)
C=0
BCS(BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z∨(N ⊕ V) = 0
BLE
Less or equal
Z∨(N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine
Note : *
Bcc is the general name for conditional branch instructions.
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Table 2.8
System Control Instructions
Instruction
Size*
Function
TRAPA
—
Starts trap-instruction exception handling.
RTE
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC
B/W
CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is written
by word access.
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the CCR with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the CCR with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically XORs the CCR with immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Note:
*
Refers to the operand size.
B: Byte
W: Word
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Table 2.9
Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.4.2
Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
• Condition Field
Specifies the branching condition of Bcc instructions.
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(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm
EA(disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA(disp)
BRA d:8
Figure 2.7 Instruction Formats
2.5
Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.
2.5.1
Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.
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Table 2.10 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:24,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
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• Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
Absolute Address—@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11,
because the upper 8 bits are ignored.
Table 2.11 Absolute Address Access Ranges
Absolute Address
Access Range
8 bits (@aa:8)
H'FF00 to H'FFFF
16 bits (@aa:16)
H'0000 to H'FFFF
24 bits (@aa:24)
H'0000 to H'FFFF
Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
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Section 2 CPU
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in
memory indirect mode. The upper bits of the absolute address are all assumed to be 0, so the
address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
Specified
by @aa:8
Dummy
Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.5.2
Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct(Rn)
rm
Operand is general register contents.
rn
Register indirect(@ERn)
0
31
23
0
23
0
23
0
23
0
General register contents
op
3
r
Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
0
31
General register contents
op
r
disp
0
31
Sign extension
4
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
op
0
31
General register contents
r
•Register indirect with pre-decrement @-ERn
disp
1, 2, or 4
31
0
General register contents
op
r
1, 2, or 4
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
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Section 2 CPU
Table 2.12 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
8 7
23
op
abs
0
H'FFFF
@aa:16
23
op
abs
16 15
0
Sign extension
@aa:24
op
0
23
abs
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC) @(d:16,PC)
op
disp
23
0
Sign
extension
8
disp
23
0
Memory indirect @@aa:8
8 7
23
op
abs
0
abs
H'0000
15
0
Memory contents
[Legend]
r, rm, rn:
op:
disp:
IMM:
abs:
23
16 15
0
H'00
Register field
Operation field
Displacement
Immediate data
Absolute address
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Section 2 CPU
2.6
Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φ or φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.9 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 20.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Bus cycle
T1 state
T2 state
T3 state
φ or φ SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.7
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active mode and subactive mode.
For the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states
are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution
state and program halt state, refer to section 6, Power-Down Modes. For details on exception
processing, refer to section 3, Exception Handling.
CPU state
Reset state
The CPU is initialized
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Sleep mode
Standby mode
Subsleep mode
Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Figure 2.11 CPU Operation States
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Power-down
modes
Section 2 CPU
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
Program halt state
Interrupt
source
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.12 State Transitions
2.8
Usage Notes
2.8.1
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2
EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
2.8.3
Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.
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Section 2 CPU
Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter
(Applicable for timer B and timer C, not for the group of this LSI.)
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal data bus
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address
Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
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Section 2 CPU
• Prior to executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
• BSET instruction executed instruction
BSET
#0,
@PDR5
The BSET instruction is executed for port 5.
• After executing BSET instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
0
1
0
0
0
0
0
1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
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Section 2 CPU
• Prior to executing BSET instruction
MOV.B
MOV.B
MOV.B
#80,
R0L,
R0L,
R0L
@RAM0
@PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
• BSET instruction executed
BSET
#0,
@RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
• After executing BSET instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PDR5
The work area (RAM0) value is written to PDR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
Rev.5.00 Nov. 02, 2005 Page 46 of 418
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Section 2 CPU
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
• BCLR instruction executed
BCLR
#0,
@PCR5
The BCLR instruction is executed for PCR5.
• After executing BCLR instruction
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
1
1
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
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Section 2 CPU
• Prior to executing BCLR instruction
MOV.B
MOV.B
MOV.B
#3F,
R0L,
R0L,
R0L
@RAM0
@PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5
0
0
1
1
1
1
1
1
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
1
• BCLR instruction executed
BCLR
#0,
@RAM0
The BCLR instructions executed for the PCR5 work area
(RAM0).
• After executing BCLR instruction
MOV.B
MOV.B
@RAM0, R0L
R0L, @PCR5
The work area (RAM0) value is written to PCR5.
P57
P56
P55
P54
P53
P52
P51
P50
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5
0
0
1
1
1
1
1
0
PDR5
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
0
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared
by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling
starts. Exception handling is the same as exception handling by the RES pin.
• Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction
generates a vector address corresponding to a vector number from 0 to 3, as specified in the
instruction code. Exception handling can be executed at all times in the program execution state,
regardless of the setting of the I bit in CCR.
• Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked by
the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the
current instruction or exception handling ends, if an interrupt request has been issued.
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1
Exception Sources and Vector Address
Relative Module
Exception Sources
Vector
Number
Vector Address
Priority
RES pin
Watchdog timer
Reset
0
H'0000 to H'0001
High

Reserved for system use
1 to 6
H'0002 to H'000D
External interrupt
pin
NMI
7
H'000E to H'000F
CPU
Trap instruction (#0)
8
H'0010 to H'0011
(#1)
9
H'0012 to H'0013
(#2)
10
H'0014 to H'0015
(#3)
11
H'0016 to H'0017
12
H'0018 to H'0019
Address break
Break conditions satisfied
Low
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Section 3 Exception Handling
Vector
Number
Vector Address
Priority
Direct transition by executing
the SLEEP instruction
13
H'001A to H'001B
High
IRQ0
Low-voltage detection
interrupt*
14
H'001C to H'001D
IRQ1
15
H'001E to H'001F
IRQ2
16
H'0020 to H'0021
IRQ3
17
H'0022 to H'0023
WKP
18
H'0024 to H'0025
Timer A
Overflow
19
H’0026 to H’0027

Reserved for system use
20
H’0028 to H’0029
Timer W
Timer W input capture A
/compare match A
Timer W input capture B
/compare match B
Timer W input capture C
/compare match C
Timer W input capture D
/compare match D
Timer W overflow
21
H’002A to H’002B
Timer V
Timer V compare match A
Timer V compare match B
Timer V overflow
22
H'002C to H'002D
SCI3
SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23
H'002E to H'002F
IIC2
Transmit data empty
Transmit end
Receive data full
Arbitration lost/Overrun error
NACK detection
Stop conditions detected
24
H'0030 to H'0031
A/D converter
A/D conversion end
25
H'0032 to H'0033
Relative Module
Exception Sources
CPU
External interrupt
pin
Note
*
Low
A low-voltage detection interrupt is enabled only in the product with an on-chip poweron reset and low-voltage detection circuit.
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Section 3 Exception Handling
3.2
Register Descriptions
Interrupts are controlled by the following registers.
•
•
•
•
•
Interrupt edge select register 1 (IEGR1)
Interrupt edge select register 2 (IEGR2)
Interrupt enable register 1 (IENR1)
Interrupt flag register 1 (IRR1)
Wakeup interrupt flag register (IWPR)
3.2.1
Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to
IRQ0.
Bit
Bit Name
Initial
Value
R/W
Description
7
NMIEG
0
R/W
NMI Edge Select
0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected
6 to 4

All 1

Reserved
These bits are always read as 1.
3
IEG3
0
R/W
IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
2
IEG2
0
R/W
IRQ2 Edge Select
0: Falling edge of IRQ2 pin input is detected
1: Rising edge of IRQ2 pin input is detected
1
IEG1
0
R/W
IRQ1 Edge Select
0: Falling edge of IRQ1 pin input is detected
1: Rising edge of IRQ1 pin input is detected
0
IEG0
0
R/W
IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
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Section 3 Exception Handling
3.2.2
Interrupt Edge Select Register 2 (IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and
WKP5 to WKP0.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
5
WPEG5
0
R/W
WKP5 Edge Select
These bits are always read as 1.
0: Falling edge of WKP5(ADTRG) pin input is detected
1: Rising edge of WKP5(ADTRG) pin input is detected
4
WPEG4
0
R/W
WKP4 Edge Select
0: Falling edge of WKP4 pin input is detected
1: Rising edge of WKP4 pin input is detected
3
WPEG3
0
R/W
WKP3 Edge Select
0: Falling edge of WKP3 pin input is detected
1: Rising edge of WKP3 pin input is detected
2
WPEG2
0
R/W
WKP2 Edge Select
0: Falling edge of WKP2 pin input is detected
1: Rising edge of WKP2 pin input is detected
1
WPEG1
0
R/W
WKP1Edge Select
0: Falling edge of WKP1 pin input is detected
1: Rising edge of WKP1 pin input is detected
0
WPEG0
0
R/W
WKP0 Edge Select
0: Falling edge of WKP0 pin input is detected
1: Rising edge of WKP0 pin input is detected
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Section 3 Exception Handling
3.2.3
Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
IENDT
0
R/W
Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
6
IENTA
0
R/W
Timer A Interrupt Enable
When this bit is set to 1, timer A overflow interrupt
requests are enabled.
5
IENWP
0
R/W
Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
4

1

Reserved
This bit is always read as 1.
3
IEN3
0
R/W
IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3
pin are enabled.
2
IEN2
0
R/W
IRQ2 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ2
pin are enabled.
1
IEN1
0
R/W
IRQ1 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ1
pin are enabled.
0
IEN0
0
R/W
IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
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Section 3 Exception Handling
3.2.4
Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3
to IRQ0 interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
7
IRRDT
0
R/W
Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
6
IRRTA
0
R/W
Timer A Interrupt Request Flag
[Setting condition]
When the timer A counter value overflows
[Clearing condition]
When IRRTA is cleared by writing 0
5, 4

All 1

Reserved
These bits are always read as 1.
3
IRRI3
0
R/W
IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI3 is cleared by writing 0
2
IRRI2
0
R/W
IRQ2 Interrupt Request Flag
[Setting condition]
When IRQ2 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI2 is cleared by writing 0
1
IRRI1
0
R/W
IRQ1 Interrupt Request Flag
[Setting condition]
When IRQ1 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI1 is cleared by writing 0
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Section 3 Exception Handling
Bit
Bit Name
Initial
Value
R/W
Description
0
IRRl0
0
R/W
IRQ0 Interrupt Request Flag
[Setting condition]
When IRQ0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IRRI0 is cleared by writing 0
3.2.5
Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1.
5
IWPF5
0
R/W
WKP5 Interrupt Request Flag
[Setting condition]
When WKP5 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF5 is cleared by writing 0.
4
IWPF4
0
R/W
WKP4 Interrupt Request Flag
[Setting condition]
When WKP4 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF4 is cleared by writing 0.
3
IWPF3
0
R/W
WKP3 Interrupt Request Flag
[Setting condition]
When WKP3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF3 is cleared by writing 0.
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Section 3 Exception Handling
Bit
Bit Name
Initial
Value
R/W
Description
2
IWPF2
0
R/W
WKP2 Interrupt Request Flag
[Setting condition]
When WKP2 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF2 is cleared by writing 0.
1
IWPF1
0
R/W
WKP1 Interrupt Request Flag
[Setting condition]
When WKP1 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF1 is cleared by writing 0.
0
IWPF0
0
R/W
WKP0 Interrupt Request Flag
[Setting condition]
When WKP0 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF0 is cleared by writing 0.
3.3
Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1.
The reset exception handling sequence is as follows. However, for the reset exception handling
sequence of the product with on-chip power-on reset circuit, refer to section 18, Power-On Reset
and Low-Voltage Detection Circuits (Optional).
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
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Section 3 Exception Handling
3.4
Interrupt Exception Handling
3.4.1
External Interrupts
As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.
NMI Interrupt
NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either
rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.
NMI is the highest-priority interrupt, and can always be accepted without depending on the I
bit value in CCR.
IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four
interrupts are given different vector addresses, and are detected individually by either rising
edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.
When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.
WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in
IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated
signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an
interrupt. These interrupts can be masked by setting bit IENWP in IENR1.
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Section 3 Exception Handling
Reset cleared
Initial program
instruction prefetch
Vector fetch Internal
processing
RES
φ
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
Figure 3.1 Reset Sequence
3.4.2
Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests
generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by
writing 0 to clear the corresponding enable bit.
3.4.3
Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
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Section 3 Exception Handling
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.
3. The CPU accepts the NMI and address break without depending on the I bit value. Other
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
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Section 3 Exception Handling
SP – 4
SP (R7)
CCR
SP – 3
SP + 1
CCR*3
SP – 2
SP + 2
PCH
SP – 1
SP + 3
PCL
SP (R7)
SP + 4
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
[Legend]
PCH : Upper 8 bits of program counter (PC)
PCL : Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
2. Register contents must always be saved and restored by word length, starting from
an even-numbered address.
3. Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling
3.4.4
Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 23
15 to 37
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note:
*
Not including EEPMOV instruction.
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(2)
(1)
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
Internal data bus
(16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
φ
Interrupt
request signal
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
Section 3 Exception Handling
Figure 3.3 Interrupt Sequence
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Section 3 Exception Handling
3.5
Usage Notes
3.5.1
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.W #xx: 16, SP).
3.5.2
Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the
stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd
address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore
register values.
3.5.3
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to
IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.
Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
CCR I bit ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register bit
Execute NOP instruction
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0.
Clear interrupt request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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Section 4 Address Break
Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4.1 shows a block diagram of the address break.
Internal address bus
Comparator
BARL
ABRKCR
Interrupt
generation
control circuit
ABRKSR
BDRH
Internal data bus
BARH
BDRL
Comparator
Interrupt
[Legend]
BARH, BARL:
BDRH, BDRL:
ABRKCR:
ABRKSR:
Break address register
Break data register
Address break control register
Address break status register
Figure 4.1 Block Diagram of Address Break
4.1
Register Descriptions
Address break has the following registers.
•
•
•
•
Address break control register (ABRKCR)
Address break status register (ABRKSR)
Break address register (BARH, BARL)
Break data register (BDRH, BDRL)
ABK0001A_000020020200
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Section 4 Address Break
4.1.1
Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Bit
Bit Name
Initial
Value
R/W
Description
7
RTINTE
1
R/W
RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
6
CSEL1
0
R/W
Condition Select 1 and 0
5
CSEL0
0
R/W
These bits set address break conditions.
00: Instruction execution cycle
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
4
ACMP2
0
R/W
Address Compare Condition Select 2 to 0
3
ACMP1
0
R/W
2
ACMP0
0
R/W
These bits set the comparison condition between the
address set in BAR and the internal address bus.
000: Compares 16-bit addresses
001: Compares upper 12-bit addresses
010: Compares upper 8-bit addresses
011: Compares upper 4-bit addresses
1XX: Reserved (setting prohibited)
1
DCMP1
0
R/W
Data Compare Condition Select 1 and 0
0
DCMP0
0
R/W
These bits set the comparison condition between the data
set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
bus
10: Compares upper 8-bit data between BDRH and data
bus
11: Compares 16-bit data between BDR and data bus
Legend: X: Don't care.
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Section 4 Address Break
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 20.1,
Register Addresses (Address Order).
Table 4.1
Access and Data Bus Used
Word Access
Byte Access
Even Address Odd
Address
Even Address Odd Address
ROM space
Upper 8 bits
Lower 8 bits
Upper 8 bits
Upper 8 bits
RAM space
Upper 8 bits
Lower 8 bits
Upper 8 bits
Upper 8 bits
I/O register with 8-bit data bus Upper 8 bits
width
Upper 8 bits
Upper 8 bits
Upper 8 bits
I/O register with 16-bit data
bus width
Lower 8 bits
—
—
4.1.2
Upper 8 bits
Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit
Bit Name
Initial
Value
R/W
Description
7
ABIF
0
R/W
Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
6
ABIE
0
R/W
Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
5 to 0
—
All 1
—
Reserved
These bits are always read as 1.
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Section 4 Address Break
4.1.3
Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4
Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
4.2
Operation
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked by the I bit in CCR of the CPU.
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Section 4 Address Break
Figures 4.2 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR = H'80
• BAR = H'025A
Program
0258
* 025A
025C
0260
0262
:
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
Underline indicates the address
to be stacked.
NOP
NOP
MOV
MOV
instruc- instruc- instruc- instruction
tion
tion 1
tion 2
Internal
prefetch prefetch prefetch prefetch processing
Stack save
φ
Address
bus
0258
025A
025C
025E
SP-2
SP-4
Interrupt
request
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (1)
When the address break is specified in the data read cycle
Register setting
• ABRKCR = H'A0
• BAR = H'025A
Program
0258
025A
* 025C
0260
0262
:
NOP
NOP
MOV.W @H'025A,R0
NOP
Underline indicates the address
NOP
to be stacked.
:
MOV
NOP
MOV
NOP
Next
MOV
instruc- instruc- instruc- instruc- instruc- instrution 2
tion
tion
tion
ction
Internal Stack
tion 1
prefetch prefetch prefetch execution prefetch prefetch processing save
φ
Address
bus
025C
025E
0260
025A
0262
0264
SP-2
Interrupt
request
Interrupt acceptance
Figure 4.2 Address Break Interrupt Operation Example (2)
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Section 4 Address Break
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Section 5 Clock Pulse Generators
Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The
subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Figure 5.1 shows a block diagram of the clock pulse generators.
OSC1
OSC2
System
clock
oscillator
φOSC
(fOSC)
Duty
correction
circuit
φOSC
(fOSC)
System
clock
divider
φOSC
φOSC/8
φOSC/16
φOSC/32
φOSC/64
System clock pulse generator
X1
X2
Subclock
oscillator
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
φW/2
φW
(fW)
Subclock
divider
φW/4
φSUB
φW/8
Prescaler W
(5 bits)
φW/8
to
φW/128
Subclock pulse generator
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2, and the
subclock is divided by prescaler W to become a clock signal from φw/128 to φw/8. Both the
system clock and subclock signals are provided to the on-chip peripheral modules.
CPG0200A_000020020200
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Section 5 Clock Pulse Generators
5.1
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system
clock generator.
OSC 2
LPM
OSC 1
LPM: Low-power mode (standby mode, subactive mode, subsleep mode)
Figure 5.2 Block Diagram of System Clock Generator
5.1.1
Connecting Crystal Resonator
Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance
crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a crystal resonator. A
resonator having the characteristics given in table 5.1 should be used.
C1
OSC 1
C2
OSC 2
C1 = C 2 = 10 to 22 pF
Figure 5.3 Typical Connection to Crystal Resonator
LS
RS
CS
OSC 1
OSC 2
C0
Figure 5.4 Equivalent Circuit of Crystal Resonator
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Section 5 Clock Pulse Generators
Table 5.1
Crystal Resonator Parameters
Frequency (MHz)
2
4
8
10
16
20
RS (max)
500 Ω
120 Ω
80 Ω
60 Ω
50 Ω
40 Ω
C0 (max)
7 pF
7 pF
7 pF
7 pF
7 pF
7 pF
5.1.2
Connecting Ceramic Resonator
Figure 5.5 shows a typical method of connecting a ceramic resonator.
C1
OSC1
C2
OSC2
C1 = 5 to 30 pF
C2 = 5 to 30 pF
Figure 5.5 Typical Connection to Ceramic Resonator
5.1.3
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.6 shows a typical
connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
OSC 2
External clock input
Open
Figure 5.6 Example of External Clock Input
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Section 5 Clock Pulse Generators
5.2
Subclock Generator
Figure 5.7 shows a block diagram of the subclock generator.
X2
8MΩ
X1
Note : Registance is a reference value.
Figure 5.7 Block Diagram of Subclock Generator
5.2.1
Connecting 32.768-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal
resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz crystal
resonator.
C1
X1
C2
X2
C1 = C 2 = 15 pF (typ.)
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator
LS
CS
RS
X1
X2
CO
CO = 1.5 pF (typ.)
RS = 14 kΩ (typ.)
fW = 32.768 kHz
Note: Constants are reference values.
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator
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Section 5 Clock Pulse Generators
5.2.2
Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in
figure 5.10.
VCL or VSS
X1
X2
Open
Figure 5.10 Pin Connection when not Using Subclock
5.3
Prescalers
5.3.1
Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from
the reset state. In standby mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write
prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider
ratio can be set separately for each on-chip peripheral function. In active mode and sleep mode,
the clock input to prescaler S is determined by the division factor designated by MA2 to MA0 in
SYSCR2.
5.3.2
Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (φW/4) as its input clock. The
divided output is used for clock time base operation of timer A. Prescaler W is initialized to H'00
by a reset, and starts counting on exit from the reset state. Even in standby mode, subactive mode,
or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins
X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register
A (TMA).
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Section 5 Clock Pulse Generators
5.4
Usage Notes
5.4.1
Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit constants will differ
depending on the resonator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the resonator element
manufacturer. Design the circuit so that the resonator element never receives voltages exceeding
its maximum rating.
5.4.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the
resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11).
Signal A
Avoid
Signal B
C1
OSC1
C2
OSC2
Figure 5.11 Example of Incorrect Board Design
Rev.5.00 Nov. 02, 2005 Page 74 of 418
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Section 6 Power-Down Modes
Section 6 Power-Down Modes
This LSI has six modes of operation after a reset. These include a normal active mode and four
power-down modes, in which power consumption is significantly reduced. Module standby mode
reduces power consumption by selectively halting on-chip module functions.
• Active mode
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
• Subactive mode
The CPU and all on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φw/2, φw/4, and φw/8.
• Sleep mode
The CPU halts. On-chip peripheral modules are operable on the system clock.
• Subsleep mode
The CPU halts. On-chip peripheral modules are operable on the subclock.
• Standby mode
The CPU and all on-chip peripheral modules halt. When the clock time-base function is
selected, timer A is operable.
• Module standby mode
Independent of the above modes, power consumption can be reduced by halting on-chip
peripheral modules that are not used in module units.
6.1
Register Descriptions
The registers related to power-down modes are listed below.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Module standby control register 1 (MSTCR1)
LPW3003A_000020020200
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Section 6 Power-Down Modes
6.1.1
System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit
Bit Name
Initial
Value
R/W
Description
7
SSBY
0
R/W
Software Standby
This bit selects the mode to transit after the execution of
the SLEEP instruction.
0: a transition is made to sleep mode or subsleep mode.
1: a transition is made to standby mode.
For details, see table 6.2.
6
STS2
0
R/W
Standby Timer Select 2 to 0
5
STS1
0
R/W
4
STS0
0
R/W
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting from
standby mode, subactive mode, or subsleep mode to
active mode or sleep mode due to an interrupt. The
designation should be made according to the clock
frequency so that the waiting time is at least 6.5 ms. The
relationship between the specified value and the number
of wait states is shown in table 6.1. When an external
clock is to be used, the minimum value (STS2 = STS1 =
STS0 = 1) is recommended.
3
NESEL
0
R/W
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch clock
signal (φW) and the system clock pulse generator
generates the oscillator clock (φOSC). This bit selects the
sampling frequency of the oscillator clock when the watch
clock signal (φW) is sampled. When φOSC = 4 to 20 MHz,
clear NESEL to 0.
0: Sampling rate is φOSC/16
1: Sampling rate is φOSC/4
2 to 0

All 0

Reserved
These bits are always read as 0.
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Section 6 Power-Down Modes
Table 6.1
Operating Frequency and Waiting Time
STS2 STS1 STS0 Waiting Time
20
MHz
16
MHz
10
MHz
8 MHz
4 MHz
2 MHz
1 MHz 0.5 MHz
0
0
1
1
0
1
0
8,192 states
0.4
0.5
0.8
1.0
2.0
4.1
8.1
16.4
1
16,384 states
0.8
1.0
1.6
2.0
4.1
8.2
16.4
32.8
0
32,768 states
1.6
2.0
3.3
4.1
8.2
16.4
32.8
65.5
1
65,536 states
3.3
4.1
6.6
8.2
16.4
32.8
65.5
131.1
0
131,072 states
6.6
8.2
13.1
16.4
32.8
65.5
131.1
262.1
1
1,024 states
0.05
0.06
0.10
0.13
0.26
0.51
1.02
2.05
0
128 states
0.00
0.00
0.01
0.02
0.03
0.06
0.13
0.26
1
16 states
0.00
0.00
0.00
0.00
0.00
0.01
0.02
0.03
Note: Time unit is ms.
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Section 6 Power-Down Modes
6.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit
Bit Name
Initial
Value
R/W
Description
7
SMSEL
0
R/W
Sleep Mode Selection
6
LSON
0
R/W
Low Speed on Flag
5
DTON
0
R/W
Direct Transfer on Flag
These bits select the mode to transit after the execution
of a SLEEP instruction, as well as bit SSBY of SYSCR1.
For details, see table 6.2.
4
MA2
0
R/W
Active Mode Clock Select 2 to 0
3
MA1
0
R/W
2
MA0
0
R/W
These bits select the operating clock frequency in active
and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction
is executed.
0XX: φOSC
100: φOSC/8
101: φOSC/16
110: φOSC/32
111: φOSC/64
1
SA1
0
R/W
Subactive Mode Clock Select 1 and 0
0
SA0
0
R/W
These bits select the operating clock frequency in
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the SLEEP
instruction is executed.
00: φW/8
01: φW/4
1X: φW/2
Legend: X : Don't care.
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Section 6 Power-Down Modes
6.1.3
Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit
Bit Name
Initial
Value
R/W
7

0

Description
Reserved
This bit is always read as 0.
6
MSTIIC
0
R/W
IIC Module Standby
IIC enters standby mode when this bit is set to 1
5
MSTS3
0
R/W
SCI3 Module Standby
4
MSTAD
0
R/W
A/D Converter Module Standby
SCI3 enters standby mode when this bit is set to 1
A/D converter enters standby mode when this bit is set to
1
3
MSTWD
0
R/W
Watchdog Timer Module Standby
Watchdog timer enters standby mode when this bit is set
to 1.When the internal oscillator is selected for the
watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit
2
MSTTW
0
R/W
Timer W Module Standby
Timer W enters standby mode when this bit is set to 1
1
MSTTV
0
R/W
Timer V Module Standby
Timer V enters standby mode when this bit is set to 1
0
MSTTA
0
R/W
Timer A Module Standby
Timer A enters standby mode when this bit is set to 1
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Section 6 Power-Down Modes
6.2
Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state of the program by executing a SLEEP
instruction. Interrupts allow for returning from the program halt state to the program execution
state of the program. A direct transition between active mode and subactive mode, which are both
program execution states, can be made without halting the program. The operating frequency can
also be changed in the same modes by making a transition directly from active mode to active
mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to
the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction
is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in
each mode.
Reset state
Program halt state
Program execution state
SLEEP
instruction
Direct transition
interrupt
SLEEP
instruction
Sleep mode
Active mode
Standby mode
Program halt state
Interrupt
Interrupt
SLEEP
instruction
Direct
transition
interrupt
Direct
transition
interrupt
Interrupt
SLEEP
instruction
SLEEP
instruction
Interrupt
SLEEP
instruction
Subactive
mode
Subsleep mode
Interrupt
Direct transition
interrupt
Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt
is accepted.
2. Details on the mode transition conditions are given in table 6.2.
Figure 6.1 Mode Transition Diagram
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Section 6 Power-Down Modes
Table 6.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
DTON
SSBY
SMSEL
LSON
Transition Mode after
SLEEP Instruction
Execution
0
0
0
0
Sleep mode
1
1
0
Legend:
*
Active mode
Subactive mode
Subsleep mode
1
1
Transition Mode due to
Interrupt
Active mode
Subactive mode
1
X
X
Standby mode
Active mode
X
0*
0
Active mode (direct
transition)
—
X
X
1
Subactive mode (direct
transition)
—
X : Don’t care.
When a state transition is performed while SMSEL is 1, timer V, SCI3, and the A/D
converter are reset, and all registers are set to their initial values. To use these
functions after entering active mode, reset the registers.
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Section 6 Power-Down Modes
Table 6.3
Internal State in Each Operating Mode
Function
Active Mode
Sleep Mode
Subactive
Mode
Subsleep
Mode
Standby
Mode
System clock oscillator
Functioning
Functioning
Halted
Halted
Halted
Subclock oscillator
Functioning
Functioning
Functioning
Functioning
Functioning
CPU
operations
Instructions
Functioning
Halted
Functioning
Halted
Halted
Registers
Functioning
Retained
Functioning
Retained
Retained
RAM
Functioning
Retained
Functioning
Retained
Retained
IO ports
Functioning
Retained
Functioning
Retained
Register
contents are
retained, but
output is the
highimpedance
state.
IRQ3 to IRQ0
Functioning
Functioning
Functioning
Functioning
Functioning
WKP5 to
WKP0
Functioning
Functioning
Functioning
Functioning
Functioning
Timer A
Functioning
Functioning
Functioning if the timekeeping time-base
function is selected, and retained if not selected
Timer V
Functioning
Functioning
Reset
Timer W
Functioning
Functioning
Retained (if internal clock φ is
selected as a count clock, the
counter is incremented by a
subclock*)
Watchdog
timer
Functioning
Functioning
Retained (functioning if the internal oscillator is
selected as a count clock*)
SCI3
Functioning
Functioning
Reset
Reset
Reset
IIC
Functioning
Functioning
Retained*
Retained
Retained
A/D converter
Functioning
Functioning
Reset
Reset
Reset
External
interrupts
Peripheral
functions
Note:
*
Registers can be read or written in subactive mode.
Rev.5.00 Nov. 02, 2005 Page 82 of 418
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Reset
Reset
Retained
Section 6 Power-Down Modes
6.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a
transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to
subactive mode when the bit is 1.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
6.2.2
Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop
functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2–STS0 in SYSCR1 has elapsed, and interrupt
exception handling starts. Standby mode is not cleared if the I bit of CCR is set to 1 or the
requested interrupt is disabled in the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.3
Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules other than timer A is
halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM,
and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states
as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1
or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is
Rev.5.00 Nov. 02, 2005 Page 83 of 418
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Section 6 Power-Down Modes
cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is
made to subactive mode when the bit is 1.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.4
Subactive Mode
The operating frequency of subactive mode is selected from φW/2, φW/4, and φW/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution. When the SLEEP instruction is executed in
subactive mode, a transition to sleep mode, subsleep mode, standby mode, active mode, or
subactive mode is made, depending on the combination of SYSCR1 and SYSCR2. When the RES
pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to
the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be
kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized,
the CPU starts reset exception handling if the RES pin is driven high.
6.3
Operating Frequency in Active Mode
Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits
in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction
execution.
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Section 6 Power-Down Modes
6.4
Direct Transition
The CPU can execute programs in two modes: active and subactive mode. A direct transition is a
transition between these two modes without stopping program execution. A direct transition can
be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct
transition also enables operating frequency modification in active or subactive mode. After the
mode transition, direct transition interrupt exception handling starts.
If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made
instead to sleep or subsleep mode. Note that if a direct transition is attempted while the I bit in
CCR is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared
by means of an interrupt.
6.4.1
Direct Transition from Active Mode to Subactive Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (1).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)}× (tcyc before transition) + (number of interrupt exception handling states) ×
(tsubcyc after transition) (1)
Example
Direct transition time = (2 + 1) × tosc + 14 × 8tw = 3tosc + 112tw
(when the CPU operating clock of φosc → φw/8 is selected)
Legend
tosc: OSC clock cycle time
tw: watch clock cycle time
tcyc: system clock (φ) cycle time
tsubcyc: subclock (φSUB) cycle time
6.4.2
Direct Transition from Subactive Mode to Active Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (2).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)} × (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) +
(number of interrupt exception handling states)} × (tcyc after transition)
(2)
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Section 6 Power-Down Modes
Example
Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc
(when the CPU operating clock of φw/8 → φosc and a waiting time of 8192 states are selected)
Legend
tosc: OSC clock cycle time
tw: watch clock cycle time
tcyc: system clock (φ) cycle time
tsubcyc: subclock (φSUB) cycle time
6.5
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the
clock supply to modules stops to enter the power-down mode. Module standby mode enables each
on-chip peripheral module to enter the standby state by setting a bit that corresponds to each
module to 1 and cancels the mode by clearing the bit to 0.
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Section 7 ROM
Section 7 ROM
The features of the 32-kbyte flash memory built into the flash memory version are summarized
below.
• Programming/erase methods
 The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The flash memory is configured as follows: 1 kbyte × 4 blocks and 28 kbytes × 1
block. To erase the entire flash memory, each block must be erased in turn.
• Reprogramming capability
 The flash memory can be reprogrammed up to 1,000 times.
• On-board programming
 On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
 Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
 For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
 Sets software protection against flash memory programming/erasing.
• Power-down mode
 Operation of the power supply circuit can be partly halted in subactive mode. As a result,
flash memory can be read with low power consumption.
7.1
Block Configuration
Figure 7.1 shows the block configuration of 32-kbyte flash memory. The thick lines indicate
erasing units, the narrow lines indicate programming units, and the values are addresses. The flash
memory is divided into 1 kbyte × 4 blocks and 28 kbytes × 1 block. Erasing is performed in these
units. Programming is performed in 128-byte units starting from an address with lower eight bits
H'00 or H'80.
ROM3321A_000120030300
Rev.5.00 Nov. 02, 2005 Page 87 of 418
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Section 7 ROM
Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'0380
H'0381
H'0382
H'0400
H'0401
H'0402
H'0480
H'0481
H'0481
H'0780
H'0781
H'0782
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'7F80
H'7F81
H'7F82
H'7FFF
Programming unit: 128 bytes
H'007F
H'00FF
1kbyte
Erase unit
H'03FF
Programming unit: 128 bytes
H'047F
H'04FF
1kbyte
Erase unit
H'07FF
Programming unit: 128 bytes
H'087F
H'08FF
1kbyte
Erase unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1kbyte
Erase unit
H'0FFF
Programming unit: 128 bytes
H'107F
28 kbytes
Figure 7.1 Flash Memory Block Configuration
7.2
Register Descriptions
The flash memory has the following registers.
•
•
•
•
•
Flash memory control register 1 (FLMCR1)
Flash memory control register 2 (FLMCR2)
Erase block register 1 (EBR1)
Flash memory power control register (FLPWCR)
Flash memory enable register (FENR)
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Section 7 ROM
7.2.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash
Memory Programming/Erasing.
Bit
Bit Name
Initial
Value
R/W
7
—
0
—
Description
Reserved
This bit is always read as 0.
6
SWE
0
R/W
Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is cleared
to 0, other FLMCR1 register bits and all EBR1 bits cannot
be set.
5
ESU
0
R/W
Erase Setup
When this bit is set to 1, the flash memory changes to the
erase setup state. When it is cleared to 0, the erase
setup state is cancelled. Set this bit to 1 before setting the
E bit to 1 in FLMCR1.
4
PSU
0
R/W
Program Setup
When this bit is set to 1, the flash memory changes to the
program setup state. When it is cleared to 0, the program
setup state is cancelled. Set this bit to 1 before setting
the P bit in FLMCR1.
3
EV
0
R/W
Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
2
PV
0
R/W
Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0, programverify mode is cancelled.
1
E
0
R/W
Erase
When this bit is set to 1, and while the SWE=1 and
ESU=1 bits are 1, the flash memory changes to erase
mode. When it is cleared to 0, erase mode is cancelled.
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Section 7 ROM
Bit
Bit Name
Initial
Value
R/W
Description
0
P
0
R/W
Program
When this bit is set to 1, and while the SWE=1 and
PSU=1 bits are 1, the flash memory changes to program
mode. When it is cleared to 0, program mode is
cancelled.
7.2.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit
Bit Name
Initial
Value
R/W
7
FLER
0
R
Description
Flash Memory Error
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When FLER
is set to 1, flash memory goes to the error-protection
state.
See 7.5.3, Error Protection, for details.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
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Section 7 ROM
7.2.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
—
All 0
—
Reserved
These bits are always read as 0.
4
EB4
0
R/W
When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased.
3
EB3
0
R/W
When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will
be erased.
2
EB2
0
R/W
When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will
be erased.
1
EB1
0
R/W
When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will
be erased.
0
EB0
0
R/W
When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will
be erased.
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7.2.4
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PDWND
0
R/W
Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to subactive
mode.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
7.2.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit
Bit Name
Initial
Value
R/W
Description
7
FLSHE
0
R/W
Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
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7.3
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST
pin settings, NMI pin settings, and input level of each port, as shown in table 7.1. The input level
of each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 7.1
Setting Programming Modes
TEST
NMI
P85
PB0
PB1
PB2
LSI State after Reset End
0
1
X
X
X
X
User Mode
0
0
1
X
X
X
Boot Mode
1
X
X
0
0
0
Programmer Mode
Legend: X : Don’t care.
7.3.1
Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 7.4, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
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Section 7 ROM
4.
5.
6.
7.
8.
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit
rate and system clock frequency of this LSI within the ranges listed in table 7.3.
In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of write data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the NMI pin. Boot mode is also cleared when a WDT overflow
occurs.
Do not change the TEST pin and NMI pin input levels in boot mode.
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Section 7 ROM
Boot Mode Operation
Host Operation
Communication Contents
Processing Contents
Transfer of number of bytes of
programming control program
Flash memory erase
Bit rate adjustment
Boot mode initiation
Item
Table 7.2
LSI Operation
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'00, H'00 . . . H'00
H'00
H'55
Boot program
erase error
H'AA reception
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
control program (repeated for N times)
H'AA reception
H'FF
H'AA
Upper bytes, lower bytes
Echoback
H'XX
Echoback
H'AA
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
H'55 reception.
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Transmits data H'AA to host.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
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Section 7 ROM
Table 7.3
System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate
System Clock Frequency Range of LSI
19,200 bps
16 to 20 MHz
9,600 bps
8 to 16 MHz
4,800 bps
4 to 16 MHz
2,400 bps
2 to 16 MHz
7.3.2
Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 7.2 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 7.4,
Flash Memory Programming/Erasing.
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Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
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Section 7 ROM
7.4
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 7.4.1, Program/Program-Verify and section 7.4.2,
Erase/Erase-Verify, respectively.
7.4.1
Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 7.3 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 7.4, and additional programming data
computation according to table 7.5.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words or in longwords from the address to which a
dummy write was performed.
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Section 7 ROM
8.
The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Write pulse application subroutine
START
Apply Write Pulse
Set SWE bit in FLMCR1
WDT enable
Wait 1 µs
Set PSU bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
*
Wait 50 µs
n= 1
Set P bit in FLMCR1
m= 0
Wait (Wait time=programming time)
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Clear P bit in FLMCR1
Wait 5 µs
Apply Write pulse
Clear PSU bit in FLMCR1
Set PV bit in FLMCR1
Wait 4 µs
Wait 5 µs
Disable WDT
Set block start address as
verify address
End Sub
H'FF dummy write to verify address
n←n+1
Wait 2 µs
*
Read verify data
Increment address
No
Verify data =
write data?
m=1
Yes
n≤6?
No
Yes
Additional-programming data computation
Reprogram data computation
No
128-byte
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
n ≤ 6?
No
Yes
Successively write 128-byte data from additionalprogramming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m= 0 ?
Yes
Clear SWE bit in FLMCR1
No
n ≤ 1000 ?
Yes
No
Clear SWE bit in FLMCR1
Wait 100 µs
Wait 100 µs
End of programming
Programming failure
Notes: * The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
Figure 7.3 Program/Program-Verify Flowchart
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Table 7.4
Reprogram Data Computation Table
Program Data
Verify Data
Reprogram Data
Comments
0
0
1
Programming completed
0
1
0
Reprogram bit
1
0
1
—
1
1
1
Remains in erased state
Table 7.5
Additional-Program Data Computation Table
Reprogram Data
Verify Data
Additional-Program
Data
Comments
0
0
0
Additional-program bit
0
1
1
No additional programming
1
0
1
No additional programming
1
1
1
No additional programming
Comments
Table 7.6
Programming Time
n
(Number of Writes)
Programming
Time
In Additional
Programming
1 to 6
30
10
7 to 1,000
200
—
Note: Time shown in µs.
7.4.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
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Section 7 ROM
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
7.4.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
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Section 7 ROM
Erase start
SWE bit ← 1
Wait 1 µs
n←1
Set EBR1
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 10
10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
*
n←n+1
Read verify data
No
Verify data + all 1s ?
Increment address
Yes
No
Last address of block ?
Yes
No
EV bit ← 0
EV bit ← 0
Wait 4 µs
Wait 4µs
All erase block erased ?
n ≤100 ?
Yes
Yes
No
Yes
SWE bit ← 0
SWE bit ← 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
Figure 7.4 Erase/Erase-Verify Flowchart
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Section 7 ROM
7.5
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
7.5.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby
mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2),
and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
7.5.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to
H'00, erase protection is set for all blocks.
7.5.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode
is aborted at the point at which the error occurred. Program mode or erase mode cannot be reRev.5.00 Nov. 02, 2005 Page 103 of 418
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Section 7 ROM
entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition
can be made to verify mode. Error protection can be cleared only by a reset.
7.6
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip 64-kbyte flash memory (FZTAT64V5).
7.7
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are halted.
Table 7.7 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the
external clock is being used.
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Section 7 ROM
Table 7.7
Flash Memory Operating States
Flash Memory Operating State
LSI Operating State
PDWND = 0 (Initial value)
PDWND = 1
Active mode
Normal operating mode
Normal operating mode
Subactive mode
Power-down mode
Normal operating mode
Sleep mode
Normal operating mode
Normal operating mode
Subsleep mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
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Section 8 RAM
Section 8 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification
RAM Size
RAM Address
Flash memory version
(F-ZTATTM version)
H8/3694F
2 kbytes
H'F780 to H'FF7F*
Mask-ROM version
H8/3694
1 kbyte
H'FB80 to H'FF7F
H8/3693
1 kbyte
H'FB80 to H'FF7F
H8/3692
512 kbytes
H'FD80 to H'FF7F
H8/3691
512 kbytes
H'FD80 to H'FF7F
H8/3690
512 kbytes
H'FD80 to H'FF7F
H8/3694N
2 kbytes
H'F780 to H'FF7F*
1 kbyte
H'FB80 to H'FF7F
EEPROM
stacked
version
Flash
memory
version
Mask-ROM
version
Note:
*
When the E7 or E8 is used, area H'F780 to H'FB7F must not be accessed.
RAM0300A_000120030300
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Section 8 RAM
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Section 9 I/O Ports
Section 9 I/O Ports
The group of this LSI has twenty-nine general I/O ports (twenty-seven general I/O ports in the
H8/3694N) and eight general input-only ports. Port 8 is a large current port, which can drive 20
mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input
port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules
or external interrupt input pins, and these functions can be switched depending on the register
settings. The registers for selecting these functions can be divided into two types: those included
in I/O ports and those included in each on-chip peripheral module. General I/O ports are
comprised of the port control register for controlling inputs/outputs and the port data register for
storing output data and can select inputs/outputs in bit units. For functions in each port, see
appendix B.1, I/O Port Block Diagrams. For the execution of bit manipulation instructions to the
port control register and port data register, see section 2.8.3, Bit Manipulation Instruction.
9.1
Port 1
Port 1 is a general I/O port also functioning as IRQ interrupt input pins, a timer A output pin, and
a timer V input pin. Figure 9.1 shows its pin configuration.
P17/IRQ3/TRGV
P16/IRQ2
P15/IRQ1
Port 1
P14/IRQ0
P12
P11
P10/TMOW
Figure 9.1 Port 1 Pin Configuration
Port 1 has the following registers.
•
•
•
•
Port mode register 1 (PMR1)
Port control register 1 (PCR1)
Port data register 1 (PDR1)
Port pull-up control register 1 (PUCR1)
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Section 9 I/O Ports
9.1.1
Port Mode Register 1 (PMR1)
PMR1 switches the functions of pins in port 1 and port 2.
Bit
Bit Name
Initial
Value
R/W
Description
7
IRQ3
0
R/W
P17/IRQ3/TRGV Pin Function Switch
This bit selects whether pin P17/IRQ3/TRGV is used as
P17 or as IRQ3/TRGV.
0: General I/O port
1: IRQ3/TRGV input pin
6
IRQ2
0
R/W
P16/IRQ2 Pin Function Switch
This bit selects whether pin P16/IRQ2 is used as P16 or
as IRQ2.
0: General I/O port
1: IRQ2 input pin
5
IRQ1
0
R/W
P15/IRQ1 Pin Function Switch
This bit selects whether pin P15/IRQ1 is used as P15 or
as IRQ1.
0: General I/O port
1: IRQ1 input pin
4
IRQ0
0
R/W
P14/IRQ0 Pin Function Switch
This bit selects whether pin P14/IRQ0 is used as P14 or
as IRQ0.
0: General I/O port
1: IRQ0 input pin
3, 2

All 1

Reserved
These bits are always read as 1.
1
TXD
0
R/W
P22/TXD Pin Function Switch
This bit selects whether pin P22/TXD is used as P22 or
as TXD.
0: General I/O port
1: TXD output pin
0
TMOW
0
R/W
P10/TMOW Pin Function Switch
This bit selects whether pin P10/TMOW is used as P10 or
as TMOW.
0: General I/O port
1: TMOW output pin
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Section 9 I/O Ports
9.1.2
Port Control Register 1 (PCR1)
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR17
0
W
6
PCR16
0
W
5
PCR15
0
W
When the corresponding pin is designated in PMR1 as a
general I/O pin, setting a PCR1 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4
PCR14
0
W
Bit 3 is a reserved bit.
3



2
PCR12
0
W
1
PCR11
0
W
0
PCR10
0
W
9.1.3
Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Bit
Bit Name
Initial
Value
R/W
Description
7
P17
0
R/W
PDR1 stores output data for port 1 pins.
6
P16
0
R/W
5
P15
0
R/W
4
P14
0
R/W
If PDR1 is read while PCR1 bits are set to 1, the value
stored in PDR1 are read. If PDR1 is read while PCR1 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR1.
3

1

Bit 3 is a reserved bit. This bit is always read as 1.
2
P12
0
R/W
1
P11
0
R/W
0
P10
0
R/W
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Section 9 I/O Ports
9.1.4
Port Pull-Up Control Register 1 (PUCR1)
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit
Bit Name
Initial
Value
R/W
Description
7
PUCR17
0
R/W
6
PUCR16
0
R/W
5
PUCR15
0
R/W
Only bits for which PCR1 is cleared are valid. The pull-up
MOS of P17 to P14 and P12 to P10 pins enter the onstate when these bits are set to 1, while they enter the
off-state when these bits are cleared to 0.
4
PUCR14
0
R/W
Bit 3 is a reserved bit. This bit is always read as 1.
3

1

2
PUCR12
0
R/W
1
PUCR11
0
R/W
0
PUCR10
0
R/W
9.1.5
Pin Functions
The correspondence between the register specification and the port functions is shown below.
P17/IRQ3/TRGV pin
Register
PMR1
Bit Name
IRQ3
Setting value 0
1
PCR1
PCR17
Pin Function
0
P17 input pin
1
P17 output pin
X
IRQ3 input/TRGV input pin
Legend: X: Don't care.
P16/IRQ2 pin
Register
PMR1
PCR1
Bit Name
IRQ2
PCR16
Pin Function
0
P16 input pin
1
P16 output pin
X
IRQ2 input pin
Setting value 0
1
Legend: X: Don't care.
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Section 9 I/O Ports
P15/IRQ1 pin
Register
PMR1
PCR1
Bit Name
IRQ1
PCR15
Pin Function
0
P15 input pin
Setting value 0
1
1
P15 output pin
X
IRQ1 input pin
Legend: X: Don't care.
P14/IRQ0 pin
Register
PMR1
PCR1
Bit Name
IRQ0
PCR14
Pin Function
0
P14 input pin
1
P14 output pin
X
IRQ0 input pin
Setting value 0
1
Legend: X: Don't care.
P12 pin
Register
PCR1
Bit Name
PCR12
Pin Function
0
P12 input pin
1
P12 output pin
Setting value
P11 pin
Register
PCR1
Bit Name
PCR11
Pin Function
Setting value
0
P11 input pin
1
P11 output pin
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Section 9 I/O Ports
P10/TMOW pin
Register
PMR1
PCR1
Bit Name
TMOW
PCR10
Pin Function
0
P10 input pin
1
P10 output pin
X
TMOW output pin
Setting value 0
1
Legend: X: Don't care.
9.2
Port 2
Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in
figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both
uses.
P22/TXD
Port 2
P21/RXD
P20/SCK3
Figure 9.2 Port 2 Pin Configuration
Port 2 has the following registers.
• Port control register 2 (PCR2)
• Port data register 2 (PDR2)
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Section 9 I/O Ports
9.2.1
Port Control Register 2 (PCR2)
PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2.
Bit
Bit Name
Initial
Value
R/W
7 to 3



Reserved
2
PCR22
0
W
1
PCR21
0
W
0
PCR20
0
W
When each of the port 2 pins P22 to P20 functions as an
general I/O port, setting a PCR2 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
9.2.2
Port Data Register 2 (PDR2)
Description
PDR2 is a general I/O port data register of port 2.
Bit
Bit Name
Initial
Value
R/W
7 to 3

All 1

Description
Reserved
These bits are always read as 1.
2
P22
0
R/W
PDR2 stores output data for port 2 pins.
1
P21
0
R/W
0
P20
0
R/W
If PDR2 is read while PCR2 bits are set to 1, the value
stored in PDR2 is read. If PDR2 is read while PCR2 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR2.
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Section 9 I/O Ports
9.2.3
Pin Functions
The correspondence between the register specification and the port functions is shown below.
P22/TXD pin
Register
PMR1
PCR2
Bit Name
TXD
PCR22
Pin Function
Setting
Value
0
0
P22 input pin
1
P22 output pin
X
TXD output pin
1
Legend: X: Don't care.
P21/RXD pin
Register
SCR3
PCR2
Bit Name
RE
PCR21
Pin Function
Setting
Value
0
0
P21 input pin
1
P21 output pin
X
RXD input pin
1
Legend: X: Don't care.
P20/SCK3 pin
Register
SCR3
Bit Name
CKE1
Setting Value
0
SMR
PCR2
CKE0
COM
PCR20
Pin Function
0
0
0
P20 input pin
1
P20 output pin
0
0
1
X
SCK3 output pin
0
1
X
X
SCK3 output pin
1
X
X
X
SCK3 input pin
Legend: X: Don't care.
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Section 9 I/O Ports
9.3
Port 5
Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input
pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting
of the I2C bus interface register has priority for functions of the pins P57/SCL and P56/SDA. Since
the output buffer for pins P56 and P57 has the NMOS push-pull structure, it differs from an output
buffer with the CMOS structure in the high-level output characteristics (see section 21, Electrical
Characteristics).
H8/3694
Port 5
H8/3694N
P57/SCL
SCL
P56/SDA
SDA
P55/WKP5/ADTRG
P55/WKP5/ADTRG
P54/WKP4
P54/WKP4
Port 5
P53/WKP3
P53/WKP3
P52/WKP2
P52/WKP2
P51/WKP1
P51/WKP1
P50/WKP0
P50/WKP0
Figure 9.3 Port 5 Pin Configuration
Port 5 has the following registers.
•
•
•
•
Port mode register 5 (PMR5)
Port control register 5 (PCR5)
Port data register 5 (PDR5)
Port pull-up control register 5 (PUCR5)
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Section 9 I/O Ports
9.3.1
Port Mode Register 5 (PMR5)
PMR5 switches the functions of pins in port 5.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0

Reserved
5
WKP5
0
R/W
P55/WKP5/ADTRG Pin Function Switch
These bits are always read as 0.
Selects whether pin P55/WKP5/ADTRG is used as P55
or as WKP5/ADTRG input.
0: General I/O port
1: WKP5/ADTRG input pin
4
WKP4
0
R/W
P54/WKP4 Pin Function Switch
Selects whether pin P54/WKP4 is used as P54 or as
WKP4.
0: General I/O port
1: WKP4 input pin
3
WKP3
0
R/W
P53/WKP3 Pin Function Switch
Selects whether pin P53/WKP3 is used as P53 or as
WKP3.
0: General I/O port
1: WKP3 input pin
2
WKP2
0
R/W
P52/WKP2 Pin Function Switch
Selects whether pin P52/WKP2 is used as P52 or as
WKP2.
0: General I/O port
1: WKP2 input pin
1
WKP1
0
R/W
P51/WKP1 Pin Function Switch
Selects whether pin P51/WKP1 is used as P51 or as
WKP1.
0: General I/O port
1: WKP1 input pin
0
WKP0
0
R/W
P50/WKP0 Pin Function Switch
Selects whether pin P50/WKP0 is used as P50 or as
WKP0.
0: General I/O port
1: WKP0 input pin
Rev.5.00 Nov. 02, 2005 Page 118 of 418
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Section 9 I/O Ports
9.3.2
Port Control Register 5 (PCR5)
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR57
0
W
6
PCR56
0
W
5
PCR55
0
W
When each of the port 5 pins P57 to P50 functions as an
general I/O port, setting a PCR5 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4
PCR54
0
W
3
PCR53
0
W
2
PCR52
0
W
1
PCR51
0
W
0
PCR50
0
W
9.3.3
Port Data Register 5 (PDR5)
Note: The PCR57 and PCR56 bits should not be set to 1
in the H8/3694N.
PDR5 is a general I/O port data register of port 5.
Bit
Bit Name
Initial
Value
R/W
Description
7
P57
0
R/W
Stores output data for port 5 pins.
6
P56
0
R/W
5
P55
0
R/W
4
P54
0
R/W
If PDR5 is read while PCR5 bits are set to 1, the value
stored in PDR5 are read. If PDR5 is read while PCR5 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR5.
3
P53
0
R/W
2
P52
0
R/W
1
P51
0
R/W
0
P50
0
R/W
Note: The P57 and P56 bits should not be set to 1 in the
H8/3694N.
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Section 9 I/O Ports
9.3.4
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0

Reserved
These bits are always read as 0.
5
PUCR55
0
R/W
4
PUCR54
0
R/W
3
PUCR53
0
R/W
2
PUCR52
0
R/W
1
PUCR51
0
R/W
0
PUCR50
0
R/W
9.3.5
Pin Functions
Only bits for which PCR5 is cleared are valid. The pull-up
MOS of the corresponding pins enter the on-state when
these bits are set to 1, while they enter the off-state when
these bits are cleared to 0.
The correspondence between the register specification and the port functions is shown below.
P57/SCL pin
Register
ICCR1
PCR5
Bit Name
ICE
PCR57
Pin Function
Setting
Value
0
0
P57 input pin
1
1
P57 output pin
X
SCL I/O pin
Legend: X: Don't care.
SCL performs the NMOS open-drain output, that enables a direct bus drive.
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Section 9 I/O Ports
P56/SDA pin
Register
ICCR1
PCR5
Bit Name
ICE
PCR56
Pin Function
Setting
Value
0
0
P56 input pin
1
P56 output pin
X
SDA I/O pin
1
Legend: X: Don't care.
SDA performs the NMOS open-drain output, that enables a direct bus drive.
P55/WKP5/ADTRG pin
Register
PMR5
PCR5
Bit Name
WKP5
PCR55
Pin Function
Setting
Value
0
0
P55 input pin
1
P55 output pin
X
WKP5/ADTRG input pin
1
Legend: X: Don't care.
P54/WKP4 pin
Register
PMR5
PCR5
Bit Name
WKP4
PCR54
Pin Function
Setting
Value
0
0
P54 input pin
1
P54 output pin
X
WKP4 input pin
1
Legend: X: Don't care.
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Section 9 I/O Ports
P53/WKP3 pin
Register
PMR5
PCR5
Bit Name
WKP3
PCR53
Pin Function
Setting
Value
0
0
P53 input pin
1
P53 output pin
X
WKP3 input pin
1
Legend: X: Don't care.
P52/WKP2 pin
Register
PMR5
PCR5
Bit Name
WKP2
PCR52
Pin Function
Setting
Value
0
0
P52 input pin
1
P52 output pin
X
WKP2 input pin
1
Legend: X: Don't care.
P51/WKP1 pin
Register
PMR5
PCR5
Bit Name
WKP1
PCR51
Pin Function
Setting
Value
0
0
P51 input pin
1
P51 output pin
X
WKP1 input pin
1
Legend: X: Don't care.
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Section 9 I/O Ports
P50/WKP0 pin
Register
PMR5
PCR5
Bit Name
WKP0
PCR50
Pin Function
Setting
Value
0
0
P50 input pin
1
P50 output pin
X
WKP0 input pin
1
Legend: X: Don't care.
9.4
Port 7
Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown
in figure 9.4. The register setting of TCSRV in timer V has priority for functions of pin
P76/TMOV. The pins, P75/TMCIV and P74/TMRIV, are also functioning as timer V input ports
that are connected to the timer V regardless of the register setting of port 7.
P76/TMOV
Port 7
P75/TMCIV
P74/TMRIV
Figure 9.4 Port 7 Pin Configuration
Port 7 has the following registers.
• Port control register 7 (PCR7)
• Port data register 7 (PDR7)
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Section 9 I/O Ports
9.4.1
Port Control Register 7 (PCR7)
PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.
Bit
Bit Name
Initial
Value
R/W
Description
7



Reserved
6
PCR76
0
W
5
PCR75
0
W
4
PCR74
0
W
Setting a PCR7 bit to 1 makes the corresponding pin an
output port, while clearing the bit to 0 makes the pin an
input port. Note that the TCSRV setting of the timer V has
priority for deciding input/output direction of the
P76/TMOV pin.
3 to 0



9.4.2
Port Data Register 7 (PDR7)
Reserved
PDR7 is a general I/O port data register of port 7.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
This bit is always read as 1.
6
P76
0
R/W
PDR7 stores output data for port 7 pins.
5
P75
0
R/W
4
P74
0
R/W
If PDR7 is read while PCR7 bits are set to 1, the value
stored in PDR7 is read. If PDR7 is read while PCR7 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR7.
3 to 0

All 1

Reserved
These bits are always read as 1.
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Section 9 I/O Ports
9.4.3
Pin Functions
The correspondence between the register specification and the port functions is shown below.
P76/TMOV pin
Register
TCSRV
Bit Name
OS3 to OS0 PCR76
Pin Function
Setting
Value
0000
0
P76 input pin
1
P76 output pin
X
TMOV output pin
Other than
the above
values
PCR7
Legend: X: Don't care.
P75/TMCIV pin
Register
PCR7
Bit Name
PCR75
Pin Function
Setting
Value
0
P75 input/TMCIV input pin
1
P75 output/TMCIV input pin
P74/TMRIV pin
Register
PCR7
Bit Name
PCR74
Pin Function
Setting
Value
0
P74 input/TMRIV input pin
1
P74 output/TMRIV input pin
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Section 9 I/O Ports
9.5
Port 8
Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown
in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD,
P83/FTIOC, P82/FTIOB, and P81/FTIOA. P80/FTCI also functions as a timer W input port that is
connected to the timer W regardless of the register setting of port 8.
P87
P86
P85
Port 8
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
Figure 9.5 Port 8 Pin Configuration
Port 8 has the following registers.
• Port control register 8 (PCR8)
• Port data register 8 (PDR8)
9.5.1
Port Control Register 8 (PCR8)
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR87
0
W
6
PCR86
0
W
5
PCR85
0
W
When each of the port 8 pins P87 to P80 functions as an
general I/O port, setting a PCR8 bit to 1 makes the
corresponding pin an output port, while clearing the bit to
0 makes the pin an input port.
4
PCR84
0
W
3
PCR83
0
W
2
PCR82
0
W
1
PCR81
0
W
0
PCR80
0
W
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Section 9 I/O Ports
9.5.2
Port Data Register 8 (PDR8)
PDR8 is a general I/O port data register of port 8.
Bit
Bit Name
Initial
Value
R/W
Description
7
P87
0
R/W
PDR8 stores output data for port 8 pins.
6
P86
0
R/W
5
P85
0
R/W
4
P84
0
R/W
If PDR8 is read while PCR8 bits are set to 1, the value
stored in PDR8 is read. If PDR8 is read while PCR8 bits
are cleared to 0, the pin states are read regardless of the
value stored in PDR8.
3
P83
0
R/W
2
P82
0
R/W
1
P81
0
R/W
0
P80
0
R/W
9.5.3
Pin Functions
The correspondence between the register specification and the port functions is shown below.
P87 pin
Register
PCR8
Bit Name
PCR87
Pin Function
Setting
Value
0
P87 input pin
1
P87 output pin
P86 pin
Register
PCR8
Bit Name
PCR86
Pin Function
Setting
Value
0
P86 input pin
1
P86 output pin
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Section 9 I/O Ports
P85 pin
Register
PCR8
Bit Name
PCR85
Pin Function
Setting
Value
0
P85 input pin
1
P85 output pin
P84/FTIOD pin
Register
TIOR1
PCR8
Bit Name
IOD2
IOD1
IOD0
PCR84
Pin Function
Setting
Value
0
0
0
0
P84 input/FTIOD input pin
1
P84 output/FTIOD input pin
X
FTIOD output pin
0
0
1
0
1
X
X
FTIOD output pin
1
X
X
0
P84 input/FTIOD input pin
1
P84 output/FTIOD input pin
Legend: X: Don't care.
P83/FTIOC pin
Register
TIOR1
PCR8
Bit Name
IOC2
IOC1
IOC0
PCR83
Pin Function
Setting
Value
0
0
0
0
P83 input/FTIOC input pin
1
P83 output/FTIOC input pin
0
0
1
X
FTIOC output pin
0
1
X
X
FTIOC output pin
1
X
X
0
P83 input/FTIOC input pin
1
P83 output/FTIOC input pin
Legend: X: Don't care.
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Section 9 I/O Ports
P82/FTIOB pin
Register
TIOR0
PCR8
Bit Name
IOB2
IOB1
IOB0
PCR82
Pin Function
Setting
Value
0
0
0
0
P82 input/FTIOB input pin
1
P82 output/FTIOB input pin
0
0
1
X
FTIOB output pin
0
1
X
X
FTIOB output pin
1
X
X
0
P82 input/FTIOB input pin
1
P82 output/FTIOB input pin
Legend: X: Don't care.
P81/FTIOA pin
Register
TIOR0
PCR8
Bit Name
IOA2
IOA1
IOA0
PCR81
Pin Function
Setting
Value
0
0
0
0
P81 input/FTIOA input pin
1
P81 output/FTIOA input pin
0
0
1
X
FTIOA output pin
0
1
X
X
FTIOA output pin
1
X
X
0
P81 input/FTIOA input pin
1
P81 output/FTIOA input pin
Legend: X: Don't care.
P80/FTCI pin
Register
PCR8
Bit Name
PCR80
Pin Function
Setting
Value
0
P80 input/FTCI input pin
1
P80 output/FTCI input pin
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Section 9 I/O Ports
9.6
Port B
Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port
B is shown in figure 9.6.
PB7/AN7
PB6/AN6
PB5/AN5
Port B
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 9.6 Port B Pin Configuration
Port B has the following register.
• Port data register B (PDRB)
9.6.1
Port Data Register B (PDRB)
PDRB is a general input-only port data register of port B.
Bit
Bit Name
Initial
Value
R/W
Description
7
PB7

R
6
PB6

R
The input value of each pin is read by reading this
register.
5
PB5

R
4
PB4

R
3
PB3

R
2
PB2

R
1
PB1

R
0
PB0

R
Rev.5.00 Nov. 02, 2005 Page 130 of 418
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However, if a port B pin is designated as an analog input
channel by ADCSR in A/D converter, 0 is read.
Section 10 Timer A
Section 10 Timer A
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1
shows a block diagram of timer A.
10.1
Features
• Timer A can be used as an interval timer or a clock time base.
• An interrupt is requested when the counter overflows.
• Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or
4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4.
Interval Timer
• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ8)
Clock Time Base
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal oscillator).
TIM08A0A_000020020200
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Section 10 Timer A
1/4
PSW
φW/4
φW/32
φW/16
φW/8
φW/4
TMA
Internal data bus
φW
φW/128
φ
÷256*
÷64*
φ/8192, φ/4096,
φ/2048, φ/512,
φ/256, φ/128,
φ/32, φ/8
÷8*
φW/32
φW/16
φW/8
φW/4
÷128*
TCA
TMOW
PSS
IRRTA
[Legend]
TMA: Timer mode register A
TCA:
Timer counter A
IRRTA: Timer A overflow interrupt request flag
PSW: Prescaler W
PSS:
Prescaler S
Note: * Can be selected only when the prescaler W output (φW/128) is used as the TCA input clock.
Figure 10.1 Block Diagram of Timer A
10.2
Input/Output Pins
Table 10.1 shows the timer A input/output pin.
Table 10.1 Pin Configuration
Name
Abbreviation I/O
Function
Clock output
TMOW
Output of waveform generated by timer A output
circuit
Output
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Section 10 Timer A
10.3
Register Descriptions
Timer A has the following registers.
• Timer mode register A (TMA)
• Timer counter A (TCA)
10.3.1
Timer Mode Register A (TMA)
TMA selects the operating mode, the divided clock output, and the input clock.
Bit
Bit Name
Initial
Value
R/W
Description
7
TMA7
0
R/W
Clock Output Select 7 to 5
6
TMA6
0
R/W
These bits select the clock output at the TMOW pin.
5
TMA5
0
R/W
000: φ/32
001: φ/16
010: φ/8
011: φ/4
100: φw/32
101: φw/16
110: φw/8
111: φw/4
For details on clock outputs, see section 10.4.3, Clock
Output.
4

1

Reserved
This bit is always read as 1.
3
TMA3
0
R/W
Internal Clock Select 3
This bit selects the operating mode of the timer A.
0: Functions as an interval timer to count the outputs of
prescaler S.
1: Functions as a clock-time base to count the outputs of
prescaler W.
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Section 10 Timer A
Bit
Bit Name
Initial
Value
R/W
Description
2
TMA2
0
R/W
Internal Clock Select 2 to 0
1
TMA1
0
R/W
These bits select the clock input to TCA when TMA3 = 0.
0
TMA0
0
R/W
000: φ/8192
001: φ/4096
010: φ/2048
011: φ/512
100: φ/256
101: φ/128
110: φ/32
111: φ/8
These bits select the overflow period when TMA3 = 1
(when a 32.768 kHz crystal oscillator with is used as φW).
000: 1s
001: 0.5 s
010: 0.25 s
011: 0.03125 s
1XX: Both PSW and TCA are reset
Legend: X: Don't care.
10.3.2
Timer Counter A (TCA)
TCA is an 8-bit readable up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in TMA. TCA values can be
read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the
IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3
and TMA2 in TMA to B’11. TCA is initialized to H'00.
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Section 10 Timer A
10.4
Operation
10.4.1
Interval Timer Operation
When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of timer A
resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to
TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt Flag Register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested. At overflow, TCA returns to H'00 and
starts counting up again. In this mode timer A functions as an interval timer that generates an
overflow output at intervals of 256 input clock pulses.
10.4.2
Clock Time Base Operation
When bit TMA3 in TMA is set to 1, timer A functions as a clock-timer base by counting clock
signals output by prescaler W. When a clock signal is input after the TCA counter value has
become H'FF, timer A overflows and IRRTA in IRR1 is set to 1. At that time, an interrupt request
is generated to the CPU if IENTA in the interrupt enable register 1 (IENR1) is 1. The overflow
period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available.
In clock time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W
to H'00.
10.4.3
Clock Output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin
TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in
TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A
32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and
subactive mode.
10.5
Usage Note
When the clock time base function is selected as the internal clock of TCA in active mode or sleep
mode, the internal clock is not synchronous with the system clock, so it is synchronized by a
synchronizing circuit. This may result in a maximum error of 1/φ (s) in the count cycle.
Rev.5.00 Nov. 02, 2005 Page 135 of 418
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Section 10 Timer A
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Section 11 Timer V
Section 11 Timer V
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or
output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at
the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary
delay from the trigger input. Figure 11.1 shows a block diagram of timer V.
11.1
Features
• Choice of seven clock signals is available.
Choice of six internal clock sources (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) or an external clock.
• Counter can be cleared by compare match A or B, or by an external reset signal. If the count
stop function is selected, the counter can be halted when cleared.
• Timer output is controlled by two independent compare match signals, enabling pulse output
with an arbitrary duty cycle, PWM output, and other applications.
• Three interrupt sources: compare match A, compare match B, timer overflow
• Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or
both edges of the TRGV input can be selected.
TIM08V0A_000120030300
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Section 11 Timer V
TCRV1
TCORB
Trigger
control
TRGV
Comparator
Clock select
TCNTV
Internal data bus
TMCIV
Comparator
φ
PSS
TCORA
Clear
control
TMRIV
TCRV0
Interrupt
request
control
Output
control
TMOV
[Legend]
TCORA:
TCORB:
TCNTV:
TCSRV:
TCRV0:
TCRV1:
PSS:
CMIA:
CMIB:
OVI:
TCSRV
CMIA
CMIB
OVI
Time constant register A
Time constant register B
Timer counter V
Timer control/status register V
Timer control register V0
Timer control register V1
Prescaler S
Compare-match interrupt A
Compare-match interrupt B
Overflow interupt
Figure 11.1 Block Diagram of Timer V
11.2
Input/Output Pins
Table 11.1 shows the timer V pin configuration.
Table 11.1 Pin Configuration
Name
Abbreviation I/O
Function
Timer V output
TMOV
Output
Timer V waveform output
Timer V clock input
TMCIV
Input
Clock input to TCNTV
Timer V reset input
TMRIV
Input
External input to reset TCNTV
Trigger input
TRGV
Input
Trigger input to initiate counting
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Section 11 Timer V
11.3
Register Descriptions
Time V has the following registers.
•
•
•
•
•
•
Timer counter V (TCNTV)
Timer constant register A (TCORA)
Timer constant register B (TCORB)
Timer control register V0 (TCRV0)
Timer control/status register V (TCSRV)
Timer control register V1 (TCRV1)
11.3.1
Timer Counter V (TCNTV)
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer
control register V0 (TCRV0). The TCNTV value can be read and written by the CPU at any time.
TCNTV can be cleared by an external reset input signal, or by compare match A or B. The
clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.
When TCNTV overflows, OVF is set to 1 in timer control/status register V (TCSRV).
TCNTV is initialized to H'00.
11.3.2
Time Constant Registers A and B (TCORA, TCORB)
TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
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Section 11 Timer V
11.3.3
Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Bit
Bit Name
Initial
Value
R/W
Description
7
CMIEB
0
R/W
Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
6
CMIEA
0
R/W
Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the CMFA
bit in TCSRV is enabled.
5
OVIE
0
R/W
Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
bit in TCSRV is enabled.
4
CCLR1
0
R/W
Counter Clear 1 and 0
3
CCLR0
0
R/W
These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on TRGE
in TCRV1.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select clock signals to input to TCNTV and the
counting condition in combination with ICKS0 in TCRV1.
Refer to table 11.2.
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Section 11 Timer V
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
TCRV0
TCRV1
Bit 2
Bit 1
Bit 0
Bit 0
CKS2
CKS1
CKS0
ICKS0
Description
0
0
0

Clock input prohibited
1
0
Internal clock: counts on φ/4, falling edge
1
Internal clock: counts on φ/8, falling edge
0
Internal clock: counts on φ/16, falling edge
1
Internal clock: counts on φ/32, falling edge
0
Internal clock: counts on φ/64, falling edge
1
Internal clock: counts on φ/128, falling edge
0

Clock input prohibited
1

External clock: counts on rising edge
0

External clock: counts on falling edge
1

External clock: counts on rising and falling edge
1
0
1
1
0
1
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Section 11 Timer V
11.3.4
Timer Control/Status Register V (TCSRV)
TCSRV indicates the status flag and controls outputs by using a compare match.
Bit
Bit Name
Initial
Value
R/W
Description
7
CMFB
0
R/W
Compare Match Flag B
Setting condition:
When the TCNTV value matches the TCORB value
Clearing condition:
After reading CMFB = 1, cleared by writing 0 to CMFB
6
CMFA
0
R/W
Compare Match Flag A
Setting condition:
When the TCNTV value matches the TCORA value
Clearing condition:
After reading CMFA = 1, cleared by writing 0 to CMFA
5
OVF
0
R/W
Timer Overflow Flag
Setting condition:
When TCNTV overflows from H'FF to H'00
Clearing condition:
After reading OVF = 1, cleared by writing 0 to OVF
4

1

3
OS3
0
R/W
Output Select 3 and 2
2
OS2
0
R/W
These bits select an output method for the TMOV pin by
the compare match of TCORB and TCNTV.
Reserved
This bit is always read as 1.
00: No change
01: 0 output
10: 1 output
11: Output toggles
1
OS1
0
R/W
Output Select 1 and 0
0
OS0
0
R/W
These bits select an output method for the TMOV pin by
the compare match of TCORA and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
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Section 11 Timer V
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
11.3.5
Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to
TCNTV.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 1

Reserved
These bits are always read as 1.
4
TVEG1
0
R/W
TRGV Input Edge Select
3
TVEG0
0
R/W
These bits select the TRGV input edge.
00: TRGV trigger input is prohibited
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
2
TRGE
0
R/W
TCNT starts counting up by the input of the edge which is
selected by TVEG1 and TVEG0.
0: Disables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
1: Enables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
1

1

Reserved
This bit is always read as 1.
0
ICKS0
0
R/W
Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
Refer to table 11.2.
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Section 11 Timer V
11.4
Operation
11.4.1
Timer V Operation
1. According to table 11.2, six internal/external clock signals output by prescaler S can be
selected as the timer V operating clock signals. When the operating clock signal is selected,
TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal
selected, and figure 11.3 shows the count timing with both edges of an external clock signal
selected.
2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0
will be set. The timing at this time is shown in figure 11.4. An interrupt request is sent to the
CPU when OVIE in TCRV0 is 1.
3. TCNTV is constantly compared with TCORA and TCORB. Compare match flag A or B
(CMFA or CMFB) is set to 1 when TCNTV matches TCORA or TCORB, respectively. The
compare-match signal is generated in the last state in which the values match. Figure 11.5
shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in
TCRV0 is 1.
4. When a compare match A or B is generated, the TMOV responds with the output value
selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is
toggled by compare match A.
5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding
compare match. Figure 11.7 shows the timing.
6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the
input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary.
Figure 11.8 shows the timing.
7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is
halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by
TVEG1 or TVEG0 in TCRV1 is input from the TGRV pin.
Rev.5.00 Nov. 02, 2005 Page 144 of 418
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Section 11 Timer V
φ
Internal clock
TCNTV input
clock
TCNTV
N–1
N
N+1
Figure 11.2 Increment Timing with Internal Clock
φ
TMCIV
(External clock
input pin)
TCNTV input
clock
TCNTV
N–1
N
N+1
Figure 11.3 Increment Timing with External Clock
φ
TCNTV
H'FF
H'00
Overflow signal
OVF
Figure 11.4 OVF Set Timing
Rev.5.00 Nov. 02, 2005 Page 145 of 418
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Section 11 Timer V
φ
TCNTV
N
TCORA or
TCORB
N
N+1
Compare match
signal
CMFA or
CMFB
Figure 11.5 CMFA and CMFB Set Timing
φ
Compare match
A signal
Timer V output
pin
Figure 11.6 TMOV Output Timing
φ
Compare match
A signal
TCNTV
N
H'00
Figure 11.7 Clear Timing by Compare Match
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Section 11 Timer V
φ
TMRIV(External
counter reset
input pin )
TCNTV reset
signal
TCNTV
N–1
N
H'00
Figure 11.8 Clear Timing by TMRIV Input
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Section 11 Timer V
11.5
Timer V Application Examples
11.5.1
Pulse Output with Arbitrary Duty Cycle
Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
TCNTV value
H'FF
Counter cleared
TCORA
TCORB
H'00
Time
TMOV
Figure 11.9 Pulse Output Example
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Section 11 Timer V
11.5.2
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary
delay from the TRGV input, as shown in figure 11.10. To set up this output:
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORB.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits TVEG1 and TVEG0 in TCRV1 and set TRGE to select the falling edge of the TRGV
input.
4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
5. After these settings, a pulse waveform will be output without further software intervention,
with a delay determined by TCORA from the TRGV input, and a pulse width determined by
(TCORB – TCORA).
TCNTV value
H'FF
Counter cleared
TCORB
TCORA
H'00
Time
TRGV
TMOV
Compare match A
Compare match B
clears TCNTV and
halts count-up
Compare match A
Compare match B
clears TCNTV and
halts count-up
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
Rev.5.00 Nov. 02, 2005 Page 149 of 418
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Section 11 Timer V
11.6
Usage Notes
The following types of contention or operation can occur in timer V operation.
1.
2.
3.
4.
Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
11.12 shows the timing.
If compare matches A and B occur simultaneously, any conflict between the output selections
for compare match A and compare match B is resolved by the following priority: toggle
output > output 1 > output 0.
Depending on the timing, TCNTV may be incremented by a switch between different internal
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown
in figure 11.3 the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a
switch between internal and external clocks.
TCNTV write cycle by CPU
T2
T1
T3
φ
Address
TCNTV address
Internal write signal
Counter clear signal
TCNTV
N
H'00
Figure 11.11 Contention between TCNTV Write and Clear
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Section 11 Timer V
TCORA write cycle by CPU
T2
T1
T3
φ
Address
TCORA address
Internal write signal
TCNTV
N
N+1
TCORA
N
M
TCORA write data
Compare match signal
Inhibited
Figure 11.12 Contention between TCORA Write and Compare Match
Clock before
switching
Clock after
switching
Count clock
TCNTV
N
N+1
N+2
Write to CKS1 and CKS0
Figure 11.13 Internal Clock Switching and TCNTV Operation
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Section 11 Timer V
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Section 12 Timer W
Section 12 Timer W
The timer W has a 16-bit timer having output compare and input capture functions. The timer W
can count external events and output pulses with an arbitrary duty cycle by compare match
between the timer counter and four general registers. Thus, it can be applied to various systems.
12.1
Features
• Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an
external clock (external events can be counted)
• Capability to process up to four pulse outputs or four pulse inputs
• Four general registers:
 Independently assignable output compare or input capture functions
 Usable as two pairs of registers; one register of each pair operates as a buffer for the output
compare or input capture register
• Four selectable operating modes :
 Waveform output by compare match
Selection of 0 output, 1 output, or toggle output
 Input capture function
Rising edge, falling edge, or both edges
 Counter clearing function
Counters can be cleared by compare match
 PWM mode
Up to three-phase PWM output can be provided with desired duty ratio.
• Any initial timer output value can be set
• Five interrupt sources
Four compare match/input capture interrupts and an overflow interrupt.
Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer
W.
TIM08W0A_000020020200
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Section 12 Timer W
Table 12.1 Timer W Functions
Input/Output Pins
Item
Counter
FTIOA
FTIOB
FTIOC
FTIOD
Count clock
Internal clocks: φ, φ/2, φ/4, φ/8
External clock: FTCI
General registers
(output compare/input
capture registers)
Period
GRA
specified in
GRA
GRB
GRC (buffer
register for
GRA in
buffer mode)
GRD (buffer
register for
GRB in
buffer mode)
Counter clearing function
GRA
compare
match
GRA
compare
match
—
—
—
Initial output value
setting function
—
Yes
Yes
Yes
Yes
Buffer function
—
Yes
Yes
—
—
Compare
0
—
Yes
Yes
Yes
Yes
match output
1
—
Yes
Yes
Yes
Yes
Toggle
—
Yes
Yes
Yes
Yes
Input capture function
—
Yes
Yes
Yes
Yes
PWM mode
—
—
Yes
Yes
Yes
Interrupt sources
Overflow
Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
Rev.5.00 Nov. 02, 2005 Page 154 of 418
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Section 12 Timer W
Internal clock: φ
φ/2
φ/4
φ/8
External clock: FTCI
FTIOA
Clock
selector
FTIOB
FTIOC
Control logic
FTIOD
Comparator
TIOR
TSRW
TIERW
TCRW
TMRW
GRD
GRC
GRB
Bus interface
[Legend]
TMRW:
TCRW:
TIERW:
TSRW:
TIOR:
TCNT:
GRA:
GRB:
GRC:
GRD:
IRRTW:
GRA
TCNT
IRRTW
Internal
data bus
Timer mode register W (8 bits)
Timer control register W (8 bits)
Timer interrupt enable register W (8 bits)
Timer status register W (8 bits)
Timer I/O control register (8 bits)
Timer counter (16 bits)
General register A (input capture/output compare register: 16 bits)
General register B (input capture/output compare register: 16 bits)
General register C (input capture/output compare register: 16 bits)
General register D (input capture/output compare register: 16 bits)
Timer W interrupt request
Figure 12.1 Timer W Block Diagram
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Section 12 Timer W
12.2
Input/Output Pins
Table 12.2 summarizes the timer W pins.
Table 12.2 Pin Configuration
Name
Abbreviation
Input/Output
Function
External clock input
FTCI
Input
External clock input pin
Input capture/output
compare A
FTIOA
Input/output
Output pin for GRA output compare
or input pin for GRA input capture
Input capture/output
compare B
FTIOB
Input/output
Output pin for GRB output compare,
input pin for GRB input capture, or
PWM output pin in PWM mode
Input capture/output
compare C
FTIOC
Input/output
Output pin for GRC output compare,
input pin for GRC input capture, or
PWM output pin in PWM mode
Input capture/output
compare D
FTIOD
Input/output
Output pin for GRD output compare,
input pin for GRD input capture, or
PWM output pin in PWM mode
12.3
Register Descriptions
The timer W has the following registers.
•
•
•
•
•
•
•
•
•
•
•
Timer mode register W (TMRW)
Timer control register W (TCRW)
Timer interrupt enable register W (TIERW)
Timer status register W (TSRW)
Timer I/O control register 0 (TIOR0)
Timer I/O control register 1 (TIOR1)
Timer counter (TCNT)
General register A (GRA)
General register B (GRB)
General register C (GRC)
General register D (GRD)
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Section 12 Timer W
12.3.1
Timer Mode Register W (TMRW)
TMRW selects the general register functions and the timer output mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
CTS
0
R/W
Counter Start
The counter operation is halted when this bit is 0, while it
can be performed when this bit is 1.
6

1

Reserved
This bit is always read as 1.
5
BUFEB
0
R/W
Buffer Operation B
Selects the GRD function.
0: GRD operates as an input capture/output compare
register
1: GRD operates as the buffer register for GRB
4
BUFEA
0
R/W
Buffer Operation A
Selects the GRC function.
0: GRC operates as an input capture/output compare
register
1: GRC operates as the buffer register for GRA
3

1

Reserved
This bit is always read as 1.
2
PWMD
0
R/W
PWM Mode D
Selects the output mode of the FTIOD pin.
0: FTIOD operates normally (output compare output)
1: PWM output
1
PWMC
0
R/W
PWM Mode C
Selects the output mode of the FTIOC pin.
0: FTIOC operates normally (output compare output)
1: PWM output
0
PWMB
0
R/W
PWM Mode B
Selects the output mode of the FTIOB pin.
0: FTIOB operates normally (output compare output)
1: PWM output
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Section 12 Timer W
12.3.2
Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer
output levels.
Bit
Bit Name
Initial
Value
R/W
Description
7
CCLR
0
R/W
Counter Clear
The TCNT value is cleared by compare match A when
this bit is 1. When it is 0, TCNT operates as a freerunning counter.
6
CKS2
0
R/W
Clock Select 2 to 0
5
CKS1
0
R/W
Select the TCNT clock source.
4
CKS0
0
R/W
000: Internal clock: counts on φ
001: Internal clock: counts on φ/2
010: Internal clock: counts on φ/4
011: Internal clock: counts on φ/8
1XX: Counts on rising edges of the external event (FTCI)
When the internal clock source (φ) is selected, subclock
sources are counted in subactive and subsleep modes.
3
TOD
0
R/W
Timer Output Level Setting D
Sets the output value of the FTIOD pin until the first
compare match D is generated.
0: Output value is 0*
1: Output value is 1*
2
TOC
0
R/W
Timer Output Level Setting C
Sets the output value of the FTIOC pin until the first
compare match C is generated.
0: Output value is 0*
1: Output value is 1*
1
TOB
0
R/W
Timer Output Level Setting B
Sets the output value of the FTIOB pin until the first
compare match B is generated.
0: Output value is 0*
1: Output value is 1*
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Section 12 Timer W
Bit
Bit Name
Initial
Value
R/W
Description
0
TOA
0
R/W
Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
Legend:
Note: *
12.3.3
X: Don't care.
The change of the setting is immediately reflected in the output value.
Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit
Bit Name
Initial
Value
R/W
Description
7
OVIE
0
R/W
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by OVF
flag in TSRW is enabled.
6 to 4

All 1

Reserved
These bits are always read as 1.
3
IMIED
0
R/W
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
2
IMIEC
0
R/W
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
1
IMIEB
0
R/W
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
0
IMIEA
0
R/W
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
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Section 12 Timer W
12.3.4
Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit
Bit Name
Initial
Value
R/W
Description
7
OVF
0
R/W
Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
6 to 4

All 1

Reserved
These bits are always read as 1.
3
IMFD
0
R/W
Input Capture/Compare Match Flag D
[Setting conditions]
•
TCNT = GRD when GRD functions as an output
compare register
•
The TCNT value is transferred to GRD by an input
capture signal when GRD functions as an input
capture register
[Clearing condition]
Read IMFD when IMFD = 1, then write 0 in IMFD
2
IMFC
0
R/W
Input Capture/Compare Match Flag C
[Setting conditions]
•
TCNT = GRC when GRC functions as an output
compare register
•
The TCNT value is transferred to GRC by an input
capture signal when GRC functions as an input
capture register
[Clearing condition]
Read IMFC when IMFC = 1, then write 0 in IMFC
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Section 12 Timer W
Bit
Bit Name
Initial
Value
R/W
Description
1
IMFB
0
R/W
Input Capture/Compare Match Flag B
[Setting conditions]
•
TCNT = GRB when GRB functions as an output
compare register
•
The TCNT value is transferred to GRB by an input
capture signal when GRB functions as an input
capture register
[Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
0
IMFA
0
R/W
Input Capture/Compare Match Flag A
[Setting conditions]
•
TCNT = GRA when GRA functions as an output
compare register
•
The TCNT value is transferred to GRA by an input
capture signal when GRA functions as an input
capture register
[Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
12.3.5
Timer I/O Control Register 0 (TIOR0)
TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and
FTIOB pins.
Bit
Bit Name
Initial
Value
R/W
7

1

Description
Reserved
This bit is always read as 1.
6
IOB2
0
R/W
I/O Control B2
Selects the GRB function.
0: GRB functions as an output compare register
1: GRB functions as an input capture register
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Section 12 Timer W
Bit
Bit Name
Initial
Value
R/W
Description
5
IOB1
0
R/W
I/O Control B1 and B0
4
IOB0
0
R/W
When IOB2 = 0,
00: No output at compare match
01: 0 output to the FTIOB pin at GRB compare match
10: 1 output to the FTIOB pin at GRB compare match
11: Output toggles to the FTIOB pin at GRB compare
match
When IOB2 = 1,
00: Input capture at rising edge at the FTIOB pin
01: Input capture at falling edge at the FTIOB pin
1X: Input capture at rising and falling edges of the FTIOB
pin
3

1

Reserved
This bit is always read as 1.
2
IOA2
0
R/W
I/O Control A2
Selects the GRA function.
0: GRA functions as an output compare register
1: GRA functions as an input capture register
1
IOA1
0
R/W
I/O Control A1 and A0
0
IOA0
0
R/W
When IOA2 = 0,
00: No output at compare match
01: 0 output to the FTIOA pin at GRA compare match
10: 1 output to the FTIOA pin at GRA compare match
11: Output toggles to the FTIOA pin at GRA compare
match
When IOA2 = 1,
00: Input capture at rising edge of the FTIOA pin
01: Input capture at falling edge of the FTIOA pin
1X: Input capture at rising and falling edges of the FTIOA
pin
Legend: X: Don't care.
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Section 12 Timer W
12.3.6
Timer I/O Control Register 1 (TIOR1)
TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and
FTIOD pins.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
6
IOD2
0
R/W
This bit is always read as 1.
I/O Control D2
Selects the GRD function.
0: GRD functions as an output compare register
1: GRD functions as an input capture register
5
IOD1
0
R/W
I/O Control D1 and D0
4
IOD0
0
R/W
When IOD2 = 0,
00: No output at compare match
01: 0 output to the FTIOD pin at GRD compare match
10: 1 output to the FTIOD pin at GRD compare match
11: Output toggles to the FTIOD pin at GRD compare
match
When IOD2 = 1,
00: Input capture at rising edge at the FTIOD pin
01: Input capture at falling edge at the FTIOD pin
1X: Input capture at rising and falling edges at the FTIOD
pin
3

1

Reserved
This bit is always read as 1.
2
IOC2
0
R/W
I/O Control C2
Selects the GRC function.
0: GRC functions as an output compare register
1: GRC functions as an input capture register
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Section 12 Timer W
Bit
Bit Name
Initial
Value
R/W
Description
1
IOC1
0
R/W
I/O Control C1 and C0
0
IOC0
0
R/W
When IOC2 = 0,
00: No output at compare match
01: 0 output to the FTIOC pin at GRC compare match
10: 1 output to the FTIOC pin at GRC compare match
11: Output toggles to the FTIOC pin at GRC compare
match
When IOC2 = 1,
00: Input capture to GRC at rising edge of the FTIOC pin
01: Input capture to GRC at falling edge of the FTIOC pin
1X: Input capture to GRC at rising and falling edges of
the FTIOC pin
Legend: X: Don't care.
12.3.7
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to
CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting
the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF
flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is
generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.
TCNT is initialized to H'0000 by a reset.
12.3.8
General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and
TIOR1.
When a general register is used as an input-compare register, its value is constantly compared with
the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA,
IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when
IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TCNT value is stored in the general register. The corresponding flag
(IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corresponding interrupt-enable bit
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Section 12 Timer W
(IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is
generated. The edge of the input-capture signal is selected in TIOR.
GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA
and BUFEB in TMRW.
For example, when GRA is set as an output-compare register and GRC is set as the buffer register
for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is
generated.
When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the
value in TCNT is transferred to GRA and the value in the buffer register GRC is transferred to
GRA whenever an input capture is generated.
GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are
initialized to H'FFFF by a reset.
12.4
Operation
The timer W has the following operating modes.
• Normal Operation
• PWM Operation
12.4.1
Normal Operation
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CTS bit in TMRW is set to 1, TCNT starts incrementing the count.
When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE
in TIERW is set to 1, an interrupt request is generated. Figure 12.2 shows free-running counting.
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Section 12 Timer W
TCNT value
H'FFFF
H'0000
Time
CTS bit
Flag cleared
by software
OVF
Figure 12.2 Free-Running Counter Operation
Periodic counting operation can be performed when GRA is set as an output compare register and
bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the
IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt
request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic
counting.
TCNT value
GRA
H'0000
Time
CTS bit
Flag cleared
by software
IMFA
Figure 12.3 Periodic Counter Operation
By setting a general register as an output compare register, compare match A, B, C, or D can cause
the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle. Figure
12.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1 output
is selected for compare match A, and 0 output is selected for compare match B. When signal is
already at the selected output level, the signal level does not change at compare match.
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Section 12 Timer W
TCNT value
H'FFFF
GRA
GRB
Time
H'0000
FTIOA
FTIOB
No change
No change
No change
No change
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)
Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter,
and toggle output is selected for both compare match A and B.
TCNT value
H'FFFF
GRA
GRB
Time
H'0000
FTIOA
Toggle output
FTIOB
Toggle output
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1)
Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter,
cleared by compare match A. Toggle output is selected for both compare match A and B.
TCNT value
Counter cleared by compare match with GRA
H'FFFF
GRA
GRB
H'0000
Time
FTIOA
Toggle
output
FTIOB
Toggle
output
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)
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Section 12 Timer W
The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a
signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can
take place on the rising edge, falling edge, or both edges. By using the input-capture function, the
pulse width and periods can be measured. Figure 12.7 shows an example of input capture when
both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates
as a free-running counter.
TCNT value
H'FFFF
H'F000
H'AA55
H'55AA
H'1000
H'0000
Time
FTIOA
GRA
H'1000
H'F000
H'55AA
FTIOB
GRB
H'AA55
Figure 12.7 Input Capture Operating Example
Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture
register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter,
and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation,
the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
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Section 12 Timer W
TCNT value
H'FFFF
H'DA91
H'5480
H'0245
H'0000
Time
FTIOA
GRA
GRC
H'0245
H'5480
H'DA91
H'0245
H'5480
Figure 12.8 Buffer Operation Example (Input Capture)
12.4.2
PWM Operation
In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB,
GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and
FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register
functions as an output compare register automatically. The output level of each pin depends on the
corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the
FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the
FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare
match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode.
If the same value is set in the cycle register and the duty register, the output does not change when
a compare match occurs.
Figure 12.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT
is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB,
TOC, and TOD = 1: initial output values are set to 1).
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Section 12 Timer W
TCNT value
Counter cleared by compare match A
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 12.9 PWM Mode Example (1)
Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and
TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and
D (TOB, TOC, and TOD = 0: initial output values are set to 1).
TCNT value
Counter cleared by compare match A
GRA
GRB
GRC
GRD
H'0000
Time
FTIOB
FTIOC
FTIOD
Figure 12.10 PWM Mode Example (2)
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Section 12 Timer W
Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
GRB
H'0520
H'0450
H'0200
Time
H'0000
GRD
GRB
H'0450
H'0200
H'0200
H'0520
H'0450
H'0520
FTIOB
Figure 12.11 Buffer Operation Example (Output Compare)
Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.
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Section 12 Timer W
TCNT value
Write to GRB
GRA
GRB
Write to GRB
H'0000
Time
Duty 0%
FTIOB
TCNT value
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Write to GRB
GRA
Write to GRB
Write to GRB
GRB
H'0000
Time
Duty 100%
FTIOB
TCNT value
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Write to GRB
GRA
Write to GRB
Write to GRB
GRB
H'0000
Time
Duty 100%
FTIOB
Duty 0%
Figure 12.12 PWM Mode Example
(TOB, TOC, and TOD = 0: initial output values are set to 0)
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Section 12 Timer W
TCNT value
Write to GRB
GRA
GRB
Write to GRB
H'0000
Time
Duty 100%
FTIOB
TCNT value
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Write to GRB
GRA
Write to GRB
Write to GRB
GRB
H'0000
Time
Duty 0%
FTIOB
TCNT value
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Write to GRB
GRA
Write to GRB
Write to GRB
GRB
H'0000
FTIOB
Time
Duty 0%
Duty 100%
Figure 12.13 PWM Mode Example
(TOB, TOC, and TOD = 1: initial output values are set to 1)
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Section 12 Timer W
12.5
Operation Timing
12.5.1
TCNT Count Timing
Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure
12.15 shows the timing when the external clock source is selected. The pulse width of the external
clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted
correctly.
φ
Internal
clock
Rising edge
TCNT input
clock
TCNT
N
N+1
N+2
Figure 12.14 Count Timing for Internal Clock Source
φ
External
clock
Rising edge
Rising edge
TCNT input
clock
TCNT
N
N+1
N+2
Figure 12.15 Count Timing for External Clock Source
12.5.2
Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when
TCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TIOR is output at the compare match output pin (FTIOA,
FTIOB, FTIOC, or FTIOD).
When TCNT matches GR, the compare match signal is generated only after the next counter clock
pulse is input.
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Section 12 Timer W
Figure 12.16 shows the output compare timing.
φ
TCNT input
clock
TCNT
N
GRA to GRD
N
N+1
Compare
match signal
FTIOA to FTIOD
Figure 12.16 Output Compare Output Timing
12.5.3
Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
φ
Input capture
input
Input capture
signal
N–1
TCNT
GRA to GRD
N
N+1
N+2
N
Figure 12.17 Input Capture Input Signal Timing
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Section 12 Timer W
12.5.4
Timing of Counter Clearing by Compare Match
Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA
value is N, the counter counts from 0 to N, and its cycle is N + 1.
φ
Compare
match signal
TCNT
N
GRA
N
H'0000
Figure 12.18 Timing of Counter Clearing by Compare Match
12.5.5
Buffer Operation Timing
Figures 12.19 and 12.20 show the buffer operation timing.
φ
Compare
match signal
TCNT
N
GRC, GRD
M
GRA, GRB
N+1
M
Figure 12.19 Buffer Operation Timing (Compare Match)
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Section 12 Timer W
φ
Input capture
signal
TCNT
N
GRA, GRB
M
GRC, GRD
N+1
N
N+1
M
N
Figure 12.20 Buffer Operation Timing (Input Capture)
12.5.6
Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Figure 12.21 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
N
GRA to GRD
N
N+1
Compare
match signal
IMFA to IMFD
IRRTW
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
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Section 12 Timer W
12.5.7
Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
φ
Input capture
signal
N
TCNT
N
GRA to GRD
IMFA to IMFD
IRRTW
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
12.5.8
Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 12.23 shows the status flag clearing timing.
TSRW write cycle
T1
T2
φ
TSRW address
Address
Write signal
IMFA to IMFD
IRRTW
Figure 12.23 Timing of Status Flag Clearing by CPU
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Section 12 Timer W
12.6
Usage Notes
The following types of contention or operation can occur in timer W operation.
1. The pulse width of the input clock signal and the input capture signal must be at least two
system clock (φ) cycles; shorter pulses will not be detected correctly.
2. Writing to registers is performed in the T2 state of a TCNT write cycle.
If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 12.24. If counting-up is
generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes
precedence.
3. Depending on the timing, TCNT may be incremented by a switch between different internal
clock sources. When TCNT is internally clocked, an increment pulse is generated from the
rising edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown in
figure 12.25 the switch is from a low clock signal to a high clock signal, the switchover is seen
as a rising edge, causing TCNT to increment.
4. If timer W enters module standby mode while an interrupt request is generated, the interrupt
request cannot be cleared. Before entering module standby mode, disable interrupt requests.
TCNT write cycle
T2
T1
φ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 12.24 Contention between TCNT Write and Clear
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Section 12 Timer W
Previous clock
New clock
Count clock
TCNT
N
N+1
N+2
N+3
The change in signal level at clock switching is
assumed to be a rising edge, and TCNT
increments the count.
Figure 12.25 Internal Clock Switching and TCNT Operation
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Section 12 Timer W
5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the
first compare match occurs. Once a compare match occurs and this compare match changes the
values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the
values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and
the generation of the compare match A to D occur at the same timing, the writing to TCRW
has the priority. Thus, output change due to the compare match is not reflected to the FTIOA
to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the
values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is
to be written to while compare match is operating, stop the counter once before accessing to
TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD,
and then restart the counter. Figure 12.26 shows an example when the compare match and the
bit manipulation instruction to TCRW occur at the same timing.
TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is in the 1 output state,
and is set to the toggle output or the 0 output by compare match B.
When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs
at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the FTIOB signal low;
the FTIOB signal remains high.
Bit
TCRW
Set value
7
6
5
4
CCLR
0
CKS2
0
CKS1
0
CKS0
0
3
TOD
0
2
1
0
TOC
1
TOB
1
TOA
0
BCLR#2, @TCRW
(1) TCRW read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TCRW: Write H'02
φ
TCRW
write signal
Compare match
signal B
FTIOB pin
Expected output
Remains high because the 1 writing to TOB has priority
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW
Occur at the Same Timing
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Section 12 Timer W
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Section 13 Watchdog Timer
Section 13 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 13.1.
φ
CLK
TCSRWD
PSS
TCWD
Internal data bus
Internal
oscillator
TMWD
[Legend]
TCSRWD:
TCWD:
PSS:
TMWD:
Timer control/status register WD
Timer counter WD
Prescaler S
Timer mode register WD
Internal reset
signal
Figure 13.1 Block Diagram of Watchdog Timer
13.1
Features
• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192) or the
internal oscillator can be selected as the timer-counter clock. When the internal oscillator is
selected, it can operate as the watchdog timer in any operating mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
WDT0110A_000020020200
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Section 13 Watchdog Timer
13.2
Register Descriptions
The watchdog timer has the following registers.
• Timer control/status register WD (TCSRWD)
• Timer counter WD (TCWD)
• Timer mode register WD (TMWD)
13.2.1
Timer Control/Status Register WD (TCSRWD)
TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the
watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using
the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit
Bit Name
Initial
Value
R/W
Description
7
B6WI
1
R/W
Bit 6 Write Inhibit
The TCWE bit can be written only when the write value of
the B6WI bit is 0.
This bit is always read as 1.
6
TCWE
0
R/W
Timer Counter WD Write Enable
TCWD can be written when the TCWE bit is set to 1.
When writing data to this bit, the value for bit 7 must be 0.
5
B4WI
1
R/W
Bit 4 Write Inhibit
The TCSRWE bit can be written only when the write
value of the B4WI bit is 0. This bit is always read as 1.
4
TCSRWE
0
R/W
Timer Control/Status Register WD Write Enable
The WDON and WRST bits can be written when the
TCSRWE bit is set to 1.
When writing data to this bit, the value for bit 5 must be 0.
3
B2WI
1
R/W
Bit 2 Write Inhibit
This bit can be written to the WDON bit only when the
write value of the B2WI bit is 0.
This bit is always read as 1.
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Section 13 Watchdog Timer
Bit
Bit Name
Initial
Value
R/W
Description
2
WDON
0
R/W
Watchdog Timer On
TCWD starts counting up when WDON is set to 1 and
halts when WDON is cleared to 0.
[Setting condition]
When 1 is written to the WDON bit while writing 0 to the
B2WI bit when the TCSRWE bit=1
[Clearing conditions]
1
B0WI
1
R/W
•
Reset by RES pin
•
When 0 is written to the WDON bit while writing 0 to
the B2WI when the TCSRWE bit=1
Bit 0 Write Inhibit
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read as
1.
0
WRST
0
R/W
Watchdog Timer Reset
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
13.2.2
•
Reset by RES pin
•
When 0 is written to the WRST bit while writing 0 to
the B0WI bit when the TCSRWE bit=1
Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to
H'00.
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Section 13 Watchdog Timer
13.2.3
Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit
Bit Name
Initial
Value
R/W
7 to 4

All 1

Description
Reserved
These bits are always read as 1.
3
CKS3
1
R/W
Clock Select 3 to 0
2
CKS2
1
R/W
Select the clock to be input to TCWD.
1
CKS1
1
R/W
1000: Internal clock: counts on φ/64
0
CKS0
1
R/W
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ8192
0XXX: Internal oscillator
For the internal oscillator overflow periods, see section
21, Electrical Characteristics.
Legend: X: Don't care.
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Section 13 Watchdog Timer
13.3
Operation
The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to
B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate
the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input
after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset
signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles. TCWD
is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An
overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the
TCWD set value.
Figure 13.2 shows an example of watchdog timer operation.
Example:
With 30ms overflow period when φ = 4 MHz
4 × 106
8192
× 30 × 10–3 = 14.6
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
TCWD overflow
H'FF
H'F1
TCWD
count value
H'00
Start
H'F1 written
to TCWD
H'F1 written to TCWD
Reset generated
Internal reset
signal
256 φosc clock cycles
Figure 13.2 Watchdog Timer Operation Example
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Section 13 Watchdog Timer
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Section 14 Serial Communication Interface 3 (SCI3)
Section 14 Serial Communication Interface 3 (SCI3)
Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous
serial communication. In the asynchronous method, serial data communication can be carried out
using standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication between processors (multiprocessor
communication function).
Figure 14.1 shows a block diagram of the SCI3.
14.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• External clock or on-chip baud rate generator can be selected as a transfer clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
Asynchronous mode
•
•
•
•
•
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RxD pin level directly in the case of a
framing error
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
SCI0010A_000020020200
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Section 14 Serial Communication Interface 3 (SCI3)
SCK3
External
clock
Internal clock (φ/64, φ/16, φ/4, φ)
Baud rate generator
BRC
BRR
SMR
Transmit/receive
control circuit
SCR3
SSR
TXD
TSR
TDR
RXD
RSR
RDR
[Legend]
Receive shift register
RSR:
Receive data register
RDR:
Transmit shift register
TSR:
Transmit data register
TDR:
Serial mode register
SMR:
SCR3: Serial control register 3
Serial status register
SSR:
Bit rate register
BRR:
Bit rate counter
BRC:
Figure 14.1 Block Diagram of SCI3
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Internal data bus
Clock
Interrupt request
(TEI, TXI, RXI, ERI)
Section 14 Serial Communication Interface 3 (SCI3)
14.2
Input/Output Pins
Table 14.1 shows the SCI3 pin configuration.
Table 14.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
SCI3 clock
SCK3
I/O
SCI3 clock input/output
SCI3 receive data input
RXD
Input
SCI3 receive data input
SCI3 transmit data output
TXD
Output
SCI3 transmit data output
14.3
Register Descriptions
The SCI3 has the following registers.
•
•
•
•
•
•
•
•
Receive shift register (RSR)
Receive data register (RDR)
Transmit shift register (TSR)
Transmit data register (TDR)
Serial mode register (SMR)
Serial control register 3 (SCR3)
Serial status register (SSR)
Bit rate register (BRR)
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
14.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
14.3.3
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR automatically, then sends the data that starts from the
LSB to the TXD pin. TSR cannot be directly accessed by the CPU.
14.3.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator
clock source.
Bit
Bit Name
Initial
Value
R/W
Description
7
COM
0
R/W
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception.
4
PM
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked, regardless
of the value in the bit. If the second stop bit is 0, it is
treated as the start bit of the next transmit character.
2
MP
0
R/W
Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and PM
bit settings are invalid. In clocked synchronous mode, this
bit should be cleared to 0.
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Section 14 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKS1
0
R/W
Clock Select 0 and 1
0
CKS0
0
R/W
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 14.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 14.3.8, Bit Rate Register (BRR)).
14.3.6
Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,
Interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
5
TE
0
R/W
Transmit Enable
4
RE
0
R/W
Receive Enable
When this bit is set to 1, transmission is enabled.
When this bit is set to 1, reception is enabled.
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Section 14 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is prohibited.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 14.6,
Multiprocessor Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, the TEI interrupt request is
enabled.
1
CKE1
0
R/W
Clock Enable 0 and 1
0
CKE0
0
R/W
Selects the clock source.
Asynchronous mode:
00: Internal baud rate generator
01: Internal baud rate generator
Outputs a clock of the same frequency as the bit rate
from the SCK3 pin.
10: External clock
Inputs a clock with a frequency 16 times the bit rate
from the SCK3 pin.
11: Reserved
Clocked synchronous mode:
00: Internal clock (SCK3 pin functions as clock output)
01: Reserved
10: External clock (SCK3 pin functions as clock input)
11: Reserved
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit
Bit Name
Initial
Value
R/W
Description
7
TDRE
1
R/W
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR3 is 0
•
When data is transferred from TDR to TSR
[Clearing conditions]
6
RDRF
0
R/W
•
When 0 is written to TDRE after reading TDRE = 1
•
When the transmit data is written to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
5
OER
0
R/W
•
When 0 is written to RDRF after reading RDRF = 1
•
When data is read from RDR
Overrun Error
[Setting condition]
•
When an overrun error occurs in reception
[Clearing condition]
•
4
FER
0
R/W
When 0 is written to OER after reading OER = 1
Framing Error
[Setting condition]
•
When a framing error occurs in reception
[Clearing condition]
•
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When 0 is written to FER after reading FER = 1
Section 14 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
3
PER
0
R/W
Parity Error
[Setting condition]
•
When a parity error is generated during reception
[Clearing condition]
•
2
TEND
1
R
When 0 is written to PER after reading PER = 1
Transmit End
[Setting conditions]
•
When the TE bit in SCR3 is 0
•
When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character
[Clearing conditions]
1
MPBR
0
R
•
When 0 is written to TEND after reading TEND = 1
•
When the transmit data is written to TDR
Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is cleared to 0,
its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit character data.
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Section 14 Serial Communication Interface 3 (SCI3)
14.3.8
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (highspeed) mode. Table 14.4 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 in SMR in clocked synchronous mode. The values shown in table 14.4 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N=
φ
64 ×
22n–1
×B
× 106 – 1
φ × 106

– 1 × 100
(N + 1) × B × 64 × 22n–1


Error (%) = 
[Clocked Synchronous Mode]
N=
Note: B:
N:
φ:
n:
φ
× 106 – 1
8 × 22n–1 × B
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
CKS1 and CKS0 setting for SMR (0 ≤ N ≤ 3)
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)
2
2.097152
2.4576
3
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
–0.04
1
174
–0.26
1
212
0.03
150
1
103
0.16
1
108
0.21
1
127
0.00
1
155
0.16
300
0
207
0.16
0
217
0.21
0
255
0.00
1
77
0.16
600
0
103
0.16
0
108
0.21
0
127
0.00
0
155
0.16
1200
0
51
0.16
0
54
–0.70
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.14
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
–2.48
0
15
0.00
0
19
–2.34
9600
0
6
–6.99
0
6
–2.48
0
7
0.00
0
9
–2.34
19200
0
2
8.51
0
2
13.78
0
3
0.00
0
4
–2.34
31250
0
1
0.00
0
1
4.86
0
1
22.88
0
2
0.00
38400
0
1
–18.62
0
1
–14.67
0
1
0.00
—
—
—
Legend:
 : A setting is available but error occurs
Operating Frequency φ (MHz)
3.6864
4
4.9152
5
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
0
6
–6.99
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
–1.70
0
4
0.00
38400
0
2
0.00
0
2
8.51
0
3
0.00
0
3
1.73
Rev.5.00 Nov. 02, 2005 Page 199 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency φ (MHz)
6
6.144
7.3728
8
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
106
–0.44
2
108
0.08
2
130
–0.07
2
141
0.03
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103
0.16
300
1
155
0.16
1
159
0.00
1
191
0.00
1
207
0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
–2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
–2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
0
6
5.33
0
7
0.00
38400
0
4
–2.34
0
4
0.00
0
5
0.00
0
6
-6.99
Operating Frequency φ (MHz)
9.8304
10
12
12.888
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
–2.34
0
19
0.00
31250
0
9
–1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
–2.34
0
9
0.00
Rev.5.00 Nov. 02, 2005 Page 200 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency φ (MHz)
14
14.7456
16
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
248
–0.17
3
64
0.70
3
70
0.03
150
2
181
0.16
2
191
0.00
2
207
0.16
300
2
90
0.16
2
95
0.00
2
103
0.16
600
1
181
0.16
1
191
0.00
1
207
0.16
1200
1
90
0.16
1
95
0.00
1
103
0.16
2400
0
181
0.16
0
191
0.00
0
207
0.16
4800
0
90
0.16
0
95
0.00
0
103
0.16
9600
0
45
–0.93
0
47
0.00
0
51
0.16
19200
0
22
–0.93
0
23
0.00
0
25
0.16
31250
0
13
0.00
0
14
–1.70
0
15
0.00
38400
—
—
—
0
11
0.00
0
12
0.16
Operating Frequency φ (MHz)
18
20
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
110
3
79
–0.12
3
88
–0.25
150
2
233
0.16
3
64
0.16
300
2
116
0.16
2
129
0.16
600
1
233
0.16
2
64
0.16
1200
1
116
0.16
1
129
0.16
2400
0
233
0.16
1
64
0.16
4800
0
116
0.16
0
129
0.16
9600
0
58
–0.96
0
64
0.16
19200
0
28
1.02
0
32
–1.36
31250
0
17
0.00
0
19
0.00
38400
0
14
–2.34
0
15
1.73
Legend:
—: A setting is available but error occurs.
Rev.5.00 Nov. 02, 2005 Page 201 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
2
62500
0
0
8
250000
0
0
2.097152 65536
0
0
9.8304
307200
0
0
2.4576
76800
0
0
10
312500
0
0
3
93750
0
0
12
375000
0
0
3.6864
115200
0
0
12.288
384000
0
0
4
125000
0
0
14
437500
0
0
4.9152
153600
0
0
14.7456
460800
0
0
5
156250
0
0
16
500000
0
0
6
187500
0
0
17.2032
537600
0
0
6.144
192000
0
0
18
562500
0
0
7.3728
230400
0
0
20
625000
0
0
Rev.5.00 Nov. 02, 2005 Page 202 of 418
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.4 Examples of BBR Setting for Various Bit Rates (Clocked Synchronous Mode)
(1)
Operating Frequency φ (MHz)
2
4
8
10
Bit Rate
(bit/s)
n
N
n
N
n
N
n
N
110
3
70
—
—
—
—
—
—
250
2
124
2
249
3
124
—
500
1
249
2
124
2
249
—
16
n
N
—
3
249
—
3
124
1k
1
124
1
249
2
124
—
—
2
249
2.5k
0
199
1
99
1
199
1
249
2
99
5k
0
99
0
199
1
99
1
124
1
199
10k
0
49
0
99
0
199
0
249
1
99
25k
0
19
0
39
0
79
0
99
0
159
50k
0
9
0
19
0
39
0
49
0
79
100k
0
4
0
9
0
19
0
24
0
39
250k
0
1
0
3
0
7
0
9
0
15
500k
0
0*
0
1
0
3
0
4
0
7
0
0*
0
1
—
—
0
3
0
0*
—
—
0
1
0
0*
—
—
0
0*
1M
2M
2.5M
4M
Legend:
Blank : No setting is available.
—
: A setting is available but error occurs.
*
: Continuous transfer is not possible.
Rev.5.00 Nov. 02, 2005 Page 203 of 418
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Section 14 Serial Communication Interface 3 (SCI3)
Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
(2)
Operating Frequency φ (MHz)
18
20
Bit Rate
(bit/s)
n
N
n
N
110
—
—
—
—
250
—
—
—
—
500
3
140
3
155
1k
3
69
3
77
2.5k
2
112
2
124
5k
1
224
1
249
10k
1
112
1
124
25k
0
179
0
199
50k
0
89
0
99
100k
0
44
0
49
250k
0
17
0
19
500k
0
8
0
9
1M
0
4
0
4
2M
—
—
—
—
2.5M
—
—
0
1
4M
—
—
—
—
Legend:
Blank : No setting is available.
—
: A setting is available but error occurs.
*
: Continuous transfer is not possible.
Rev.5.00 Nov. 02, 2005 Page 204 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
14.4
Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units,
enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure,
so data can be read or written during transmission or reception, enabling continuous data transfer.
LSB
MSB
Serial Start
data
bit
Transmit/receive data
7 or 8 bits
1 bit
1
Parity
bit
Stop bit
Mark state
1 or
2 bits
1 bit,
or none
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication
14.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock source, according to the setting of the
COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the
SCK3 pin, the clock frequency should be 16 times the bit rate used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14.3.
Clock
Serial data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (frame)
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Rev.5.00 Nov. 02, 2005 Page 205 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
14.4.2
SCI3 Initialization
Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to
0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of
the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization.
[1]
Start initialization
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
immediately after CKE1, CKE0, and RE
are set to 1.
Clear TE and RE bits in SCR3 to 0
[1]
Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR
[3]
Wait
[2]
Set the data transfer format in SMR.
[3]
Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4]
Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1. RE
settings enable the RXD pin to be used.
For transmission, set the TXD bit in
PMR1 to 1 to enable the TXD output pin
to be used. Also set the RIE, TIE, TEIE,
and MPIE bits, depending on whether
interrupts are required. In asynchronous
mode, the bits are marked at
transmission and idled at reception to
wait for the start bit.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR3 to 1, and set RIE, TIE, TEIE,
and MPIE bits. For transmit (TE=1),
also set the TxD bit in PMR1.
<Initialization completion>
[4]
Set the clock selection in SCR3.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
Figure 14.4 Sample SCI3 Initialization Flowchart
Rev.5.00 Nov. 02, 2005 Page 206 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
14.4.3
Data Transmission
Figure 14.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.
Continuous transmission is possible because the TXI interrupt routine writes next transmit data
to TDR before transmission of the current transmit data has been completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI
interrupt request is generated.
6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
1 frame
Parity Stop Start
bit
bit bit
0/1
1
0
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
Mark
state
1
1 frame
TDRE
TEND
TXI interrupt
LSI
operation request
generated
User
processing
TDRE flag
cleared to 0
TXI interrupt request generated
TEI interrupt request
generated
Data written
to TDR
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev.5.00 Nov. 02, 2005 Page 207 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR
Yes
[2]
All data transmitted?
[1] Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. When data is
written to TDR, the TDRE flag is
automaticaly cleared to 0.
[2] To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR. When data
is written to TDR, the TDRE flag is
automaticaly cleared to 0.
[3] To output a break in serial
transmission, after setting PCR to 1
and PDR to 0, clear TxD in PMR1
to 0, then clear the TE bit in SCR3
to 0.
No
Read TEND flag in SSR
No
TEND = 1
Yes
[3]
No
Break output?
Yes
Clear PDR to 0 and
set PCR to 1
Clear TE bit in SCR3 to 0
<End>
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
Rev.5.00 Nov. 02, 2005 Page 208 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
14.4.4
Serial Data Reception
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
Mark state
(idle state)
1
1 frame
RDRF
FER
LSI
operation
RXI request
User
processing
RDRF
cleared to 0
0 stop bit
detected
RDR data read
ERI request in
response to
framing error
Framing error
processing
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev.5.00 Nov. 02, 2005 Page 209 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flowchart
for serial data reception.
Table 14.5 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
OER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains the state it had before data reception.
Rev.5.00 Nov. 02, 2005 Page 210 of 418
REJ09B0028-0500
Section 14 Serial Communication Interface 3 (SCI3)
Start reception
Read OER, PER, and
FER flags in SSR
[1]
Yes
OER+PER+FER = 1
[4]
No
Error processing
(Continued on next page)
Read RDRF flag in SSR
[2]
No
RDRF = 1
Yes
Read receive data in RDR
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
[2] Read SSR and check that RDRF = 1,
then read the receive data in RDR.
The RDRF flag is cleared automatically.
[3] To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag and read
RDR.
The RDRF flag is cleared automatically.
[4] If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the OER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
Yes
All data received?
(A)
[3]
No
Clear RE bit in SCR3 to 0
<End>
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)
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Section 14 Serial Communication Interface 3 (SCI3)
[4]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and
FER flags in SSR to 0
<End>
Figure 14.8 Sample Serial Reception Data Flowchart (2)
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Section 14 Serial Communication Interface 3 (SCI3)
14.5
Operation in Clocked Synchronous Mode
Figure 14.9 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clocked
synchronous serial communication, data on the transmission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the
SCI3, the transmitter and receiver are independent units, enabling full-duplex communication
through the use of a common clock. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
8-bit
One unit of transfer data (character or frame)
*
*
Synchronization
clock
LSB
Bit 0
Serial data
MSB
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 14.9 Data Format in Clocked Synchronous Communication
14.5.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the serial clock is output from the SCK3 pin. Eight serial clock pulses are output in the transfer of
one character, and when no transfer is performed the clock is fixed high.
14.5.2
SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 14.4.
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Section 14 Serial Communication Interface 3 (SCI3)
14.5.3
Serial Data Transmission
Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
this time, a transmit data empty interrupt (TXI) is generated.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the TXD
pin.
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
7. The SCK3 pin is fixed high.
Figure 14.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
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Section 14 Serial Communication Interface 3 (SCI3)
Serial
clock
Serial
data
Bit 0
Bit 1
1 frame
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
LSI
TXI interrupt
operation request
generated
TDRE flag
cleared
to 0
User
processing
Data written
to TDR
TXI interrupt request generated
TEI interrupt request
generated
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
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Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
[2]
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0 and clocks are
output to start the data transmission.
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Write transmit data to TDR
[2]
All data transmitted?
Yes
No
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR3 to 0
<End>
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3)
14.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronous clock input or
output, starts receiving data.
2. The SCI3 stores the received data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
User
processing
RXI interrupt
request
generated
RDRF flag
cleared
to 0
RDR data read
RXI interrupt request generated
RDR data has
not been read
(RDRF = 1)
ERI interrupt request
generated by
overrun error
Overrun error
processing
Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart
for serial data reception.
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Section 14 Serial Communication Interface 3 (SCI3)
Start reception
[1]
[1]
Read OER flag in SSR
[2]
Yes
OER = 1
[4]
No
Error processing
[3]
(Continued below)
Read RDRF flag in SSR
[2]
[4]
No
RDRF = 1
Yes
Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.
Read receive data in RDR
Yes
All data received?
[3]
No
Clear RE bit in SCR3 to 0
<End>
[4]
Error processing
Overrun error processing
Clear OER flag in SSR to 0
<End>
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3)
14.5.5
Simultaneous Serial Data Transmission and Reception
Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mode, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
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Section 14 Serial Communication Interface 3 (SCI3)
Start transmission/reception
Read TDRE flag in SSR
[1]
[1]
No
TDRE = 1
Yes
Write transmit data to TDR
Read OER flag in SSR
OER = 1
No
Read RDRF flag in SSR
Yes
[4]
Error processing
[2]
No
RDRF = 1
Yes
Read receive data in RDR
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[4] If an overrun error occurs, read the
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 14.13.
Yes
All data received?
[3]
No
Clear TE and RE bits in SCR to 0
<End>
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)
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Section 14 Serial Communication Interface 3 (SCI3)
14.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 14.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is
set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
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Section 14 Serial Communication Interface 3 (SCI3)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
(MPB = 0)
ID transmission cycle = Data transmission cycle =
receiving station
Data transmission to
specification
receiving station specified by ID
[Legend]
MPB: Multiprocessor bit
Figure 14.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
14.6.1
Multiprocessor Serial Data Transmission
Figure 14.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
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Section 14 Serial Communication Interface 3 (SCI3)
Start transmission
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
[2]
Yes
Set MPBT bit in SSR
[3]
Write transmit data to TDR
Yes
[2]
Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.
All data transmitted?
No
Read TEND flag in SSR
No
TEND = 1
Yes
No
[3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0
<End>
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart
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Section 14 Serial Communication Interface 3 (SCI3)
14.6.2
Multiprocessor Serial Data Reception
Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure
14.18 shows an example of SCI3 operation for multiprocessor format reception.
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Section 14 Serial Communication Interface 3 (SCI3)
[1]
[2]
Start reception
Set MPIE bit in SCR3 to 1
[1]
Read OER and FER flags in SSR
[2]
[3]
Yes
FER+OER = 1
No
Read RDRF flag in SSR
[3]
No
[4]
[5]
RDRF = 1
Yes
Read receive data in RDR
No
This station’s ID?
Set the MPIE bit in SCR3 to 1.
Read OER and FER in SSR to check for
errors. Receive error processing is performed
in cases where a receive error occurs.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again.
When data is read from RDR, the RDRF flag
is automatically cleared to 0.
Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
If a receive error occurs, read the OER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the OER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RxD pin value.
Yes
Read OER and FER flags in SSR
Yes
FER+OER = 1
No
Read RDRF flag in SSR
[4]
No
RDRF = 1
[5]
Error processing
Yes
Read receive data in RDR
(Continued on
next page)
Yes
All data received?
No
[A]
Clear RE bit in SCR3 to 0
<End>
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 14 Serial Communication Interface 3 (SCI3)
[5]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
[A]
Framing error processing
Clear OER, and
FER flags in SSR to 0
<End>
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 14 Serial Communication Interface 3 (SCI3)
Start
bit
Serial
data
1
0
Receive
data (ID1)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data1)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
RDRF flag
cleared
to 0
RXI interrupt
request
MPIE cleared
to 0
User
processing
RXI interrupt request
is not generated, and
RDR retains its state
RDR data read
When data is not
this station's ID,
MPIE is set to 1
again
(a) When data does not match this receiver's ID
Start
bit
Serial
data
1
0
Receive
data (ID2)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data2)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
LSI
operation
User
processing
ID1
ID2
RXI interrupt
request
MPIE cleared
to 0
RDRF flag
cleared
to 0
RDR data read
Data2
RXI interrupt
request
When data is
this station's
ID, reception
is continued
RDRF flag
cleared
to 0
RDR data read
MPIE set to 1
again
(b) When data matches this receiver's ID
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 14 Serial Communication Interface 3 (SCI3)
14.7
Interrupts
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty,
receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6
shows the interrupt sources.
Table 14.6 SCI3 Interrupt Requests
Interrupt Requests
Abbreviation
Interrupt Sources
Receive Data Full
RXI
Setting RDRF in SSR
Transmit Data Empty
TXI
Setting TDRE in SSR
Transmission End
TEI
Setting TEND in SSR
Receive Error
ERI
Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the
generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
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Section 14 Serial Communication Interface 3 (SCI3)
14.8
Usage Notes
14.8.1
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
14.8.2
Mark State and Break Sending
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or
send a break during serial data transmission. To maintain the communication line at mark state
until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin
becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission,
first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
14.8.3
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
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Section 14 Serial Communication Interface 3 (SCI3)
14.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.19.
Thus, the reception margin in asynchronous mode is given by formula (1) below.


1
D – 0.5
M = (0.5 –
)–
– (L – 0.5) F × 100(%)
2N
N


... Formula (1)
Where N
D
L
F
: Ratio of bit rate to clock (N = 16)
: Clock duty (D = 0.5 to 1.0)
: Frame length (L = 9 to 12)
: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
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2
Section 15 I C Bus Interface 2 (IIC2)
Section 15 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The register configuration that controls the I2C bus differs partly from the
Philips configuration, however.
Figure 15.1 shows a block diagram of the I2C bus interface 2.
Figure 15.2 shows an example of I/O pin connections to external circuits.
15.1
Features
• Selection of I2C format or clocked synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
2
I C bus format
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• Direct bus drive
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Clocked synchronous format
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
IFIIC10A_000020020200
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Section 15 I C Bus Interface 2 (IIC2)
Transfer clock
generation
circuit
SCL
Transmission/
reception
control circuit
Output
control
ICCR1
ICCR2
ICMR
Internal data bus
Noise canceler
ICDRT
SDA
Output
control
ICDRS
SAR
Address
comparator
Noise canceler
ICDRR
Bus state
decision circuit
Arbitration
decision circuit
ICSR
ICIER
[Legend]
ICCR1 : I2C bus control register 1
ICCR2 : I2C bus control register 2
ICMR : I2C bus mode register
ICSR : I2C bus status register
ICIER : I2C bus interrupt enable register
ICDRT : I2C bus transmit data register
ICDRR : I2C bus receive data register
ICDRS : I2C bus shift register
SAR : Slave address register
Interrupt
generator
Figure 15.1 Block Diagram of I2C Bus Interface 2
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Interrupt request
2
Section 15 I C Bus Interface 2 (IIC2)
Vcc
SCL in
Vcc
SCL
SCL
SDA
SDA
SCL out
SDA in
SCL in
SCL out
SCL
SDA
(Master)
SCL
SDA
SDA out
SCL in
SCL out
SDA in
SDA in
SDA out
SDA out
(Slave 1)
(Slave 2)
Figure 15.2 External Circuit Connections of I/O Pins
15.2
Input/Output Pins
Table 15.1 summarizes the input/output pins used by the I2C bus interface 2.
Table 15.1 I2C Bus Interface Pins
Name
Abbreviation
I/O
Function
Serial clock
SCL
I/O
IIC serial clock input/output
Serial data
SDA
I/O
IIC serial data input/output
15.3
Register Descriptions
The I2C bus interface 2 has the following registers:
•
•
•
•
•
•
I2C bus control register 1 (ICCR1)
I2C bus control register 2 (ICCR2)
I2C bus mode register (ICMR)
I2C bus interrupt enable register (ICIER)
I2C bus status register (ICSR)
I2C bus slave address register (SAR)
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Section 15 I C Bus Interface 2 (IIC2)
• I2C bus transmit data register (ICDRT)
• I2C bus receive data register (ICDRR)
• I2C bus shift register (ICDRS)
15.3.1
I2C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
ICE
0
R/W
I2C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to port
function.)
1: This bit is enabled for transfer operations. (SCL and SDA
pins are bus drive state.)
6
RCVD
0
R/W
Reception Disable
This bit enables or disables the next operation when TRS is
0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
5
MST
0
R/W
Master/Slave Select
4
TRS
0
R/W
Transmit/Receive Select
In master mode with the I2C bus format, when arbitration is
lost, MST and TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of the TRS bit
should be made between transfer frames.
After data receive has been started in slave receive mode,
when the first seven bits of the receive data agree with the
slave address that is set to SAR and the eighth bit is 1,
TRS is automatically set to 1. If an overrun error occurs in
master mode with the clock synchronous serial format,
MST is cleared to 0 and slave receive mode is entered.
Operating modes are described below according to MST
and TRS combination. When clocked synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
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Section 15 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
3
CKS3
0
R/W
Transfer Clock Select 3 to 0
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits should be set according to the necessary
transfer rate (see table 15.2) in master mode. In slave
mode, these bits are used for reservation of the setup time
in transmit mode. The time is 10 tcyc when CKS3 = 0 and 20
tcyc when CKS3 = 1.
Table 15.2 Transfer Rate
Bit 3
Bit 2
Bit 1
Bit 0
CKS3
CKS2
CKS1
CKS0
Clock
φ = 5 MHz
φ = 8 MHz
0
0
0
0
φ/28
179 kHz
286 kHz
357 kHz
571 kHz
714 kHz
1
φ/40
125 kHz
200 kHz
250 kHz
400 kHz
500 kHz
0
φ/48
104 kHz
167 kHz
208 kHz
333 kHz
417 kHz
1
φ/64
78.1 kHz
125 kHz
156 kHz
250 kHz
313 kHz
1
1
0
1
1
0
0
1
1
0
1
Transfer Rate
φ = 10 MHz φ = 16 MHz φ = 20 MHz
0
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
φ/100
50.0 kHz
80.0 kHz
100 kHz
160 kHz
200 kHz
0
φ/112
44.6 kHz
71.4 kHz
89.3 kHz
143 kHz
179 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
0
φ/56
89.3 kHz
143 kHz
179 kHz
286 kHz
357 kHz
1
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
0
φ/96
52.1 kHz
83.3 kHz
104 kHz
167 kHz
208 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
0
φ/160
31.3 kHz
50.0 kHz
62.5 kHz
100 kHz
125 kHz
1
φ/200
25.0 kHz
40.0 kHz
50.0 kHz
80.0 kHz
100 kHz
0
φ/224
22.3 kHz
35.7 kHz
44.6 kHz
71.4 kHz
89.3 kHz
1
φ/256
19.5 kHz
31.3 kHz
39.1 kHz
62.5 kHz
78.1 kHz
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Section 15 I C Bus Interface 2 (IIC2)
15.3.2
I2C Bus Control Register 2 (ICCR2)
ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the control part of the I2C bus interface 2.
Bit
Bit Name
Initial
Value
R/W
Description
7
BBSY
0
R/W
Bus Busy
2
This bit enables to confirm whether the I C bus is
occupied or released and to issue start/stop conditions in
master mode. With the clocked synchronous serial
2
format, this bit has no meaning. With the I C bus format,
this bit is set to 1 when the SDA level changes from high
to low under the condition of SCL = high, assuming that
the start condition has been issued. This bit is cleared to
0 when the SDA level changes from low to high under the
condition of SCL = high, assuming that the stop condition
has been issued. Write 1 to BBSY and 0 to SCP to issue
a start condition. Follow this procedure when also retransmitting a start condition. Write 0 in BBSY and 0 in
SCP to issue a stop condition. To issue start/stop
conditions, use the MOV instruction.
6
SCP
1
W
Start/Stop Issue Condition Disable
The SCP bit controls the issue of start/stop conditions in
master mode.
To issue a start condition, write 1 in BBSY and 0 in SCP.
A retransmit start condition is issued in the same way. To
issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not
stored.
5
SDAO
1
R/W
SDA Output Value Control
This bit is used with SDAOP when modifying output level
of SDA. This bit should not be manipulated during
transfer.
0: When reading, SDA pin outputs low.
When writing, SDA pin is changed to output low.
1: When reading, SDA pin outputs high.
When writing, SDA pin is changed to output Hi-Z
(outputs high by external pull-up resistance).
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Section 15 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
4
SDAOP
1
R/W
SDAO Write Protect
This bit controls change of output level of the SDA pin by
modifying the SDAO bit. To change the output level, clear
SDAO and SDAOP to 0 or set SDAO to 1 and clear
SDAOP to 0 by the MOV instruction. This bit is always
read as 1.
3
SCLO
1
R
This bit monitors SCL output level. When SCLO is 1, SCL
pin outputs high. When SCLO is 0, SCL pin outputs low.
2

1

Reserved
This bit is always read as 1, and cannot be modified.
1
IICRST
0
R/W
IIC Control Part Reset
This bit resets the control part except for I2C registers. If
this bit is set to 1 when hang-up occurs because of
2
2
communication failure during I C operation, I C control
part can be reset without setting ports and initializing
registers.
0

1

Reserved
This bit is always read as 1, and cannot be modified.
15.3.3
I2C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Bit
Bit Name
Initial
Value
R/W
Description
7
MLS
0
R/W
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I2C bus format is used.
6
WAIT
0
R/W
Wait Insertion Bit
In master mode with the I2C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of
the clock for the final data bit, low period is extended for
two transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no
wait inserted.
2
The setting of this bit is invalid in slave mode with the I C
bus format or with the clocked synchronous serial format.
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Section 15 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
5, 4

All 1

Reserved
3
BCWP
1
R/W
These bits are always read as 1, and cannot be modified.
BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction. In clock synchronous serial
mode, BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
2
BC2
0
R/W
Bit Counter 2 to 0
1
BC1
0
R/W
0
BC0
0
R/W
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits is
indicated. With the I2C bus format, the data is transferred
with one addition acknowledge bit. Bit BC2 to BC0
settings should be made during an interval between
transfer frames. If bits BC2 to BC0 are set to a value
other than 000, the setting should be made while the
SCL pin is low. The value returns to 000 at the end of a
data transfer, including the acknowledge bit. With the
clock synchronous serial format, these bits should not be
modified.
2
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I C Bus Format
Clock Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bits
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
2
Section 15 I C Bus Interface 2 (IIC2)
15.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
6
TEIE
0
R/W
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(TEI) at the rising of the ninth clock while the TDRE bit in
ICSR is 1. TEI can be canceled by clearing the TEND bit
or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5
RIE
0
R/W
Receive Interrupt Enable
This bit enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request
(ERI) with the clocked synchronous format, when a
receive data is transferred from ICDRS to ICDRR and the
RDRF bit in ICSR is set to 1. RXI can be canceled by
clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clocked
synchronous format are disabled.
1: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clocked
synchronous format are enabled.
4
NAKIE
0
R/W
NACK Receive Interrupt Enable
This bit enables or disables the NACK receive interrupt
request (NAKI) and the overrun error (setting of the OVE
bit in ICSR) interrupt request (ERI) with the clocked
synchronous format, when the NACKF and AL bits in
ICSR are set to 1. NAKI can be canceled by clearing the
NACKF, OVE, or NAKIE bit to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
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Section 15 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
3
STIE
0
R/W
Stop Condition Detection Interrupt Enable
0: Stop condition detection interrupt request (STPI) is
disabled.
1: Stop condition detection interrupt request (STPI) is
enabled.
2
ACKE
0
R/W
Acknowledge Bit Judgement Select
0: The value of the receive acknowledge bit is ignored,
and continuous transfer is performed.
1: If the receive acknowledge bit is 1, continuous transfer
is halted.
1
ACKBR
0
R
Receive Acknowledge
In transmit mode, this bit stores the acknowledge data
that are returned by the receive device. This bit cannot be
modified.
0: Receive acknowledge = 0
1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
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Section 15 I C Bus Interface 2 (IIC2)
15.3.5
I2C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit
Bit Name
Initial
Value
R/W
7
TDRE
0
R/W
Description
Transmit Data Register Empty
[Setting conditions]
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
•
When TRS is set
•
When a start condition (including re-transfer) has
been issued
•
When transmit mode is entered from receive mode in
slave mode
[Clearing conditions]
6
TEND
0
R/W
•
When 0 is written in TDRE after reading TDRE = 1
•
When data is written to ICDRT with an instruction
Transmit End
[Setting conditions]
•
When the ninth clock of SCL rises with the I C bus
format while the TDRE flag is 1
•
When the final bit of transmit frame is sent with the
clock synchronous serial format
2
[Clearing conditions]
5
RDRF
0
R/W
•
When 0 is written in TEND after reading TEND = 1
•
When data is written to ICDRT with an instruction
Receive Data Register Full
[Setting condition]
•
When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
•
When 0 is written in RDRF after reading RDRF = 1
•
When ICDRR is read with an instruction
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Section 15 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
4
NACKF
0
R/W
No Acknowledge Detection Flag
[Setting condition]
•
When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is
1
[Clearing condition]
•
3
STOP
0
R/W
When 0 is written in NACKF after reading NACKF = 1
Stop Condition Detection Flag
[Setting conditions]
•
In master mode, when a stop condition is detected
after frame transfer
•
In slave mode, when a stop condition is detected
after the general call address or the first byte slave
address, next to detection of start condition, accords
with the address set in SAR
[Clearing condition]
•
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When 0 is written in STOP after reading STOP = 1
2
Section 15 I C Bus Interface 2 (IIC2)
Bit
Bit Name
Initial
Value
R/W
Description
2
AL/OVE
0
R/W
Arbitration Lost Flag/Overrun Error Flag
This flag indicates that arbitration was lost in master mode
with the I2C bus format and that the final bit has been
received while RDRF = 1 with the clocked synchronous
format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I2C bus interface
detects data differing from the data it sent, it sets AL to 1
to indicate that the bus has been taken by another master.
[Setting conditions]
•
If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
•
When the SDA pin outputs high in master mode while
a start condition is detected
•
When the final bit is received with the clocked
synchronous format while RDRF = 1
[Clearing condition]
•
1
AAS
0
R/W
When 0 is written in AL/OVE after reading AL/OVE = 1
Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first frame
following a start condition matches bits SVA6 to SVA0 in
SAR.
[Setting conditions]
•
When the slave address is detected in slave receive
mode
•
When the general call address is detected in slave
receive mode.
[Clearing condition]
•
0
ADZ
0
R/W
When 0 is written in AAS after reading AAS = 1
General Call Address Recognition Flag
This bit is valid in I2C bus format slave receive mode.
[Setting condition]
•
When the general call address is detected in slave
receive mode
[Clearing condition]
•
When 0 is written in ADZ after reading ADZ = 1
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Section 15 I C Bus Interface 2 (IIC2)
15.3.6
Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode
with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
received after a start condition, the chip operates as the slave device.
Initial
Value
R/W
Description
SVA6 to
SVA0
All 0
R/W
Slave Address 6 to 0
FS
0
Bit
Bit Name
7 to 1
0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
2
connected to the I C bus.
R/W
Format Select
2
0: I C bus format is selected.
1: Clocked synchronous serial format is selected.
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Section 15 I C Bus Interface 2 (IIC2)
15.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1
and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H’FF. The initial value of ICDRT is H’FF.
15.3.8
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit register that stores the receive data. When data of one byte is received, ICDRR
transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a
receive-only register, therefore the CPU cannot write to this register. The initial value of ICDRR
is H’FF.
15.3.9
I2C Bus Shift Register (ICDRS)
ICDRS is a register that is used to transfer/receive data. In transmission, data is transferred from
ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from
ICDRS to ICDRR after data of one byte is received. This register cannot be read directly from the
CPU.
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Section 15 I C Bus Interface 2 (IIC2)
15.4
Operation
The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode
by setting FS in SAR.
15.4.1
I2C Bus Format
Figure 15.3 shows the I2C bus formats. Figure 15.4 shows the I2C bus timing. The first frame
following a start condition always consists of 8 bits.
(a) I2C bus format (FS = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
n: Transfer bit count
(n = 1 to 8)
m: Transfer frame count
(m ≥ 1)
m
(b) I2C bus format (Start condition retransmission, FS = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
m1
1
m2
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 15.3 I2C Bus Formats
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
DATA
8
9
A
1-7
DATA
8
9
A
P
Figure 15.4 I2C Bus Timing
Legend
S:
SLA:
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
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Section 15 I C Bus Interface 2 (IIC2)
R/W:
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P:
Stop condition. The master device drives SDA from low to high while SCL is high.
15.4.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to
figures 15.5 and 15.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting)
2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the
transmit data is prepared or the stop condition is issued.
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 15 I C Bus Interface 2 (IIC2)
SCL
(Master output)
1
2
3
4
5
6
SDA
(Master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
7
8
Bit 1
Slave address
9
1
Bit 0
Bit 7
2
Bit 6
R/W
SDA
(Slave output)
A
TDRE
TEND
Address + R/W
ICDRT
ICDRS
User
processing
Data 1
Address + R/W
[2] Instruction of start
condition issuance
Data 2
Data 1
[4] Write data to ICDRT (second byte)
[5] Write data to ICDRT (third byte)
[3] Write data to ICDRT (first byte)
Figure 15.5 Master Transmit Mode Operation Timing (1)
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
1
2
3
4
5
6
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
8
9
Bit 0
A/A
A
TDRE
TEND
Data n
ICDRT
ICDRS
Data n
User
[5] Write data to ICDRT
processing
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
Figure 15.6 Master Transmit Mode Operation Timing (2)
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Section 15 I C Bus Interface 2 (IIC2)
15.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. For master receive mode operation timing, refer to
figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown
below.
1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master
transmit mode to master receive mode. Then, clear the TDRE bit to 0.
2. When ICDRR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. The master device outputs the
level specified by ACKBT in ICIER to SDA, at the 9th receive clock pulse.
3. After the reception of first frame data is completed, the RDRF bit in ICST is set to 1 at the rise
of 9th receive clock pulse. At this time, the receive data is read by reading ICDRR, and RDRF
is cleared to 0.
4. The continuous reception is performed by reading ICDRR every time RDRF is set. If 8th
receive clock pulse falls after reading ICDRR by the other processing while RDRF is 1, SCL is
fixed low until ICDRR is read.
5. If next frame is the last receive data, set the RCVD bit in ICCR1 to 1 before reading ICDRR.
This enables the issuance of the stop condition after the next reception.
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
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Section 15 I C Bus Interface 2 (IIC2)
Master transmit mode
SCL
(Master output)
Master receive mode
9
1
2
3
4
5
6
7
8
SDA
(Master output)
9
1
A
SDA
(Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
User
processing
Data 1
[3] Read ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
Figure 15.7 Master Receive Mode Operation Timing (1)
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Section 15 I C Bus Interface 2 (IIC2)
SCL
(Master output)
9
SDA
(Master output)
A
SDA
(Slave output)
1
2
3
4
5
6
7
8
9
A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDRF
RCVD
ICDRS
Data n
Data n-1
ICDRR
Data n
Data n-1
User
processing
[5] Read ICDRR after setting RCVD
[7] Read ICDRR,
and clear RCVD
[6] Issue stop
condition [8] Set slave
receive mode
Figure 15.8 Master Receive Mode Operation Timing (2)
15.4.4
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 15.9 and 15.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
with TDRE = 1. When TEND is set, clear TEND.
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
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Section 15 I C Bus Interface 2 (IIC2)
Slave receive mode
Slave transmit mode
SCL
(Master output)
9
1
2
3
4
5
6
7
8
9
SDA
(Master output)
1
A
SCL
(Slave output)
SDA
(Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TDRE
TEND
TRS
Data 1
ICDRT
ICDRS
Data 2
Data 1
Data 3
Data 2
ICDRR
User
processing
[2] Write data to ICDRT (data 1)
[2] Write data to ICDRT (data 2)
[2] Write data to ICDRT (data 3)
Figure 15.9 Slave Transmit Mode Operation Timing (1)
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Section 15 I C Bus Interface 2 (IIC2)
Slave receive
mode
Slave transmit mode
SCL
(Master output)
9
SDA
(Master output)
A
1
2
3
4
5
6
7
8
9
A
SCL
(Slave output)
SDA
(Slave output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDRE
TEND
TRS
ICDRT
ICDRS
Data n
ICDRR
User
processing
[3] Clear TEND
[4] Read ICDRR (dummy read)
after clearing TRS
[5] Clear TDRE
Figure 15.10 Slave Transmit Mode Operation Timing (2)
15.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 15.11 and 15.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
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Section 15 I C Bus Interface 2 (IIC2)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
Bit 7
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[2] Read ICDRR
[2] Read ICDRR (dummy read)
Figure 15.11 Slave Receive Mode Operation Timing (1)
SCL
(Master output)
9
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
SCL
(Slave output)
SDA
(Slave output)
A
A
RDRF
ICDRS
Data 2
Data 1
ICDRR
Data 1
User
processing
[3] Set ACKBT
[3] Read ICDRR [4] Read ICDRR
Figure 15.12 Slave Receive Mode Operation Timing (2)
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Section 15 I C Bus Interface 2 (IIC2)
15.4.6
Clocked Synchronous Serial Format
This module can be operated with the clocked synchronous serial format, by setting the FS bit in
SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When
MST is 0, the external clock input is selected.
Data Transfer Format
Figure 15.13 shows the clocked synchronous serial transfer format.
The transfer data is output from the rise to the fall of the SCL clock, and the data at the rising edge
of the SCL clock is guaranteed. The MLS bit in ICMR sets the order of data transfer, in either the
MSB first or LSB first. The output level of SDA can be changed during the transfer wait, by the
SDAO bit in ICCR2.
SCL
SDA
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5 Bit 6
Bit 7
Figure 15.13 Clocked Synchronous Serial Transfer Format
Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 15.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
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Section 15 I C Bus Interface 2 (IIC2)
SCL
1
2
7
8
1
7
8
1
SDA
(Output)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
Bit 0
TRS
TDRE
Data 1
ICDRT
Data 1
ICDRS
User
processing
Data 2
[3] Write data [3] Write data
to ICDRT
to ICDRT
[2] Set TRS
Data 3
Data 2
Data 3
[3] Write data
to ICDRT
[3] Write data
to ICDRT
Figure 15.14 Transmit Mode Operation Timing
Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 15.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1. (Initial
setting)
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock is risen while RDRF is 1, the overrun is detected and
AL/OVE in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
fixed high after receiving the next byte data.
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Section 15 I C Bus Interface 2 (IIC2)
SCL
1
2
7
8
1
7
8
SDA
(Input)
Bit 0
Bit 1
Bit 6
Bit 7
Bit 0
Bit 6
Bit 7
1
2
Bit 0
MST
TRS
RDRF
Data 2
Data 1
ICDRS
Data 3
Data 1
ICDRR
User
processing
[2] Set MST
(when outputting the clock)
[3] Read ICDRR
Data 2
[3] Read ICDRR
Figure 15.15 Receive Mode Operation Timing
15.4.7
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.16 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
SCL or SDA
input signal
D
C
Q
Latch
Q
D
Latch
March detector
Internal
SCL or SDA
signal
System clock
period
Sampling
clock
Figure 15.16 Block Diagram of Noise Conceler
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Section 15 I C Bus Interface 2 (IIC2)
15.4.8
Example of Use
Flowcharts in respective modes that use the I2C bus interface are shown in figures 15.17 to 15.20.
Start
Initialize
Read BBSY in ICCR2
[1]
Test the status of the SCL and SDA lines.
[2]
Set master transmit mode.
[3]
Issue the start condition.
[1]
No
BBSY=0 ?
Yes
Set MST and TRS
in ICCR1 to 1.
[2]
[4]
Set the first byte (slave address + R/W) of transmit data.
Write 1 to BBSY
and 0 to SCP.
[3]
[5]
Wait for 1 byte to be transmitted.
Write transmit data
in ICDRT
[4]
[6]
Test the acknowledge transferred from the specified slave device.
[7]
Set the second and subsequent bytes (except for the final byte) of transmit data.
[8]
Wait for ICDRT empty.
[9]
Set the last byte of transmit data.
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Read ACKBR in ICIER
[6]
ACKBR=0 ?
[10] Wait for last byte to be transmitted.
No
[11] Clear the TEND flag.
Yes
Transmit
mode?
Yes
No
Write transmit data in ICDRT
Mater receive mode
[7]
[12] Clear STOP flag.
Read TDRE in ICSR
No
[8]
[13] Issue the stop condition.
TDRE=1 ?
[14] Wait for the creation of stop condition.
Yes
No
[15] Set slave receive mode. Clear TDRE.
Last byte?
[9]
Yes
Write transmit data in ICDRT
Read TEND in ICSR
No
[10]
TEND=1 ?
Yes
Clear TEND in ICSR
[11]
Clear STOP in ISCR
[12]
Write 0 to BBSY
and SCP
[13]
Read STOP in ICSR
[14]
No
STOP=1 ?
Yes
Set MST to 1 and TRS
to 0 in ICCR1
[15]
Clear TDRE in ICSR
End
Figure 15.17 Sample Flowchart for Master Transmit Mode
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Section 15 I C Bus Interface 2 (IIC2)
Mater receive mode
[1]
Clear TEND, select master receive mode, and then clear TDRE.*
[2]
Set acknowledge to the transmit device.*
[3]
Dummy-read ICDDR.*
[4]
Wait for 1 byte to be received
[5]
Check whether it is the (last receive - 1).
[6]
Read the receive data last.
[7]
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[8]
Read the (final byte - 1) of receive data.
[9]
Wait for the last byte to be receive.
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
[1]
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
Read RDRF in ICSR
No
[4]
RDRF=1 ?
Yes
Last receive
- 1?
No
Read ICDRR
Yes
[5]
[10] Clear STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
Set ACKBT in ICIER to 1
[7]
Set RCVD in ICCR1 to 1
Read ICDRR
[13] Read the last byte of receive data.
[14] Clear RCVD.
[8]
[15] Set slave receive mode.
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Clear STOP in ICSR
Write 0 to BBSY
and SCP
[9]
[10]
[11]
Read STOP in ICSR
No
[12]
STOP=1 ?
Yes
Read ICDRR
[13]
Clear RCVD in ICCR1 to 0
[14]
Clear MST in ICCR1 to 0
[15]
End
Note: Do not activate an interrupt during the execution of steps [1] to [3].
Supplementary explanation: When one byte is received, steps [2] to [6] are
skipped after step [1], before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Figure 15.18 Sample Flowchart for Master Receive Mode
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Section 15 I C Bus Interface 2 (IIC2)
[1] Clear the AAS flag.
Slave transmit mode
Clear AAS in ICSR
[1]
Write transmit data
in ICDRT
[2]
[3] Wait for ICDRT empty.
[4] Set the last byte of transmit data.
Read TDRE in ICSR
[5] Wait for the last byte to be transmitted.
[3]
No
TDRE=1 ?
Yes
Yes
[6] Clear the TEND flag .
[7] Set slave receive mode.
Last
byte?
No
[2] Set transmit data for ICDRT (except for the last data).
[8] Dummy-read ICDRR to release the SCL line.
[4]
[9] Clear the TDRE flag.
Write transmit data
in ICDRT
Read TEND in ICSR
[5]
No
TEND=1 ?
Yes
Clear TEND in ICSR
[6]
Clear TRS in ICCR1 to 0
[7]
Dummy read ICDRR
[8]
Clear TDRE in ICSR
[9]
End
Figure 15.19 Sample Flowchart for Slave Transmit Mode
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Section 15 I C Bus Interface 2 (IIC2)
Slave receive mode
[1] Clear the AAS flag.
Clear AAS in ICSR
[1]
Clear ACKBT in ICIER to 0
[2]
Dummy-read ICDRR
[3]
[2] Set acknowledge to the transmit device.
[3] Dummy-read ICDRR.
[5] Check whether it is the (last receive - 1).
Read RDRF in ICSR
No
[4]
RDRF=1 ?
[6] Read the receive data.
[7] Set acknowledge of the last byte.
Yes
Last receive
- 1?
[4] Wait for 1 byte to be received.
Yes
No
Read ICDRR
[5]
[8] Read the (last byte - 1) of receive data.
[9] Wait the last byte to be received.
[6]
[10] Read for the last byte of receive data.
Set ACKBT in ICIER to 1
[7]
Read ICDRR
[8]
Read RDRF in ICSR
No
[9]
RDRF=1 ?
Yes
Read ICDRR
[10]
End
Supplementary explanation: When one byte is received, steps [2] to [6] are skipped after step [1],
before jumping to step [7]. The step [8] is dummy-read in ICDRR.
Figure 15.20 Sample Flowchart for Slave Receive Mode
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Section 15 I C Bus Interface 2 (IIC2)
15.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun. Table 15.3 shows the contents of
each interrupt request.
Table 15.3 Interrupt Requests
Interrupt Request
Abbreviation
Interrupt Condition
Clocked
Synchronous
I2C Mode Mode
Transmit Data Empty
TXI
(TDRE = 1) • (TIE = 1)
{
{
Transmit End
TEI
(TEND = 1) • (TEIE = 1)
{
{
Receive Data Full
RXI
(RDRF = 1) • (RIE = 1)
{
{
STOP Recognition
STPI
(STOP = 1) (STIE = 1)
{
×
NACK Receive
NAKI
{(NACKF = 1) + (AL = 1)}
(NAKIE = 1)
{
×
{
{
Arbitration
Lost/Overrun
•
•
When interrupt conditions described in table 15.3 are 1 and the I bit in CCR is 0, the CPU
executes an interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
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Section 15 I C Bus Interface 2 (IIC2)
15.6
Bit Synchronous Circuit
In master mode,this module has a possibility that high level period may be short in the two states
described below.
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 15.21 shows the timing of the bit synchronous circuit and table 15.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
VIH
SCL
Internal SCL
Figure 15.21 The Timing of the Bit Synchronous Circuit
Table 15.4 Time for Monitoring SCL
CKS3
CKS2
Time for Monitoring SCL
0
0
7.5 tcyc
1
19.5 tcyc
0
17.5 tcyc
1
41.5 tcyc
1
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Section 15 I C Bus Interface 2 (IIC2)
15.7
Usage Notes
15.7.1
Issue (Retransmission) of Start/Stop Conditions
In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing
under the following condition 1 or 2, such conditions may not be output successfully. To avoid
this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check
the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock.
1. When the rising of SCL falls behind the time specified in section 17.6, Bit Synchronous
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
2. When the bit synchronous circuit is activated by extending the low period of eighth and ninth
clocks, that is driven by the slave device
15.7.2
WAIT Setting in I2C Bus Mode Register (ICMR)
If the WAIT bit is set to 1, and the SCL signal is driven low for two or more transfer clocks by the
slave device at the eighth and ninth clocks, the high period of ninth clock may be shortened. To
avoid this, set the WAIT bit in ICMR to 0.
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Section 16 A/D Converter
Section 16 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
16.1.
16.1
•
•
•
•
•
•
•
•
Features
10-bit resolution
Eight input channels
Conversion time: at least 3.5 µs per channel (at 20-MHz operation)
Two operating modes
 Single mode: Single-channel A/D conversion
 Scan mode: Continuous A/D conversion on 1 to 4 channels
Four data registers
 Conversion results are held in a data register for each channel
Sample-and-hold function
Two conversion start methods
 Software
 External trigger signal
Interrupt request
 An A/D conversion end interrupt request (ADI) can be generated
ADCMS32A_000020020200
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Section 16 A/D Converter
Module data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Analog multiplexer
10-bit D/A
Bus interface
Successive approximations
register
AVCC
Internal data bus
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
C
S
R
A
D
C
R
+
φ/4
Control circuit
Comparator
Sample-andhold circuit
ADTRG
[Legend]
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 16.1 Block Diagram of A/D Converter
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φ/8
ADI
interrupt
Section 16 A/D Converter
16.2
Input/Output Pins
Table 16.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are
divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input
pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the
analog block in the A/D converter.
Table 16.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply
Analog input pin 0
AN0
Input
Group 0 analog input
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
A/D external trigger input pin
ADTRG
Input
Group 1 analog input
External trigger input for starting
A/D conversion
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Section 16 A/D Converter
16.3
Register Descriptions
The A/D converter has the following registers.
•
•
•
•
•
•
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
A/D data register D (ADDRD)
A/D control/status register (ADCSR)
A/D control register (ADCR)
16.3.1
A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each analog input
channel, are shown in table 16.2.
The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0.
The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
Therefore byte access to ADDR should be done by reading the upper byte first then the lower one.
Word access is also possible. ADDR is initialized to H'0000.
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register to Be Stored Results of A/D Conversion
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
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Section 16 A/D Converter
16.3.2
A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit
Bit Name
Initial
Value
R/W
Description
7
ADF
0
R/W
A/D End Flag
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends once on all the
channels selected in scan mode
[Clearing condition]
•
6
ADIE
0
R/W
When 0 is written after reading ADF = 1
A/D Interrupt Enable
A/D conversion end interrupt request (ADI) is enabled
by ADF when this bit is set to 1
5
ADST
0
R/W
A/D Start
Setting this bit to 1 starts A/D conversion. In single
mode, this bit is cleared to 0 automatically when
conversion on the specified channel is complete. In
scan mode, conversion continues sequentially on the
specified channels until this bit is cleared to 0 by
software, a reset, or a transition to standby mode.
4
SCAN
0
R/W
Scan Mode
Selects single mode or scan mode as the A/D
conversion operating mode.
0: Single mode
1: Scan mode
3
CKS
0
R/W
Clock Select
Selects the A/D conversions time.
0: Conversion time = 134 states (max.)
1: Conversion time = 70 states (max.)
Clear the ADST bit to 0 before switching the conversion
time.
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Section 16 A/D Converter
Bit
Bit Name
Initial
Value
R/W
Description
2
CH2
0
R/W
Channel Select 2 to 0
1
CH1
0
R/W
Select analog input channels.
0
CH0
0
R/W
When SCAN = 0
When SCAN = 1
000: AN0
000: AN0
001: AN1
001: AN0 and AN1
010: AN2
010: AN0 to AN2
011: AN3
011: AN0 to AN3
100: AN4
100: AN4
101: AN5
101: AN4 and AN5
110: AN6
110: AN4 to AN6
111: AN7
111: AN4 to AN7
16.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit
Bit Name
Initial
Value
R/W
Description
7
TRGE
0
R/W
Trigger Enable
A/D conversion is started at the falling edge and the
rising edge of the external trigger signal (ADTRG)
when this bit is set to 1.
The selection between the falling edge and rising edge
of the external trigger pin (ADTRG) conforms to the
WPEG5 bit in the interrupt edge select register 2
(IEGR2)
6 to 1
—
All 1
—
Reserved
These bits are always read as 1.
0
—
0
R/W
Reserved
Do not set this bit to 1, though the bit is
readable/writable.
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Section 16 A/D Converter
16.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The
ADST bit can be set at the same time as the operating mode or analog input channel is changed.
16.4.1
Single Mode
In single mode, A/D conversion is performed once for the analog input of the specified single
channel as follows:
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
external trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register of the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and the A/D converter enters the wait state.
16.4.2
Scan Mode
In scan mode, A/D conversion is performed sequentially for the analog input of the specified
channels (four channels maximum) as follows:
1. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D
conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt requested is generated. A/D conversion
starts again on the first channel in the group.
4. The ADST bit is not automatically cleared to 0. Steps [2] and [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
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Section 16 A/D Converter
16.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then
starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
tSPL
tCONV
[Legend]
ADCSR write cycle
(1) :
ADCSR address
(2) :
A/D conversion start delay time
tD :
tSPL : Input sampling time
tCONV : A/D conversion time
Figure 16.2 A/D Conversion Timing
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Section 16 A/D Converter
Table 16.3 A/D Conversion Time (Single Mode)
CKS = 0
Item
Symbol
Min
CKS = 1
Typ
Max
Min
Typ
Max
A/D conversion start delay time
tD
6
—
9
4
—
5
Input sampling time
tSPL
—
31
—
—
15
—
A/D conversion time
tCONV
131
—
134
69
—
70
Note: All values represent the number of states.
16.4.4
External Trigger Input Timing
A/D conversion can also be started by an external trigger input. When the TRGE bit in ADCR is
set to 1, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG input
pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, in both single
and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3
shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 16.3 External Trigger Input Timing
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Section 16 A/D Converter
16.5
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 16.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 16.5).
• Nonlinearity error
The deviation from the ideal A/D conversion characteristic as the voltage changes from zero to
full scale. This does not include the offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 16 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
8
2
8
3
8
4
8
5
8
6
8
7 FS
8
Analog
input voltage
Figure 16.4 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 16.5 A/D Conversion Accuracy Definitions (2)
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Section 16 A/D Converter
16.6
Usage Notes
16.6.1
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the
A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;
if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be
possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with
a large capacitance provided externally, the input load will essentially comprise only the internal
input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass
filter effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., 5 mV/µs or greater) (see figure 16.6). When converting a high-speed
analog signal or converting in scan mode, a low-impedance buffer should be inserted.
16.6.2
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI
Sensor output
impedance
up to 5 kΩ
A/D converter
equivalent circuit
10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
Figure 16.6 Analog Input Circuit Example
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20 pF
Section 17 EEPROM
Section 17 EEPROM
The H8/3694N has an on-chip 512-byte EEPROM. The block diagram of the EEPROM is shown
in figure 17.1.
17.1
Features
• Two writing methods:
1-byte write
Page write: Page size 8 bytes
• Three reading methods:
Current address read
Random address read
Sequential read
• Acknowledge polling possible
• Write cycle time:
10 ms (power supply voltage Vcc = 2.7 V or more)
• Write/Erase endurance:
104 cycles/byte (byte write mode), 105 cycles/page (page write mode)
• Data retention:
10 years after the write cycle of 104 cycles (page write mode)
• Interface with the CPU
I2C bus interface (complies with the standard of Philips Corporation)
Device code 1010
Sleep address code can be changed (initial value: 000)
The I2C bus is open to the outside, so the EEPROM can be directly accessed from the outside.
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Section 17 EEPROM
EEPROM Data bus
Y decoder
H'FF10
SDA
SCL
I2C bus interface
control circuit
Y-select/
Sense amp.
Memory
array
User area
(512 bytes)
X decoder
Key control circuit
Address bus
EEPROM Key
register (EKR)
Slave address
register
ESAR
Power-on reset
Booster circuit
EEPROM module
[Legend]
ESAR: Register for referring the slave address
(specifies the slave address of the memory array)
Figure 17.1 Block Diagram of EEPROM
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H'0000
H'01FF
H'FF09
Section 17 EEPROM
17.2
Input/Output Pins
Pins used in the EEPROM are listed in table 17.1.
Table 17.1 Pin Configuration
Pin name
Symbol
Input/Output
Function
Serial clock pin
SCL
Input
The SCL pin is used to control serial input/output
data timing. The data is input at the rising edge of
the clock and output at the falling edge of the clock.
The SCL pin needs to be pulled up by resistor as that
2
pin is open-drain driven structure of the I C pin. Use
proper resistor value for your system by considering
VOL, IOL, and the CIN pin capacitance in section 21.2.2,
DC Characteristics and in section 21.2.3, AC
Characteristics. Maximum clock frequency is 400
kHz.
Serial data pin
SDA
Input/Output
The SDA pin is bidirectional for serial data transfer.
The SDA pin needs to be pulled up by resistor as that
pin is open-drain driven structure. Use proper
resistor value for your system by considering VOL, IOL,
and the CIN pin capacitance in section 21.2.2, DC
Characteristics and in section 21.2.3, AC
Characteristics. Except for a start condition and a
stop condition which will be discussed later, the highto-low and low-to-high change of SDA input should
be done during SCL low periods.
17.3
Register Description
The EEPROM has a following register.
• EEPROM key register (EKR)
17.3.1
EEPROM Key Register (EKR)
EKR is an 8-bit readable/writable register, which changes the slave address code written in the
EEPROM. The slave address code is changed by writing H'5F in EKR and then writing either of
H'00 to H'07 as an address code to the H'FF09 address in the EEPROM by the byte write method.
EKR is initialized to H'FF.
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Section 17 EEPROM
17.4
Operation
17.4.1
EEPROM Interface
The HD64N3694G has a multi-chip structure with two internal chips of the HD64F3694G (FZTAT™ version) and 512-byte EEPROM. The HD6483694G has a multi-chip structure with two
internal chips of the HD6433694G (mask-ROM version) and 512-byte EEPROM.
The EEPROM interface is the I2C bus interface. This I2C bus is open to the outside, so the
communication with the external devices connected to the I2C bus can be made.
17.4.2
Bus Format and Timing
The I2C bus format and the I2C bus timing follow section 15.4.1, I2C Bus Format. The bus formats
specific for the EEPROM are the following two.
1. The EEPROM address is configured of two bytes, the write data is transferred in the order of
upper address and lower address from each MSB side.
2. The write data is transmitted from the MSB side.
The bus format and bus timing of the EEPROM are shown in figure 17.2.
Stop
conditon
Start
condition
Slave address
SCL
1
2
3
4
5
R/W ACK
6
7
8
SDA
9
Upper memory
lower memory
ACK
ACK
address
address
1
8
A15
A8
9
1
8
A7
A0
9
Data
Data
ACK
1
8
D7
D0
9
ACK
1
8
D7
D0
9
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
Figure 17.2 EEPROM Bus Format and Bus Timing
17.4.3
Start Condition
A high-to-low transition of the SDA input with the SCL input high is needed to generate the start
condition for starting read, write operation.
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Section 17 EEPROM
17.4.4
Stop Condition
A low-to-high transition of the SDA input with the SCL input high is needed to generate the stop
condition for stopping read, write operation.
The standby operation starts after a read sequence by a stop condition. In the case of write
operation, a stop condition terminates the write data inputs and place the device in an internallytimed write cycle to the memories. After the internally-timed write cycle (tWC) which is specified
as tWC, the device enters a standby mode.
17.4.5
Acknowledge
All address data and serial data such as read data and write data are transmitted to and from in 8bit unit. The acknowledgement is the signal that indicates that this 8-bit data is normally
transmitted to and from.
In the write operation, EEPROM sends "0" to acknowledge in the ninth cycle after receiving the
data. In the read operation, EEPROM sends a read data following the acknowledgement after
receiving the data. After sending read data, the EEPROM enters the bus open state. If the
EEPROM receives "0" as an acknowledgement, it sends read data of the next address. If the
EEPROM does not receive acknowledgement "0" and receives a following stop condition, it stops
the read operation and enters a standby mode. If the EEPROM receives neither acknowledgement
"0" nor a stop condition, the EEPROM keeps bus open without sending read data.
17.4.6
Slave Addressing
The EEPROM device receives a 7-bit slave address and a 1-bit R/W code following the generation
of the start conditions. The EEPROM enables the chip for a read or a write operation with this
operation.
The slave address consists of a former 4-bit device code and latter 3-bit slave address as shown in
table 17.2. The device code is used to distinguish device type and this LSI uses "1010" fixed code
in the same manner as in a general-purpose EEPROM. The slave address code selects one device
out of all devices with device code 1010 (8 devices in maximum) which are connected to the I2C
bus. This means that the device is selected if the inputted slave address code received in the order
of A2, A1, A0 is equal to the corresponding slave address reference register (ESAR).
The slave address code is stored in the address H'FF09 in the EEPROM. It is transferred to ESAR
from the slave address register in the memory array during 10 ms after the reset is released. An
access to the EEPROM is not allowed during transfer.
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Section 17 EEPROM
The initial value of the slave address code written in the EEPROM is H'00. It can be written in the
range of H'00 to H'07. Be sure to write the data by the byte write method.
The next one bit of the slave address is the R/W code. 0 is for a write and 1 is for a read.
The EEPROM turns to a standby state if the device code is not "1010" or slave address code
doesn’t coincide.
Table 17.2 Slave Addresses
Bit
Bit name
Initial
Value
Setting
Value
7
Device code D3

1
6
Device code D2

0
5
Device code D1

1
4
Device code D0

0
3
Slave address code A2 0
A2
The initial value can be changed
2
Slave address code A1 0
A1
The initial value can be changed
1
Slave address code A0 0
A0
The initial value can be changed
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Remarks
Section 17 EEPROM
17.4.7
Write Operations
There are two types write operations; byte write operation and page write operation. To initiate
the write operation, input 0 to R/W code following the slave address.
1. Byte Write
A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then
the EEPROM sends acknowledgement "0" at the ninth bit. This enters the write mode. Then,
two bytes of the memory address are received from the MSB side in the order of upper and
lower. Upon receipt of one-byte memory address, the EEPROM sends acknowledgement "0"
and receives a following a one-byte write data. After receipt of write data, the EEPROM sends
acknowledgement "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally controlled write cycle and terminates receipt of SCL and SDA inputs until
completion of the write cycle. The EEPROM returns to a standby mode after completion of
the write cycle.
The byte write operation is shown in figure 17.3.
SCL
1
2
3
4
5
6
7
8
9
SDA
R/W ACK
Slave address
1
8
A15
A8
Upper memory
address
9
ACK
1
8
A7
A0
lower memory
address
9
ACK
1
8
D7
D0
Write Data
9
ACK
Stop
conditon
Start
condition
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Figure 17.3 Byte Write Operation
2. Page Write
This LSI is capable of the page write operation which allows any number of bytes up to 8 bytes
to be written in a single write cycle. The write data is input in the same sequence as the byte
write in the order of a start condition, slave address + R/W code, memory address (n), and
write data (Dn) with every ninth bit acknowledgement "0" output. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) is input instead of
receiving a stop condition after receiving the write data (Dn). LSB 3 bits (A2 to A0) in the
EEPROM address are automatically incremented to be the (n+1) address upon receiving write
data (Dn+1). Thus the write data can be received sequentially.
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Section 17 EEPROM
Addresses in the page are incremented at each receipt of the write data and the write data can
be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last
address of the page, the address will roll over to the first address of the same page. When the
address is rolled over, write data is received twice or more to the same address, however, the
last received data is valid. At the receipt of the stop condition, write data reception is
terminated and the write operation is entered.
The page write operation is shown in figure 17.4.
SCL
1
2
3
4
5
6
7
8
9
SDA
Slave address
R/W ACK
1
8
A15
A8
9
1
8
A7
A0
9
1
8
D7
D0
Upper memory
lower memory
ACK
ACK Write Data
address
address
9
D7
ACK
D0
Write Data ACK
Stop
conditon
Start
condition
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
Figure 17.4 Page Write Operation
17.4.8
Acknowledge Polling
Acknowledge polling feature is used to show if the EEPROM is in an internally-timed write cycle
or not. This feature is initiated by the input of the 8-bit slave address + R/W code following the
start condition during an internally-timed write cycle. Acknowledge polling will operate R/W
code = "0". The ninth acknowledgement judges if the EEPROM is an internally-timed write cycle
or not. Acknowledgement "1" shows the EEPROM is in a internally-timed write cycle and
acknowledgement "0" shows the internally-timed write cycle has been completed. The
acknowledge polling starts to function after a write data is input, i.e., when the stop condition is
input.
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Section 17 EEPROM
17.4.9
Read Operation
There are three read operations; current address read, random address read, and sequential read.
Read operations are initiated in the same way as write operations with the exception of R/W = 1.
1. Current Address Read
The internal address counter maintains the (n+1) address that is made by the last address (n)
accessed during the last read or write operation, with incremented by one. Current address
read accesses the (n+1) address kept by the internal address counter.
After receiving in the order of a start condition and the slave address + R/W code (R/W = 1),
the EEPROM outputs the 1-byte data of the (n+1) address from the most significant bit
following acknowledgement "0". If the EEPROM receives in the order of acknowledgement
"1" and a following stop condition, the EEPROM stops the read operation and is turned to a
standby state.
In case the EEPROM has accessed the last address H'01FF at previous read operation, the
current address will roll over and returns to zero address. In case the EEPROM has accessed
the last address of the page at previous write operation, the current address will roll over within
page addressing and returns to the first address in the same page.
The current address is valid while power is on. The current address after power on will be
undefined. After power is turned on, define the address by the random address read operation
described below is necessary.
The current address read operation is shown in figure 17.5.
SCL
1
2
3
4
5
6
7
8
9
SDA
Slave address
R/W ACK
1
8
D7
D0
Read Data
9
ACK
Stop
conditon
Start
condition
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Figure 17.5 Current Address Read Operation
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Section 17 EEPROM
2. Random Address Read
This is a read operation with defined read address. A random address read requires a dummy
write to set read address. The EEPROM receives a start condition, slave address + R/W code
(R/W = 0), memory address (upper) and memory address (lower) sequentially. The EEPROM
outputs acknowledgement "0" after receiving memory address (lower) then enters a current
address read with receiving a start condition again. The EEPROM outputs the read data of the
address which was defined in the dummy write operation. After receiving acknowledgement
"1" and a following stop condition, the EEPROM stops the random read operation and returns
to a standby state.
The random address read operation is shown in figure 17.6.
SCL
1
2
3
4
5
6
7
8
9
SDA
Slave address
R/W ACK
1
8
A15
A8
9
1
8
A7
A0
9
1
Upper memory
lower memory
ACK
ACK
address
address
Start
condition
2
3
4
5
6
Slave address
Start
condition
7
8
9
R ACK
1
8
D7
D0
Read Data
9
ACK
Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
Figure 17.6 Random Address Read Operation
3. Sequential Read
This is a mode to read the data sequentially. Data is sequential read by either a current address
read or a random address read. If the EEPROM receives acknowledgement "0" after 1-byte
read data is output, the read address is incremented and the next 1-byte read data are coming
out. Data is output sequentially by incrementing addresses as long as the EEPROM receives
acknowledgement "0" after the data is output. The address will roll over and returns address
zero if it reaches the last address H'01FF. The sequential read can be continued after roll over.
The sequential read is terminated if the EEPROM receives acknowledgement "1" and a
following stop condition as the same manner as in the random address read.
The condition of a sequential read when the current address read is used is shown in figure
17.7.
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Section 17 EEPROM
SCL
1
2
3
4
5
6
7
8
9
SDA
Slave address
R/W ACK
1
8
9
D7
D0
Read Data ACK
· · · ·
1
8
D7
D0
Read Data
9
ACK
Start
condition
Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Figure 17.7 Sequential Read Operation (when current address read is used)
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Section 17 EEPROM
17.5
Usage Notes
17.5.1
Data Protection at VCC On/Off
When VCC is turned on or off, the data might be destroyed by malfunction. Be careful of the
notices described below to prevent the data to be destroyed.
1. SCL and SDA should be fixed to VCC or VSS during VCC on/off.
2. VCC should be turned off after the EEPROM is placed in a standby state.
3. When VCC is turned on from the intermediate level, malfunction is caused, so VCC should be
turned on from the ground level (VSS).
4. VCC turn on speed should be longer than 10 us.
17.5.2
Write/Erase Endurance
The endurance is 105 cycles/page (1% cumulative failure rate) in case of page programming and
104 cycles/byte in case of byte programming. The data retention time is more than 10 years when a
device is page-programmed less than 104 cycles.
17.5.3
Noise Suppression Time
This EEPROM has a noise suppression function at SCL and SDA inputs, that cuts noise of width
less than 50 ns. Be careful not to allow noise of width more than 50 ns because the noise of with
more than 50 ms is recognized as an active pulse.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Section 18 Power-On Reset and Low-Voltage Detection
Circuits (Optional)
This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits.
The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect)
and LVDR (reset by low voltage detect) circuits.
This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the
power supply voltage fall and to recreate the state before the power supply voltage fall when the
power supply voltage rises again.
Even if the power supply voltage falls, the unstable state when the power supply voltage falls
below the guaranteed operating voltage can be removed by entering standby mode when
exceeding the guaranteed operating voltage and during normal operation. Thus, system stability
can be improved. If the power supply voltage falls more, the reset state is automatically entered. If
the power supply voltage rises again, the reset state is held for a specified period, then active mode
is automatically entered.
Figure 18.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
18.1
Features
• Power-on reset circuit
Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit
LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the
voltage falls below a specified value.
LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls
below or rises above respective specified values.
Two pairs of detection levels for reset generation voltage are available: when only the LVDR
circuit is used, or when the LVDI and LVDR circuits are both used.
LVI0000A_000020030300
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
φ
CK
R
OVF
PSS
R
RES
Internal reset
signal
Q
Noise canceler
S
CRES
Power-on reset circuit
Noise canceler
Vcc
Ladder
resistor
Internal data bus
LVDCR
Vreset
+
−
Vint
LVDRES
+
−
LVDINT
Interrupt
control
circuit
LVDSR
Reference
voltage
generator
Interrupt
request
Low-voltage detection circuit
[Legend]
PSS:
LVDCR:
LVDSR:
LVDRES:
LVDINT:
Vreset:
Vint:
Prescaler S
Low-voltage-detection control register
Low-voltage-detection status register
Low-voltage-detection reset signal
Low-voltage-detection interrupt signal
Reset detection voltage
Power-supply fall/rise detection voltage
Figure 18.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
18.2
Register Descriptions
The low-voltage detection circuit has the following registers.
• Low-voltage-detection control register (LVDCR)
• Low-voltage-detection status register (LVDSR)
18.2.1
Low-Voltage-Detection Control Register (LVDCR)
LVDCR is used to enable or disable the low-voltage detection circuit, set the detection levels for
the LVDR function, enable or disable the LVDR function, and enable or disable generation of an
interrupt when the power-supply voltage rises above or falls below the respective levels.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Table 18.1 shows the relationship between the LVDCR settings and select functions. LVDCR
should be set according to table 18.1.
Bit
Bit Name
Initial
Value
R/W
Description
7
LVDE
0*
R/W
LVD Enable
0: The low-voltage detection circuit is not used (In
standby mode)
1: The low-voltage detection circuit is used

6 to 4
All 1

Reserved
These bits are always read as 1, and cannot be modified.
3
LVDSEL
0*
R/W
LVDR Detection Level Select
0: Reset detection voltage is 2.3 V (typ.)
1: Reset detection voltage is 3.6 V (typ.)
When the falling or rising voltage detection interrupt is
used, reset detection voltage of 2.3 V (typ.) should be
used. When only a reset detection interrupt is used, reset
detection voltage of 3.6 V (typ.) should be used.
2
LVDRE
0*
R/W
LVDR Enable
0: Disables the LVDR function
1: Enables the LVDR function
1
LVDDE
0
R/W
Voltage-Fall-Interrupt Enable
0: Interrupt on the power-supply voltage falling below the
selected detection level disabled
1: Interrupt on the power-supply voltage falling below the
selected detection level enabled
0
LVDUE
0
R/W
Voltage-Rise-Interrupt Enable
0: Interrupt on the power-supply voltage rising above the
selected detection level disabled
1: Interrupt on the power-supply voltage rising above the
selected detection level enabled
Note:
*
Not initialized by LVDR but initialized by a power-on reset or WDT reset.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Table 18.1 LVDCR Settings and Select Functions
LVDCR Settings
Select Functions
LVDE
LVDSEL
LVDRE
LVDDE
LVDUE
Power-On
Reset
LVDR
Low-VoltageDetection
Falling
Interrupt
0
*
*
*
*
O



1
1
1
0
0
O
O


1
0
0
1
0
O

O

1
0
0
1
1
O

O
O
1
0
1
1
1
O
O
O
O
Legend:
18.2.2
Low-VoltageDetection
Rising
Interrupt
*: means invalid.
Low-Voltage-Detection Status Register (LVDSR)
LVDSR indicates whether the power-supply voltage falls below or rises above the respective
specified values.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 2

All 1

Reserved
These bits are always read as 1, and cannot be modified.
1
LVDDF
0*
R/W
LVD Power-Supply Voltage Fall Flag
[Setting condition]
When the power-supply voltage falls below Vint (D) (typ.
= 3.7 V)
[Clearing condition]
Writing 0 to this bit after reading it as 1
0
LVDUF
0*
R/W
LVD Power-Supply Voltage Rise Flag
[Setting condition]
When the power supply voltage falls below Vint (D) while
the LVDUE bit in LVDCR is set to 1, then rises above Vint
(U) (typ. = 4.0 V) before falling below Vreset1 (typ. = 2.3
V)
[Clearing condition]
Writing 0 to this bit after reading it as 1
Note:
*
Initialized by LVDR.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
18.3
Operation
18.3.1
Power-On Reset Circuit
Figure 18.2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the on-chip pull-up resistor (typ. 150 kΩ). Since the state of the RES pin is transmitted within the
chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin
reaches the specified value, the prescaler S is released from its reset state and it starts counting.
The OVF signal is generated to release the internal reset signal after the prescaler S has counted
131,072 clock (φ) cycles. The noise cancellation circuit of approximately 100 ns is incorporated to
prevent the incorrect operation of the chip by noise on the RES pin.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle after
power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance
which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power
supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) ≤ 90 × CRES (µF) + 162/fOSC (MHz)
(tPWON ≤ 3000 ms, CRES ≥ 0.22 µF, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
tPWON
Vcc
Vpor
Vss
RES
Vss
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 18.2 Operational Timing of Power-On Reset Circuit
18.3.2
Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit:
Figure 18.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 50 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have
stabilized by a software timer, etc., then set the LVDRE bit in LVDCR to 1. After that, the output
settings of ports must be made. To cancel the low-voltage detection circuit, first the LVDRE bit
should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and LVDRE bits
must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.6 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (φ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
VCC
Vreset
VLVDRmin
VSS
LVDRES
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 18.3 Operational Timing of LVDR Circuit
LVDI (Interrupt by Low Voltage Detect) Circuit:
Figure 18.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50
µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized
by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the
output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0.
The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode or subsleep
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
Rev.5.00 Nov. 02, 2005 Page 295 of 418
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously
generated.
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function
is performed.
Vint (U)
Vint (D)
Vcc
Vreset1
VSS
LVDINT
LVDDE
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 18.4 Operational Timing of LVDI Circuit
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Procedures for Clearing Settings when Using LVDR and LVDI:
To operate or release the low-voltage detection circuit normally, follow the procedure described
below. Figure 18.5 shows the timing for the operation and release of the low-voltage detection
circuit.
1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1.
2. Wait for 50 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply
have stabilized by a software timer, etc. Then, clear the LVDDF and LVDUF bits in LVDSR
to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, as required.
3. To release the low-voltage detection circuit, start by clearing all of the LVDRE, LVDDE, and
LVDUE bits to 0. Then clear the LVDE bit to 0. The LVDE bit must not be cleared to 0 at the
same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 18.5 Timing for Operation/Release of Low-Voltage Detection Circuit
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Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Rev.5.00 Nov. 02, 2005 Page 298 of 418
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Section 19 Power Supply Circuit
Section 19 Power Supply Circuit
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the
voltage of the power supply connected to the external VCC pin. As a result, the current consumed
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the
internal voltage will be practically the same as the external voltage. It is, of course, also possible to
use the same level of external power supply voltage and internal power supply voltage without
using the internal power supply step-down circuit.
19.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF between VCL and VSS, as shown in figure 19.1. The internal step-down circuit is made effective
simply by adding this external circuit. In the external circuit interface, the external power supply
voltage connected to VCC and the GND potential connected to VSS are the reference levels. For
example, for port input/output levels, the VCC level is the reference for the high level, and the VSS
level is that for the low level. The A/D converter analog power supply is not affected by the
internal step-down circuit.
VCC
Step-down circuit
Internal
logic
VCC = 3.0 to 5.5 V
VCL
Stabilization
capacitance
(approx. 0.1 µF)
Internal
power
supply
VSS
Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used
PSCKT00A_000020020200
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Section 19 Power Supply Circuit
19.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the VCL pin and VCC pin, as shown in figure 19.2. The external power supply is then input directly
to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V.
Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V)
is input.
VCC
Step-down circuit
Internal
logic
VCC = 3.0 to 3.6 V
VCL
Internal
power
supply
VSS
Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
Rev.5.00 Nov. 02, 2005 Page 300 of 418
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Section 20 List of Registers
Section 20 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• The symbol  in the register-name column represents a reserved address or range of reserved
addresses.
Do not attempt to access reserved addresses.
• When the address is 16-bit wide, the address of the upper byte is given in the list.
• Registers are classified by functional modules.
• The data bus width is indicated.
• The number of access states is indicated.
2.
•
•
•
Register bits
Bit configurations of the registers are described in the same order as the register addresses.
Reserved bits are indicated by  in the bit name column.
When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev.5.00 Nov. 02, 2005 Page 301 of 418
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Section 20 List of Registers
20.1
Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Data
Bus
Width
Access
State
—
—
LVDC*1
8
2
LVDC*1
8
2
H'F732 to —
H'F747
—
—
Register Name
Abbreviation
Bit
No
—
—
—
H'F000 to —
H'F72F
Low-voltage detection control
register
LVDCR
8
H'F730
Low-voltage detection status register LVDSR
8
H'F731
—
—
—
I2C bus control register 1
Address
Module
Name
ICCR1
8
H'F748
IIC2
8
2
2
ICCR2
8
H'F749
IIC2
8
2
2
ICMR
8
H'F74A
IIC2
8
2
2
ICIER
8
H'F74B
IIC2
8
2
2
I C bus status register
ICSR
8
H'F74C
IIC2
8
2
Slave address register
SAR
8
H'F74D
IIC2
8
2
I C bus transmit data register
ICDRT
8
H'F74E
IIC2
8
2
I2C bus receive data register
ICDRR
8
H'F74F
IIC2
8
2
—
—
—
H'F750 to —
H'FF7F
—
—
Timer mode register W
TMRW
8
H'FF80
Timer W
8
2
Timer control register W
TCRW
8
H'FF81
Timer W
8
2
Timer interrupt enable register W
TIERW
8
H'FF82
Timer W
8
2
Timer status register W
TSRW
8
H'FF83
Timer W
8
2
Timer I/O control register 0
TIOR0
8
H'FF84
Timer W
8
2
Timer I/O control register 1
TIOR1
8
H'FF85
Timer W
8
I C bus control register 2
I C bus mode register
I C bus interrupt enable register
2
Timer counter
General register A
Rev.5.00 Nov. 02, 2005 Page 302 of 418
REJ09B0028-0500
TCNT
GRA
16
16
H'FF86
H'FF88
Timer W
Timer W
2
2
2
2
2
16*
16*
Section 20 List of Registers
Register Name
Abbreviation
Bit
No
General register B
GRB
16
General register C
GRC
16
16
Address
Module
Name
Data
Bus
Width
Access
State
H'FF8A
Timer W
16*2
2
Timer W
2
2
H'FF8C
16*
2
General register D
GRD
H'FF8E
Timer W
16*
2
Flash memory control register 1
FLMCR1 8
H'FF90
ROM
8
2
Flash memory control register 2
FLMCR2 8
H'FF91
ROM
8
2
Flash memory power control register FLPWCR 8
H'FF92
ROM
8
2
Erase block register 1
EBR1
8
H'FF93
ROM
8
2
—
—
—
H'FF94 to —
H'FF9A
—
—
Flash memory enable register
FENR
8
H'FF9B
8
2
—
—
—
H'FF9C to —
H'FF9F
—
—
Timer control register V0
TCRV0
8
H'FFA0
Timer V
8
3
Timer control/status register V
TCSRV
8
H'FFA1
Timer V
8
3
Timer constant register A
TCORA
8
H'FFA2
Timer V
8
3
Timer constant register B
TCORB
8
H'FFA3
Timer V
8
3
ROM
Timer counter V
TCNTV
8
H'FFA4
Timer V
8
3
Timer control register V1
TCRV1
8
H'FFA5
Timer V
8
3
Timer mode register A
TMA
8
H'FFA6
Timer A
8
2
Timer counter A
TCA
8
H'FFA7
Timer A
8
2
Serial mode register
SMR
8
H'FFA8
SCI3
8
3
Bit rate register
BRR
8
H'FFA9
SCI3
8
3
Serial control register 3
SCR3
8
H'FFAA
SCI3
8
3
Transmit data register
TDR
8
H'FFAB
SCI3
8
3
Serial status register
SSR
8
H'FFAC
SCI3
8
3
Receive data register
RDR
8
H'FFAD
SCI3
8
3
—
—
—
H'FFAE,
H'FFAF
—
—
—
A/D data register A
ADDRA
16
H'FFB0
A/D
converter
8
3
Rev.5.00 Nov. 02, 2005 Page 303 of 418
REJ09B0028-0500
Section 20 List of Registers
Data
Bus
Width
Access
State
A/D
converter
8
3
H'FFB4
A/D
converter
8
3
16
H'FFB6
A/D
converter
8
3
ADCSR
8
H'FFB8
A/D
converter
8
3
A/D control register
ADCR
8
H'FFB9
A/D
converter
8
3
—
—
—
H'FFBA to —
H'FFBF
—
—
Timer control/status register WD
TCSRW
D
8
H'FFC0
WDT*3
8
2
Timer counter WD
TCWD
8
H'FFC1
WDT*3
8
2
3
Register Name
Abbreviation
Bit
No
Address
A/D data register B
ADDRB
16
H'FFB2
A/D data register C
ADDRC
16
A/D data register D
ADDRD
A/D control/status register
Module
Name
Timer mode register WD
TMWD
8
H'FFC2
WDT*
8
2
—
—
—
H'FFC3
—
—
—
—
—
—
H'FFC4 to —
H'FFC7
—
—
Address break control register
ABRKCR 8
H'FFC8
Address
break
8
2
Address break status register
ABRKSR 8
H'FFC9
Address
break
8
2
Break address register H
BARH
8
H'FFCA
Address
break
8
2
Break address register L
BARL
8
H'FFCB
Address
break
8
2
Break data register H
BDRH
8
H'FFCC
Address
break
8
2
Break data register L
BDRL
8
H'FFCD
Address
break
8
2
—
—
—
H'FFCE,
H'FFCF
—
—
—
Rev.5.00 Nov. 02, 2005 Page 304 of 418
REJ09B0028-0500
Section 20 List of Registers
Address
Module
Name
Data
Bus
Width
Access
State
8
H'FFD0
I/O port
8
2
PUCR5
8
H'FFD1
I/O port
8
2
—
—
—
H'FFD2,
H'FFD3
I/O port
—
—
Port data register 1
PDR1
8
H'FFD4
I/O port
8
2
Port data register 2
PDR2
8
H'FFD5
I/O port
8
2
—
—
8
H'FFD6,
H'FFD7
I/O port
—
—
Register Name
Abbreviation
Bit
No
Port pull-up control register 1
PUCR1
Port pull-up control register 5
Port data register 5
PDR5
8
H'FFD8
I/O port
8
2
—
—
—
H'FFD9
I/O port
—
—
Port data register 7
PDR7
8
H'FFDA
I/O port
8
2
Port data register 8
PDR8
8
H'FFDB
I/O port
8
2
—
—
—
H'FFDC
I/O port
—
—
Port data register B
PDRB
8
H'FFDD
I/O port
8
2
—
—
—
H'FFDE,
H'FFDF
I/O port
—
—
Port mode register 1
PMR1
8
H'FFE0
I/O port
8
2
Port mode register 5
PMR5
8
H'FFE1
I/O port
8
2
—
—
—
H'FFE2,
H'FFE3
I/O port
—
—
Port control register 1
PCR1
8
H'FFE4
I/O port
8
2
Port control register 2
PCR2
8
H'FFE5
I/O port
8
2
—
—
—
H'FFE6,
H'FFE7
I/O port
—
—
Port control register 5
PCR5
8
H'FFE8
I/O port
8
2
—
—
—
H'FFE9
I/O port
—
—
Port control register 7
PCR7
8
H'FFEA
I/O port
8
2
Port control register 8
PCR8
8
H'FFEB
I/O port
8
2
—
—
—
H'FFEC to I/O port
H'FFEF
—
—
Rev.5.00 Nov. 02, 2005 Page 305 of 418
REJ09B0028-0500
Section 20 List of Registers
Bit
No
Address
Module
Name
Data
Bus
Access
Width State
Register Name
Abbreviation
System control register 1
SYSCR1 8
H'FFF0
Power-down
8
2
System control register 2
SYSCR2 8
H'FFF1
Power-down
8
2
Interrupt edge select register 1
IEGR1
8
H'FFF2
Interrupts
8
2
Interrupt edge select register 2
IEGR2
8
H'FFF3
Interrupts
8
2
Interrupt enable register 1
IENR1
8
H'FFF4
Interrupts
8
2
—
—
—
H'FFF5
I/O port
—
—
Interrupt flag register 1
IRR1
8
H'FFF6
Interrupts
8
2
—
—
—
H'FFE7
I/O port
—
—
Wake-up interrupt flag register
IWPR
8
H'FFF8
Interrupts
8
2
Module standby control register 1
MSTCR1 8
H'FFF9
Power-down
8
2
—
—
H'FFFA to —
H'FFFF
—
—
—
• EEPROM
Address
Module
Name
Data
Bus
Access
Width State
8
H'FF09
EEPROM
—
—
8
H'FF10
EEPROM
—
—
Register Name
Abbreviation
Bit
No
EEPROM slave address register
—
EEPROM key register
EKR
Notes: 1. LVDC: Low-voltage detection circuits (optional)
2. Only word access can be used.
3. WDT: Watchdog timer
Rev.5.00 Nov. 02, 2005 Page 306 of 418
REJ09B0028-0500
Section 20 List of Registers
20.2
Register Bits
The addresses and bit names of the registers in the on-chip peripheral modules are listed below.
The 16-bit register is indicated in two rows, 8 bits for each row.
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
—
—
—
—
—
—
—
—
—
—
LVDCR
LVDE
—
—
—
LVDSEL LVDRE
LVDDE
LVDUE
LVDC
LVDSR
—
—
—
—
—
—
LVDDF
LVDUF
(optional)*
—
—
—
—
—
—
—
—
—
—
IIC2
1
ICCR1
ICE
RCVD
MST
TRS
CKS3
CKS2
CKS1
CKS0
ICCR2
BBSY
SCP
SDAO
SDAOP
SCKO
—
IICRST
—
ICMR
MLS
WAIT
—
—
BCWP
BC2
BC1
BC0
ICIER
TIE
TEIE
RIE
NAKIE
STIE
ACKE
ACKBR
ACKBT
ICSR
TDRE
TEND
RDRF
NACKF
STOP
AL/OVE
AAS
ADZ
SAR
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
ICDRT
ICDRT7
ICDRT6
ICDRT5
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
ICDRR
ICDRR7
ICDRR6
ICDRR5
ICDRR4
ICDRR3
ICDRR2
ICDRR1
ICDRR0
—
—
—
—
—
—
—
—
—
—
TMRW
CTS
—
BUFEB
BUFEA
—
PWMD
PWMC
PWMB
Timer W
TCRW
CCLR
CKS2
CKS1
CKS0
TOD
TOC
TOB
TOA
TIERW
OVIE
—
—
—
IMIED
IMIEC
IMIEB
IMIEA
TSRW
OVF
—
—
—
IMFD
IMFC
IMFB
IMFA
TIOR0
—
IOB2
IOB1
IOB0
—
IOA2
IOA1
IOA0
TIOR1
—
IOD2
IOD1
IOD0
—
IOC2
IOC1
IOC0
TCNT
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9
GRA
GRB
GRC
GRD
TCNT8
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
GRA15
GRA14
GRA13
GRA12
GRA11
GRA10
GRA9
GRA8
GRA7
GRA6
GRA5
GRA4
GRA3
GRA2
GRA1
GRA0
GRB15
GRB14
GRB13
GRB12
GRB11
GRB10
GRB9
GRB8
GRB7
GRB6
GRB5
GRB4
GRB3
GRB2
GRB1
GRB0
GRC15
GRC14
GRC13
GRC12
GRC11
GRC10
GRC9
GRC8
GRC7
GRC6
GRC5
GRC4
GRC3
GRC2
GRC1
GRC0
GRD15
GRD14
GRD13
GRD12
GRD11
GRD10
GRD9
GRD8
GRD7
GRD6
GRD5
GRD4
GRD3
GRD2
GRD1
GRD0
Rev.5.00 Nov. 02, 2005 Page 307 of 418
REJ09B0028-0500
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
ROM
FLMCR2
FLER
—
—
—
—
—
—
—
FLPWCR
PDWND —
—
—
—
—
—
—
EBR1
—
—
—
EB4
EB3
EB2
EB1
EB0
FENR
FLSHE
—
—
—
—
—
—
—
TCRV0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
TCSRV
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
TCORA
TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0
TCORB
TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0
TCNTV
TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0
TCRV1
—
—
—
TVEG1
TVEG0
TRGE
—
ICKS0
TMA
TMA7
TMA6
TMA5
—
TMA3
TMA2
TMA1
TMA0
TCA
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
SMR
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
BRR
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
SCR3
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
RDR
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
ADDRA
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
ADDRB
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
ADDRC
Timer V
Timer A
SCI3
A/D
converter
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
ADDRD
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
ADCSR
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
ADCR
TRGE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCSRWD B6WI
TCWE
B4WI
TCSRW
E
B2WI
WDON
B0WI
WRST
WDT*2
TCWD
TCWD6
TCWD5
TCWD4
TCWD3
TCWD2
TCWD1
TCWD0
TCWD7
Rev.5.00 Nov. 02, 2005 Page 308 of 418
REJ09B0028-0500
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
TMWD
—
—
—
—
CKS3
CKS2
CKS1
CKS0
WDT*2
—
—
—
—
—
—
—
—
—
—
ABRKCR
RTINTE
CSEL1
CSEL0
ACMP2
ACMP1
ACMP0
DCMP1
DCMP0
Address
break
ABRKSR
ABIF
ABIE
—
—
—
—
—
—
BARH
BARH7
BARH6
BARH5
BARH4
BARH3
BARH2
BARH1
BARH0
BARL
BARL7
BARL6
BARL5
BARL4
BARL3
BARL2
BARL1
BARL0
BDRH
BDRH7
BDRH6
BDRH5
BDRH4
BDRH3
BDRH2
BDRH1
BDRH0
BDRL
BDRL7
BDRL6
BDRL5
BDRL4
BDRL3
BDRL2
BDRL1
BDRL0
—
—
—
—
—
—
—
—
—
PUCR1
PUCR17 PUCR16 PUCR15 PUCR14 —
PUCR5
—
—
PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PDR1
P17
P16
P15
P14
—
P12
P11
P10
PDR2
—
—
—
—
—
P22
P21
P20
PDR5
P57*
P56*
P55
P54
P53
P52
P51
P50
PDR7
—
P76
P75
P74
—
—
—
—
PDR8
P87
P86
P85
P84
P83
P82
P81
P80
3
—
PUCR12 PUCR11 PUCR10 I/O port
3
PDRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PMR1
IRQ3
IRQ2
IRQ1
IRQ0
—
—
TXD
TMOW
PMR5
—
—
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
PCR1
PCR17
PCR16
PCR15
PCR14
—
PCR12
PCR11
PCR10
PCR2
—
—
—
—
—
PCR22
PCR21
PCR20
PCR5
PCR57*
PCR56*
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
PCR7
—
PCR76
PCR75
PCR74
—
—
—
—
PCR8
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
SYSCR1
SSBY
STS2
STS1
STS0
NESEL
—
—
—
SYSCR2
SMSEL
LSON
DTON
MA2
MA1
MA0
SA1
SA0
IEGR1
NMIEG
—
—
—
IEG3
IEG2
IEG1
IEG0
IEGR2
—
—
WPEG5
WPEG4
WPEG3
WPEG2
WPEG1
WPEG0
IENR1
IENDT
IENTA
IENWP
—
IEN3
IEN2
IEN1
IEN0
IRR1
IRRDT
IRRTA
—
—
IRRI3
IRRI2
IRRI1
IRRI0
IWPR
—
—
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
MSTCR1
—
MSTIIC
MSTS3
MSTAD
MSTWD MSTTW
MSTTV
MSTTA
Power-down
—
—
—
—
—
—
—
—
—
3
3
—
Power-down
Interrupts
Rev.5.00 Nov. 02, 2005 Page 309 of 418
REJ09B0028-0500
Section 20 List of Registers
• EEPROM
Register
Name
Bit 7
Bit 6
Bit 5
EKR
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
EEPROM
Notes: 1. LVDC: Low-voltage detection circuits (optional)
2. WDT: Watchdog timer
TM
3. These bits are reserved in the EEPROM stacked F-ZTAT and mask-ROM versions.
Rev.5.00 Nov. 02, 2005 Page 310 of 418
REJ09B0028-0500
Section 20 List of Registers
20.3
Registers States in Each Operating Mode
Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
LVDCR
Initialized
—
—
—
—
—
LVDC
LVDSR
Initialized
—
—
—
—
—
(optional)*
ICCR1
Initialized
—
—
—
—
—
IIC2
ICCR2
Initialized
—
—
—
—
—
ICMR
Initialized
—
—
—
—
—
ICIER
Initialized
—
—
—
—
—
ICSR
Initialized
—
—
—
—
—
SAR
Initialized
—
—
—
—
—
ICDRT
Initialized
—
—
—
—
—
ICDRR
Initialized
—
—
—
—
—
TMRW
Initialized
—
—
—
—
—
TCRW
Initialized
—
—
—
—
—
TIERW
Initialized
—
—
—
—
—
TSRW
Initialized
—
—
—
—
—
TIOR0
Initialized
—
—
—
—
—
TIOR1
Initialized
—
—
—
—
—
TCNT
Initialized
—
—
—
—
—
GRA
Initialized
—
—
—
—
—
GRB
Initialized
—
—
—
—
—
GRC
Initialized
—
—
—
—
—
GRD
Initialized
—
—
—
—
—
FLMCR1
Initialized
—
—
Initialized
Initialized
Initialized
FLMCR2
Initialized
—
—
—
—
—
FLPWCR
Initialized
—
—
—
—
—
EBR1
Initialized
—
—
Initialized
Initialized
Initialized
FENR
Initialized
—
—
—
—
—
TCRV0
Initialized
—
—
Initialized
Initialized
Initialized
TCSRV
Initialized
—
—
Initialized
Initialized
Initialized
TCORA
Initialized
—
—
Initialized
Initialized
Initialized
TCORB
Initialized
—
—
Initialized
Initialized
Initialized
1
Timer W
ROM
Timer V
Rev.5.00 Nov. 02, 2005 Page 311 of 418
REJ09B0028-0500
Section 20 List of Registers
Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
TCNTV
Initialized
—
—
Initialized
Initialized
Initialized
Timer V
TCRV1
Initialized
—
—
Initialized
Initialized
Initialized
TMA
Initialized
—
—
—
—
—
TCA
Initialized
—
—
—
—
—
SMR
Initialized
—
—
Initialized
Initialized
Initialized
BRR
Initialized
—
—
Initialized
Initialized
Initialized
SCR3
Initialized
—
—
Initialized
Initialized
Initialized
TDR
Initialized
—
—
Initialized
Initialized
Initialized
SSR
Initialized
—
—
Initialized
Initialized
Initialized
RDR
Initialized
—
—
Initialized
Initialized
Initialized
ADDRA
Initialized
—
—
Initialized
Initialized
Initialized
ADDRB
Initialized
—
—
Initialized
Initialized
Initialized
ADDRC
Initialized
—
—
Initialized
Initialized
Initialized
ADDRD
Initialized
—
—
Initialized
Initialized
Initialized
ADCSR
Initialized
—
—
Initialized
Initialized
Initialized
ADCR
Initialized
—
—
Initialized
Initialized
Initialized
TCSRWD Initialized
—
—
—
—
—
TCWD
Initialized
—
—
—
—
—
TMWD
Initialized
—
—
—
—
—
ABRKCR
Initialized
—
—
—
—
—
ABRKSR
Initialized
—
—
—
—
—
BARH
Initialized
—
—
—
—
—
BARL
Initialized
—
—
—
—
—
BDRH
Initialized
—
—
—
—
—
BDRL
Initialized
—
—
—
—
—
PUCR1
Initialized
—
—
—
—
—
PUCR5
Initialized
—
—
—
—
—
PDR1
Initialized
—
—
—
—
—
PDR2
Initialized
—
—
—
—
—
PDR5
Initialized
—
—
—
—
—
PDR7
Initialized
—
—
—
—
—
PDR8
Initialized
—
—
—
—
—
PDRB
Initialized
—
—
—
—
—
Rev.5.00 Nov. 02, 2005 Page 312 of 418
REJ09B0028-0500
Timer A
SCI3
A/D converter
2
WDT*
Address Break
I/O port
Section 20 List of Registers
Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
PMR1
Initialized
—
—
—
—
—
I/O port
PMR5
Initialized
—
—
—
—
—
PCR1
Initialized
—
—
—
—
—
PCR2
Initialized
—
—
—
—
—
PCR5
Initialized
—
—
—
—
—
PCR7
Initialized
—
—
—
—
—
PCR8
Initialized
—
—
—
—
—
SYSCR1
Initialized
—
—
—
—
—
Power-down
SYSCR2
Initialized
—
—
—
—
—
Power-down
IEGR1
Initialized
—
—
—
—
—
Interrupts
IEGR2
Initialized
—
—
—
—
—
Interrupts
IENR1
Initialized
—
—
—
—
—
Interrupts
IRR1
Initialized
—
—
—
—
—
Interrupts
IWPR
Initialized
—
—
—
—
—
Interrupts
MSTCR1
Initialized
—
—
—
—
—
Power-down
• EEPROM
Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
EKR
—
—
—
—
—
—
EEPROM
Notes:  is not initialized
1. LVDC: Low-voltage detection circuits (optional)
2. WDT: Watchdog timer
Rev.5.00 Nov. 02, 2005 Page 313 of 418
REJ09B0028-0500
Section 20 List of Registers
Rev.5.00 Nov. 02, 2005 Page 314 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Section 21 Electrical Characteristics
21.1
Absolute Maximum Ratings
Table 21.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Input voltage
VIN
–0.3 to VCC +0.3
V
Port B
–0.3 to AVCC +0.3
V
X1
–0.3 to 4.3
V
Ports other than ports
B and X1
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Note:
*
Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
21.2
Electrical Characteristics (F-ZTAT™ Version, EEPROM Stacked
F-ZTATTM Version)
21.2.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
φOSC (MHz)
φW (kHz)
20.0
32.768
10.0
2.0
3.0
4.0
• AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
5.5
VCC (V)
3.0
4.0
5.5
VCC (V)
• AVCC = 3.3 to 5.5 V
• All operating modes
Rev.5.00 Nov. 02, 2005 Page 315 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
φ (MHz)
φSUB (kHz)
20.0
16.384
10.0
8.192
4.096
1.0
3.0
4.0
5.5
VCC (V)
3.0
• AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 0 )
4.0
5.5
• AVCC = 3.3 to 5.5 V
• Subactive mode
• Subsleep mode
φ (kHz)
2500
1250
78.125
3.0
4.0
5.5 VCC (V)
• AVCC = 3.3 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 1 )
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
φ (MHz)
20.0
10.0
2.0
3.3
4.0
• VCC = 3.0 to 5.5 V
• Active mode
• Sleep mode
Rev.5.00 Nov. 02, 2005 Page 316 of 418
REJ09B0028-0500
5.5
AVCC (V)
VCC (V)
Section 21 Electrical Characteristics
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection
Circuit is Used
φosc (MHz)
20.0
16.0
2.0
Vcc(V)
3.0
4.5
5.5
Operation guarantee range
Operation guarantee range except
A/D conversion accuracy
Rev.5.00 Nov. 02, 2005 Page 317 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.2
DC Characteristics
Table 21.2 DC Characteristics (1)
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Input high VIH
voltage
Test Condition
Min
Typ
Max
Unit
VCC × 0.8
—
VCC + 0.3
V
VCC × 0.9
—
VCC + 0.3
VCC × 0.7
—
VCC + 0.3
VCC × 0.8
—
VCC + 0.3
VCC × 0.7
—
AVCC + 0.3 V
VCC × 0.8
—
AVCC + 0.3
VCC – 0.5
—
VCC + 0.3
VCC – 0.3
—
VCC + 0.3
VCC = 4.0 to 5.5 V
RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG,TMRIV,
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
–0.3
—
VCC × 0.2
–0.3
—
VCC × 0.1
RXD, SCL, SDA, VCC = 4.0 to 5.5 V
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76,
P80 to P87
PB0 to PB7
–0.3
—
VCC × 0.3
–0.3
—
VCC × 0.2
OSC1
–0.3
—
0.5
–0.3
—
0.3
VCC = 4.0 to 5.5 V
RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG,TMRIV,
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
RXD, SCL, SDA, VCC = 4.0 to 5.5 V
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76,
P80 to P87
PB0 to PB7
OSC1
Input low
voltage
VIL
VCC = 4.0 to 5.5 V
VCC = 4.0 to 5.5 V
VCC = 4.0 to 5.5 V
Rev.5.00 Nov. 02, 2005 Page 318 of 418
REJ09B0028-0500
V
V
V
V
V
Notes
Section 21 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Output
high
voltage
VOH
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P55,
P74 to P76,
P80 to P87
VCC = 4.0 to 5.5 V VCC – 1.0
—
—
V
VCC – 0.5
—
—
P56, P57
VCC = 4.0 to 5.5 V VCC – 2.5
—
—
—
—
Notes
–IOH = 1.5 mA
–IOH = 0.1 mA
V
–IOH = 0.1 mA
VCC = 3.0 to 4.0 V VCC – 2.0
–IOH = 0.1 mA
Output
low
voltage
VOL
VCC = 4.0 to 5.5
VIOL = 1.6 mA
—
—
0.6
IOL = 0.4 mA
—
—
0.4
VCC = 4.0 to 5.5 V —
—
1.5
—
1.0
—
0.4
—
—
0.4
VCC = 4.0 to 5.5 V —
—
0.6
—
—
0.4
VIN = 0.5 V to
OSC1, NMI,
WKP0 to WKP5, (VCC – 0.5 V)
IRQ0 to IRQ3,
ADTRG, TRGV,
TMRIV, TMCIV,
FTCI, FTIOA to
FTIOD, RXD,
SCK3, SCL, SDA
—
—
1.0
µA
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76,
P80 to P87
VIN = 0.5 V to
(VCC – 0.5 V)
—
—
1.0
µA
PB0 to PB7
VIN = 0.5 V to
(AVCC – 0.5 V)
—
—
1.0
µA
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76
P80 to P87
V
V
IOL = 20.0 mA
VCC = 4.0 to 5.5 V —
IOL = 10.0 mA
VCC = 4.0 to 5.5 V —
IOL = 1.6 mA
IOL = 0.4 mA
SCL, SDA
V
IOL = 6.0 mA
IOL = 3.0 mA
Input/
output
leakage
current
| IIL |
Rev.5.00 Nov. 02, 2005 Page 319 of 418
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Section 21 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Min
Typ
Max
Unit Notes
Pull-up
MOS
current
–Ip
P10 to P12,
P14 to P17,
P50 to P55
VCC = 5.0 V,
VIN = 0.0 V
50.0
—
300.0
µA
VCC = 3.0 V,
VIN = 0.0 V
—
60.0
—
Input
capacitance
Cin
All input pins
except power
supply pins
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
—
—
15.0
pF
—
—
25.0
pF
HD64N3694G
Active mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
20.0
30.0
mA
*
Active mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
8.0
—
Active mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
2.0
3.0
Active mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
1.2
—
Sleep mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
16.0
22.5
Sleep mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
8.0
—
Sleep mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
1.8
2.7
Sleep mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
1.2
—
VCC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
—
40.0
70.0
VCC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/8)
—
30.0
—
SDA, SCL
IOPE1
Active
mode
current
consumption
VCC
IOPE2
VCC
ISLEEP1
Sleep
mode
current
consumption
VCC
ISLEEP2
VCC
Subactive ISUB
mode
current
consumption
VCC
Rev.5.00 Nov. 02, 2005 Page 320 of 418
REJ09B0028-0500
Reference
value
*
Reference
value
mA
*
*
Reference
value
mA
*
*
Reference
value
mA
*
*
Reference
value
µA
*
*
Reference
value
Section 21 Electrical Characteristics
Values
Item
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
Subsleep ISUBSP
mode
current
consumption
VCC
VCC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
—
30.0
50.0
µA
*
ISTBY
Standby
mode
current
consumption
VCC
32-kHz crystal
resonator not
used
—
—
5.0
µA
*
RAM data VRAM
retaining
voltage
VCC
2.0
—
—
V
Note:
Symbol
*
Pin states during current consumption measurement are given below (excluding current
in the pull-up MOS transistors and output buffers).
Mode
RES Pin
Internal State
Other Pins
Oscillator Pins
Active mode 1
VCC
Operates
VCC
Main clock:
ceramic or crystal
resonator
Active mode 2
Sleep mode 1
Operates
(φOSC/64)
VCC
Sleep mode 2
Only timers operate
Subclock:
Pin X1 = VSS
VCC
Only timers operate
(φOSC/64)
Subactive mode
VCC
Operates
VCC
Main clock:
ceramic or crystal
resonator
Subsleep mode
VCC
Only timers operate
VCC
Subclock:
crystal resonator
Standby mode
VCC
CPU and timers
both stop
VCC
Main clock:
ceramic or crystal
resonator
Subclock:
Pin X1 = VSS
Rev.5.00 Nov. 02, 2005 Page 321 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.2 DC Characteristics (2)
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
Values
Item
Symbol
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
EEPROM
current
consumption
IEEW
VCC
VCC = 5.0 V, tSCL = 2.5
µs (when writing)
—
—
2.0
mA
*
IEER
VCC
VCC = 5.0 V, tSCL = 2.5
µs (when reading)
—
—
0.3
mA
IEESTBY
VCC
VCC = 5.0 V, tSCL = 2.5
µs (at standby)
—
—
3.0
µA
Note:
*
The current consumption of the EEPROM chip is shown.
For the current consumption of H8/3694N, add the above current values to the current
consumption of H8/3694F.
Rev.5.00 Nov. 02, 2005 Page 322 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.2 DC Characteristics (3)
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Applicable
Item
Symbol
Pins
Test Condition
Allowable output low
current (per pin)
IOL
Output pins
except port 8,
SCL, and SDA
Port 8
Allowable output low
current (total)
∑IOL
Allowable output high –IOH
current (total)
Typ
Max
Unit
VCC = 4.0 to 5.5 V —
—
2.0
mA
—
—
20.0
Port 8
—
—
10.0
SCL and SDA
—
—
6.0
Output pins
except port 8,
SCL, and SDA
—
—
0.5
Output pins
except port 8,
SCL, and SDA
VCC = 4.0 to 5.5 V —
—
40.0
Port 8,
SCL, and SDA
—
—
80.0
Output pins
except port 8,
SCL, and SDA
—
—
20.0
Port 8,
SCL, and SDA
—
—
40.0
All output pins
VCC = 4.0 to 5.5 V —
—
2.0
—
—
0.2
All output pins
VCC = 4.0 to 5.5 V —
—
30.0
—
—
8.0
current (per pin)
Allowable output high –∑IOH 
Min
mA
mA
mA
Rev.5.00 Nov. 02, 2005 Page 323 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.3
AC Characteristics
Table 21.3 AC Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Item
Symbol
Applicable
Pins
System clock
oscillation
fOSC
OSC1, OSC2 VCC = 4.0 to 5.5 V
Test Condition
frequency
System clock (φ)
Min
Typ
Max
Unit
Reference
Figure
2.0
—
20.0
MHz
*
tOSC
*
2.0
tcyc
1
cycle time
10.0
—
64
12.8
—
—
Subclock oscillation fW
frequency
X1, X2
—
32.768 —
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5
—
µs
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
2
—
—
tcyc
tsubcyc
Instruction cycle
time
Oscillation
stabilization time
(crystal resonator)
OSC1,
OSC2
—
—
10.0
ms
Oscillation
trc
stabilization time
(ceramic resonator)
OSC1,
OSC2
—
—
5.0
ms
Oscillation
stabilization time
trcx
X1, X2
—
—
2.0
s
External clock
tCPH
OSC1
VCC = 4.0 to 5.5 V
20.0
—
—
ns
40.0
—
—
tCPL
OSC1
VCC = 4.0 to 5.5 V
20.0
—
—
tCPr
OSC1
VCC = 4.0 to 5.5 V
External clock
low width
External clock
rise time
External clock
tCPf
OSC1
fall time
RES pin low
width
tREL
RES
Rev.5.00 Nov. 02, 2005 Page 324 of 418
REJ09B0028-0500
VCC = 4.0 to 5.5 V
40.0
—
—
—
—
10.0
—
—
15.0
2
µs
trc
high width
1
2
*
Figure 21.1
ns
ns
—
—
10.0
—
—
15.0
ns
At power-on and in trc
modes other than
those below
—
—
ms
In active mode and 200
sleep mode
operation
—
—
ns
Figure 21.2
Section 21 Electrical Characteristics
Item
Symbol
Input pin high
width
tIH
Input pin low
width
tIL
Applicable
Pins
Values
Test Condition
Min
Typ
Max
Unit
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2
—
—
tcyc
tsubcyc
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2
—
—
tcyc
tsubcyc
Reference
Figure
Figure 21.3
Notes: 1. When an external clock is input, the minimum system clock oscillation frequency is
1.0 MHz.
2. Determined by MA2, MA1, MA0, SA1, and SA0 of system control register 2 (SYSCR2).
Rev.5.00 Nov. 02, 2005 Page 325 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.4 I2C Bus Interface Timing
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Test
Condition
Values
Max
Unit
Reference
Figure
12tcyc + 600 —
—
ns
Figure 21.4
3tcyc + 300
—
ns
Item
Symbol
SCL input cycle time
tSCL
SCL input high width
tSCLH
SCL input low width
tSCLL
5tcyc + 300
—
—
ns
SCL and SDA input
fall time
tSf
—
—
300
ns
SCL and SDA input
spike pulse removal
time
tSP
—
—
1tcyc
ns
SDA input bus-free
time
tBUF
5tcyc
—
—
ns
Start condition input
hold time
tSTAH
3tcyc
—
—
ns
Retransmission start
condition input setup
time
tSTAS
3tcyc
—
—
ns
Setup time for stop
condition input
tSTOS
3tcyc
—
—
ns
Data-input setup time tSDAS
1tcyc+20
—
—
ns
Data-input hold time
tSDAH
0
—
—
ns
Capacitive load of
SCL and SDA
cb
0
—
400
pF
SCL and SDA output
fall time
tSf
VCC = 4.0 to —
5.5 V
—
250
ns
—
—
300
Rev.5.00 Nov. 02, 2005 Page 326 of 418
REJ09B0028-0500
Min
Typ
—
Section 21 Electrical Characteristics
Table 21.5 Serial Communication Interface (SCI) Timing
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Item
Input
clock
cycle
Asynchronous
Symbol
Applicable
Pins
tScyc
SCK3
Values
Test Condition
Clocked
synchronous
Input clock pulse
width
tSCKW
SCK3
Transmit data delay
time (clocked
synchronous)
tTXD
TXD
Receive data setup
time (clocked
synchronous)
tRXS
Receive data hold
time (clocked
synchronous)
tRXH
RXD
RXD
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
Min
Typ Max Unit
Reference
Figure
4
—
—
Figure 21.5
6
—
—
0.4
—
0.6
tScyc
—
—
1
tcyc
—
—
1
50.0
—
—
100.0 —
—
50.0
—
—
100.0 —
—
tcyc
Figure 21.6
ns
ns
Rev.5.00 Nov. 02, 2005 Page 327 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.4
A/D Converter Characteristics
Table 21.6 A/D Converter Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Item
Symbol
Applicable
Pins
Test
Condition
Values
Min
Typ Max
Unit
Reference
Figure
V
*
Analog power supply AVCC
voltage
AVCC
3.3
VCC
5.5
Analog input voltage AVIN
AN0 to
AN7
VSS – 0.3
—
AVCC + 0.3 V
Analog power supply AIOPE
current
AVCC
—
2.0
mA
AVCC = 5.0 V —
1
fOSC =
20 MHz
2
AISTOP1
AVCC
—
50
—
µA
*
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
*
Analog input
capacitance
CAIN
AN0 to
AN7
—
—
30.0
pF
Allowable signal
source impedance
RAIN
AN0 to
AN7
—
—
5.0
kΩ
10
10
10
bit
—
—
tcyc
Resolution (data
length)
Conversion time
(single mode)
AVCC = 3.3 to 134
5.5 V
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
AVCC = 4.0 to 70
5.5 V
—
—
tcyc
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
Conversion time
(single mode)
Rev.5.00 Nov. 02, 2005 Page 328 of 418
REJ09B0028-0500
3
Section 21 Electrical Characteristics
Item
Symbol
Applicable
Pins
Conversion time
(single mode)
Test
Condition
Values
Min
AVCC = 4.0 to 134
5.5 V
Typ Max
Unit
—
—
tcyc
Nonlinearity error
—
—
±3.5
LSB
Offset error
—
—
±3.5
LSB
Full-scale error
—
—
±3.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±4.0
LSB
Reference
Figure
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
21.2.5
Watchdog Timer Characteristics
Table 21.7 Watchdog Timer Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Item
Symbol
On-chip
oscillator
overflow
time
tOVF
Note:
*
Applicable
Pins
Test
Condition
Values
Min
Typ
Max
Unit
Reference
Figure
0.2
0.4
—
s
*
Shows the time to count from 0 to 255, at which point an internal reset is generated,
when the internal oscillator is selected.
Rev.5.00 Nov. 02, 2005 Page 329 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.6
Flash Memory Characteristics
Table 21.8 Flash Memory Characteristics
VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Item
Symbol
1 2 4
Programming time (per 128 bytes)* * *
Test
Condition
Values
Min
Typ
Max
Unit
tP
—
7
200
ms
Erase time (per block) * * *
tE
—
100
1200
ms
Reprogramming count
NWEC
1000
10000
—
Times
Programming
Wait time after SWE
1
bit setting*
x
1
—
—
µs
Wait time after PSU
1
bit setting*
y
50
—
—
µs
Wait time after P bit setting
z1
1≤n≤6
28
30
32
µs
z2
7 ≤ n ≤ 1000
198
200
202
µs
z3
Additionalprogramming
8
10
12
µs
1 3 6
1 4
**
Wait time after P bit clear*
α
5
—
—
µs
Wait time after PSU
1
bit clear*
β
5
—
—
µs
Wait time after PV
1
bit setting*
γ
4
—
—
µs
Wait time after
1
dummy write*
ε
2
—
—
µs
Wait time after PV bit clear*
η
2
—
—
µs
Wait time after SWE
1
bit clear*
θ
100
—
—
µs
Maximum programming
1 4 5
count * * *
N
—
—
1000
Times
1
1
Rev.5.00 Nov. 02, 2005 Page 330 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Item
Erasing
Symbol
Test
Condition
Values
Min
Typ
Max
Unit
Wait time after SWE
1
bit setting*
x
1
—
—
µs
Wait time after ESU
1
bit setting*
y
100
—
—
µs
Wait time after E bit
1 6
setting* *
z
10
—
100
ms
Wait time after E bit clear*
α
10
—
—
µs
Wait time after ESU
1
bit clear*
β
10
—
—
µs
Wait time after EV
1
bit setting*
γ
20
—
—
µs
Wait time after
1
dummy write*
ε
2
—
—
µs
Wait time after EV bit clear*
η
4
—
—
µs
Wait time after SWE
1
bit clear*
θ
100
—
—
µs
N
—
—
120
Times
1
1
1 6 7
Maximum erase count * * *
Notes: 1. Make the time settings in accordance with the program/erase algorithms.
2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash
memory control register 1 (FLMCR1) is set. The program-verify time is not included.)
3. The time required to erase one block. (Indicates the time for which the E bit in flash
memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)
4. Programming time maximum value (tP (max.)) = wait time after P bit setting (z) ×
maximum programming count (N)
5. Set the maximum programming count (N) according to the actual set values of z1, z2,
and z3, so that it does not exceed the programming time maximum value (tP (max.)).
The wait time after P bit setting (z1, z2) should be changed as follows according to the
value of the programming count (n).
Programming count (n)
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (tE (max.)) = wait time after E bit setting (z) × maximum
erase count (N)
7. Set the maximum erase count (N) according to the actual set value of (z), so that it
does not exceed the erase time maximum value (tE (max.)).
Rev.5.00 Nov. 02, 2005 Page 331 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.7
EEPROM Characteristics
Table 21.9 EEPROM Characteristics
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Values
Typ Max
Reference
Unit Figure
2500

ns
600


µs
tSCLL
1200


ns
SCL, SDA input spike pulse
removal time
tSP


50
ns
SDA input bus-free time
tBUF
1200


ns
Start condition input hold time
tSTAH
600


ns
Retransmit start condition input
setup time
tSTAS
600


ns
Stop condition input setup time
tSTOS
600


ns
Data input setup time
tSDAS
160


ns
Data input hold time
tSDAH
0


ns
SCL, SDA input fall time
tSf


300
ns
SDA input rise time
tSr


300
ns
Data output hold time
tDH
50


ns
SCL, SDA capacitive load
Cb
0

400
pF
Access time
tAA
100

900
ns
Cycle time at writing*
tWC


10
ms
Reset release time
tRES


13
ms
Item
Symbol
SCL input cycle time
tSCL
SCL input high pulse width
tSCLH
SCL input low pulse width
Note:
*
Test
Condition Min
Figure 21.7
Cycle time at writing is a time from the stop condition to write completion (internal
control).
Rev.5.00 Nov. 02, 2005 Page 332 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.8
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 21.10 Power-Supply-Voltage Detection Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Item
Symbol
Test
Condition
Min
Typ
Max
Unit
Power-supply falling detection
voltage
Vint (D)
LVDSEL = 0
3.3
3.7
—
V
Power-supply rising detection
voltage
Vint (U)
LVDSEL = 0
—
4.0
4.5
V
Reset detection voltage 1*1
Vreset1
LVDSEL = 0
—
2.3
2.7
V
Reset detection voltage 2*2
Vreset2
LVDSEL = 1
3.0
3.6
4.2
V
Lower-limit voltage of LVDR
3
operation*
VLVDRmin
1.0
—
—
V
LVD stabilization time
tLVDON
50
—
—
µs
Current consumption in standby
mode
ISTBY

—
350
µA
LVDE = 1,
Vcc = 5.0 V,
When a 32kHz crystal
resonator is
not used
Notes: 1. This voltage should be used when the falling and rising voltage detection function is
used.
2. Select the low-voltage reset 2 when only the low-voltage detection reset is used.
3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset
may not occur. Therefore sufficient evaluation is required.
Rev.5.00 Nov. 02, 2005 Page 333 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.2.9
Power-On Reset Circuit Characteristics (Optional)
Table 21.11 Power-On Reset Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Item
Symbol
Pull-up resistance of RES pin
Power-on reset start voltage*
Note:
*
Test Condition Min
Typ
Max
Unit
RRES
100
150
—
kΩ
Vpor
—
—
100
mV
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after
charge of the RES pin is removed completely. In order to remove charge of the RES
pin, it is recommended that the diode be placed in the Vcc side. If the power-supply
voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
21.3
Electrical Characteristics (Mask-ROM Version, EEPROM Stacked
Mask-ROM Version)
21.3.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
φOSC (MHz)
φW (kHz)
20.0
32.768
10.0
2.0
2.7
4.0
• AVCC = 3.0 to 5.5 V
• Active mode
• Sleep mode
Rev.5.00 Nov. 02, 2005 Page 334 of 418
REJ09B0028-0500
5.5
VCC (V)
2.7
4.0
• AVCC = 3.0 to 5.5 V
• All operating modes
5.5
VCC (V)
Section 21 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
φ (MHz)
φSUB (kHz)
20.0
16.384
10.0
8.192
4.096
1.0
2.7
φ (kHz)
4.0
5.5
VCC (V)
• AVCC = 3.0 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 0)
2.7
4.0
5.5
VCC (V)
• AVCC = 3.0 to 5.5 V
• Subactive mode
• Subsleep mode
2500
1250
78.125
2.7
4.0
5.5 VCC (V)
• AVCC = 3.0 to 5.5 V
• Active mode
• Sleep mode
(When MA2 in SYSCR2 = 1)
Rev.5.00 Nov. 02, 2005 Page 335 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
φ (MHz)
20.0
10.0
2.0
3.0
4.0
5.5
AVCC (V)
• VCC = 2.7 to 5.5 V
• Active mode
• Sleep mode
Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection
Circuit is Used
φosc (MHz)
20.0
16.0
2.0
Vcc(V)
3.0
4.5
5.5
Operation guarantee range
Operation guarantee range except
A/D conversion accuracy
Rev.5.00 Nov. 02, 2005 Page 336 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
21.3.2
DC Characteristics
Table 21.12 DC Characteristics (1)
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
RXD, SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76,
P80 to P87
VCC = 4.0 to 5.5 V
PB0 to PB7
VCC = 4.0 to 5.5 V
OSC1
Input low VIL
voltage
Test Condition
RES, NMI,
VCC = 4.0 to 5.5 V
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG,TMRIV,
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
VCC = 4.0 to 5.5 V
Min
Typ
Max
Unit
VCC × 0.8
—
VCC + 0.3
V
VCC × 0.9
—
VCC + 0.3
VCC × 0.7
—
VCC + 0.3
VCC × 0.8
—
VCC + 0.3
V
VCC × 0.7
—
AVCC + 0.3 V
VCC × 0.8
—
AVCC + 0.3
VCC – 0.5
—
VCC + 0.3
VCC – 0.3
—
VCC + 0.3
VCC = 4.0 to 5.5 V
RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG,TMRIV,
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
–0.3
—
VCC × 0.2
–0.3
—
VCC × 0.1
RXD, SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76,
P80 to P87,
PB0 to PB7
VCC = 4.0 to 5.5 V
–0.3
—
VCC × 0.3
–0.3
—
VCC × 0.2
OSC1
VCC = 4.0 to 5.5 V
–0.3
—
0.5
–0.3
—
0.3
Notes
V
V
V
V
Rev.5.00 Nov. 02, 2005 Page 337 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Output
high
voltage
VOH
P10 to P12,
P14 to P17,
P20 to P22,
VCC = 4.0 to 5.5 V VCC – 1.0
Min
Typ
Max
Unit
—
—
V
P50 to P55,
P74 to P76,
P80 to P87
–IOH = 0.1 mA
VCC – 0.5
—
—
P56, P57
VCC = 4.0 to 5.5 V VCC – 2.5
—
—
—
—
—
0.6
–IOH = 1.5 mA
V
–IOH = 0.1 mA
VCC =2.7 to 4.0 V
VCC – 2.0
–IOH = 0.1 mA
Output
low
voltage
VOL
P10 to P12,
P14 to P17,
P20 to P22,
VCC = 4.0 to 5.5 V —
V
IOL = 1.6 mA
P50 to P57,
P74 to P76
IOL = 0.4 mA
—
—
0.4
P80 to P87
VCC = 4.0 to 5.5 V —
—
1.5
—
1.0
—
0.4
—
—
0.4
VCC = 4.0 to 5.5 V —
—
0.6
—
—
0.4
VIN = 0.5 V to
OSC1, NMI,
WKP0 to WKP5, (VCC – 0.5 V)
IRQ0 to IRQ3,
ADTRG, TRGV,
TMRIV, TMCIV,
FTCI, FTIOA to
FTIOD, RXD,
SCK3, SCL, SDA
—
—
1.0
µA
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76,
P80 to P87
VIN = 0.5 V to
(VCC – 0.5 V)
—
—
1.0
µA
PB0 to PB7
VIN = 0.5 V to
(AVCC – 0.5 V)
—
—
1.0
µA
V
IOL = 20.0 mA
VCC = 4.0 to 5.5 V —
IOL = 10.0 mA
VCC = 4.0 to 5.5 V —
IOL = 1.6 mA
IOL = 0.4 mA
SCL, SDA
V
IOL = 6.0 mA
IOL = 3.0 mA
Input/
output
leakage
current
| IIL |
Rev.5.00 Nov. 02, 2005 Page 338 of 418
REJ09B0028-0500
Notes
Section 21 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Pull-up
MOS
current
–Ip
P10 to P12,
P14 to P17,
P50 to P55
VCC = 5.0 V,
VIN = 0.0 V
50.0
—
300.0
µA
VCC = 3.0 V,
VIN = 0.0 V
—
60.0
—
Input
capacitance
Cin
All input pins
except power
supply pins
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
—
—
15.0
pF
—
—
25.0
pF
HD6483694G
Active mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
20.0
30.0
mA
*
Active mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
8.0
—
Active mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
2.0
3.0
Active mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
1.2
—
Sleep mode 1
VCC = 5.0 V,
fOSC = 20 MHz
—
10.0
17.5
Sleep mode 1
VCC = 3.0 V,
fOSC = 10 MHz
—
5.5
—
Sleep mode 2
VCC = 5.0 V,
fOSC = 20 MHz
—
1.6
2.4
Sleep mode 2
VCC = 3.0 V,
fOSC = 10 MHz
—
0.8
—
VCC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
—
40.0
70.0
VCC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/8)
—
30.0
—
SDA, SCL
IOPE1
Active
mode
current
consumption
VCC
IOPE2
VCC
ISLEEP1
Sleep
mode
current
consumption
VCC
ISLEEP2
VCC
Subactive ISUB
mode
current
consumption
VCC
Notes
Reference
value
*
Reference
value
mA
*
*
Reference
value
mA
*
*
Reference
value
mA
*
*
Reference
value
µA
*
*
Reference
value
Rev.5.00 Nov. 02, 2005 Page 339 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Values
Item
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
Subsleep ISUBSP
mode
current
consumption
VCC
VCC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
—
30.0
50.0
µA
*
ISTBY
Standby
mode
current
consumption
VCC
32-kHz crystal
—
resonator not used
—
5.0
µA
*
RAM data VRAM
retaining
voltage
VCC
—
—
V
Note:
Symbol
*
2.0
Pin states during current consumption measurement are given below (excluding current
in the pull-up MOS transistors and output buffers).
Mode
RES Pin
Internal State
Other Pins
Oscillator Pins
Active mode 1
VCC
Operates
VCC
Main clock:
ceramic or crystal
resonator
Active mode 2
Sleep mode 1
Operates
(φOSC/64)
VCC
Sleep mode 2
Only timers operate
Subclock:
Pin X1 = VSS
VCC
Only timers operate
(φOSC/64)
Subactive mode
VCC
Operates
VCC
Main clock:
ceramic or crystal
resonator
Subsleep mode
VCC
Only timers operate
VCC
Subclock:
crystal resonator
Standby mode
VCC
CPU and timers
both stop
VCC
Main clock:
ceramic or crystal
resonator
Subclock:
Pin X1 = VSS
Rev.5.00 Nov. 02, 2005 Page 340 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.12 DC Characteristics (2)
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
Values
Item
Symbol
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
EEPROM
current
consumption
IEEW
VCC
VCC = 5.0 V, tSCL = 2.5
µs (when writing)
—
—
2.0
mA
*
IEER
VCC
VCC = 5.0 V, tSCL = 2.5
µs (when reading)
—
—
0.3
mA
IEESTBY
VCC
VCC = 5.0 V, tSCL = 2.5
µs (at standby)
—
—
3.0
µA
Note:
*
The current consumption of the EEPROM chip is shown.
For the current consumption of H8/3694N, add the above current values to the current
consumption of H8/3694.
Rev.5.00 Nov. 02, 2005 Page 341 of 418
REJ09B0028-0500
Section 21 Electrical Characteristics
Table 21.12 DC Characteristics (3)
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Applicable
Item
Symbol Pins
Allowable output low
current (per pin)
IOL
Allowable output low
current (total)
∑IOL
Typ
Max
Unit
Output pins except port VCC = 4.0 to 5.5 V —
8, SCL, and SDA
—
2.0
mA
Port 8
—
—
20.0
Port 8
—
—
10.0
SCL, and SDA
—
—
6.0
Output pins except port
8, SCL, and SDA
—
—
0.5
Output pins except port VCC = 4.0 to 5.5 V —
8, SCL, and SDA
—
40.0
Port 8,
SCL, and SDA
—
—
80.0
Output pins except port
8, SCL, and SDA
—
—
20.0
Port 8,
SCL, and SDA
—
—
40.0
Test Condition
Min
Allowable output high
current (per pin)
–IOH
All output pins
VCC = 4.0 to 5.5 V —
—
2.0
—
—
0.2
Allowable output high
current (total)
–∑IOH All output pins
VCC = 4.0 to 5.5 V —
—
30.0
—
—
8.0
Rev.5.00 Nov. 02, 2005 Page 342 of 418
REJ09B0028-0500
mA
mA
mA
Section 21 Electrical Characteristics
21.3.3
AC Characteristics
Table 21.13 AC Characteristics
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Item
Symbol
System clock
oscillation
fOSC
Applicable
Pins
Test Condition
OSC1,
OSC2
VCC = 4.0 to 5.5 V
frequency
System clock (φ)
cycle time
Values
Min
Typ
Max
Unit
Reference
Figure
2.0
—
20.0
MHz
*
tOSC
*
2.0
tcyc
1
10.0
—
64
12.8
—
—
Subclock oscillation fW
frequency
X1, X2
—
32.768 —
kHz
Watch clock (φW)
cycle time
tW
X1, X2
—
30.5
—
µs
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
2
—
—
tcyc
tsubcyc
Instruction cycle
time
Oscillation
stabilization time
(crystal resonator)
OSC1,
OSC2
—
—
10.0
ms
Oscillation
trc
stabilization time
(ceramic resonator)
OSC1,
OSC2
—
—
5.0
ms
Oscillation
stabilization time
trcx
X1, X2
—
—
2.0
s
External clock
high width
tCPH
OSC1
VCC = 4.0 to 5.5 V
20.0
—
—
ns
40.0
—
—
External clock
low width
tCPL
OSC1
VCC = 4.0 to 5.5 V
20.0
—
—
40.0
—
—
External clock
rise time
tCPr
OSC1
VCC = 4.0 to 5.5 V
—
—
10.0
—
—
15.0
External clock
fall time
tCPf
—
—
10.0
—
—
15.0
RES pin low
width
tREL
At power-on and in trc
modes other than
those below
—
—
ms
In active mode and 200
sleep mode
operation
—
—
ns
RES
VCC = 4.0 to 5.5 V
2
µs
trc
OSC1
1
2
*
Figure 21.1
ns
ns
ns
Figure 21.2
Rev.5.00 Nov. 02, 2005 Page 343 of 418
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Section 21 Electrical Characteristics
Item
Symbol
Input pin high
width
tIH
Input pin low
width
tIL
Applicable
Pins
Values
Min
Typ
Max
Unit
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2
—
—
tcyc
tsubcyc
NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2
—
—
tcyc
tsubcyc
Notes: 1
Test Condition
Reference
Figure
Figure 21.3
When an external clock is input, the minimum system clock oscillation frequency is
1.0 MHz.
2. Determined by MA2, MA1, MA0, SA1, and SA0 of system control register 2 (SYSCR2).
Rev.5.00 Nov. 02, 2005 Page 344 of 418
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Section 21 Electrical Characteristics
Table 21.14 I2C Bus Interface Timing
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified.
Test
Condition Min
Values
Max
Unit
Reference
Figure
12tcyc + 600 —
—
ns
Figure 21.4
3tcyc + 300
—
ns
Item
Symbol
SCL input cycle time
tSCL
SCL input high width
tSCLH
SCL input low width
tSCLL
5tcyc + 300
—
—
ns
SCL and SDA input
fall time
tSf
—
—
300
ns
SCL and SDA input
spike pulse removal
time
tSP
—
—
1tcyc
ns
SDA input bus-free
time
tBUF
5tcyc
—
—
ns
Start condition input
hold time
tSTAH
3tcyc
—
—
ns
Retransmission start
condition input setup
time
tSTAS
3tcyc
—
—
ns
Setup time for stop
condition input
tSTOS
3tcyc
—
—
ns
1tcyc+20
—
—
ns
Data-input setup time tSDAS
Typ
—
Data-input hold time
tSDAH
0
—
—
ns
Capacitive load of
SCL and SDA
cb
0
—
400
pF
SCL and SDA output
fall time
tSf
VCC = 4.0 to —
5.5 V
—
250
ns
—
—
300
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Section 21 Electrical Characteristics
Table 21.15 Serial Communication Interface (SCI) Timing
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified.
Item
Input
clock
cycle
Asynchronous
Symbol
Min
Typ
Max Unit
Reference
Figure
tScyc
SCK3
4
—
—
Figure 21.5
6
—
—
0.4
—
0.6
tScyc
—
—
1
tcyc
—
—
1
50.0
—
—
100.0
—
—
50.0
—
—
100.0
—
—
Clocked
synchronous
Input clock pulse
width
tSCKW
SCK3
Transmit data delay
time (clocked
synchronous)
tTXD
TXD
Receive data setup
time (clocked
synchronous)
tRXS
Receive data hold
time (clocked
synchronous)
tRXH
RXD
RXD
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Values
Applicable
Pins
Test Condition
VCC = 4.0 to 5.5 V
VCC = 4.0 to 5.5 V
VCC = 4.0 to 5.5 V
tcyc
ns
ns
Figure 21.6
Section 21 Electrical Characteristics
21.3.4
A/D Converter Characteristics
Table 21.16 A/D Converter Characteristics
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Item
Symbol
Applicable
Pins
Test
Condition
Values
Min
Typ
Max
Unit
Reference
Figure
VCC
5.5
V
*
Analog power supply AVCC
voltage
AVCC
3.0
Analog input voltage AVIN
AN0 to
AN7
VSS – 0.3 —
Analog power supply AIOPE
current
AVCC
AVCC = 5.0 V —
1
AVCC + 0.3 V
—
2.0
mA
fOSC =
20 MHz
2
AISTOP1
AVCC
—
50
—
µA
*
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
*
Analog input
capacitance
CAIN
AN0 to
AN7
—
—
30.0
pF
Allowable signal
source impedance
RAIN
AN0 to
AN7
—
—
5.0
kΩ
10
10
10
bit
—
—
tcyc
Resolution (data
length)
Conversion time
(single mode)
AVCC = 3.0 to 134
5.5 V
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
AVCC = 4.0 to 70
5.5 V
—
—
tcyc
Conversion time
(single mode)
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±8.0
LSB
3
Rev.5.00 Nov. 02, 2005 Page 347 of 418
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Section 21 Electrical Characteristics
Item
Symbol
Values
Applicable Test
Pins
Condition
Conversion time
(single mode)
Min
AVCC = 4.0 to 5.5 V 134
Typ
Max
Unit
—
—
tcyc
Nonlinearity error
—
—
±3.5
LSB
Offset error
—
—
±3.5
LSB
Full-scale error
—
—
±3.5
LSB
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
—
±4.0
LSB
Reference
Figure
Notes: 1 Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
21.3.5
Watchdog Timer Characteristics
Table 21.17 Watchdog Timer Characteristics
VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Item
Symbol
On-chip
oscillator
overflow
time
tOVF
Note:
*
Applicable
Test
Pins
Condition
Values
Reference
Min
Typ
Max
Unit
Figure
0.2
0.4
—
s
*
Shows the time to count from 0 to 255, at which point an internal reset is generated,
when the internal oscillator is selected.
Rev.5.00 Nov. 02, 2005 Page 348 of 418
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Section 21 Electrical Characteristics
21.3.6
EEPROM Characteristics
Table 21.18 EEPROM Characteristics
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
Values
Test
Condition Min
Typ Max Unit
Item
Symbol
SCL input cycle time
tSCL
2500

SCL input high pulse width
tSCLH
600


µs
SCL input low pulse width
tSCLL
1200


ns
SCL, SDA input spike pulse
removal time
tSP


50
ns
SDA input bus-free time
tBUF
1200


ns
Start condition input hold time
tSTAH
600


ns
Retransmit start condition input
setup time
tSTAS
600


ns
Stop condition input setup time
tSTOS
600


ns
Data input setup time
tSDAS
160


ns
Data input hold time
tSDAH
0


ns
SCL, SDA input fall time
tSf


300
ns
SDA input rise time
tSr


300
ns
Data output hold time
tDH
50


ns
SCL, SDA capacitive load
Cb
0

400
pF
Access time
tAA
100

900
ns
Cycle time at writing*
tWC


10
ms
Reset release time
tRES


13
ms
Note:
*
ns
Reference
Figure
Figure 21.7
Cycle time at writing is a time from the stop condition to write completion (internal
control).
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Section 21 Electrical Characteristics
21.3.7
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
Table 21.19 Power-Supply-Voltage Detection Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Values
Item
Symbol
Test
Condition
Power-supply falling detection
voltage
Vint (D)
LVDSEL = 0
3.3
3.7
—
V
Power-supply rising detection
voltage
Vint (U)
LVDSEL = 0
—
4.0
4.5
V
Reset detection voltage 1*1
Vreset1
LVDSEL = 0
—
2.3
2.7
V
Reset detection voltage 2*
2
Vreset2
LVDSEL = 1
3.0
3.6
4.2
V
Lower-limit voltage of LVDR
3
operation*
VLVDRmin
1.0
—
—
V
LVD stabilization time
tLVDON
50
—
—
µs
Current consumption in standby
mode
ISTBY
—
—
350
µA
LVDE = 1,
Vcc = 5.0 V,
When a 32kHz crystal
resonator is
not used
Min
Typ
Max
Unit
Notes: 1. This voltage should be used when the falling and rising voltage detection function is
used.
2. Select the low-voltage reset 2 when only the low-voltage detection reset is used.
3. When the power-supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises, a reset
may not occur. Therefore sufficient evaluation is required.
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Section 21 Electrical Characteristics
21.3.8
Power-On Reset Circuit Characteristics (Optional)
Table 21.20 Power-On Reset Circuit Characteristics
VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Typ
Max
Unit
RRES
100
150
—
kΩ
Vpor
—
—
100
mV
Symbol
Pull-up resistance of RES pin
Power-on reset start voltage*
21.4
*
Values
Min
Item
Note:
Test
Condition
The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after
charge of the RES pin is removed completely. In order to remove charge of the RES
pin, it is recommended that the diode be placed in the Vcc side. If the power-supply
voltage (Vcc) rises from the point over 100 mV, a power-on reset may not occur.
Operation Timing
t OSC
VIH
OSC1
VIL
t CPH
t CPr
t CPL
t CPf
Figure 21.1 System Clock Input Timing
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Section 21 Electrical Characteristics
VCC × 0.7
VCC
OSC1
tREL
RES
VIL
VIL
tREL
Figure 21.2 RES Low Width Timing
NMI
IRQ0 to IRQ3
WKP0 to WKP5
ADTRG
FTCI
FTIOA to FTIOD
TMCIV, TMRIV
TRGV
VIH
VIL
t IL
t IH
Figure 21.3 Input Timing
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOS
SCL
P*
S*
tSf
Sr*
tSCLL
P*
tSDAS
tSCL
tSDAH
Note: * S, P, and Sr represent the following:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Figure 21.4 I2C Bus Interface Input/Output Timing
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Section 21 Electrical Characteristics
t SCKW
SCK3
t Scyc
Figure 21.5 SCK3 Input Clock Timing
t Scyc
SCK3
VIH or VOH *
VIL or VOL *
t TXD
*
TXD
(transmit data)
VOH
VOL
*
t RXS
t RXH
RXD
(receive data)
Note:
* Output timing reference levels
Output high:
V OH= 2.0 V
Output low:
V OL= 0.8 V
Load conditions are shown in figure 21.8.
Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode
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Section 21 Electrical Characteristics
1/fSCL
tSf
tSCLH
tSP
tSCLL
SCL
tSTAS
tSDAH
tSTAH
tSTOS
tSDAS
tSr
SDA
(in)
tBUF
tAA
tDH
SDA
(out)
Figure 21.7 EEPROM Bus Timing
21.5
Output Load Condition
VCC
2.4 kΩ
LSI output pin
30 pF
12 k Ω
Figure 21.8 Output Load Circuit
Rev.5.00 Nov. 02, 2005 Page 354 of 418
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Appendix
Appendix A Instruction Set
A.1
Instruction List
Condition Code
Symbol
Description
Rd
General destination register
Rs
General source register
Rn
General register
ERd
General destination register (address register or 32-bit register)
ERs
General source register (address register or 32-bit register)
ERn
General register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
PC
Program counter
SP
Stack pointer
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
disp
Displacement
→
Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+
Addition of the operands on both sides
–
Subtraction of the operand on the right from the operand on the left
×
Multiplication of the operands on both sides
÷
Division of the operand on the left by the operand on the right
∧
Logical AND of the operands on both sides
∨
Logical OR of the operands on both sides
⊕
Logical exclusive OR of the operands on both sides
¬
NOT (logical complement)
( ), < >
Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Rev.5.00 Nov. 02, 2005 Page 355 of 418
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Appendix
Symbol
Description
↔
Condition Code Notation (cont)
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
1
Set to 1
—
Not affected by execution of the instruction
∆
Varies depending on conditions, described in notes
Rev.5.00 Nov. 02, 2005 Page 356 of 418
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Appendix
Table A.1
Instruction Set
1. Data Transfer Instructions
Condition Code
— —
MOV.B @(d:16, ERs), Rd
B
4
@(d:16, ERs) → Rd8
— —
MOV.B @(d:24, ERs), Rd
B
8
@(d:24, ERs) → Rd8
— —
MOV.B @ERs+, Rd
B
@ERs → Rd8
ERs32+1 → ERs32
— —
MOV.B @aa:8, Rd
B
2
@aa:8 → Rd8
— —
MOV.B @aa:16, Rd
B
4
@aa:16 → Rd8
— —
MOV.B @aa:24, Rd
B
6
@aa:24 → Rd8
— —
MOV.B Rs, @ERd
B
Rs8 → @ERd
— —
MOV.B Rs, @(d:16, ERd)
B
4
Rs8 → @(d:16, ERd)
— —
MOV.B Rs, @(d:24, ERd)
B
8
Rs8 → @(d:24, ERd)
— —
MOV.B Rs, @–ERd
B
ERd32–1 → ERd32
Rs8 → @ERd
— —
MOV.B Rs, @aa:8
B
2
Rs8 → @aa:8
— —
MOV.B Rs, @aa:16
B
4
Rs8 → @aa:16
— —
MOV.B Rs, @aa:24
B
6
Rs8 → @aa:24
— —
MOV.W #xx:16, Rd
W 4
#xx:16 → Rd16
— —
MOV.W Rs, Rd
W
Rs16 → Rd16
— —
MOV.W @ERs, Rd
W
@ERs → Rd16
— —
2
2
2
2
2
2
MOV.W @(d:16, ERs), Rd W
4
@(d:16, ERs) → Rd16
— —
MOV.W @(d:24, ERs), Rd W
8
@(d:24, ERs) → Rd16
— —
@ERs → Rd16
ERs32+2 → @ERd32
— —
MOV.W @ERs+, Rd
W
MOV.W @aa:16, Rd
W
4
@aa:16 → Rd16
— —
MOV.W @aa:24, Rd
W
6
@aa:24 → Rd16
— —
MOV.W Rs, @ERd
W
Rs16 → @ERd
— —
2
2
MOV.W Rs, @(d:16, ERd) W
4
Rs16 → @(d:16, ERd)
— —
MOV.W Rs, @(d:24, ERd) W
8
Rs16 → @(d:24, ERd)
— —
0 —
0 —
0 —
0 —
Advanced
@ERs → Rd8
B
↔ ↔ ↔ ↔ ↔ ↔
— —
MOV.B @ERs, Rd
2
↔ ↔ ↔ ↔ ↔ ↔
— —
Rs8 → Rd8
B
C
↔ ↔ ↔ ↔ ↔ ↔ ↔
#xx:8 → Rd8
MOV.B Rs, Rd
V
↔ ↔ ↔ ↔ ↔ ↔ ↔
Z
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
N
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
H
↔ ↔ ↔ ↔ ↔
I
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
2
Rn
B
No. of
States*1
↔ ↔ ↔ ↔ ↔
MOV MOV.B #xx:8, Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
6
0 —
10
0 —
6
4
0 —
6
0 —
8
0 —
4
0 —
2
0 —
4
0 —
6
0 —
10
0 —
6
6
0 —
8
0 —
4
0 —
6
0 —
10
Rev.5.00 Nov. 02, 2005 Page 357 of 418
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Appendix
No. of
States*1
Condition Code
— —
@(d:24, ERs) → ERd32
— —
@ERs → ERd32
ERs32+4 → ERs32
— —
6
@aa:16 → ERd32
— —
8
@aa:24 → ERd32
— —
ERs32 → @ERd
— —
ERs32 → @(d:16, ERd)
— —
ERs32 → @(d:24, ERd)
— —
ERd32–4 → ERd32
ERs32 → @ERd
— —
6
ERs32 → @aa:16
— —
8
ERs32 → @aa:24
— —
0 —
0 —
POP POP.W Rn
W
2 @SP → Rn16
SP+2 → SP
— —
POP.L ERn
L
4 @SP → ERn32
SP+4 → SP
— —
0 —
PUSH PUSH.W Rn
W
2 SP–2 → SP
Rn16 → @SP
— —
0 —
PUSH.L ERn
L
4 SP–4 → SP
ERn32 → @SP
— —
0 —
MOVFPE
MOVFPE @aa:16, Rd
B
4
Cannot be used in
this LSI
Cannot be used in
this LSI
MOVTPE
MOVTPE Rs, @aa:16
B
4
Cannot be used in
this LSI
Cannot be used in
this LSI
W
MOV.W Rs, @aa:16
W
MOV.W Rs, @aa:24
W
MOV.L #xx:32, Rd
L
MOV.L ERs, ERd
L
MOV.L @ERs, ERd
L
MOV.L @(d:16, ERs), ERd
L
6
MOV.L @(d:24, ERs), ERd
L
10
MOV.L @ERs+, ERd
L
MOV.L @aa:16, ERd
L
MOV.L @aa:24, ERd
L
MOV.L ERs, @ERd
L
MOV.L ERs, @(d:16, ERd)
L
6
MOV.L ERs, @(d:24, ERd)
L
10
MOV.L ERs, @–ERd
L
MOV.L ERs, @aa:16
L
MOV.L ERs, @aa:24
L
2
6
2
4
4
4
Rev.5.00 Nov. 02, 2005 Page 358 of 418
REJ09B0028-0500
4
Advanced
@(d:16, ERs) → ERd32
↔
— —
↔
@ERs → ERd32
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
ERs32 → ERd32
↔ ↔ ↔ ↔ ↔ ↔
— —
↔ ↔ ↔ ↔ ↔ ↔
#xx:32 → Rd32
0 —
↔ ↔ ↔
— —
↔ ↔ ↔
— —
Rs16 → @aa:24
↔
Rs16 → @aa:16
6
C
↔
4
V
↔
Z
↔
I
↔
N
— —
↔
H
ERd32–2 → ERd32
Rs16 → @ERd
0 —
MOV MOV.W Rs, @–ERd
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
6
6
0 —
8
0 —
6
0 —
2
0 —
8
0 —
10
0 —
14
0 —
10
10
0 —
12
0 —
8
0 —
10
0 —
14
0 —
10
10
0 —
12
0 —
6
10
6
10
Appendix
2. Arithmetic Instructions
No. of
States*1
Condition Code
Z
V
C
↔ ↔
— (2)
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
ERd32+ERs32 →
ERd32
— (2)
↔
↔
(3)
↔ ↔
Rd16+Rs16 → Rd16
— (1)
ERd32+#xx:32 →
ERd32
Rd8+#xx:8 +C → Rd8
—
2
B
2
Rd8+Rs8 +C → Rd8
—
ADDS ADDS.L #1, ERd
L
2
ERd32+1 → ERd32
— — — — — —
2
ADDS.L #2, ERd
L
2
ERd32+2 → ERd32
— — — — — —
2
ADDS.L #4, ERd
L
2
ERd32+4 → ERd32
— — — — — —
2
INC.B Rd
B
2
Rd8+1 → Rd8
— —
INC.W #1, Rd
W
2
Rd16+1 → Rd16
— —
INC.W #2, Rd
W
2
Rd16+2 → Rd16
— —
INC.L #1, ERd
L
2
ERd32+1 → ERd32
— —
INC.L #2, ERd
L
2
ERd32+2 → ERd32
— —
DAA
DAA Rd
B
2
Rd8 decimal adjust
→ Rd8
— *
SUB
SUB.B Rs, Rd
B
2
Rd8–Rs8 → Rd8
—
SUB.W #xx:16, Rd
W 4
Rd16–#xx:16 → Rd16
— (1)
SUB.W Rs, Rd
W
Rd16–Rs16 → Rd16
— (1)
SUB.L #xx:32, ERd
L
SUB.L ERs, ERd
L
ADD.W Rs, Rd
W
ADD.L #xx:32, ERd
L
ADD.L ERs, ERd
L
ADDX ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
6
2
2
(3)
2
4
2
6
2
—
2
—
2
—
2
—
2
—
2
* —
2
Rd8–Rs8–C → Rd8
—
SUBS SUBS.L #1, ERd
L
2
ERd32–1 → ERd32
— — — — — —
2
SUBS.L #2, ERd
L
2
ERd32–2 → ERd32
— — — — — —
2
SUBS.L #4, ERd
L
2
ERd32–4 → ERd32
— — — — — —
2
B
2
Rd8–1 → Rd8
— —
DEC.W #1, Rd
W
2
Rd16–1 → Rd16
— —
DEC.W #2, Rd
W
2
Rd16–2 → Rd16
— —
Rd8–#xx:8–C → Rd8
—
↔ ↔
2
ERd32–ERs32 → ERd32 — (2)
(3)
(3)
↔ ↔ ↔
DEC DEC.B Rd
2
↔ ↔ ↔
SUBX.B Rs, Rd
B
ERd32–#xx:32 → ERd32 — (2)
6
↔ ↔ ↔
2
SUBX SUBX.B #xx:8, Rd
2
↔ ↔ ↔ ↔ ↔ ↔ ↔
2
B
↔ ↔ ↔ ↔ ↔ ↔ ↔
INC
B
2
↔ ↔ ↔ ↔ ↔
W 4
↔ ↔ ↔ ↔ ↔ ↔
ADD.W #xx:16, Rd
2
↔ ↔ ↔ ↔ ↔
B
↔ ↔ ↔ ↔ ↔ ↔ ↔
ADD.B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
2
ADD ADD.B #xx:8, Rd
↔
↔ ↔ ↔ ↔ ↔
— (1)
↔ ↔ ↔ ↔ ↔
Rd16+#xx:16 → Rd16
2
↔
—
↔ ↔
Rd8+Rs8 → Rd8
↔
—
Advanced
N
↔ ↔
I
Rd8+#xx:8 → Rd8
Normal
H
↔ ↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
2
@ERn
B
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
4
2
6
2
2
2
—
2
—
2
—
2
Rev.5.00 Nov. 02, 2005 Page 359 of 418
REJ09B0028-0500
Appendix
No. of
States*1
Condition Code
Advanced
V
C
ERd32–1 → ERd32
— —
L
2
ERd32–2 → ERd32
— —
↔ ↔
—
2
DAS.Rd
B
2
Rd8 decimal adjust
→ Rd8
— *
↔ ↔ ↔
2
DEC.L #2, ERd
↔ ↔ ↔
—
* —
2
B
2
Rd8 × Rs8 → Rd16
(unsigned multiplication)
— — — — — —
14
W
2
Rd16 × Rs16 → ERd32
(unsigned multiplication)
— — — — — —
22
B
4
Rd8 × Rs8 → Rd16
(signed multiplication)
— —
↔
W
4
Rd16 × Rs16 → ERd32
(signed multiplication)
— —
B
2
W
DIVXU DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP CMP.B #xx:8, Rd
16
— —
24
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
— — (6) (7) — —
14
2
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
— — (6) (7) — —
22
B
4
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
— — (8) (7) — —
16
W
4
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
— — (8) (7) — —
24
Rd8–#xx:8
—
Rd8–Rs8
—
Rd16–#xx:16
— (1)
Rd16–Rs16
— (1)
ERd32–#xx:32
— (2)
ERd32–ERs32
— (2)
B
2
CMP.B Rs, Rd
B
CMP.W #xx:16, Rd
W 4
CMP.W Rs, Rd
W
CMP.L #xx:32, ERd
L
CMP.L ERs, ERd
L
2
2
6
2
Rev.5.00 Nov. 02, 2005 Page 360 of 418
REJ09B0028-0500
↔ ↔ ↔ ↔ ↔ ↔
MULXS. W Rs, ERd
— —
↔ ↔ ↔ ↔ ↔ ↔
MULXS MULXS. B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
MULXU. W Rs, ERd
↔ ↔
MULXU MULXU. B Rs, Rd
↔ ↔ ↔ ↔ ↔ ↔
DAS
I
Normal
Z
2
↔
N
L
↔
H
DEC DEC.L #1, ERd
↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
4
2
4
2
Appendix
No. of
States*1
Condition Code
W
2
0–Rd16 → Rd16
—
NEG.L ERd
L
2
0–ERd32 → ERd32
—
EXTU EXTU.W Rd
W
2
0 → (<bits 15 to 8>
of Rd16)
— — 0
EXTU.L ERd
L
2
0 → (<bits 31 to 16>
of ERd32)
— — 0
EXTS EXTS.W Rd
W
2
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
— —
EXTS.L ERd
L
2
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
— —
Advanced
↔ ↔ ↔
NEG.W Rd
Normal
C
↔ ↔ ↔
—
↔ ↔ ↔
V
↔ ↔ ↔ ↔
0–Rd8 → Rd8
2
0 —
2
↔
2
0 —
2
↔
H
B
0 —
2
↔
Z
↔
I
NEG NEG.B Rd
↔ ↔ ↔
N
↔
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
0 —
2
2
2
Rev.5.00 Nov. 02, 2005 Page 361 of 418
REJ09B0028-0500
Appendix
3. Logic Instructions
AND.B Rs, Rd
B
AND.W #xx:16, Rd
W 4
AND.W Rs, Rd
W
AND.L #xx:32, ERd
L
AND.L ERs, ERd
L
OR.B #xx:8, Rd
B
OR.B Rs, Rd
B
OR.W #xx:16, Rd
W 4
OR.W Rs, Rd
W
OR.L #xx:32, ERd
L
OR.L ERs, ERd
L
XOR.B #xx:8, Rd
B
XOR.B Rs, Rd
B
XOR.W #xx:16, Rd
W 4
XOR.W Rs, Rd
W
XOR.L #xx:32, ERd
L
XOR.L ERs, ERd
L
4
ERd32⊕ERs32 → ERd32 — —
NOT.B Rd
B
2
¬ Rd8 → Rd8
— —
NOT.W Rd
W
2
¬ Rd16 → Rd16
— —
NOT.L ERd
L
2
¬ Rd32 → Rd32
— —
Z
Rd8∧Rs8 → Rd8
— —
Rd16∧#xx:16 → Rd16
— —
Rd16∧Rs16 → Rd16
— —
4
2
2
2
6
4
2
2
2
ERd32∧ERs32 → ERd32 — —
Rd8⁄#xx:8 → Rd8
— —
Rd8⁄Rs8 → Rd8
— —
Rd16⁄#xx:16 → Rd16
— —
Rd16⁄Rs16 → Rd16
— —
ERd32⁄#xx:32 → ERd32
— —
ERd32⁄ERs32 → ERd32
— —
Rd8⊕#xx:8 → Rd8
— —
Rd8⊕Rs8 → Rd8
— —
Rd16⊕#xx:16 → Rd16
— —
Rd16⊕Rs16 → Rd16
— —
ERd32⊕#xx:32 → ERd32 — —
6
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
N
— —
ERd32∧#xx:32 → ERd32 — —
6
Rev.5.00 Nov. 02, 2005 Page 362 of 418
REJ09B0028-0500
H
Rd8∧#xx:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
NOT
2
@(d, ERn)
2
@ERn
B
Rn
#xx
XOR
Condition Code
Operand Size
OR
No. of
States*1
AND.B #xx:8, Rd
Mnemonic
AND
@–ERn/@ERn+
Addressing Mode and
Instruction Length (bytes)
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
4
0 —
2
0 —
6
0 —
4
0 —
2
0 —
2
0 —
2
Appendix
4. Shift Instructions
W
2
SHAL.L ERd
L
2
SHAR SHAR.B Rd
B
2
SHAR.W Rd
W
2
SHAR.L ERd
L
2
SHLL SHLL.B Rd
B
2
SHLL.W Rd
W
2
SHLL.L ERd
L
2
SHLR SHLR.B Rd
B
2
SHLR.W Rd
W
2
SHLR.L ERd
L
2
ROTXL ROTXL.B Rd
B
2
ROTXL.W Rd
W
2
ROTXL.L ERd
L
2
B
2
ROTXR.W Rd
W
2
ROTXR.L ERd
L
2
ROTL ROTL.B Rd
B
2
ROTL.W Rd
W
2
ROTL.L ERd
L
2
ROTR ROTR.B Rd
B
2
ROTR.W Rd
W
2
ROTR.L ERd
L
2
ROTXR ROTXR.B Rd
0
MSB
LSB
V
C
— —
— —
— —
C
MSB
— —
LSB
— —
— —
0
C
MSB
LSB
— —
— —
— —
0
C
MSB
LSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
MSB
LSB
— —
— —
— —
C
— —
MSB
LSB
— —
— —
C
MSB
LSB
— —
— —
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Advanced
Z
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
I
C
N
↔ ↔ ↔
SHAL.W Rd
H
— —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
2
Condition Code
Operation
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
SHAL SHAL.B Rd
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev.5.00 Nov. 02, 2005 Page 363 of 418
REJ09B0028-0500
Appendix
5. Bit-Manipulation Instructions
B
BSET #xx:3, @aa:8
B
BSET Rn, Rd
B
BSET Rn, @ERd
B
BSET Rn, @aa:8
B
B
BCLR #xx:3, @ERd
B
BCLR #xx:3, @aa:8
B
BCLR Rn, Rd
B
BCLR Rn, @ERd
B
BCLR Rn, @aa:8
B
BNOT BNOT #xx:3, Rd
B
BNOT #xx:3, @ERd
B
BNOT #xx:3, @aa:8
B
BNOT Rn, Rd
B
BNOT Rn, @ERd
B
BNOT Rn, @aa:8
B
BTST BTST #xx:3, Rd
B
BTST #xx:3, @ERd
B
BTST #xx:3, @aa:8
B
BTST Rn, Rd
B
BTST Rn, @ERd
B
BTST Rn, @aa:8
B
BLD #xx:3, Rd
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
2
Rev.5.00 Nov. 02, 2005 Page 364 of 418
REJ09B0028-0500
Condition Code
Operation
(#xx:3 of Rd8) ← 1
— — — — — —
2
(#xx:3 of @ERd) ← 1
— — — — — —
8
(#xx:3 of @aa:8) ← 1
— — — — — —
8
(Rn8 of Rd8) ← 1
— — — — — —
2
(Rn8 of @ERd) ← 1
— — — — — —
8
(Rn8 of @aa:8) ← 1
— — — — — —
8
(#xx:3 of Rd8) ← 0
— — — — — —
2
(#xx:3 of @ERd) ← 0
— — — — — —
8
(#xx:3 of @aa:8) ← 0
— — — — — —
8
(Rn8 of Rd8) ← 0
— — — — — —
2
(Rn8 of @ERd) ← 0
— — — — — —
8
(Rn8 of @aa:8) ← 0
— — — — — —
8
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
— — — — — —
2
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
— — — — — —
8
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
— — — — — —
8
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
— — — — — —
2
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
— — — — — —
8
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
— — — — — —
8
¬ (#xx:3 of Rd8) → Z
— — —
¬ (#xx:3 of @ERd) → Z
— — —
¬ (#xx:3 of @aa:8) → Z
— — —
¬ (Rn8 of @Rd8) → Z
— — —
¬ (Rn8 of @ERd) → Z
— — —
¬ (Rn8 of @aa:8) → Z
— — —
(#xx:3 of Rd8) → C
— — — — —
— —
2
— —
6
— —
6
— —
2
— —
6
— —
6
↔
BSET #xx:3, @ERd
BCLR BCLR #xx:3, Rd
BLD
B
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔
BSET BSET #xx:3, Rd
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
Appendix
B
BLD #xx:3, @aa:8
B
BILD BILD #xx:3, Rd
BST
BILD #xx:3, @ERd
B
BILD #xx:3, @aa:8
B
BST #xx:3, Rd
B
BST #xx:3, @ERd
B
BST #xx:3, @aa:8
B
BIST BIST #xx:3, Rd
B
BIST #xx:3, @ERd
B
BIST #xx:3, @aa:8
B
BAND BAND #xx:3, Rd
B
BAND #xx:3, @ERd
B
BAND #xx:3, @aa:8
B
BIAND BIAND #xx:3, Rd
BOR
B
B
BIAND #xx:3, @ERd
B
BIAND #xx:3, @aa:8
B
BOR #xx:3, Rd
B
BOR #xx:3, @ERd
B
BOR #xx:3, @aa:8
B
BIOR BIOR #xx:3, Rd
B
BIOR #xx:3, @ERd
B
BIOR #xx:3, @aa:8
B
BXOR BXOR #xx:3, Rd
B
BXOR #xx:3, @ERd
B
BXOR #xx:3, @aa:8
B
BIXOR BIXOR #xx:3, Rd
B
BIXOR #xx:3, @ERd
B
BIXOR #xx:3, @aa:8
B
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
H
N
Z
V
C
(#xx:3 of @ERd) → C
— — — — —
6
(#xx:3 of @aa:8) → C
— — — — —
¬ (#xx:3 of Rd8) → C
— — — — —
¬ (#xx:3 of @ERd) → C
— — — — —
¬ (#xx:3 of @aa:8) → C
— — — — —
C → (#xx:3 of Rd8)
— — — — — —
2
C → (#xx:3 of @ERd24)
— — — — — —
8
C → (#xx:3 of @aa:8)
— — — — — —
8
¬ C → (#xx:3 of Rd8)
— — — — — —
2
¬ C → (#xx:3 of @ERd24)
— — — — — —
8
¬ C → (#xx:3 of @aa:8)
— — — — — —
8
C∧(#xx:3 of Rd8) → C
— — — — —
2
C∧(#xx:3 of @ERd24) → C
— — — — —
C∧(#xx:3 of @aa:8) → C
— — — — —
C∧ ¬ (#xx:3 of Rd8) → C
— — — — —
C∧ ¬ (#xx:3 of @ERd24) → C
— — — — —
C∧ ¬ (#xx:3 of @aa:8) → C
— — — — —
C∨(#xx:3 of Rd8) → C
— — — — —
C∨(#xx:3 of @ERd24) → C
— — — — —
C∨(#xx:3 of @aa:8) → C
— — — — —
C∨ ¬ (#xx:3 of Rd8) → C
— — — — —
C∨ ¬ (#xx:3 of @ERd24) → C
— — — — —
C∨ ¬ (#xx:3 of @aa:8) → C
— — — — —
C⊕(#xx:3 of Rd8) → C
— — — — —
C⊕(#xx:3 of @ERd24) → C
— — — — —
C⊕(#xx:3 of @aa:8) → C
— — — — —
C⊕ ¬ (#xx:3 of Rd8) → C
— — — — —
C⊕ ¬ (#xx:3 of @ERd24) → C — — — — —
4
4
Advanced
I
Normal
—
@@aa
@(d, PC)
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
Condition Code
Operation
↔ ↔ ↔ ↔ ↔
BLD #xx:3, @ERd
No. of
States*1
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BLD
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
C⊕ ¬ (#xx:3 of @aa:8) → C
— — — — —
6
2
6
6
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Rev.5.00 Nov. 02, 2005 Page 365 of 418
REJ09B0028-0500
Appendix
6. Branching Instructions
Bcc
No. of
States*1
Condition Code
BRA d:8 (BT d:8)
—
2
BRA d:16 (BT d:16)
—
4
BRN d:8 (BF d:8)
—
2
BRN d:16 (BF d:16)
—
4
BHI d:8
—
2
BHI d:16
—
4
BLS d:8
—
2
BLS d:16
—
4
BCC d:8 (BHS d:8)
—
2
BCC d:16 (BHS d:16)
—
4
BCS d:8 (BLO d:8)
—
2
BCS d:16 (BLO d:16)
—
4
BNE d:8
—
2
BNE d:16
—
4
BEQ d:8
—
2
BEQ d:16
—
4
BVC d:8
—
2
BVC d:16
—
4
BVS d:8
—
2
BVS d:16
—
4
BPL d:8
—
2
BPL d:16
—
4
BMI d:8
—
2
BMI d:16
—
4
BGE d:8
—
2
BGE d:16
—
4
BLT d:8
—
2
BLT d:16
—
BGT d:8
I
H
N
Z
V
C
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
— — — — — —
6
— — — — — —
4
4
— — — — — —
6
—
2
Z∨ (N⊕V) = 0 — — — — — —
4
BGT d:16
—
4
— — — — — —
6
BLE d:8
—
2
Z∨ (N⊕V) = 1 — — — — — —
4
BLE d:16
—
4
— — — — — —
6
Rev.5.00 Nov. 02, 2005 Page 366 of 418
REJ09B0028-0500
If condition Always
is true then
PC ← PC+d
Never
else next;
Advanced
Branch
Condition
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
C∨ Z = 0
C∨ Z = 1
C=0
C=1
Z=0
Z=1
V=0
V=1
N=0
N=1
N⊕V = 0
N⊕V = 1
Appendix
JMP
BSR
JSR
RTS
JMP @ERn
—
JMP @aa:24
—
JMP @@aa:8
—
BSR d:8
—
BSR d:16
—
JSR @ERn
—
JSR @aa:24
—
JSR @@aa:8
—
RTS
—
No. of
States*1
Condition Code
H
N
Z
V
C
Advanced
I
Normal
—
@@aa
@(d, PC)
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
PC ← ERn
— — — — — —
PC ← aa:24
— — — — — —
PC ← @aa:8
— — — — — —
8
10
2
PC → @–SP
PC ← PC+d:8
— — — — — —
6
8
4
PC → @–SP
PC ← PC+d:16
— — — — — —
8
10
PC → @–SP
PC ← ERn
— — — — — —
6
8
PC → @–SP
PC ← aa:24
— — — — — —
8
10
PC → @–SP
PC ← @aa:8
— — — — — —
8
12
2 PC ← @SP+
— — — — — —
8
10
2
4
2
2
4
2
4
6
Rev.5.00 Nov. 02, 2005 Page 367 of 418
REJ09B0028-0500
Appendix
7. System Control Instructions
No. of
States*1
Condition Code
Normal
Advanced
—
CCR ← @SP+
PC ← @SP+
↔
↔
10
—
Transition to powerdown state
— — — — — —
2
#xx:8 → CCR
↔
W
6
@(d:16, ERs) → CCR
LDC @(d:24, ERs), CCR
W
10
@(d:24, ERs) → CCR
LDC @ERs+, CCR
W
↔
↔
↔
↔
LDC @aa:16, CCR
W
6
@aa:16 → CCR
LDC @aa:24, CCR
W
8
@aa:24 → CCR
↔ ↔
↔ ↔
↔ ↔ ↔ ↔ ↔
↔
LDC @(d:16, ERs), CCR
↔ ↔
↔ ↔ ↔ ↔ ↔
↔
W
↔
↔ ↔ ↔ ↔ ↔
↔
LDC @ERs, CCR
↔
↔ ↔ ↔ ↔ ↔
B
↔ ↔
↔ ↔ ↔ ↔ ↔
C
B
W
STC CCR, @aa:16
W
STC CCR, @aa:24
W
ANDC ANDC #xx:8, CCR
B
B
B
ORC #xx:8, CCR
XORC XORC #xx:8, CCR
NOP
6
8
12
8
10
CCR → Rd8
— — — — — —
2
CCR → @ERd
— — — — — —
6
6
CCR → @(d:16, ERd)
— — — — — —
8
10
CCR → @(d:24, ERd)
— — — — — —
12
ERd32–2 → ERd32
CCR → @ERd
— — — — — —
8
6
CCR → @aa:16
— — — — — —
8
8
CCR → @aa:24
— — — — — —
10
2
CCR∧#xx:8 → CCR
2
CCR∨#xx:8 → CCR
2
CCR⊕#xx:8 → CCR
2
4
4
—
Rev.5.00 Nov. 02, 2005 Page 368 of 418
REJ09B0028-0500
2
↔ ↔
STC CCR, @–ERd
2
2 PC ← PC+2
8
↔ ↔ ↔
W
@ERs → CCR
ERs32+2 → ERs32
4
↔ ↔ ↔
STC CCR, @(d:24, ERd)
@ERs → CCR
4
↔ ↔ ↔
W
Rs8 → CCR
2
↔ ↔ ↔
STC CCR, @(d:16, ERd)
2
↔ ↔ ↔
B
W
NOP
V
LDC Rs, CCR
STC CCR, @ERd
ORC
Z
LDC #xx:8, CCR
STC CCR, Rd
STC
N
↔ ↔ ↔
LDC
H
↔ ↔
SLEEP SLEEP
@@aa
RTE
RTE
@(d, PC)
16
@aa
1 — — — — — 14
@ERn
2 PC → @–SP
CCR → @–SP
<vector> → PC
Rn
—
#xx
I
TRAPA TRAPA #x:2
↔ ↔ ↔ ↔ ↔
Operation
—
@–ERn/@ERn+
@(d, ERn)
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
2
— — — — — —
2
2
2
Appendix
8. Block Transfer Instructions
EEPMOV
No. of
States*1
H
N
Z
V
C
Normal
—
@@aa
@(d, PC)
I
EEPMOV. B
—
4 if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until
R4L=0
else next
— — — — — — 8+
4n*2
EEPMOV. W
—
4 if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until
R4=0
else next
— — — — — — 8+
4n*2
Advanced
Condition Code
Operation
@aa
@–ERn/@ERn+
@(d, ERn)
@ERn
Rn
#xx
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes)
Notes: 1. The number of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases see appendix A.3, Number of
Execution States.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev.5.00 Nov. 02, 2005 Page 369 of 418
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Rev.5.00 Nov. 02, 2005 Page 370 of 418
MULXU
5
STC
Table A-2
(2)
LDC
3
BVC
8
SUBX
OR
XOR
AND
MOV
C
D
E
F
BILD
BIST
BLD
BST
MOV
BVS
9
B
JMP
BPL
BMI
MOV
Table A-2 Table A-2
(2)
(2)
Table A-2 Table A-2
(2)
(2)
A
Table A-2 Table A-2
EEPMOV
(2)
(2)
SUB
ADD
Table A-2
TRAPA
(2)
BEQ
B
BIAND
BAND
AND
RTE
BNE
CMP
BIXOR
BXOR
XOR
BSR
BCS
A
BIOR
BOR
OR
RTS
BCC
MOV.B
Table A-2
(2)
LDC
7
ADDX
BTST
DIVXU
BLS
AND.B
ANDC
6
9
BCLR
MULXU
BHI
XOR.B
XORC
5
ADD
BNOT
DIVXU
BRN
OR.B
ORC
4
8
7
BSET
BRA
6
2
1
Table A-2 Table A-2 Table A-2 Table A-2
(2)
(2)
(2)
(2)
NOP
4
3
2
1
0
0
BSR
BGE
C
CMP
MOV
Instruction when most significant bit of BH is 1.
Instruction when most significant bit of BH is 0.
JSR
BGT
SUBX
ADDX
E
Table A-2
(3)
BLT
D
BLE
Table A-2
(2)
Table A-2
(2)
F
Table A.2
AL
1st byte 2nd byte
AH AL BH BL
A.2
AH
Instruction code:
Appendix
Operation Code Map
Operation Code Map (1)
ADD
MOV
7A
BRN
ADD
BRA
58
MOV
DAS
1F
1
79
SUBS
1B
NOT
17
DEC
ROTXR
13
1A
ROTXL
12
DAA
0F
SHLR
ADDS
0B
11
INC
0A
SHLL
MOV
01
10
0
CMP
CMP
BHI
2
SUB
SUB
BLS
NOT
ROTXR
ROTXL
SHLR
SHLL
3
4
OR
OR
BCC
LDC/STC
1st byte 2nd byte
AH AL BH BL
XOR
XOR
BCS
DEC
EXTU
INC
5
AND
AND
BNE
6
BEQ
DEC
EXTU
INC
7
BVC
SUB
NEG
9
BVS
ROTR
ROTL
SHAR
SHAL
ADDS
SLEEP
8
BPL
A
MOV
BMI
NEG
CMP
SUB
ROTR
ROTL
SHAR
C
D
BGE
BLT
DEC
EXTS
INC
Table A-2 Table A-2
(3)
(3)
ADD
SHAL
B
BGT
E
F
BLE
DEC
EXTS
INC
Table A-2
(3)
Table A.2
BH
AH AL
Instruction code:
Appendix
Operation Code Map (2)
Rev.5.00 Nov. 02, 2005 Page 371 of 418
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Rev.5.00 Nov. 02, 2005 Page 372 of 418
DIVXS
3
BSET
7Faa7 * 2
BNOT
BNOT
BCLR
BCLR
Notes: 1. r is the register designation field.
2. aa is the absolute address field.
BSET
7Faa6 * 2
BTST
BCLR
7Eaa7 * 2
BNOT
BTST
BSET
7Dr07 * 1
7Eaa6 * 2
BSET
7Dr06 * 1
BTST
BCLR
MULXS
2
7Cr07 * 1
BNOT
DIVXS
1
BTST
MULXS
0
7Cr06 * 1
01F06
01D05
01C05
01406
CL
BIOR
BOR
BIOR
BOR
OR
4
BIXOR
BXOR
BIXOR
BXOR
XOR
5
BIAND
BAND
BIAND
BAND
AND
6
7
BIST
BILD
BST
BLD
BIST
BILD
BST
BLD
1st byte 2nd byte 3rd byte 4th byte
AH AL BH BL CH CL DH DL
8
LDC
STC
9
A
LDC
STC
B
C
LDC
STC
D
E
LDC
STC
F
Instruction when most significant bit of DH is 1.
Instruction when most significant bit of DH is 0.
Table A.2
AH
ALBH
BLCH
Instruction code:
Appendix
Operation Code Map (3)
Appendix
A.3
Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,
L=M=N=0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev.5.00 Nov. 02, 2005 Page 373 of 418
REJ09B0028-0500
Appendix
Table A.3
Number of Cycles in Each Instruction
Access Location
Execution Status
(Instruction Cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3*
Word data access
SM
2 or 3*
Internal operation
SN
Note:
*
1
Depends on which on-chip peripheral module is accessed. See section 20.1, Register
Addresses (Address Order).
Rev.5.00 Nov. 02, 2005 Page 374 of 418
REJ09B0028-0500
Appendix
Table A.4
Number of Cycles in Each Instruction
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W #xx:16, Rd
2
ADD.W Rs, Rd
1
ADD.L #xx:32, ERd
3
ADD.L ERs, ERd
1
ADDS
ADDS #1/2/4, ERd
1
ADDX
ADDX #xx:8, Rd
1
ADDX Rs, Rd
1
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
AND.W #xx:16, Rd
2
AND.W Rs, Rd
1
AND.L #xx:32, ERd
3
AND
Stack
K
AND.L ERs, ERd
2
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
BAND #xx:3, @ERd
2
1
BAND #xx:3, @aa:8
2
1
Bcc
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
Rev.5.00 Nov. 02, 2005 Page 375 of 418
REJ09B0028-0500
Appendix
Instruction Mnemonic
Bcc
BCLR
BIAND
BILD
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Stack
Access
Access
Operation
I
J
L
M
N
K
BLT d:8
2
BGT d:8
2
BLE d:8
2
BRA d:16(BT d:16)
2
2
BRN d:16(BF d:16)
2
2
BHI d:16
2
2
BLS d:16
2
2
BCC d:16(BHS d:16)
2
2
BCS d:16(BLO d:16)
2
2
BNE d:16
2
2
BEQ d:16
2
2
BVC d:16
2
2
BVS d:16
2
2
BPL d:16
2
2
BMI d:16
2
2
BGE d:16
2
2
BLT d:16
2
2
BGT d:16
2
2
BLE d:16
2
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @ERd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @ERd
2
2
BCLR Rn, @aa:8
2
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @ERd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD #xx:3, @ERd
2
1
BILD #xx:3, @aa:8
2
1
Rev.5.00 Nov. 02, 2005 Page 376 of 418
REJ09B0028-0500
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
BIOR
BIOR #xx:8, Rd
1
BIOR #xx:8, @ERd
2
1
BIOR #xx:8, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @ERd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @ERd
2
1
1
BIST
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
Stack
K
BIXOR #xx:3, @aa:8
2
BLD #xx:3, Rd
1
BLD #xx:3, @ERd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @ERd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @ERd
2
2
2
BNOT Rn, @aa:8
2
BOR #xx:3, Rd
1
BOR #xx:3, @ERd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @ERd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @ERd
2
2
BSET Rn, @aa:8
2
2
BSR d:8
2
1
BSR d:16
2
1
BST #xx:3, Rd
1
BST #xx:3, @ERd
2
2
BST #xx:3, @aa:8
2
2
2
Rev.5.00 Nov. 02, 2005 Page 377 of 418
REJ09B0028-0500
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
BTST
BTST #xx:3, Rd
1
BTST #xx:3, @ERd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @ERd
2
1
1
BXOR
CMP
Stack
K
BTST Rn, @aa:8
2
BXOR #xx:3, Rd
1
BXOR #xx:3, @ERd
2
1
BXOR #xx:3, @aa:8
2
1
CMP.B #xx:8, Rd
1
CMP.B Rs, Rd
1
CMP.W #xx:16, Rd
2
CMP.W Rs, Rd
1
CMP.L #xx:32, ERd
3
CMP.L ERs, ERd
1
DAA
DAA Rd
1
DAS
DAS Rd
1
DEC
DEC.B Rd
1
DEC.W #1/2, Rd
1
DEC.L #1/2, ERd
1
DIVXS.B Rs, Rd
2
12
DIVXS.W Rs, ERd
2
20
DIVXU.B Rs, Rd
1
12
DIVXU.W Rs, ERd
1
DUVXS
DIVXU
EEPMOV
EXTS
EXTU
20
1
EEPMOV.B
2
2n+2*
EEPMOV.W
2
2n+2*1
EXTS.W Rd
1
EXTS.L ERd
1
EXTU.W Rd
1
EXTU.L ERd
1
Rev.5.00 Nov. 02, 2005 Page 378 of 418
REJ09B0028-0500
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
INC
INC.B Rd
1
INC.W #1/2, Rd
1
INC.L #1/2, ERd
1
JMP @ERn
2
JMP @aa:24
2
JMP @@aa:8
2
JSR @ERn
2
1
JSR @aa:24
2
1
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
LDC@ERs, CCR
2
1
LDC@(d:16, ERs), CCR
3
1
LDC@(d:24,ERs), CCR
5
1
LDC@ERs+, CCR
2
1
LDC@aa:16, CCR
3
1
LDC@aa:24, CCR
4
1
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @ERs, Rd
1
1
MOV.B @(d:16, ERs), Rd
2
1
MOV.B @(d:24, ERs), Rd
4
1
MOV.B @ERs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B @aa:24, Rd
3
1
MOV.B Rs, @Erd
1
1
MOV.B Rs, @(d:16, ERd)
2
1
MOV.B Rs, @(d:24, ERd)
4
1
MOV.B Rs, @-ERd
1
1
MOV.B Rs, @aa:8
1
1
JMP
JSR
LDC
MOV
Stack
K
2
2
1
1
2
1
2
2
2
Rev.5.00 Nov. 02, 2005 Page 379 of 418
REJ09B0028-0500
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
MOV
MOV.B Rs, @aa:16
2
1
MOV.B Rs, @aa:24
3
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @ERs, Rd
1
1
MOV.W @(d:16,ERs), Rd
2
1
MOV.W @(d:24,ERs), Rd
4
1
MOV.W @ERs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W @aa:24, Rd
3
1
MOV.W Rs, @ERd
1
1
MOV.W Rs, @(d:16,ERd)
2
1
MOV.W Rs, @(d:24,ERd)
4
1
MOV.W Rs, @-ERd
1
1
MOV.W Rs, @aa:16
2
1
MOV.W Rs, @aa:24
3
1
MOV.L #xx:32, ERd
3
MOV.L ERs, ERd
1
MOV.L @ERs, ERd
2
2
MOV.L @(d:16,ERs), ERd
3
2
MOV.L @(d:24,ERs), ERd
5
2
MOV.L @ERs+, ERd
2
2
MOV.L @aa:16, ERd
3
2
MOV.L @aa:24, ERd
4
2
MOV.L ERs,@ERd
2
2
MOV.L ERs, @(d:16,ERd)
3
2
MOV.L ERs, @(d:24,ERd)
5
2
MOV.L ERs, @-ERd
2
2
MOV.L ERs, @aa:16
3
2
MOV.L ERs, @aa:24
4
2
MOV
2
Stack
K
MOVFPE
MOVFPE @aa:16, Rd*
2
1
MOVTPE
MOVTPE Rs,@aa:16*2
2
1
Rev.5.00 Nov. 02, 2005 Page 380 of 418
REJ09B0028-0500
2
2
2
2
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
MULXS
MULXS.B Rs, Rd
2
12
MULXS.W Rs, ERd
2
20
MULXU
MULXU.B Rs, Rd
1
12
MULXU.W Rs, ERd
1
20
NEG.B Rd
1
NEG.W Rd
1
NEG
NEG.L ERd
1
NOP
NOP
1
NOT
NOT.B Rd
1
NOT.W Rd
1
NOT.L ERd
1
OR
Stack
K
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
OR.W #xx:16, Rd
2
OR.W Rs, Rd
1
OR.L #xx:32, ERd
3
OR.L ERs, ERd
2
ORC
ORC #xx:8, CCR
1
POP
POP.W Rn
1
1
2
POP.L ERn
2
2
2
PUSH.W Rn
1
1
2
PUSH.L ERn
2
2
2
ROTL.B Rd
1
ROTL.W Rd
1
ROTL.L ERd
1
ROTR.B Rd
1
ROTR.W Rd
1
ROTR.L ERd
1
ROTXL.B Rd
1
ROTXL.W Rd
1
ROTXL.L ERd
1
PUSH
ROTL
ROTR
ROTXL
Rev.5.00 Nov. 02, 2005 Page 381 of 418
REJ09B0028-0500
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
L
M
N
ROTXR
ROTXR.B Rd
1
ROTXR.W Rd
1
ROTXR.L ERd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAL.W Rd
1
SHAL.L ERd
1
SHAR.B Rd
1
SHAR.W Rd
1
SHAR.L ERd
1
SHAR
SHLL
SHLR
SHLL.B Rd
1
SHLL.W Rd
1
SHLL.L ERd
1
SHLR.B Rd
1
SHLR.W Rd
1
Stack
K
SHLR.L ERd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
STC CCR, @ERd
2
1
STC CCR, @(d:16,ERd)
3
1
STC CCR, @(d:24,ERd)
5
1
STC CCR,@-ERd
2
1
STC CCR, @aa:16
3
1
STC CCR, @aa:24
4
1
SUB.B Rs, Rd
1
SUB.W #xx:16, Rd
2
SUB.W Rs, Rd
1
SUB.L #xx:32, ERd
3
SUB.L ERs, ERd
1
SUBS #1/2/4, ERd
1
SUB
SUBS
Rev.5.00 Nov. 02, 2005 Page 382 of 418
REJ09B0028-0500
2
Appendix
Instruction
Branch
Byte Data
Word Data
Internal
Fetch
Addr. Read Operation
Access
Access
Operation
Instruction Mnemonic
I
J
K
L
M
N
SUBX
SUBX #xx:8, Rd
1
1
2
SUBX. Rs, Rd
1
TRAPA
TRAPA #xx:2
2
XOR
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC #xx:8, CCR
1
XORC
Stack
4
Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1
times respectively.
2. It can not be used in this LSI.
Rev.5.00 Nov. 02, 2005 Page 383 of 418
REJ09B0028-0500
Appendix
A.4
Combinations of Instructions and Addressing Modes
Table A.5
Combinations of Instructions and Addressing Modes
Arithmetic
operations
MOVTPE
ADD, CMP
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
MULXU,
—
@aa:24
@@aa:8
BWL BWL
WL BWL
B
B
—
L
— BWL
BWL BWL
—
—
—
—
@(d:16.PC)
B
—
—
@aa:16
@aa:8
@ERn+/@ERn
@ERn
BWL BWL BWL BWL BWL BWL
—
—
—
—
—
—
—
—
—
—
—
—
@(d:8.PC)
Data
MOV
transfer
POP, PUSH
instructions
MOVFPE,
Rn
#xx
Instructions
@(d:24.ERn)
Functions
@(d:16.ERn)
Addressing Mode
—
—
—
—
—
—
—
—
—
—
WL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
BW
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
B
WL
BWL
BWL
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
B
—
W
W
—
W
W
—
W
W
—
W
W
—
—
—
—
W
W
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
MULXS,
DIVXU,
DIVXS
NEG
Logical
operations
EXTU, EXTS
AND, OR, XOR
NOT
Shift operations
Bit manipulations
BCC, BSR
Branching
instructions JMP, JSR
RTS
TRAPA
System
control
RTE
instructions
SLEEP
LDC
STC
ANDC, ORC,
XORC
NOP
Block data transfer instructions
Rev.5.00 Nov. 02, 2005 Page 384 of 418
REJ09B0028-0500
Appendix
Appendix B I/O Port Block Diagrams
B.1
I/O Port Block Diagrams
RES goes low in a reset, and SBY goes low in a reset and in standby mode.
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
TRGV
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.1 Port 1 Block Diagram (P17)
Rev.5.00 Nov. 02, 2005 Page 385 of 418
REJ09B0028-0500
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
IRQ
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.2 Port 1 Block Diagram (P16 to P14)
Rev.5.00 Nov. 02, 2005 Page 386 of 418
REJ09B0028-0500
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PDR
PCR
[Legend]
PUCR: Port pull-up control register
PDR: Port data register
PCR: Port control register
Figure B.3 Port 1 Block Diagram (P12, P11)
Rev.5.00 Nov. 02, 2005 Page 387 of 418
REJ09B0028-0500
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
Timer A
TMOW
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.4 Port 1 Block Diagram (P10)
Rev.5.00 Nov. 02, 2005 Page 388 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
PMR
PDR
PCR
SCI3
TxD
[Legend]
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.5 Port 2 Block Diagram (P22)
Rev.5.00 Nov. 02, 2005 Page 389 of 418
REJ09B0028-0500
Appendix
SBY
Internal data bus
PDR
PCR
SCI3
RE
RxD
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.6 Port 2 Block Diagram (P21)
Rev.5.00 Nov. 02, 2005 Page 390 of 418
REJ09B0028-0500
Appendix
SBY
SCI3
SCKIE
SCKOE
Internal data bus
PDR
PCR
SCKO
SCKI
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.7 Port 2 Block Diagram (P20)
Rev.5.00 Nov. 02, 2005 Page 391 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
IIC2
ICE
SDAO/SCLO
SDAI/SCLI
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.8 Port 5 Block Diagram (P57, P56)*
Note: * This diagram is applied to the SCL and SDA pins in the H8/3694N.
Rev.5.00 Nov. 02, 2005 Page 392 of 418
REJ09B0028-0500
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
ADTRG
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.9 Port 5 Block Diagram (P55)
Rev.5.00 Nov. 02, 2005 Page 393 of 418
REJ09B0028-0500
Appendix
Internal data bus
RES
SBY
PUCR
Pull-up MOS
PMR
PDR
PCR
WKP
[Legend]
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Figure B.10 Port 5 Block Diagram (P54 to P50)
Rev.5.00 Nov. 02, 2005 Page 394 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
Timer V
OS3
OS2
OS1
OS0
PDR
PCR
TMOV
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.11 Port 7 Block Diagram (P76)
Rev.5.00 Nov. 02, 2005 Page 395 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
Timer V
TMCIV
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.12 Port 7 Block Diagram (P75)
Rev.5.00 Nov. 02, 2005 Page 396 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
Timer V
TMRIV
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.13 Port 7 Block Diagram (P74)
Rev.5.00 Nov. 02, 2005 Page 397 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.14 Port 8 Block Diagram (P87 to P85)
Rev.5.00 Nov. 02, 2005 Page 398 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
Timer W
Output
control
signals
A to D
PDR
PCR
FTIOA
FTIOB
FTIOC
FTIOD
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.15 Port 8 Block Diagram (P84 to P81)
Rev.5.00 Nov. 02, 2005 Page 399 of 418
REJ09B0028-0500
Appendix
Internal data bus
SBY
PDR
PCR
Timer W
FTCI
[Legend]
PDR: Port data register
PCR: Port control register
Figure B.16 Port 8 Block Diagram (P80)
Rev.5.00 Nov. 02, 2005 Page 400 of 418
REJ09B0028-0500
Appendix
Internal data bus
A/D converter
CH3 to CH0
DEC
VIN
Figure B.17 Port B Block Diagram (PB7 to PB0)
B.2
Port States in Each Operating State
Port
Reset
Sleep
Subsleep
Standby
Subactive
Active
P17 to P14,
P12 to P10
High
impedance
Retained
Retained
High
Functioning
impedance*1
Functioning
P22 to P20
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
P57 to P50*2 High
impedance
Retained
Retained
High
Functioning
impedance*1
Functioning
P76 to P74
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
P87 to P80
High
impedance
Retained
Retained
High
impedance
Functioning
Functioning
PB7 to PB0
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
Notes: 1. High level output when the pull-up MOS is in on state.
2. The P55 to P50 pins are applied to the H8/3694N.
Rev.5.00 Nov. 02, 2005 Page 401 of 418
REJ09B0028-0500
Appendix
Appendix C Product Code Lineup
Product Classification
Product Code Model Marking
Package Code
H8/3694
HD64F3694H
HD64F3694H
QFP-64 (FP-64A)
HD64F3694FP
HD64F3694FP
LQFP-64 (FP-64E)
HD64F3694FX
HD64F3694FX
LQFP-48 (FP-48F)
Flash memory Standard
version
product
Mask ROM
version
HD64F3694FY
HD64F3694FY
LQFP-48 (FP-48B)
HD64F3694FT
HD64F3694FT
QFN-48(TNP-48)
Product with HD64F3694GH HD64F3694GH
POR & LVDC HD64F3694GFP HD64F3694GFP
LQFP-64 (FP-64E)
HD64F3694GFX HD64F3694GFX
LQFP-48 (FP-48F)
HD64F3694GFY HD64F3694GFY
LQFP-48 (FP-48B)
HD64F3694GFT HD64F3694GFT
QFN-48(TNP-48)
HD6433694H
HD6433694(***)H
QFP-64 (FP-64A)
HD6433694FP
HD6433694(***)FP
LQFP-64 (FP-64E)
HD6433694FX
HD6433694(***)FX
LQFP-48 (FP-48F)
HD6433694FY
HD6433694(***)FY
LQFP-48 (FP-48B)
HD6433694FT
HD6433694(***)FT
QFN-48(TNP-48)
Product with HD6433694GH
POR & LVDC
HD6433694G(***)H
QFP-64 (FP-64A)
Standard
product
QFP-64 (FP-64A)
HD6433694GFP HD6433694G(***)FP LQFP-64 (FP-64E)
HD6433694GFX HD6433694G(***)FX LQFP-48 (FP-48F)
HD6433694GFY HD6433694G(***)FY LQFP-48 (FP-48B)
HD6433694GFT HD6433694G(***)FT QFN-48(TNP-48)
H8/3693
Mask ROM
version
Standard
product
HD6433693H
HD6433693(***)H
QFP-64 (FP-64A)
HD6433693FP
HD6433693(***)FP
LQFP-64 (FP-64E)
HD6433693FX
HD6433693(***)FX
LQFP-48 (FP-48F)
HD6433693FY
HD6433693(***)FY
LQFP-48 (FP-48B)
HD6433693FT
HD6433693(***)FT
QFN-48(TNP-48)
Product with HD6433693GH HD6433693G(***)H QFP-64 (FP-64A)
POR & LVDC HD6433693GFP HD6433693G(***)FP LQFP-64 (FP-64E)
HD6433693GFX HD6433693G(***)FX LQFP-48 (FP-48F)
HD6433693GFY HD6433693G(***)FY LQFP-48 (FP-48B)
HD6433693GFT HD6433693G(***)FT QFN-48(TNP-48)
Rev.5.00 Nov. 02, 2005 Page 402 of 418
REJ09B0028-0500
Appendix
Product Classification
H8/3692 Mask ROM
version
H8/3691 Mask ROM
version
Product Code Model Marking
Package Code
HD6433692H
HD6433692(***)H
QFP-64 (FP-64A)
HD6433692FP
HD6433692(***)FP
LQFP-64 (FP-64E)
HD6433692FX
HD6433692(***)FX
LQFP-48 (FP-48F)
HD6433692FY
HD6433692(***)FY
LQFP-48 (FP-48B)
HD6433692FT
HD6433692(***)FT
QFN-48(TNP-48)
Product with HD6433692GH
POR & LVDC
HD6433692G(***)H
QFP-64 (FP-64A)
HD6433692GFP
HD6433692G(***)FP
LQFP-64 (FP-64E)
HD6433692GFX
HD6433692G(***)FX
LQFP-48 (FP-48F)
HD6433692GFY
HD6433692G(***)FY
LQFP-48 (FP-48B)
HD6433692GFT
HD6433692G(***)FT
QFN-48(TNP-48)
HD6433691H
HD6433691(***)H
QFP-64 (FP-64A)
HD6433691FP
HD6433691(***)FP
LQFP-64 (FP-64E)
HD6433691FX
HD6433691(***)FX
LQFP-48 (FP-48F)
HD6433691FY
HD6433691(***)FY
LQFP-48 (FP-48B)
HD6433691FT
HD6433691(***)FT
QFN-48(TNP-48)
Standard
product
Standard
product
Product with HD6433691GH HD6433691G(***)H
POR & LVDC HD6433691GFP HD6433691G(***)FP
H8/3690 Mask ROM
version
QFP-64 (FP-64A)
LQFP-64 (FP-64E)
HD6433691GFX
HD6433691G(***)FX
LQFP-48 (FP-48F)
HD6433691GFY
HD6433691G(***)FY
LQFP-48 (FP-48B)
HD6433691GFT
HD6433691G(***)FT
QFN-48(TNP-48)
HD6433690H
HD6433690(***)H
QFP-64 (FP-64A)
HD6433690FP
HD6433690(***)FP
LQFP-64 (FP-64E)
HD6433690FX
HD6433690(***)FX
LQFP-48 (FP-48F)
HD6433690FY
HD6433690(***)FY
LQFP-48 (FP-48B)
HD6433690FT
HD6433690(***)FT
QFN-48(TNP-48)
Product with HD6433690GH
POR & LVDC
HD6433690G(***)H
QFP-64 (FP-64A)
HD6433690GFP
HD6433690G(***)FP
LQFP-64 (FP-64E)
HD6433690GFX
HD6433690G(***)FX
LQFP-48 (FP-48F)
HD6433690GFY
HD6433690G(***)FY
LQFP-48 (FP-48B)
HD6433690GFT
HD6433690G(***)FT
QFN-48(TNP-48)
Standard
product
Rev.5.00 Nov. 02, 2005 Page 403 of 418
REJ09B0028-0500
Appendix
Product Classification
Product Code Model Marking
H8/3694N EEPROM Flash
Product with HD64N3694GFP HD64N3694GFP
stacked memory POR & LVDC
version
version
Mask
ROM
version
HD6483694GFP
REJ09B0028-0500
LQFP-64 (FP-64E)
HD6483694G(***)FP LQFP-64 (FP-64E)
Legend:
(***): ROM code.
POR & LVDC: Power-on reset and low-voltage detection circuits.
Rev.5.00 Nov. 02, 2005 Page 404 of 418
Package Code
64
e
ZD
1
y
*3
bp
Index mark
D
16
33
x
F
M
17
32
E
*2
49
48
*1
MASS[Typ.]
0.4g
Detail F
L1
L
Terminal cross section
b1
bp
θ
11.8
0.5
L
1.0
1.25
ZE
L1
1.25
ZD
0.7
0.08
8°
0.10
0.5
0.22
y
0.3
0°
0.15
0.27
x
e
θ
c1
0.20
0.17
c
0.22
b1
0.12
0.17
0.20
bp
1.70
0.10
A1
12.2
12.2
Max
A
0.00
12.0
12.0
HD
11.8
A2
HE
10
1.45
E
10
Nom
Dimension in Millimeters
Min
D
Reference
Symbol
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c1
HD
Previous Code
FP-64E/FP-64EV
A2
A1
c
A
HE
ZE
RENESAS Code
PLQP0064KC-A
c
JEITA Package Code
P-LQFP64-10x10-0.50
Appendix
Appendix D Package Dimensions
The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have
priority.
Figure D.1 FP-64E Package Dimensions
Rev.5.00 Nov. 02, 2005 Page 405 of 418
REJ09B0028-0500
Figure D.2 FP-64A Package Dimensions
64
e
1
ZD
D
HD
y
*3
bp
16
33
x
F
M
17
32
E
*2
49
48
*1
Previous Code
FP-64A/FP-64AV
MASS[Typ.]
1.2g
Detail F
L1
L
Terminal cross section
b1
bp
θ
17.2
16.9
16.9
A2
HD
HE
0.5
1.6
0.8
L
L1
1.0
ZE
1.1
0.10
1.0
ZD
0.15
8°
y
0.8
0.22
x
e
θ
0°
0.17
0.15
c
c1
0.35
b1
0.12
0.29
bp
0.45
0.25
0.00
A1
0.37
3.05
17.5
17.5
Max
A
0.10
17.2
14
2.70
E
14
Nom
Dimension in Millimeters
Min
D
Reference
Symbol
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c1
HE
ZE
RENESAS Code
PRQP0064GB-A
c
REJ09B0028-0500
A2
A1
Rev.5.00 Nov. 02, 2005 Page 406 of 418
c
JEITA Package Code
P-QFP64-14x14-0.80
Appendix
A
48
e
ZD
1
*3
bp
y
Index mark
D
HD
12
25
x
M
F
13
24
E
*2
37
36
*1
MASS[Typ.]
0.4g
Detail F
L1
L
Terminal cross section
b1
bp
θ
11.8
0.1
0.5
L
1.0
1.425
ZE
L1
1.425
ZD
0.6
0.10
8°
0.22
0.13
0.65
0.15
0.17
0.37
y
0.4
0°
0.12
0.30
0.32
x
e
θ
c1
c
b1
0.27
0.15
bp
A1
12.2
12.2
1.70
0.05
12.0
12.0
Max
A
HE
HD
11.8
10
1.45
E
A2
10
Nom
Dimension in Millimeters
Min
D
Reference
Symbol
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c1
Previous Code
FP-48F/FP-48FV
A2
A1
c
A
HE
ZE
RENESAS Code
PLQP0048JA-A
c
JEITA Package Code
P-LQFP48-10x10-0.65
Appendix
Figure D.3 FP-48F Package Dimensions
Rev.5.00 Nov. 02, 2005 Page 407 of 418
REJ09B0028-0500
Figure D.4 FP-48B Package Dimensions
48
e
ZD
1
D
HD
*3
bp
y
12
25
x
M
F
13
24
E
*2
37
36
*1
Previous Code
FP-48B/FP-48BV
MASS[Typ.]
0.2g
Detail F
L1
L
Terminal cross section
b1
bp
θ
0.10
0.17
L1
1.0
0.5
0.75
ZE
L
0.75
ZD
0.6
0.08
8°
0.22
0.27
0.08
0.5
0.15
0.17
0.20
0.22
y
0.4
0°
0.12
0.17
1.70
9.2
9.2
Max
x
e
θ
c1
c
b1
bp
A1
0.03
9.0
8.8
A
9.0
8.8
A2
HE
7
1.40
E
HD
7
Nom
Dimension in Millimeters
Min
D
Reference
Symbol
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
c1
HE
ZE
RENESAS Code
PLQP0048KC-A
c
REJ09B0028-0500
A2
A1
Rev.5.00 Nov. 02, 2005 Page 408 of 418
c
JEITA Package Code
P-LQFP48-7x7-0.50
Appendix
A
E
c
c1
HE
48
37
1
36
x4
D
y
y1
t
HD
ZD
12
25
RENESAS Code
PVQN0048KA-A
13
24
ZE
A2
A
1
Previous Code
TNP-48/TNP-48V
MASS[Typ.]
0.1g
b
b1
×M
e
Lp
A
JEITA Package Code
P-VQFN48-7x7-0.50
7.0
0.5
0.47
0.05
c
1
E
Z
0.15
0.17
0.75
D
c
7.2
0.75
HE
Z
7.2
HD
t
0.22
0.20
0.20
0.35
0.05
0.12
0.23
0.20
y
1
p
1
y
x
L
e
b
0.04
0.27
0.17
b
0.22
1.00
0.02
0.005
A1
Max
A
0.90
E
A2
7.0
Nom
Dimension in Millimeters
Min
D
Reference
Symbol
Appendix
Figure D.5 TNP-48 Package Dimensions
Rev.5.00 Nov. 02, 2005 Page 409 of 418
REJ09B0028-0500
Appendix
Appendix E EEPROM Stacked-Structure
Cross-Sectional View
Figure E.1 EEPROM Stacked-Structure Cross-Sectional View
Rev.5.00 Nov. 02, 2005 Page 410 of 418
REJ09B0028-0500
Main Revisions and Additions in this Edition
Item
Page Revision (See Manual for Details)
Preface
vi, vii
Notes:
When using the on-chip emulator (E7, E8) for H8/3694 program
development and debugging, the following restrictions must be
noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be
used.
3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not
available to the user.
5. When the E7 or E8 is used, address breaks can be set as
either available to the user or for use by the E7 or E8. If
address breaks are set as being used by the E7 or E8, the
address break control registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin
(open-drain in output mode), P85 and P87 are input pins,
and P86 is an output pin.
Note has been deleted.
Figure 1.1 Internal Block
Diagram of H8/3694
TM
Group of F-ZTAT
and Mask-ROM Versions,
Figure 1.2 Internal Block
Diagram of H8/3694N
(EEPROM Stacked
Version)
4, 5
Timer V
IIC2
A/D
converter
POR/LVD
(optional)
Port B
Section 1 Overview
Data bus (upper)
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Address bus
AVCC
Rev.5.00 Nov. 02, 2005 Page 411 of 418
REJ09B0028-0500
Item
Page Revision (See Manual for Details)
Section 5 Clock Pulse
Generators
70
C1
OSC 1
Figure 5.3 Typical
Connection to Crystal
Resonator
Figure 5.5 Typical
Connection to Ceramic
Resonator
OSC 2
71
C2
C1 = C 22 = 10 to 22 pF
C1
OSC1
C2
OSC2
Section 6 Power-Down
Modes
6.1.1 System Control
Register 1 (SYSCR1)
76
Bit
Bit Name Description
3
NESEL
C1 = 5 to 30 pF
C2 = 5 to 30 pF
Noise Elimination Sampling Frequency
Select
The subclock pulse generator generates the
watch clock signal (φW) and the system clock
pulse generator generates the oscillator
clock (φOSC). This bit selects the sampling
frequency of the oscillator clock when the
watch clock signal (φW) is sampled. When
φOSC = 4 to 20 MHz, clear NESEL to 0.
Section 8 RAM
107
Section 13 Watchdog
Timer
13.2.1 Timer
Control/Status Register
WD (TCSRWD)
184
Note: * When the E7 or E8 is used, area H'F780 to H'FB7F
must not be accessed.
Bit
Bit Name Description
4
TCSRWE Timer Control/Status Register WD Write Enable
Rev.5.00 Nov. 02, 2005 Page 412 of 418
REJ09B0028-0500
Item
Page Revision (See Manual for Details)
2
Section 15 I C Bus
Interface 2 (IIC2)
15.3.5 I2C Bus Status
Register (ICSR)
242
Bit
Bit Name
Description
3
STOP
Stop Condition Detection Flag
[Setting conditions]
•
In master mode, when a stop condition is
detected after frame transfer
•
In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with
the address set in SAR
15.7 Usage Notes
264
Section 16 A/D Converter 268
16.3.1 A/D Data Registers
A to D (ADDRA to
ADDRD)
Section 18 Power-On
Reset and Low-Voltage
Detection Circuits
(Optional)
Added
Therefore byte access to ADDR should be done by reading the
upper byte first then the lower one. Word access is also
possible. ADDR is initialized to H'0000.
290
RES
Figure 18.1 Block
Diagram of Power-On
Reset Circuit and LowVoltage Detection Circuit
Section 21 Electrical
Characteristics
Table 21.2 DC
Characteristics (1)
CRES
318
Item
Input high
voltage
Values
Applicable
Symbol Pins
Test Condition
Min
VIH
VCC = 4.0 to 5.5 V
VCC × 0.7
PB0 to PB7
VCC × 0.8
Input low
voltage
VIL
RXD,SCL,
SDA,
P10 to P12,
:
P80 to P87
PB0 to PB7
VCC = 4.0 to 5.5 V
–0.3
–0.3
Rev.5.00 Nov. 02, 2005 Page 413 of 418
REJ09B0028-0500
Item
Page
Table 21.2 DC
Characteristics (1)
321
Revision (See Manual for Details)
Mode
RES Pin
Internal State
Active mode 1
VCC
Operates
Active mode 2
Operates
(φOSC/64)
Sleep mode 1
VCC
Only timers operate
Sleep mode 2
Table 21.12 DC
Characteristics (1)
Only timers operate
(φOSC/64)
337
Item
Input high
voltage
Values
Applicable
Symbol Pins
Test Condition
Min
VIH
VCC = 4.0 to 5.5 V
VCC × 0.7
PB0 to PB7
VCC × 0.8
Input low
voltage
340
VIL
RXD, SCL,
SDA
P10 to P12,
:
P80 to P87
PB0 to PB7
VCC = 4.0 to 5.5 V
–0.3
Mode
RES Pin
Internal State
Active mode 1
VCC
Operates
Active mode 2
Operates
(φOSC/64)
Sleep mode 1
VCC
Only timers operate
Only timers operate
(φOSC/64)
Sleep mode 2
Figure 21.4 I2C Bus
Interface Input/Output
Timing
352
tSTAH
tSCLH
SCL
P*
Appendix D Package
Dimensions
405 to Swapped with new ones.
409
Rev.5.00 Nov. 02, 2005 Page 414 of 418
REJ09B0028-0500
–0.3
S*
tSf
tSCLL
tSCL
Index
A
A/D converter ......................................... 265
Sample-and-hold circuit...................... 272
Scan mode........................................... 271
Single mode ........................................ 271
Address break ........................................... 63
Addressing modes..................................... 34
Absolute address................................... 36
Immediate ............................................. 36
Memory indirect ................................... 37
Program-counter relative ...................... 36
Register direct....................................... 35
Register indirect.................................... 35
Register indirect with displacement...... 35
Register indirect with post-increment... 35
Register indirect with pre-decrement.... 36
C
Clock pulse generators.............................. 69
Prescaler S ............................................ 73
Prescaler W........................................... 73
Subclock generator ............................... 72
System clock generator......................... 70
Condition field.......................................... 33
Condition-code register (CCR)................. 19
CPU .......................................................... 13
Random address read .......................... 286
Sequential read.................................... 286
Slave address reference register
(ESAR)................................................ 281
Slave addressing.................................. 281
Start condition..................................... 280
Stop condition ..................................... 281
Effective address....................................... 38
Effective address extension....................... 33
Exception handling ................................... 49
Reset exception handling ...................... 56
Trap instruction..................................... 49
F
Flash memory ........................................... 87
Boot mode............................................. 93
Boot program ........................................ 93
Erase/erase-verify ............................... 100
Erasing units ......................................... 87
Error protection................................... 103
Hardware protection............................ 103
Power-down state................................ 104
Program/program-verify ....................... 98
Programmer mode............................... 104
Programming units................................ 87
Programming/erasing in user
program mode ....................................... 96
Software protection............................. 103
E
EEPROM................................................ 277
Acknowledge ...................................... 281
Acknowledge polling.......................... 284
Byte write ........................................... 283
Current address read ........................... 285
EEPROM interface ............................. 280
Page write ........................................... 283
G
General registers ....................................... 18
I
I/O ports .................................................. 109
Rev.5.00 Nov. 02, 2005 Page 415 of 418
REJ09B0028-0500
I/O port block diagrams ...................... 385
I C bus data format ................................. 246
I2C bus interface 2 (IIC2) ....................... 231
Acknowledge...................................... 247
Bit synchronous circuit....................... 263
Clocked synchronous serial format..... 255
Noise canceler .................................... 257
Slave address ...................................... 246
Start condition .................................... 246
Stop condition..................................... 247
Transfer rate........................................ 235
Instruction set ........................................... 24
Arithmetic operations instructions........ 26
Bit Manipulation instructions ............... 29
Block data transfer instructions ............ 33
Branch instructions ............................... 31
Data transfer instructions...................... 25
Logic operations instructions................ 28
Shift instructions................................... 28
System control instructions................... 32
Internal power supply stepdown circuit ............................................ 299
Interrupt
Internal interrupts ................................. 58
Interrupt response time ......................... 60
IRQ3 to IRQ0 interrupts ....................... 57
NMI interrupt........................................ 57
WKP5 to WKP0 interrupts ................... 57
Interrupt mask bit (I)................................. 19
2
L
Large current ports...................................... 2
Low-voltage detection circuit ................. 289
LVDI ...................................................... 295
LVDI (interrupt by low voltage detect)
circuit...................................................... 295
LVDR ..................................................... 294
LVDR (reset by low voltage
detect) circuit .......................................... 294
Rev.5.00 Nov. 02, 2005 Page 416 of 418
REJ09B0028-0500
M
Memory map............................................. 14
Module standby function .......................... 86
O
On-board programming modes ................. 93
Operation field .......................................... 33
P
Package ....................................................... 3
Package dimensions................................ 405
Pin arrangement .......................................... 6
Power-down modes................................... 75
Sleep mode............................................ 83
Standby mode ....................................... 83
Subactive mode..................................... 84
Subsleep mode ...................................... 83
Power-on reset ........................................ 289
Power-on reset circuit ............................. 293
Product code lineup ................................ 402
Program counter (PC) ............................... 19
R
Register
ABRKCR...................... 64, 304, 309, 312
ABRKSR ...................... 65, 304, 309, 312
ADCR ......................... 270, 304, 308, 312
ADCSR ....................... 269, 304, 308, 312
ADDRA ...................... 268, 303, 308, 312
ADDRB ...................... 268, 304, 308, 312
ADDRC ...................... 268, 304, 308, 312
ADDRD ...................... 268, 304, 308, 312
BARH ........................... 66, 304, 309, 312
BARL............................ 66, 304, 309, 312
BDRH ........................... 66, 304, 309, 312
BDRL............................ 66, 304, 309, 312
BRR ............................ 198, 303, 308, 312
EBR1 ............................ 91, 303, 308, 311
EKR ............................ 279, 306, 310, 313
FENR............................ 92, 303, 308, 311
FLMCR1....................... 89, 303, 308, 311
FLMCR2....................... 90, 303, 308, 311
FLPWCR ...................... 92, 303, 308, 311
GRA............................ 165, 302, 307, 311
GRB............................ 165, 303, 307, 311
GRC............................ 165, 303, 307, 311
GRD............................ 165, 303, 307, 311
ICCR1......................... 234, 302, 307, 311
ICCR2......................... 236, 302, 307, 311
ICDRR........................ 245, 302, 307, 311
ICDRS ................................................ 245
ICDRT ........................ 245, 302, 307, 311
ICIER.......................... 239, 302, 307, 311
ICMR.......................... 237, 302, 307, 311
ICSR ........................... 241, 302, 307, 311
IEGR1........................... 51, 306, 309, 313
IEGR2........................... 52, 306, 309, 313
IENR1........................... 53, 306, 309, 313
IRR1 ............................. 54, 306, 309, 313
IWPR ............................ 55, 306, 309, 313
LVDCR....................... 290, 302, 307, 311
LVDSR ....................... 292, 302, 307, 311
MSTCR1....................... 79, 306, 309, 313
PCR1........................... 111, 305, 309, 313
PCR2........................... 115, 305, 309, 313
PCR5........................... 119, 305, 309, 313
PCR7........................... 124, 305, 309, 313
PCR8........................... 126, 305, 309, 313
PDR1 .......................... 111, 305, 309, 312
PDR2 .......................... 115, 305, 309, 312
PDR5 .......................... 119, 305, 309, 312
PDR7 .......................... 124, 305, 309, 312
PDR8 .......................... 127, 305, 309, 312
PDRB.......................... 130, 305, 309, 312
PMR1.......................... 110, 305, 309, 313
PMR5.......................... 118, 305, 309, 313
PUCR1........................ 112, 305, 309, 312
PUCR5 ........................ 120, 305, 309, 312
RDR ............................ 192, 303, 308, 312
RSR..................................................... 192
SAR............................. 244, 302, 307, 311
SCR3........................... 194, 303, 308, 312
SMR ............................ 193, 303, 308, 312
SSR ............................. 196, 303, 308, 312
SYSCR1........................ 76, 306, 309, 313
SYSCR2........................ 78, 306, 309, 313
TCA ............................ 134, 303, 308, 312
TCNT .......................... 164, 302, 307, 311
TCNTV ....................... 139, 303, 308, 312
TCORA....................... 139, 303, 308, 311
TCORB ....................... 139, 303, 308, 311
TCRV0........................ 140, 303, 308, 311
TCRV1........................ 143, 303, 308, 312
TCRW......................... 158, 302, 307, 311
TCSRV........................ 142, 303, 308, 311
TCSRWD.................... 184, 304, 308, 312
TCWD......................... 185, 304, 308, 312
TDR ............................ 192, 303, 308, 312
TIERW........................ 159, 302, 307, 311
TIOR0 ......................... 161, 302, 307, 311
TIOR1 ......................... 163, 302, 307, 311
TMA............................ 133, 303, 308, 312
TMRW ........................ 157, 302, 307, 311
TMWD........................ 186, 304, 309, 312
TSR ..................................................... 192
TSRW ......................... 160, 302, 307, 311
Register field............................................. 33
S
Serial communication interface 3
(SCI3) ..................................................... 189
Asynchronous mode............................ 205
Bit rate................................................. 198
Break................................................... 229
Clocked synchronous mode ................ 213
Framing error ...................................... 209
Rev.5.00 Nov. 02, 2005 Page 417 of 418
REJ09B0028-0500
Mark state ........................................... 229
Multiprocessor communication
function............................................... 221
Overrun error ...................................... 209
Parity error.......................................... 209
Stacked-structure cross sectional
view of H8/3694N .................................. 410
Stack pointer (SP)..................................... 19
Timer V................................................... 137
Timer W.................................................. 153
V
Vector address........................................... 49
W
T
Timer A .................................................. 131
Rev.5.00 Nov. 02, 2005 Page 418 of 418
REJ09B0028-0500
Watchdog timer....................................... 183
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/3694 Group
Publication Date: 1st Edition, Jul, 2001
Rev.5.00, Nov. 02, 2005
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
2005. Renesas Technology Corp. All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
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REJ09B0028-0500