Qimonda HYS64D32020HDL-6-C 200-pin small outline dual-in-line memory module Datasheet

September 2006
HYS64D 32020[ H / G] DL – 5 – C
HYS64D[32/16]0x0[H/G]DL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Internet Data Sheet
Rev. 1.31
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
HYS64D32020[H/G]DL–5–C, HYS64D[32/16]0x0[H/G]DL–6–C
Revision History: 2006-09, Rev. 1.31
Page
Subjects (major changes since last revision)
All
Qimonda update
All
Adapted internet edition
Previous Revision: 2006-01, Rev. 1.3
24
Changed tRFC (for DDR400) from 70 ns to 65 ns as programmed in byte 42 SPD Code
Previous Revision: 2005-03, Rev. 1.2
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03292006-VN6D-DETI
2
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
1
Overview
This chapter lists all main features of the product family HYS64D[32/16]0x0[G/H]DL–[5/6]–C and the ordering information.
1.1
Features
• Non-parity 200-Pin Small Outline Dual-In-Line Memory
Modules
• One rank 16M ×64 and two ranks 32M ×64 organization
• Standard Double Data Rate Synchronous DRAMs (DDR
SDRAM)
• Single +2.5 V (± 0.2 V) power supply
• Built with 256-Mbit DDR SDRAMs organised as ×16 in P–
TSOPII–66–1 packages
• Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• RAS-lockout supported tRAP=tRCD
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E2PROM
• Standard form factor: 67.60 mm × 31.75 mm × 3.80 mm
• Standard reference layout Raw Cards A and C
• Gold contacts
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
@CL3
@CL2.5
@CL2
Rev. 1.31, 2006-09
03292006-VN6D-DETI
fCK3
fCK2.5
fCK2
3
–5
–6
Unit
DDR400B
DDR333B
—
200
166
MHz
166
166
MHz
133
133
MHz
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
1.2
Description
The
HYS64D3 2020 [H/G]DL –5– C
and
HYS64D[32/16]0x0[H/G]DL–6–C are industry standard
200-Pin Small Outline Dual-In-Line Memory Modules (SODIMMs) organized as 32M × 64. The memory array is
designed with Double Data Rate Synchronous DRAMs (DDR
SDRAM). A variety of decoupling capacitors are mounted on
the PC board. The DIMMs feature serial presence detect
based on a serial E2PROM device using the 2-Pin I2C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
TABLE 2
Ordering Information for Lead Containing Products
Product Type
Compliance Code
Description
SDRAM Technology
PC3200S–3033–1–A1
two ranks 256 MB SO-DIMM
256 Mbit (×16)
HYS64D16000GDL–6–C
PC2700S–2533–0–C1
one rank 128 MB SO-DIMM
256 Mbit (×16)
HYS64D32020GDL–6–C
PC2700S–2533–0–A1
two ranks 256 MB SO-DIMM
256 Mbit (×16)
PC3200 (CL=3.0)
HYS64D32020GDL–5–C
PC2700 (CL=2.5)
TABLE 3
Ordering Information for RoHS Compliant Products
Product Type
1)
Compliance Code
Description
SDRAM Technology
PC3200S–3033–1–A1
two ranks 256 MB SO-DIMM
256 Mbit (×16)
HYS64D16000HDL–6–C
PC2700S–2533–0–C1
one rank 128 MB SO-DIMM
256 Mbit (×16)
HYS64D32020HDL–6–C
PC2700S–2533–0–A1
two ranks 256 MB SO-DIMM
256 Mbit (×16)
PC3200 (CL=3.0)
HYS64D32020HDL–5–C
PC2700 (CL=2.5)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Notes
1. Allproduct types end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS64D32020GDL-6-C, indicating rev. C dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and
SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge
latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Rev. 1.31, 2006-09
03292006-VN6D-DETI
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Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered Small Outline DDR
SDRAM DIMM is listed by function in Table 4 (200 pins). The
abbreviations used in columns Pin and Buffer Type are
explained in Table 5 and Table 6 respectively. The pin
numbering is depicted in Figure 1.
TABLE 4
Pin Configuration of SO-DIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
35
CK0
I
SSTL
Clock Signal
160
CK1
I
SSTL
Clock Signal
89
CK2
I
SSTL
Clock Signal
NC
NC
–
37
CK0
I
SSTL
Complement Clock
158
CK1
I
SSTL
Complement Clock
91
CK2
I
SSTL
Complement Clock
Clock Signals
NC
NC
–
96
CKE0
I
SSTL
Clock Enable Rank 0
95
CKE1
I
SSTL
Clock Enable Rank 1
Note: 2-rank module
NC
NC
–
Note: 1-rank module
Control Signals
121
S0
I
SSTL
Chip Select Rank 0
122
S1
I
SSTL
Chip Select Rank 1
Note: 2-ranks module
NC
NC
–
Note: 1-rank module
118
RAS
I
SSTL
Row Address Strobe
120
CAS
I
SSTL
Column Address Strobe
119
WE
I
SSTL
Write Enable
Rev. 1.31, 2006-09
03292006-VN6D-DETI
5
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
Bank Address Bus 1:0
Address Signals
117
BA0
I
SSTL
116
BA1
I
SSTL
112
A0
I
SSTL
111
A1
I
SSTL
110
A2
I
SSTL
109
A3
I
SSTL
108
A4
I
SSTL
107
A5
I
SSTL
106
A6
I
SSTL
105
A7
I
SSTL
102
A8
I
SSTL
101
A9
I
SSTL
115
A10
I
SSTL
AP
I
SSTL
100
A11
I
SSTL
99
A12
I
SSTL
Address Signal 12
Note: Module base on 256 Mbit or larger dies
NC
NC
–
Note: 128 Mbit based module
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module
NC
NC
–
Note: Module base on 512 Mbit or larger dies
5
DQ0
I/O
SSTL
Data Bus 63:0
7
DQ1
I/O
SSTL
13
DQ2
I/O
SSTL
17
DQ3
I/O
SSTL
6
DQ4
I/O
SSTL
8
DQ5
I/O
SSTL
14
DQ6
I/O
SSTL
18
DQ7
I/O
SSTL
19
DQ8
I/O
SSTL
23
DQ9
I/O
SSTL
29
DQ10
I/O
SSTL
31
DQ11
I/O
SSTL
20
DQ12
I/O
SSTL
24
DQ13
I/O
SSTL
123
Address Bus 11:0
Data Signals
Rev. 1.31, 2006-09
03292006-VN6D-DETI
6
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
30
DQ14
I/O
SSTL
Data Bus 63:0
32
DQ15
I/O
SSTL
41
DQ16
I/O
SSTL
43
DQ17
I/O
SSTL
49
DQ18
I/O
SSTL
53
DQ19
I/O
SSTL
42
DQ20
I/O
SSTL
44
DQ21
I/O
SSTL
50
DQ22
I/O
SSTL
54
DQ23
I/O
SSTL
55
DQ24
I/O
SSTL
59
DQ25
I/O
SSTL
65
DQ26
I/O
SSTL
67
DQ27
I/O
SSTL
56
DQ28
I/O
SSTL
60
DQ29
I/O
SSTL
66
DQ30
I/O
SSTL
68
DQ31
I/O
SSTL
127
DQ32
I/O
SSTL
129
DQ33
I/O
SSTL
135
DQ34
I/O
SSTL
139
DQ35
I/O
SSTL
128
DQ36
I/O
SSTL
130
DQ37
I/O
SSTL
136
DQ38
I/O
SSTL
140
DQ39
I/O
SSTL
141
DQ40
I/O
SSTL
145
DQ41
I/O
SSTL
151
DQ42
I/O
SSTL
153
DQ43
I/O
SSTL
142
DQ44
I/O
SSTL
146
DQ45
I/O
SSTL
152
DQ46
I/O
SSTL
154
DQ47
I/O
SSTL
163
DQ48
I/O
SSTL
165
DQ49
I/O
SSTL
171
DQ50
I/O
SSTL
175
DQ51
I/O
SSTL
164
DQ52
I/O
SSTL
166
DQ53
I/O
SSTL
Rev. 1.31, 2006-09
03292006-VN6D-DETI
7
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
172
DQ54
I/O
SSTL
Data Bus 63:0
176
DQ55
I/O
SSTL
177
DQ56
I/O
SSTL
181
DQ57
I/O
SSTL
187
DQ58
I/O
SSTL
189
DQ59
I/O
SSTL
178
DQ60
I/O
SSTL
182
DQ61
I/O
SSTL
188
DQ62
I/O
SSTL
190
DQ63
I/O
SSTL
71
CB0
I/O
SSTL
NC
NC
–
73
79
83
72
74
80
84
CB1
I/O
SSTL
NC
NC
–
CB2
I/O
SSTL
NC
NC
–
CB3
I/O
SSTL
NC
NC
–
CB4
I/O
SSTL
NC
NC
–
CB5
I/O
SSTL
NC
NC
–
CB6
I/O
SSTL
NC
NC
–
CB7
I/O
SSTL
NC
NC
–
11
DQS0
I/O
SSTL
25
DQS1
I/O
SSTL
47
DQS2
I/O
SSTL
61
DQS3
I/O
SSTL
133
DQS4
I/O
SSTL
147
DQS5
I/O
SSTL
169
DQS6
I/O
SSTL
183
DQS7
I/O
SSTL
77
DQS8
I/O
SSTL
NC
NC
–
Rev. 1.31, 2006-09
03292006-VN6D-DETI
Check Bit 0
Check Bit 1
Check Bit 2
Check Bit 3
Check Bit 4
Check Bit 5
Check Bit 6
Check Bit 7
Data Strobes 7:0
Data Strobe 8
8
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
12
DM0
I
SSTL
Data Mask 7:0
26
DM1
I
SSTL
48
DM2
I
SSTL
62
DM3
I
SSTL
134
DM4
I
SSTL
148
DM5
I
SSTL
170
DM6
I
SSTL
184
DM7
I
SSTL
78
DM8
I
SSTL
NC
NC
–
195
SCL
I
CMOS
Serial Bus Clock
193
SDA
I/O
OD
Serial Bus Data
194
SA0
I
CMOS
Slave Address Select Bus 2:0
196
SA1
I
CMOS
198
SA2
I
CMOS
Data Mask 8
EEPROM
Power Supplies
1,2
197
9,10, 21, 22,
33, 34, 36,
22, 33, 34,
36, 45, 46,
57, 58, 69,
70, 81, 82,
92, 93, 94,
113, 114,
131, 132,
143, 144,
155, 156,
157, 167,
168, 179,
180, 191, 192
VREF
VDDSPD
VDD
Rev. 1.31, 2006-09
03292006-VN6D-DETI
AI
–
I/O Reference Voltage
PWR
–
EEPROM Power Supply
PWR
–
Power Supply
9
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Pin#
Name
3, 4, 15, 16,
VSS
27, 28, 38,
39, 40, 51,
52, 63, 64,
75, 76, 87,
88, 90, 103,
104, 125,
126, 137,
138,149, 150,
159, 161,
162, 173,
174,185, 186
Pin
Type
Buffer
Type
Function
GND
–
Ground Plane
Other Pins
199
VDDID
O
OD
VDD Identification
85, 86, 97,
98, 124, 200
NC
NC
–
Not connected
Rev. 1.31, 2006-09
03292006-VN6D-DETI
10
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 5
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.31, 2006-09
03292006-VN6D-DETI
11
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
FIGURE 1
Pin Configuration Diagram 200-Pin SO-DIMM
95() 3LQ
'4
3LQ
9'' 3LQ
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3LQ
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3LQ
9'' 3LQ
'46
3LQ
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'
Rev. 1.31, 2006-09
03292006-VN6D-DETI
12
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
3
Electrical Characteristics
3.1
Operating Conditions
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit
Note/ Test
Condition
min.
typ.
max.
–0.5
–
VDDQ + 0.5
V
–
–1
–
+3.6
V
–
–1
–
+3.6
V
–
Storage temperature (plastic)
VIN, VOUT
VIN
VDD
VDDQ
TA
TSTG
Power dissipation (per SDRAM component)
Short circuit output current
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
–1
–
+3.6
V
–
0
–
+70
°C
–
-55
–
+150
°C
–
PD
–
1
–
W
–
IOUT
–
50
–
mA
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
Rev. 1.31, 2006-09
03292006-VN6D-DETI
Symbol
VDD
VDD
VDDQ
VDDQ
VDDSPD
VSS,
VSSQ
VREF
VTT
Unit Note1)/Test Condition
Values
Min.
Typ.
Max.
2.3
2.5
2.7
V
2.5
2.6
2.7
V
2.3
2.5
2.7
V
2.5
2.6
2.7
V
fCK ≤ 166 MHz
fCK > 166 MHz 2)
fCK ≤ 166 MHz 3)
fCK > 166 MHz 2)3)
2.3
2.5
3.6
V
—
0
—
0
V
—
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
4)
VREF – 0.04
—
VREF + 0.04
V
5)
13
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Parameter
Symbol
Unit Note1)/Test Condition
Values
Min.
Typ.
Max.
VIH(DC)
Input Low (Logic0) Voltage
VIL(DC)
Input Voltage Level, CK and VIN(DC)
VREF + 0.15
—
V
8)
–0.3
—
V
8)
–0.3
—
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
8)
Input Differential Voltage, CK VID(DC)
and CK Inputs
0.36
—
VDDQ + 0.6
V
8)6)
VI-Matching Pull-up Current
to Pull-down Current
VIRatio
0.71
—
1.4
—
7)
Input Leakage Current
II
–2
—
2
µA
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V
Input High (Logic1) Voltage
CK Inputs
8)9)
µA
DQs are disabled; 0 V ≤ VOUT ≤
IOZ
–5
Output High Current, Normal IOH
Strength Driver
—
—
–16.2
mA
VDDQ 8)
VOUT = 1.95 V 8)
16.2
—
—
mA
VOUT = 0.35 V8)
Output Leakage Current
Output Low Current, Normal
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C
2)
3)
4)
5)
6)
7)
8)
9)
IOL
—
5
DDR400 conditions apply for all clock frequencies above 166 MHz
Under all conditions, VDDQ must be less than or equal to VDD.
Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature
and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
Inputs are not recognized as valid until VREF stabilizes.
Values are shown per DDR SDRAM component
Rev. 1.31, 2006-09
03292006-VN6D-DETI
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Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
3.2
Current Specification and Conditions
TABLE 9
IDD Conditions
Parameter
Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operating Current Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
IDD7
Rev. 1.31, 2006-09
03292006-VN6D-DETI
15
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 10
Product Type
HYS64D32020HDL–5–C
HYS64D32020GDL–5–C
HYS64D16000HDL–6–C
HYS64D16000GDL–6–C
HYS64D32020HDL–6–C
HYS64D32020GDL–6–C
IDD Specification
Organization
256MB
128MB
256MB
×64
×64
×64
2 Ranks
1 Rank
2 Ranks
–5
–6
–6
Unit
Note 1)2)
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
450
580
240
300
380
480
mA
3)
490
620
280
340
420
520
mA
3)4)
30
40
20
20
30
40
mA
5)
240
290
100
120
200
240
mA
5)
160
220
70
100
140
190
mA
5)
100
140
40
60
90
120
mA
5)
300
360
140
150
260
300
mA
5)
510
620
280
340
420
520
mA
3)4)
530
640
300
360
440
540
mA
3)
730
980
480
640
620
820
mA
3)
11.2
22.4
5.6
11.2
11.2
22.4
mA
5)
1010
1220
720
860
860
1040
mA
3)4)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently depending on actual to DQ loading
capacitance.
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1))
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Rev. 1.31, 2006-09
03292006-VN6D-DETI
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Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
3.3
AC Characteristics
TABLE 11
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
DQ output access time from CK/CK
CK high-level width
Clock cycle time
CK low-level width
Auto precharge write recovery +
precharge time
Symbol
tAC
tCH
tCK
tCL
tDAL
–5
–6
DDR400B
DDR333
Unit Note1)/ Test
Condition
Min.
Max.
Min.
Max.
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
0.45
0.55
0.45
0.55
tCK
2)3)4)5)
5
8
6
12
ns
CL = 3.0 2)3)4)5)
6
12
6
12
ns
CL = 2.5 2)3)4)5)
7.5
12
7.5
12
ns
CL = 2.0 2)3)4)5)
0.45
0.55
0.45
0.55
tCK
tCK
2)3)4)5)
(tWR/tCK)+(tRP/tCK)
2)3)4)5)6)
tDH
DQ and DM input pulse width (each tDIPW
0.4
—
0.45
—
ns
2)3)4)5)
1.75
—
1.75
—
ns
2)3)4)5)
DQS output access time from CK/CK tDQSCK
–0.6
+0.6
–0.6
+0.6
ns
2)3)4)5)
tDQSL,H
0.35
—
0.35
—
tCK
2)3)4)5)
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
—
+0.40
—
+0.45
ns
TSOPII 2)3)4)5)
Write command to 1st DQS latching
transition
0.72
1.25
0.75
1.25
tCK
2)3)4)5)
tDS
DQS falling edge hold time from CK tDSH
0.4
—
0.45
—
ns
2)3)4)5)
0.2
—
0.2
—
tCK
2)3)4)5)
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
tHZ
Min. (tCL, tCH)
—
Min. (tCL, tCH)
—
ns
2)3)4)5)
—
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
tIH
0.6
—
0.75
—
ns
DQ and DM input hold time
input)
DQS input low (high) pulse width
(write cycle)
tDQSS
DQ and DM input setup time
(write cycle)
Data-out high-impedance time from
CK/CK
Address and control input hold time
Fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
ns
Slow slew rate
3)4)5)6)8)
Control and Addr. input pulse width
(each input)
Rev. 1.31, 2006-09
03292006-VN6D-DETI
tIPW
2.2
—
17
2.2
—
ns
2)3)4)5)9)
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Parameter
Symbol
Address and control input setup time tIS
–5
–6
DDR400B
DDR333
Unit Note1)/ Test
Condition
Min.
Max.
Min.
Max.
0.6
—
0.75
—
ns
Fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
ns
Slow slew rate
3)4)5)6)8)
Data-out low-impedance time from
CK/CK
tLZ
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)7)
Mode register set command cycle
time
tMRD
2
—
2
—
tCK
2)3)4)5)
DQ/DQS output hold time
tQH
tQHS
tRAP
tRAS
tRC
tHP – tQH
—
tHP – tQHS
—
ns
2)3)4)5)
—
+0.50
—
+0.55
ns
TSOPII 2)3)4)5)
tRCD
—
tRCD
—
ns
2)3)4)5)
40
70E+3
42
70E+3
ns
2)3)4)5)
55
—
60
—
ns
2)3)4)5)
tRCD
tREFI
tRFC
15
—
18
—
ns
2)3)4)5)
—
7.8
—
7.8
µs
2)3)4)5)10)
65
—
72
—
ns
2)3)4)5)
tRP
tRPRE
tRPST
tRRD
15
—
18
—
ns
2)3)4)5)
2)3)4)5)
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
Active to Read or Write delay
Average Periodic Refresh Interval
Auto-refresh to Active/Auto-refresh
command period
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
tWPRE
Write preamble setup time
tWPRES
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay tWTR
Exit self-refresh to non-read
tXSNR
Write preamble
0.9
1.1
0.9
1.1
0.40
0.60
0.40
0.60
tCK
tCK
10
—
12
—
ns
2)3)4)5)
0.25
—
0.25
—
tCK
2)3)4)5)
0
—
0
—
ns
2)3)4)5)11)
2)3)4)5)
0.40
0.60
0.40
0.60
tCK
2)3)4)5)12)
15
—
15
—
ns
2)3)4)5)
2
—
1
—
tCK
2)3)4)5)
75
—
75
—
ns
2)3)4)5)
command
2)3)4)5)
Exit self-refresh to read command
tXSRD
200
—
200
—
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥Σ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
Rev. 1.31, 2006-09
03292006-VN6D-DETI
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Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 1.31, 2006-09
03292006-VN6D-DETI
19
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
• Table 12 “SPD Codes for HYSHYS64D32020[H/G]DL–5–C” on Page 20
• Table 13 “SPD Codes for HYS64D16000[H/G]DL–6–C” on Page 23
• Table 14 “SPD Codes for HYS64D32020[G/H]DL–6–C” on Page 26
TABLE 12
SPD Codes for HYSHYS64D32020[H/G]DL–5–C
Product Type
HYS64D32020HDL–5–C
HYS64D32020GDL–5–C
Organization
256MB
256MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
Label Code
PC3200S–30331
PC3200S–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
1
Total number of Bytes in E2PROM
08
08
2
Memory Type (DDR = 07h)
07
07
3
Number of Row Addresses
0D
0D
4
Number of Column Addresses
09
09
5
Number of DIMM Ranks
02
02
6
Data Width (LSB)
40
40
7
Data Width (MSB)
00
00
8
Interface Voltage Levels
04
04
9
tCK @ CLmax (Byte 18) [ns]
50
50
10
tAC SDRAM @ CLmax (Byte 18) [ns]
50
50
11
Error Correction Support
00
00
12
Refresh Rate
82
82
13
Primary SDRAM Width
10
10
14
Error Checking SDRAM Width
00
00
15
tCCD [cycles]
01
01
16
Burst Length Supported
0E
0E
17
Number of Banks on SDRAM Device
04
04
18
CAS Latency
1C
1C
19
CS Latency
01
01
Rev. 1.31, 2006-09
03292006-VN6D-DETI
20
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
HYS64D32020HDL–5–C
HYS64D32020GDL–5–C
Organization
256MB
256MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
Label Code
PC3200S–30331
PC3200S–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
20
Write Latency
02
02
21
DIMM Attributes
20
20
22
Component Attributes
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
60
60
24
tAC SDRAM @ CLmax -0.5 [ns]
50
50
25
tCK @ CLmax -1 (Byte 18) [ns]
75
75
26
tAC SDRAM @ CLmax -1 [ns]
50
50
27
tRPmin [ns]
3C
3C
28
tRRDmin [ns]
28
28
29
tRCDmin [ns]
3C
3C
30
tRASmin [ns]
28
28
31
Module Density per Rank
20
20
32
tAS, tCS [ns]
60
60
33
tAH, tCH [ns]
60
60
34
tDS [ns]
40
40
35
tDH [ns]
40
40
36 - 40
Not used
00
00
41
tRCmin [ns]
37
37
42
tRFCmin [ns]
41
41
43
tCKmax [ns]
28
28
44
tDQSQmax [ns]
28
28
45
tQHSmax [ns]
50
50
46
not used
00
00
47
DIMM PCB Height
01
01
48 - 61
Not used
00
00
62
SPD Revision
10
10
63
Checksum of Byte 0-62
F6
F6
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
Rev. 1.31, 2006-09
03292006-VN6D-DETI
21
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
HYS64D32020HDL–5–C
HYS64D32020GDL–5–C
Organization
256MB
256MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
Label Code
PC3200S–30331
PC3200S–30331
JEDEC SPD Revision
Rev. 1.0
Rev. 1.0
Byte#
Description
HEX
HEX
70
Manufacturer’s JEDEC ID Code (7)
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
72
Module Manufacturer Location
xx
xx
73
Part Number, Char 1
36
36
74
Part Number, Char 2
34
34
75
Part Number, Char 3
44
44
76
Part Number, Char 4
33
33
77
Part Number, Char 5
32
32
78
Part Number, Char 6
30
30
79
Part Number, Char 7
32
32
80
Part Number, Char 8
30
30
81
Part Number, Char 9
48
47
82
Part Number, Char 10
44
44
83
Part Number, Char 11
4C
4C
84
Part Number, Char 12
35
35
85
Part Number, Char 13
43
43
86
Part Number, Char 14
20
20
87
Part Number, Char 15
20
20
88
Part Number, Char 16
20
20
89
Part Number, Char 17
20
20
90
Part Number, Char 18
20
20
91
Module Revision Code
1x
1x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95 - 98
Module Serial Number
xx
xx
00
00
99 - 127 Not used
Rev. 1.31, 2006-09
03292006-VN6D-DETI
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Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 13
SPD Codes for HYS64D16000[H/G]DL–6–C
Product Type
HYS64D16000HDL–6–C
HYS64D16000GDL–6–C
Organization
0.13 GByte
0.13 GByte
×64
×64
1 Rank (×16)
1 Rank (×16)
Label Code
PC2700S–25330
PC2700S–25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
1
Total number of Bytes in E2PROM
08
08
2
Memory Type (DDR = 07h)
07
07
3
Number of Row Addresses
0D
0D
4
Number of Column Addresses
09
09
5
Number of DIMM Ranks
01
01
6
Data Width (LSB)
40
40
7
Data Width (MSB)
00
00
8
Interface Voltage Levels
04
04
9
tCK @ CLmax (Byte 18) [ns]
60
60
10
tAC SDRAM @ CLmax (Byte 18) [ns]
70
70
11
Error Correction Support
00
00
12
Refresh Rate
82
82
13
Primary SDRAM Width
10
10
14
Error Checking SDRAM Width
00
00
15
tCCD [cycles]
01
01
16
Burst Length Supported
0E
0E
17
Number of Banks on SDRAM Device
04
04
18
CAS Latency
0C
0C
19
CS Latency
01
01
20
Write Latency
02
02
21
DIMM Attributes
20
20
22
Component Attributes
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
24
tAC SDRAM @ CLmax -0.5 [ns]
70
70
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
27
tRPmin [ns]
48
48
28
tRRDmin [ns]
30
30
29
tRCDmin [ns]
48
48
Rev. 1.31, 2006-09
03292006-VN6D-DETI
23
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
HYS64D16000HDL–6–C
HYS64D16000GDL–6–C
Organization
0.13 GByte
0.13 GByte
×64
×64
1 Rank (×16)
1 Rank (×16)
Label Code
PC2700S–25330
PC2700S–25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
30
tRASmin [ns]
2A
2A
31
Module Density per Rank
20
20
32
tAS, tCS [ns]
75
75
33
tAH, tCH [ns]
75
75
34
tDS [ns]
45
45
35
tDH [ns]
45
45
36 - 40
Not used
00
00
41
tRCmin [ns]
3C
3C
42
tRFCmin [ns]
48
48
43
tCKmax [ns]
30
30
44
tDQSQmax [ns]
2D
2D
45
tQHSmax [ns]
55
55
46
not used
00
00
47
DIMM PCB Height
00
00
48 - 61
Not used
00
00
62
SPD Revision
00
00
63
Checksum of Byte 0-62
E8
E8
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
72
Module Manufacturer Location
xx
xx
73
Part Number, Char 1
36
36
74
Part Number, Char 2
34
34
75
Part Number, Char 3
44
44
76
Part Number, Char 4
31
31
77
Part Number, Char 5
36
36
78
Part Number, Char 6
30
30
79
Part Number, Char 7
30
30
Rev. 1.31, 2006-09
03292006-VN6D-DETI
24
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
HYS64D16000HDL–6–C
HYS64D16000GDL–6–C
Organization
0.13 GByte
0.13 GByte
×64
×64
1 Rank (×16)
1 Rank (×16)
Label Code
PC2700S–25330
PC2700S–25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
80
Part Number, Char 8
30
30
81
Part Number, Char 9
48
47
82
Part Number, Char 10
44
44
83
Part Number, Char 11
4C
4C
84
Part Number, Char 12
36
36
85
Part Number, Char 13
43
43
86
Part Number, Char 14
20
20
87
Part Number, Char 15
20
20
88
Part Number, Char 16
20
20
89
Part Number, Char 17
20
20
90
Part Number, Char 18
20
20
91
Module Revision Code
1x
1x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95 - 98
Module Serial Number
xx
xx
00
00
99 - 127 Not used
Rev. 1.31, 2006-09
03292006-VN6D-DETI
25
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
TABLE 14
SPD Codes for HYS64D32020[G/H]DL–6–C
Product Type
HYS64D32020HDL–6–C
HYS64D32020GDL–6–C
Organization
256MB
256MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
Label Code
PC2700S–25330
PC2700S–25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
0
Programmed SPD Bytes in E2PROM
80
80
1
Total number of Bytes in E2PROM
08
08
2
Memory Type (DDR = 07h)
07
07
3
Number of Row Addresses
0D
0D
4
Number of Column Addresses
09
09
5
Number of DIMM Ranks
02
02
6
Data Width (LSB)
40
40
7
Data Width (MSB)
00
00
8
Interface Voltage Levels
04
04
9
tCK @ CLmax (Byte 18) [ns]
60
60
10
tAC SDRAM @ CLmax (Byte 18) [ns]
70
70
11
Error Correction Support
00
00
12
Refresh Rate
82
82
13
Primary SDRAM Width
10
10
14
Error Checking SDRAM Width
00
00
15
tCCD [cycles]
01
01
16
Burst Length Supported
0E
0E
17
Number of Banks on SDRAM Device
04
04
18
CAS Latency
0C
0C
19
CS Latency
01
01
20
Write Latency
02
02
21
DIMM Attributes
20
20
22
Component Attributes
C1
C1
23
tCK @ CLmax -0.5 (Byte 18) [ns]
75
75
24
tAC SDRAM @ CLmax -0.5 [ns]
70
70
25
tCK @ CLmax -1 (Byte 18) [ns]
00
00
26
tAC SDRAM @ CLmax -1 [ns]
00
00
27
tRPmin [ns]
48
48
28
tRRDmin [ns]
30
30
29
tRCDmin [ns]
48
48
Rev. 1.31, 2006-09
03292006-VN6D-DETI
26
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
HYS64D32020HDL–6–C
HYS64D32020GDL–6–C
Organization
256MB
256MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
Label Code
PC2700S–25330
PC2700S–25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
30
tRASmin [ns]
2A
2A
31
Module Density per Rank
20
20
32
tAS, tCS [ns]
75
75
33
tAH, tCH [ns]
75
75
34
tDS [ns]
45
45
35
tDH [ns]
45
45
36 - 40
Not used
00
00
41
tRCmin [ns]
3C
3C
42
tRFCmin [ns]
48
48
43
tCKmax [ns]
30
30
44
tDQSQmax [ns]
2D
2D
45
tQHSmax [ns]
55
55
46
not used
00
00
47
DIMM PCB Height
00
00
48 - 61
Not used
00
00
62
SPD Revision
00
00
63
Checksum of Byte 0-62
E9
E9
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
72
Module Manufacturer Location
xx
xx
73
Part Number, Char 1
36
36
74
Part Number, Char 2
34
34
75
Part Number, Char 3
44
44
76
Part Number, Char 4
33
33
77
Part Number, Char 5
32
32
78
Part Number, Char 6
30
30
79
Part Number, Char 7
32
32
Rev. 1.31, 2006-09
03292006-VN6D-DETI
27
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Product Type
HYS64D32020HDL–6–C
HYS64D32020GDL–6–C
Organization
256MB
256MB
×64
×64
2 Ranks (×16)
2 Ranks (×16)
Label Code
PC2700S–25330
PC2700S–25330
JEDEC SPD Revision
Rev. 0.0
Rev. 0.0
Byte#
Description
HEX
HEX
80
Part Number, Char 8
30
30
81
Part Number, Char 9
48
47
82
Part Number, Char 10
44
44
83
Part Number, Char 11
4C
4C
84
Part Number, Char 12
36
36
85
Part Number, Char 13
43
43
86
Part Number, Char 14
20
20
87
Part Number, Char 15
20
20
88
Part Number, Char 16
20
20
89
Part Number, Char 17
20
20
90
Part Number, Char 18
20
20
91
Module Revision Code
1x
1x
92
Test Program Revision Code
xx
xx
93
Module Manufacturing Date Year
xx
xx
94
Module Manufacturing Date Week
xx
xx
95 - 98
Module Serial Number
xx
xx
00
00
99 - 127 Not used
Rev. 1.31, 2006-09
03292006-VN6D-DETI
28
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
5
Package Outlines
FIGURE 2
Package Outline SO-DIMM Raw Card A (L-DIM-200-6)
0
$;
“
“
“
“
“ “
“
“
“
“ “
“
“
0
,1
'HWD LOR IF RQWD FWV “ “ %XU QLVK H G QR E X U UDOORZ
H G Rev. 1.31, 2006-09
03292006-VN6D-DETI
*/' 29
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
FIGURE 3
Package Outline SO-DIMM Raw Card C (L-DIM-200-11)
0$
;
“
“ “
“
“ “
“
“
“
“ “
“
0
,1
'HWD LOR IF RQ WD FWV “
“
%XU QLVK H G Q R EX U UD OORZ
HG Rev. 1.31, 2006-09
03292006-VN6D-DETI
*/' 30
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
List of Figures
Figure 1
Figure 2
Figure 3
Pin Configuration Diagram 200-Pin SO-DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package Outline SO-DIMM Raw Card A (L-DIM-200-6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline SO-DIMM Raw Card C (L-DIM-200-11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Rev. 1.31, 2006-09
03292006-VN6D-DETI
31
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information for Lead Containing Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information for RoHS Compliant Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration of SO-DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Timing - Absolute Specifications for PC3200 and PC2700. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPD Codes for HYSHYS64D32020[H/G]DL–5–C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPD Codes for HYS64D16000[H/G]DL–6–C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SPD Codes for HYS64D32020[G/H]DL–6–C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Rev. 1.31, 2006-09
03292006-VN6D-DETI
32
Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.2
3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13
13
15
17
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Rev. 1.31, 2006-09
03292006-VN6D-DETI
33
Internet Data Sheet
Edition 2006-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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