Holt HI-8482PST Arinc 429 dual line receiver Datasheet

HI-8482
ARINC 429 DUAL LINE RECEIVER
OUT2A - 8
The HI-8482 line receiver is one of several options offered by Holt Integrated Circuits to interface to the ARINC
bus. The digital data processing for serial-to-parallel conversion and clock recovery can be accomplished with the
HI-6010, HI-8683 or similar devices.
The HI-8482 is available in a variety of ceramic & plastic
packages including Small Outline (SOIC), J-Lead PLCC,
Cerquad, DIP & Leadless Chip Carrier (LCC).
FEATURES
! Converts ARINC 429 levels to digital data
-VS - 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+VL - 9
N/C - 10
19 - CAP1A
1 - -VS
20 - TESTB
16 - IN1B
+VL - 9
All the ARINC inputs have built-in hysteresis to reject
noise that may be present on the ARINC bus. Additional
input noise filtering can also be accomplished with external capacitors.
20 - PIN
PLASTIC
J-LEAD PLCC
17 - CAP1B
15 - OUT1A
14 - GND
N/C - 13
IN2A - 6
CAP2A - 7
18 - IN1A
OUT1B - 12
OUT2B - 5
The self-test inputs force the outputs to either a ZERO,
ONE, or NULL state for system tests. While in self-test
mode, the ARINC inputs are ignored.
HI-8482J
HI-8482JT
+VS - 11
IN2B - 4
2 - TESTA
The HI-8482 bus interface unit is a silicon gate CMOS device designed as a dual differential line receiver in accordance with the requirements of the ARINC 429 bus specification. The device translates incoming ARINC 429 signals to normal CMOS/TTL levels on each of its two independent receive channels. The HI-8482 is also functionally equivalent to the Fairchild/Raytheon RM3183.
PIN CONFIGURATIONS (Top Views)
N/C - 10
GENERAL DESCRIPTION
3 - CAP2B
August 2006
HI-8482PSI
HI-8482PST
20 - PIN
PLASTIC
SMALL
OUTLINE
(SOIC) - WB
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +VS
(See page 6 for additional Package Pin Configurations)
! Direct replacement for the RM3183
TRUTH TABLE
! Greater than 2 volt receiving hysteresis
ARINC INPUTS
! TTL and CMOS outputs and test inputs
V (A) - V (B)
TEST A
TEST B
OUT A
OUT B
Null
0
0
0
0
Zero
0
0
0
1
! Military screening available
! 20-Pin SOIC, PLCC, CERQUAD, DIP &
LCC packages are available
(DS8482 Rev. F)
TEST INPUTS
OUTPUTS
One
0
0
1
0
Don't Care
0
1
0
1
Don't Care
1
0
1
0
Don't Care
1
1
0
0
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/06
HI-8482
FUNCTIONAL DESCRIPTION
The HI-8482 contains two independent ARINC 429 receive
channels. The diagram in Figure 1 illustrates a typical HI8482 receive channel.
ARINC LEVELS
The ARINC 429 specification requires the following
detection levels:
The differential ARINC signal input is converted to a positive
signal referenced to ground through level shifters and a
unity gain differential amplifier.
A positive differential input signal is converted to a positive
signal on the plus output of the differential amplifier. This
output is proportional in amplitude to the original input
signal. At the same time, the corresponding MINUS output
is pulled to GND. Likewise when a negative input signal is
present at the ARINC inputs, a positive signal is present on
the MINUS output and the PLUS output is pulled to GND.
The outputs of the differential amplifier are compared with
the ONE, ZERO and NULL threshold levels to produce the
appropriate logic level on the OUTA and OUTB outputs of
the device. The ARINC clock signal may be recovered
through a NOR function of OUTA and OUTB.
The test inputs logically disconnect the outputs of the
comparators from OUTA and OUTB and force the device
outputs to one of the three valid states (Figure 5). This
alleviates having to ground the ARINC inputs during test
mode operation.
STATE
ONE
NULL
ZERO
The HI-8482 guarantees recognition of these levels with a
common mode voltage with respect to GND less than
±5V for the worst case condition.
NOISE
The input hysteresis is set to reject voltage level transitions in the undefined region between the maximum
ZERO level and the minimum NULL level and the undefined region between the maximum NULL level and the
minimum ONE level. Therefore, once a valid input
differential voltage threshold is detected, the outputs will
remain at a valid logic state until a new valid input voltage
is detected.
In addition to the hysteresis, the CAPA and CAPB pins
make it possible to add simple RC filters to the ARINC
inputs.
TYPICAL CHANNEL
+Vs
DIFFERENTIAL VOLTAGE
+6.5V to +13V
+2.5V to -2.5V
-6.5V to -13V
+VL
TESTA
TESTB
INA
OUTA
Detect
Level
LEVEL
SHIFT
Comp
CAPA
PLUS
INB
DIFF
AMP
LEVEL
SHIFT
MINUS
Comparators
w / hysteresis
OUTB
Comp
CAPB
Detect
Level
-Vs
GND
FIGURE 1 - BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8482
TYPICAL APPLICATIONS
ground (GND) connection should be sturdy and isolated from large
switching currents to provide a quiet ground reference.
APPLICATIONS
The HI-8482 can be used with HI-3182 or HI-8585 Line Drivers to
provide a complete analog ARINC 429 interface solution. A simple
application, which can be used in systems requiring a repeater
type circuit for long transmissions or for test interfaces, is given in
Figure 3. More HI-3182 or HI-8585 drivers may be added to test
multiple ARINC channels, as shown.
The standard connections for the HI-8482 are shown in Figure 2.
Decoupling of the supply should be done near the IC to avoid
propagation of noise spikes due to switching transients. The
+5V
+15V
HI-8482
ARINC
CHANNEL 1
IN1A
OUT1A
A
IN1B
OUT1B
B
OUT2A
A
OUT2B
B
CHANNEL 1
DATA OUT
TO LOGIC
39 pF
CAP1A
39 pF
CAP1B
IN2A
ARINC
CHANNEL 2
IN2B
39 pF
39 pF
CHANNEL 2
DATA OUT
TO LOGIC
CAP2A
CAP2B
TESTA
LOGIC
TEST
INPUTS
N/C
TESTB
N/C
-15V
FIGURE 2 - ARINC RECEIVER STANDARD CONNECTIONS
ARINC
INPUT
CHANNEL
IN1A
OUT1A
DATA (A)
AOUT
IN1B
OUT1B
DATA (B)
BOUT
1/2
HI-8482
A
B
ARINC
OUTPUT
CHANNEL 1
HI-3182
or HI-8585
DATA (A)
AOUT
DATA (B)
BOUT
HI-3182
or HI-8585
TO ADDITIONAL
CHANNELS
FIGURE 3 - ARINC REPEATER CIRCUIT
HOLT INTEGRATED CIRCUITS
3
A
B
ARINC
OUTPUT
CHANNEL 2
HI-8482
PIN DESCRIPTION TABLE
SYMBOL FUNCTION
DESCRIPTION
SYMBOL FUNCTION
CAP1A
INPUT
Filter capacitor input for terminal A of
channel 1
CAP1B
INPUT
Filter capacitor input for terminal B of
channel 1
DESCRIPTION
IN2B
INPUT
ARINC input terminal B of channel 2
OUT1A
OUTPUT
TTL output terminal A of channel 1
OUT1B
OUTPUT
TTL output terminal B of channel 1
OUT2A
OUTPUT
TTL output terminal A of channel 2
TTL output terminal B of channel 2
CAP2A
INPUT
Filter capacitor input for terminal A of
channel 2
OUT2B
OUTPUT
CAP2B
INPUT
Filter capacitor input for terminal B of
channel 2
TESTA
INPUT
Test input terminal A
0 Volts
TESTB
INPUT
Test input terminal B
GND
POWER
IN1A
INPUT
ARINC input terminal A of channel 1
+VL
POWER
+5 Volts ±10%
IN1B
INPUT
ARINC input terminal B of channel 1
+Vs
POWER
+12 Volts ±10% or +15 Volts ±10%
IN2A
INPUT
ARINC input terminal A of channel 2
-Vs
POWER
-12 Volts ±10% or -15 Volts ±10%
TIMING DIAGRAMS
+10V
ARINC
DIFFERENTIAL
INPUT
0V
-10V
tPLH
tr
90%
50%
OUTA
tf
10%
tPHL
tPHL
tPLH
50%
OUTB
FIGURE 4
+5V
TESTA
0V
+5V
TESTB
0V
tTLH
tr
90%
50%
OUTA (test)
tf
10%
tTHL
tTHL
tTLH
50%
OUTB (test)
FIGURE 5
HOLT INTEGRATED CIRCUITS
4
HI-8482
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to Gnd = 0V)
Supply Voltage, +VS:......................................................................+20 VDC
-VS: .......................................................................-20 VDC
+VL:........................................................................+7 VDC
Operating Temperature Range: (Industrial) .........................-40°C to +85°C
(Hi-Temp) ........................-55°C to +125°C
(Military) ..........................-55°C to +125°C
Internal Power Dissipation: ..............................................................900mW
Voltage at ARINC Inputs: .......................................................-29V to +29V
Voltage at Any Other Input:.............................................-0.3V to VL + 0.3V
Output Short Circuit Protected: .............................................Not Protected
Storage Temperature Range: .........................................-65°C to +150°C
Soldering Temperature: (Ceramic).................................30 sec. at +300°C
(Plastic - leads)........................10 sec. at +280°C
(Plastic - body) ................................+220°C Max.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
±12 < VS < ±15, VL = +5V, Operating temperature range (unless otherwise noted)
PARAMETERS
SYMBOL TEST CONDITIONS
ARINC inputs - IN1A, IN1B, IN2A, IN2B
V(A) - V(B)
V(A) - V(B)
V(A) - V(B)
(|V(A)| - |V(B)|) / 2
Input resistance - input A to input B
Input resistance - input A or B to Gnd
Input capacitance - input A to B
Input capacitance - input A or B to Gnd
Test inputs - TESTA, TESTB
Logic 1 input voltage
Logic 0 input voltage
Logic 1 input current (magnitude)
Logic 0 input current
VIH
VIL
VNULL
VCM
RI
RG
CI
CG
VIH
VIL
IIH
IIL
OUTA = 1
OUTB = 1
OUTA = OUTB = 0
Frequency = 80KHz
Supply pins floating
Supply pins floating
Filter caps disconnected
Filter caps disconnected
MIN
TYP
MAX
UNITS
6.5
-6.5
-2.5
10
-10
0
±5
50K
25K
5
5
13
-13
2.5
10
10
volts
volts
volts
volts
ohms
ohms
pF
pF
0.8
15
1
volts
volts
µA
µA
30K
19K
-
see note 1
see note 1
ARINC inputs to Gnd, TA = 25°C
ARINC inputs to Gnd, TA = 25°C
VIH = 2.7V
VIL = 0V
2.7
4
3.5
5
0.5
Outputs - OUT1A, OUT1B, OUT2A, OUT2B
Voltage - sourcing 100µA
Voltage - sourcing 2.8mA
Voltage - sinking 100µA
Voltage - sinking 2.0mA
Rise time
Fall time
Propagation delay - low to high (ARINC)
VOH
VOH
VOL
VOL
tr
tf
tPLH
TA = 25°C
Full temperature range
TA = 25°C
Full temperature range
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C
CL = 50pF, TA = 25°C and filter caps disconnected
Propagation delay - high to low (ARINC)
tPHL
CL = 50pF, TA = 25°C and filter caps disconnected
Propagation delay - low to high (TESTA/B)
tTLH
CL = 50pF, TA = 25°C
50
ns
Propagation delay - low to high (TESTA/B)
tTHL
CL = 50pF, TA = 25°C
50
ns
Supply current
+VS current
+VS current
-VS current
-VS current
+VL current
+VL current
IDD
IDD
IEE
IEE
ICC
ICC
±VS
±VS
±VS
±VS
±VS
±VS
Notes:
=
=
=
=
=
=
±15V,
±12V,
±15V,
±12V,
±15V,
±12V,
TA
TA
TA
TA
TA
TA
=25°C,
=25°C,
=25°C,
=25°C,
=25°C,
=25°C,
TESTA
TESTA
TESTA
TESTA
TESTA
TESTA
and TESTB
and TESTB
and TESTB
and TESTB
and TESTB
and TESTB
1. Guaranteed by design.
HOLT INTEGRATED CIRCUITS
5
=
=
=
=
=
=
0V
0V
0V
0V
0V
0V
40
30
600
0.08
0.8
70
70
600
3.7
3
8.7
7.4
9
8.6
volts
volts
volts
volts
ns
ns
ns
ns
7
6
15
14
20
18
mA
mA
mA
mA
mA
mA
HI-8482
ADDITIONAL HI-8482 PIN CONFIGURATIONS
4
5
6
7
8
IN2B
OUT2B
IN2A
CAP2A
OUT2A
-VS - 1
20 - TESTB
-VS - 1
20 - TESTB
TESTA - 2
19 - CAP1A
TESTA - 2
19 - CAP1A
18 - IN1A
CAP2B - 3
18 - IN1A
20-PIN
J-LEAD
CERQUAD
18
17
16
15
14
-
HI-8482S
HI-8482ST
HI-8482SM-01
IN1A
CAP1B
IN1B
OUT1A
GND
HI-8482U
HI-8482UT
-
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+VL - 9
N/C - 10
HI-8482C
HI-8482CT
HI-8482CM-01
20-PIN
CERAMIC
SIDE-BRAZED
DIP
4
5
6
7
8
20-PIN
CERAMIC LCC
18
17
16
15
14
-
IN1A
CAP1B
IN1B
OUT1A
GND
+VL - 9
N/C - 10
+VS - 11
OUT1B - 12
N/C - 13
-
+VL - 9
N/C - 10
+VS - 11
OUT1B - 12
N/C - 13
IN2B
OUT2B
IN2A
CAP2A
OUT2A
3 - CAP2B
2 - TESTA
1 - -VS
20 - TESTB
19 - CAP1A
3 - CAP2B
2 - TESTA
1 - -VS
20 - TESTB
19 - CAP1A
(All 20-Pin Package Configurations)
17 - CAP1B
16 - IN1B
15 - OUT1A
IN2B - 4
OUT2B - 5
IN2A - 6
14 - GND
CAP2A - 7
13 - N/C
OUT2A - 8
12 - OUT1B
11 - +VS
+VL - 9
N/C - 10
HOLT INTEGRATED CIRCUITS
6
HI-8482D
HI-8482DT
20-PIN
CERDIP
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +VS
HI-8482
ORDERING INFORMATION & THERMAL CHARACTERISTICS
HI - 8482 x x (Ceramic DIP & LCC)
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
LEAD
FINISH
Blank
-40°C TO +85°C
I
NO
Gold
T
-55°C TO +125°C
T
NO
Gold
M-01
-55°C TO +125°C
M
YES
PART
NUMBER
Tin / Lead (Sn / Pb) Solder
THERMAL RES.
QJC
QJA
PACKAGE
DESCRIPTION
C
20 PIN CERAMIC SIDE BRAZED DIP
28°C/W
95°C/W
S
20 PIN CERAMIC LEADLESS CHIP CARRIER
25°C/W
85°C/W
HI - 8482 x x (CerDIP & CerQUAD)
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
LEAD
FINISH
Blank
-40°C TO +85°C
I
NO
Tin / Lead (Sn / Pb) Solder
T
-55°C TO +125°C
T
NO
Tin / Lead (Sn / Pb) Solder
PART
NUMBER
THERMAL RES.
QJA
QJC
PACKAGE
DESCRIPTION
D
20 PIN CERDIP
28°C/W
90°C/W
U
20 PIN J-LEAD CERQUAD
25°C/W
95°C/W
HI - 8482 xx x x (Plastic PLCC & SOIC - Wide Body)
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
Blank
100% Matte Tin (Pb-free, RoHS compliant)
F
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
Blank
(8482J Only)
-40°C TO +85°C
I
NO
I
(8482PS Only)
-40°C TO +85°C
I
NO
T
(8482J or 8482PS)
-55°C TO +125°C
T
NO
PART
NUMBER
J
PS
PACKAGE
DESCRIPTION
20 PIN PLASTIC J-LEAD PLCC
THERMAL RES.
QJC
QJA
30°C/W
85°C/W
20 PIN PLASTIC SMALL OUTLINE (SOIC) - WB 17°C/W
90°C/W
HOLT INTEGRATED CIRCUITS
7
HI-8482 PACKAGE DIMENSIONS
inches (millimeters)
20-PIN PLASTIC SMALL OUTLINE (SOIC) - WB
(Wide Body)
Package Type: 20HW
.5035 ± .0075
(12.789 ± .191)
.0105 ± .0015
(.2667 ± .0381)
.4065 ± .0125
(10.325 ± .318)
.296 ± .003
(7.518 ± .076)
SEE DETAIL A
.018
TYP
(.457)
.090 ± .010
(2.286 ± .254)
0° to 8°
.050
TYP
(1.27)
DETAIL A
.033 ± .017
(.838 ± .432)
.0075 ± .0035
(.191 ± .089)
20-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 20C
1.000 ± .010
(25.400 ± .254)
.310 ± .010
(7.874 ± .254)
.050 TYP.
(1.270 TYP.)
.200 MAX.
(5.080 MAX.)
.125 MIN.
(3.175 MIN.)
.300 ± .010
(7.620 ± .254)
.085 ± .009
(2.159 ± .229)
.017 ± .002
(.432 ± .051)
.100 ± .005
(2.540 ± .127)
HOLT INTEGRATED CIRCUITS
8
.010 + .002/ -.001
(.254 + .051/ -.025)
HI-8482 PACKAGE DIMENSIONS
inches (millimeters)
20-PIN CERDIP
Package Type: 20D
1.060 MAX.
(26.924 MAX.)
.005 MIN.
(.127 MIN.)
.070 MAX.
(1.778 MAX.)
.288 ± .005
(7.315 ± .127)
.060 TYP.
(1.524 TYP.)
.100 ± .010
(2.540 ± .254)
.310 ± .010
(7.874 ± .254)
.200 MAX.
(5.080 MAX.)
.170 MAX.
(4.318 MAX.)
.015 MIN.
(.381 MIN.)
.125 MIN.
(3.175 MIN.)
0° to 15°
.018 ± .003
(.457 ± .760)
.010 ± .002
(.254 ± .051)
20-PIN PLASTIC PLCC
Package Type: 20J
.045 x 45°
PIN NO. 1 IDENT
.045 x 45°
.050 ± .005
(1.27 ± .127)
.353 ± .003
(8.966 ± .076)
SQ.
.390 ± .005
(9.906 ± .127)
SQ.
.017 ± .004
(.432 ± .102)
SEE DETAIL
A
.009
.011
.173 ± .008
(4.394 ± .203)
.310 ± .020
(7.874 ± .508 )
DETAIL A
HOLT INTEGRATED CIRCUITS
9
.015 ± .002
(.381 ± .051)
.020 MIN
(.508 MIN)
R .025
.045
HI-8482 PACKAGE DIMENSIONS
inches (millimeters)
20-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 20S
.020 INDEX
(.508 INDEX)
.040 x 45° 3 PLCS
(1.016 x 45° 3 PLCS)
.175 ± .004
(4.445 ± .101)
.080 ± .020
(2.032 ±.508)
PIN 1
.075 ± .004
(1.905 ± .101)
.009R ± .006
(.229R ± .152)
.350 ± .008
(8.890 ± .203)
SQ.
.050 BSC
(1.270 BSC)
PIN 1
.050 ±.005
(1.270 ± .127)
.025 ± .003
(.635 ± .076)
20-PIN J-LEAD CERQUAD
2
Package Type: 20U
1 20 19
.405 MAX.
(10.287) MAX.
SQ.
.375 ± .008
(9.525 ± .203)
.190 MAX.
(4.826) MAX.
.040 TYP.
(1.016) TYP.
.019 ± .003
(.483 ± .076)
.050 TYP.
(1.270) TYP.
HOLT INTEGRATED CIRCUITS
10
.335 ± .010
(8.509 ± .254)
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