TI LM3S9B95-EQR80-C1 Stellarisâ® lm3s9b95 microcontroller Datasheet

TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION
Stellaris® LM3S9B95 Microcontroller
D ATA SH E E T
D S -LM 3S 9B 95 - 7 2 9 9
C opyri ght © 2007-2010 Texas Instruments
Incorporated
Copyright
Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications
are subject to change without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments Incorporated
108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Stellaris® LM3S9B95 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 37
About This Document .................................................................................................................... 42
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
42
42
42
43
1
Architectural Overview .......................................................................................... 45
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.1.9
1.2
1.3
1.4
1.4.1
1.4.2
Functional Overview ...................................................................................................... 47
ARM Cortex™-M3 ......................................................................................................... 47
On-Chip Memory ........................................................................................................... 49
External Peripheral Interface ......................................................................................... 50
Serial Communications Peripherals ................................................................................ 51
System Integration ........................................................................................................ 57
Advanced Motion Control ............................................................................................... 62
Analog .......................................................................................................................... 64
JTAG and ARM Serial Wire Debug ................................................................................ 66
Packaging and Temperature .......................................................................................... 67
Target Applications ........................................................................................................ 67
High-Level Block Diagram ............................................................................................. 67
Additional Features ....................................................................................................... 69
Memory Map ................................................................................................................ 69
Hardware Details .......................................................................................................... 69
2
ARM Cortex-M3 Processor Core ........................................................................... 70
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
Block Diagram .............................................................................................................. 71
Functional Description ................................................................................................... 71
Programming Model ...................................................................................................... 71
Serial Wire and JTAG Debug ......................................................................................... 78
Embedded Trace Macrocell (ETM) ................................................................................. 78
Trace Port Interface Unit (TPIU) ..................................................................................... 78
ROM Table ................................................................................................................... 79
Memory Protection Unit (MPU) ....................................................................................... 79
Nested Vectored Interrupt Controller (NVIC) .................................................................... 79
System Timer (SysTick) ................................................................................................. 80
3
Memory Map ........................................................................................................... 83
4
Interrupts ................................................................................................................. 86
5
JTAG Interface ........................................................................................................ 89
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
Block Diagram ..............................................................................................................
Signal Description .........................................................................................................
Functional Description ...................................................................................................
JTAG Interface Pins ......................................................................................................
JTAG TAP Controller .....................................................................................................
Shift Registers ..............................................................................................................
Operational Considerations ............................................................................................
Initialization and Configuration .......................................................................................
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90
91
91
93
93
94
96
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5.5
5.5.1
5.5.2
Register Descriptions .................................................................................................... 97
Instruction Register (IR) ................................................................................................. 97
Data Registers .............................................................................................................. 99
6
System Control ..................................................................................................... 101
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.3
6.4
6.5
Signal Description .......................................................................................................
Functional Description .................................................................................................
Device Identification ....................................................................................................
Reset Control ..............................................................................................................
Non-Maskable Interrupt ...............................................................................................
Power Control .............................................................................................................
Clock Control ..............................................................................................................
System Control ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
101
101
102
102
106
107
107
114
115
116
117
7
Internal Memory ................................................................................................... 209
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
7.4
7.5
7.6
Block Diagram ............................................................................................................ 209
Functional Description ................................................................................................. 209
SRAM ........................................................................................................................ 210
ROM .......................................................................................................................... 210
Flash Memory ............................................................................................................. 212
Flash Memory Initialization and Configuration ............................................................... 213
Flash Memory Programming ........................................................................................ 213
32-Word Flash Memory Write Buffer ............................................................................. 215
Nonvolatile Register Programming ............................................................................... 215
Register Map .............................................................................................................. 216
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 217
Memory Register Descriptions (System Control Offset) .................................................. 228
8
Micro Direct Memory Access (μDMA) ................................................................ 246
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.4
Block Diagram ............................................................................................................ 247
Functional Description ................................................................................................. 247
Channel Assignments .................................................................................................. 248
Priority ........................................................................................................................ 249
Arbitration Size ............................................................................................................ 249
Request Types ............................................................................................................ 249
Channel Configuration ................................................................................................. 250
Transfer Modes ........................................................................................................... 252
Transfer Size and Increment ........................................................................................ 260
Peripheral Interface ..................................................................................................... 260
Software Request ........................................................................................................ 260
Interrupts and Errors .................................................................................................... 261
Initialization and Configuration ..................................................................................... 261
Module Initialization ..................................................................................................... 261
Configuring a Memory-to-Memory Transfer ................................................................... 261
Configuring a Peripheral for Simple Transmit ................................................................ 263
Configuring a Peripheral for Ping-Pong Receive ............................................................ 264
Configuring Channel Assignments ................................................................................ 267
Register Map .............................................................................................................. 267
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8.5
8.6
μDMA Channel Control Structure ................................................................................. 268
μDMA Register Descriptions ........................................................................................ 275
9
General-Purpose Input/Outputs (GPIOs) ........................................................... 304
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.3
9.4
9.5
Signal Description ....................................................................................................... 304
Functional Description ................................................................................................. 309
Data Control ............................................................................................................... 310
Interrupt Control .......................................................................................................... 311
Mode Control .............................................................................................................. 312
Commit Control ........................................................................................................... 312
Pad Control ................................................................................................................. 313
Identification ............................................................................................................... 313
Initialization and Configuration ..................................................................................... 313
Register Map .............................................................................................................. 314
Register Descriptions .................................................................................................. 317
10
External Peripheral Interface (EPI) ..................................................................... 360
10.1
10.2
10.3
10.3.1
10.3.2
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
EPI Block Diagram ......................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Non-Blocking Reads ....................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
SDRAM Mode .............................................................................................................
Host Bus Mode ...........................................................................................................
General-Purpose Mode ...............................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
361
362
364
365
366
366
367
371
380
388
389
11
General-Purpose Timers ...................................................................................... 433
11.1
11.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.5
11.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
GPTM Reset Conditions ..............................................................................................
32-Bit Timer Operating Modes ......................................................................................
16-Bit Timer Operating Modes ......................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
32-Bit One-Shot/Periodic Timer Mode ...........................................................................
32-Bit Real-Time Clock (RTC) Mode .............................................................................
16-Bit One-Shot/Periodic Timer Mode ...........................................................................
Input Edge-Count Mode ...............................................................................................
16-Bit Input Edge Timing Mode ....................................................................................
16-Bit PWM Mode .......................................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
12
Watchdog Timers ................................................................................................. 481
434
434
437
437
438
439
445
445
445
446
446
447
447
448
448
449
12.1
Block Diagram ............................................................................................................ 482
12.2
Functional Description ................................................................................................. 482
12.2.1 Register Access Timing ............................................................................................... 483
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12.3
12.4
12.5
Initialization and Configuration ..................................................................................... 483
Register Map .............................................................................................................. 483
Register Descriptions .................................................................................................. 484
13
Analog-to-Digital Converter (ADC) ..................................................................... 506
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.4
13.4.1
13.4.2
13.5
13.6
Block Diagram ............................................................................................................ 507
Signal Description ....................................................................................................... 508
Functional Description ................................................................................................. 509
Sample Sequencers .................................................................................................... 509
Module Control ............................................................................................................ 510
Hardware Sample Averaging Circuit ............................................................................. 513
Analog-to-Digital Converter .......................................................................................... 513
Differential Sampling ................................................................................................... 515
Internal Temperature Sensor ........................................................................................ 518
Digital Comparator Unit ............................................................................................... 518
Initialization and Configuration ..................................................................................... 523
Module Initialization ..................................................................................................... 523
Sample Sequencer Configuration ................................................................................. 524
Register Map .............................................................................................................. 524
Register Descriptions .................................................................................................. 526
14
Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 584
14.1
Block Diagram ............................................................................................................
14.2
Signal Description .......................................................................................................
14.3
Functional Description .................................................................................................
14.3.1 Transmit/Receive Logic ...............................................................................................
14.3.2 Baud-Rate Generation .................................................................................................
14.3.3 Data Transmission ......................................................................................................
14.3.4 Serial IR (SIR) .............................................................................................................
14.3.5 ISO 7816 Support .......................................................................................................
14.3.6 Modem Handshake Support .........................................................................................
14.3.7 LIN Support ................................................................................................................
14.3.8 FIFO Operation ...........................................................................................................
14.3.9 Interrupts ....................................................................................................................
14.3.10 Loopback Operation ....................................................................................................
14.3.11 DMA Operation ...........................................................................................................
14.4
Initialization and Configuration .....................................................................................
14.5
Register Map ..............................................................................................................
14.6
Register Descriptions ..................................................................................................
585
585
587
588
588
589
589
590
590
592
593
593
594
594
595
596
597
15
Synchronous Serial Interface (SSI) .................................................................... 646
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.3.4
15.3.5
15.4
15.5
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Bit Rate Generation .....................................................................................................
FIFO Operation ...........................................................................................................
Interrupts ....................................................................................................................
Frame Formats ...........................................................................................................
DMA Operation ...........................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
6
647
647
648
649
649
649
650
657
658
659
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Stellaris® LM3S9B95 Microcontroller
15.6
Register Descriptions .................................................................................................. 660
16
Inter-Integrated Circuit (I2C) Interface ................................................................ 688
16.1
16.2
16.3
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.4
16.5
16.6
16.7
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
I2C Bus Functional Overview ........................................................................................
Available Speed Modes ...............................................................................................
Interrupts ....................................................................................................................
Loopback Operation ....................................................................................................
Command Sequence Flow Charts ................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions (I2C Master) ...............................................................................
Register Descriptions (I2C Slave) .................................................................................
17
Inter-Integrated Circuit Sound (I2S) Interface .................................................... 725
17.1
17.2
17.3
17.3.1
17.3.2
17.4
17.5
17.6
Block Diagram ............................................................................................................
Signal Description .......................................................................................................
Functional Description .................................................................................................
Transmit .....................................................................................................................
Receive ......................................................................................................................
Initialization and Configuration .....................................................................................
Register Map ..............................................................................................................
Register Descriptions ..................................................................................................
18
Controller Area Network (CAN) Module ............................................................. 762
689
689
690
690
692
693
694
694
701
702
703
716
726
726
727
729
733
735
736
737
18.1
Block Diagram ............................................................................................................ 763
18.2
Signal Description ....................................................................................................... 763
18.3
Functional Description ................................................................................................. 764
18.3.1 Initialization ................................................................................................................. 765
18.3.2 Operation ................................................................................................................... 766
18.3.3 Transmitting Message Objects ..................................................................................... 767
18.3.4 Configuring a Transmit Message Object ........................................................................ 767
18.3.5 Updating a Transmit Message Object ........................................................................... 768
18.3.6 Accepting Received Message Objects .......................................................................... 769
18.3.7 Receiving a Data Frame .............................................................................................. 769
18.3.8 Receiving a Remote Frame .......................................................................................... 769
18.3.9 Receive/Transmit Priority ............................................................................................. 770
18.3.10 Configuring a Receive Message Object ........................................................................ 770
18.3.11 Handling of Received Message Objects ........................................................................ 771
18.3.12 Handling of Interrupts .................................................................................................. 773
18.3.13 Test Mode ................................................................................................................... 774
18.3.14 Bit Timing Configuration Error Considerations ............................................................... 776
18.3.15 Bit Time and Bit Rate ................................................................................................... 776
18.3.16 Calculating the Bit Timing Parameters .......................................................................... 778
18.4
Register Map .............................................................................................................. 781
18.5
CAN Register Descriptions .......................................................................................... 782
19
Ethernet Controller .............................................................................................. 814
19.1
Block Diagram ............................................................................................................ 815
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19.2
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.4
19.4.1
19.4.2
19.5
19.6
19.7
Signal Description ....................................................................................................... 816
Functional Description ................................................................................................. 817
MAC Operation ........................................................................................................... 817
Internal MII Operation .................................................................................................. 820
PHY Operation ............................................................................................................ 821
Interrupts .................................................................................................................... 823
DMA Operation ........................................................................................................... 824
Initialization and Configuration ..................................................................................... 824
Hardware Configuration ............................................................................................... 824
Software Configuration ................................................................................................ 825
Register Map .............................................................................................................. 826
Ethernet MAC Register Descriptions ............................................................................. 828
MII Management Register Descriptions ......................................................................... 854
20
Universal Serial Bus (USB) Controller ............................................................... 875
20.1
20.2
20.3
20.3.1
20.3.2
20.3.3
20.3.4
20.4
20.4.1
20.4.2
20.5
20.6
Block Diagram ............................................................................................................ 876
Signal Description ....................................................................................................... 876
Functional Description ................................................................................................. 878
Operation as a Device ................................................................................................. 878
Operation as a Host .................................................................................................... 883
OTG Mode .................................................................................................................. 887
DMA Operation ........................................................................................................... 889
Initialization and Configuration ..................................................................................... 890
Pin Configuration ......................................................................................................... 890
Endpoint Configuration ................................................................................................ 890
Register Map .............................................................................................................. 891
Register Descriptions .................................................................................................. 902
21
Analog Comparators .......................................................................................... 1014
21.1
21.2
21.3
21.3.1
21.4
21.5
21.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Internal Reference Programming ................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
1015
1015
1016
1017
1018
1019
1019
22
Pulse Width Modulator (PWM) .......................................................................... 1027
22.1
22.2
22.3
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
22.3.6
22.3.7
22.3.8
22.4
22.5
Block Diagram ........................................................................................................... 1028
Signal Description ..................................................................................................... 1029
Functional Description ............................................................................................... 1032
PWM Timer ............................................................................................................... 1032
PWM Comparators .................................................................................................... 1032
PWM Signal Generator .............................................................................................. 1034
Dead-Band Generator ............................................................................................... 1035
Interrupt/ADC-Trigger Selector ................................................................................... 1035
Synchronization Methods .......................................................................................... 1035
Fault Conditions ........................................................................................................ 1036
Output Control Block .................................................................................................. 1037
Initialization and Configuration .................................................................................... 1038
Register Map ............................................................................................................ 1039
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22.6
Register Descriptions ................................................................................................. 1041
23
Quadrature Encoder Interface (QEI) ................................................................. 1104
23.1
23.2
23.3
23.4
23.5
23.6
Block Diagram ...........................................................................................................
Signal Description .....................................................................................................
Functional Description ...............................................................................................
Initialization and Configuration ....................................................................................
Register Map ............................................................................................................
Register Descriptions .................................................................................................
24
Pin Diagram ........................................................................................................ 1127
1104
1105
1106
1108
1109
1110
25
Signal Tables ...................................................................................................... 1129
25.1
25.2
25.3
100-Pin LQFP Package Pin Tables ............................................................................. 1130
108-Pin BGA Package Pin Tables ............................................................................... 1165
Connections for Unused Signals ................................................................................. 1202
26
Operating Characteristics ................................................................................. 1204
27
Electrical Characteristics .................................................................................. 1205
27.1
DC Characteristics .................................................................................................... 1205
27.1.1 Maximum Ratings ...................................................................................................... 1205
27.1.2 Recommended DC Operating Conditions .................................................................... 1205
27.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics .............................................. 1206
27.1.4 Flash Memory Characteristics .................................................................................... 1206
27.1.5 GPIO Module Characteristics ..................................................................................... 1206
27.1.6 USB Module Characteristics ....................................................................................... 1207
27.1.7 Ethernet Controller Characteristics ............................................................................. 1207
27.1.8 Current Specifications ................................................................................................ 1207
27.2
AC Characteristics ..................................................................................................... 1207
27.2.1 Load Conditions ........................................................................................................ 1207
27.2.2 Clocks ...................................................................................................................... 1208
27.2.3 JTAG and Boundary Scan .......................................................................................... 1210
27.2.4 Reset ........................................................................................................................ 1211
27.2.5 Sleep Modes ............................................................................................................. 1213
27.2.6 General-Purpose I/O (GPIO) ...................................................................................... 1213
27.2.7 External Peripheral Interface (EPI) .............................................................................. 1213
27.2.8 Analog-to-Digital Converter ........................................................................................ 1218
27.2.9 Synchronous Serial Interface (SSI) ............................................................................. 1219
27.2.10 Inter-Integrated Circuit (I2C) Interface ......................................................................... 1221
27.2.11 Inter-Integrated Circuit Sound (I2S) Interface ............................................................... 1221
27.2.12 Ethernet Controller ................................................................................................... 1223
27.2.13 Universal Serial Bus (USB) Controller ......................................................................... 1226
27.2.14 Analog Comparator ................................................................................................... 1226
A
Register Quick Reference ................................................................................. 1227
B
Ordering and Contact Information ................................................................... 1276
B.1
B.2
B.3
B.4
Ordering Information ..................................................................................................
Part Markings ............................................................................................................
Kits ...........................................................................................................................
Support Information ...................................................................................................
C
Package Information .......................................................................................... 1278
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1276
1277
1277
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List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure 10-10.
Figure 10-11.
Figure 10-12.
Figure 10-13.
Figure 10-14.
Figure 10-15.
Figure 10-16.
Figure 10-17.
Figure 10-18.
Figure 10-19.
Figure 10-20.
®
Stellaris LM3S9B95 Microcontroller High-Level Block Diagram ............................ 68
CPU Block Diagram ............................................................................................. 71
TPIU Block Diagram ............................................................................................ 79
JTAG Module Block Diagram ................................................................................ 90
Test Access Port State Machine ........................................................................... 93
IDCODE Register Format ..................................................................................... 99
BYPASS Register Format .................................................................................... 99
Boundary Scan Register Format ......................................................................... 100
Basic RST Configuration .................................................................................... 103
External Circuitry to Extend Power-On Reset ....................................................... 104
Reset Circuit Controlled by Switch ...................................................................... 104
Power Architecture ............................................................................................ 107
Main Clock Tree ................................................................................................ 110
Internal Memory Block Diagram .......................................................................... 209
μDMA Block Diagram ......................................................................................... 247
Example of Ping-Pong μDMA Transaction ........................................................... 253
Memory Scatter-Gather, Setup and Configuration ................................................ 255
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 256
Peripheral Scatter-Gather, Setup and Configuration ............................................. 258
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 259
Digital I/O Pads ................................................................................................. 309
Analog/Digital I/O Pads ...................................................................................... 310
GPIODATA Write Example ................................................................................. 311
GPIODATA Read Example ................................................................................. 311
EPI Block Diagram ............................................................................................. 362
SDRAM Non-Blocking Read Cycle ...................................................................... 369
SDRAM Normal Read Cycle ............................................................................... 370
SDRAM Write Cycle ........................................................................................... 371
Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 378
Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 378
Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 1, RDHIGH = 1 ............................................................................................... 379
Continuous Read Mode Accesses ...................................................................... 379
Write Followed by Read to External FIFO ............................................................ 380
Two-Entry FIFO ................................................................................................. 380
Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 384
Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 384
Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 385
FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 385
FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 385
FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 386
FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 386
FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 386
FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 386
iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 387
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Stellaris® LM3S9B95 Microcontroller
Figure 10-21.
Figure 10-22.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 11-5.
Figure 12-1.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10.
Figure 13-11.
Figure 13-12.
Figure 13-13.
Figure 13-14.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 16-4.
Figure 16-5.
Figure 16-6.
Figure 16-7.
Figure 16-8.
Figure 16-9.
EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 387
EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 388
GPTM Module Block Diagram ............................................................................ 434
16-Bit Input Edge-Count Mode Example .............................................................. 441
16-Bit Input Edge-Time Mode Example ............................................................... 443
16-Bit PWM Mode Example ................................................................................ 444
Timer Daisy Chain ............................................................................................. 444
WDT Module Block Diagram .............................................................................. 482
Implementation of Two ADC Blocks .................................................................... 507
ADC Module Block Diagram ............................................................................... 507
ADC Sample Phases ......................................................................................... 512
Doubling the ADC Sample Rate .......................................................................... 512
Skewed Sampling .............................................................................................. 513
Internal Voltage Conversion Result ..................................................................... 514
External Voltage Conversion Result .................................................................... 515
Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 516
Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 517
Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 517
Internal Temperature Sensor Characteristic ......................................................... 518
Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 521
Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 522
High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 523
UART Module Block Diagram ............................................................................. 585
UART Character Frame ..................................................................................... 588
IrDA Data Modulation ......................................................................................... 590
LIN Message ..................................................................................................... 592
LIN Synchronization Field ................................................................................... 593
SSI Module Block Diagram ................................................................................. 647
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 651
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 651
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 652
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 652
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 653
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 654
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 654
Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 655
MICROWIRE Frame Format (Single Frame) ........................................................ 656
MICROWIRE Frame Format (Continuous Transfer) ............................................. 657
MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 657
I2C Block Diagram ............................................................................................. 689
I2C Bus Configuration ........................................................................................ 690
START and STOP Conditions ............................................................................. 691
Complete Data Transfer with a 7-Bit Address ....................................................... 691
R/S Bit in First Byte ............................................................................................ 691
Data Validity During Bit Transfer on the I2C Bus ................................................... 692
Master Single TRANSMIT .................................................................................. 695
Master Single RECEIVE ..................................................................................... 696
Master TRANSMIT with Repeated START ........................................................... 697
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Table of Contents
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 698
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 699
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 700
Figure 16-13. Slave Command Sequence ................................................................................ 701
Figure 17-1. I2S Block Diagram ............................................................................................. 726
Figure 17-2. I2S Data Transfer ............................................................................................... 729
Figure 17-3. Left-Justified Data Transfer ................................................................................ 729
Figure 17-4. Right-Justified Data Transfer .............................................................................. 729
Figure 18-1. CAN Controller Block Diagram ............................................................................ 763
Figure 18-2. CAN Data/Remote Frame .................................................................................. 765
Figure 18-3. Message Objects in a FIFO Buffer ...................................................................... 773
Figure 18-4. CAN Bit Time .................................................................................................... 777
Figure 19-1. Ethernet Controller ............................................................................................. 815
Figure 19-2. Ethernet Controller Block Diagram ...................................................................... 815
Figure 19-3. Ethernet Frame ................................................................................................. 817
Figure 19-4. Interface to an Ethernet Jack .............................................................................. 825
Figure 20-1. USB Module Block Diagram ............................................................................... 876
Figure 21-1. Analog Comparator Module Block Diagram ....................................................... 1015
Figure 21-2. Structure of Comparator Unit ............................................................................ 1017
Figure 21-3. Comparator Internal Reference Structure .......................................................... 1017
Figure 22-1. PWM Unit Diagram .......................................................................................... 1029
Figure 22-2. PWM Module Block Diagram ............................................................................ 1029
Figure 22-3. PWM Count-Down Mode .................................................................................. 1033
Figure 22-4. PWM Count-Up/Down Mode ............................................................................. 1034
Figure 22-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1034
Figure 22-6. PWM Dead-Band Generator ............................................................................. 1035
Figure 23-1. QEI Block Diagram .......................................................................................... 1105
Figure 23-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1107
Figure 24-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1127
Figure 24-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1128
Figure 27-1. Load Conditions ............................................................................................... 1208
Figure 27-2. JTAG Test Clock Input Timing ........................................................................... 1210
Figure 27-3. JTAG Test Access Port (TAP) Timing ................................................................ 1211
Figure 27-4. External Reset Timing (RST) ............................................................................ 1211
Figure 27-5. Power-On Reset Timing ................................................................................... 1212
Figure 27-6. Brown-Out Reset Timing .................................................................................. 1212
Figure 27-7. Software Reset Timing ..................................................................................... 1212
Figure 27-8. Watchdog Reset Timing ................................................................................... 1212
Figure 27-9. MOSC Failure Reset Timing ............................................................................. 1213
Figure 27-10. SDRAM Initialization and Load Mode Register Timing ........................................ 1214
Figure 27-11. SDRAM Read Timing ....................................................................................... 1215
Figure 27-12. SDRAM Write Timing ....................................................................................... 1215
Figure 27-13. Host-Bus 8/16 Mode Read Timing ..................................................................... 1216
Figure 27-14. Host-Bus 8/16 Mode Write Timing ..................................................................... 1216
Figure 27-15. General-Purpose Mode Read and Write Timing ................................................. 1217
Figure 27-16. General-Purpose Mode iRDY Timing ................................................................. 1217
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Stellaris® LM3S9B95 Microcontroller
Figure 27-17. ADC Input Equivalency Diagram ....................................................................... 1219
Figure 27-18. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1220
Figure 27-19. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1220
Figure 27-20. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1221
Figure 27-21. I2C Timing ....................................................................................................... 1221
Figure 27-22. I2S Master Mode Transmit Timing ..................................................................... 1222
Figure 27-23. I2S Master Mode Receive Timing ...................................................................... 1222
Figure 27-24. I2S Slave Mode Transmit Timing ....................................................................... 1223
Figure 27-25. I2S Slave Mode Receive Timing ........................................................................ 1223
Figure 27-26. External XTLP Oscillator Characteristics ........................................................... 1225
Figure C-1. 100-Pin LQFP Package .................................................................................... 1278
Figure C-2. 108-Ball BGA Package ..................................................................................... 1280
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Texas Instruments-Advance Information
Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 6-8.
Table 6-9.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 8-6.
Table 8-7.
Table 8-8.
Table 8-9.
Table 8-10.
Table 8-11.
Table 8-12.
Table 8-13.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Revision History .................................................................................................. 37
Documentation Conventions ................................................................................ 43
16-Bit Cortex-M3 Instruction Set Summary ............................................................ 72
32-Bit Cortex-M3 Instruction Set Summary ............................................................ 74
Memory Map ....................................................................................................... 83
Exception Types .................................................................................................. 86
Interrupts ............................................................................................................ 87
Signals for JTAG_SWD_SWO (100LQFP) ............................................................. 90
Signals for JTAG_SWD_SWO (108BGA) .............................................................. 91
JTAG Port Pins State after Power-On Reset or RST assertion ................................ 92
JTAG Instruction Register Commands ................................................................... 97
Signals for System Control & Clocks (100LQFP) .................................................. 101
Signals for System Control & Clocks (108BGA) ................................................... 101
Reset Sources ................................................................................................... 102
Clock Source Options ........................................................................................ 108
Possible System Clock Frequencies Using the SYSDIV Field ............................... 111
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 111
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 112
System Control Register Map ............................................................................. 116
RCC2 Fields that Override RCC fields ................................................................. 137
Flash Memory Protection Policy Combinations .................................................... 213
User-Programmable Flash Memory Resident Registers ....................................... 216
Flash Register Map ............................................................................................ 216
μDMA Channel Assignments .............................................................................. 248
Request Type Support ....................................................................................... 250
Control Structure Memory Map ........................................................................... 251
Channel Control Structure .................................................................................. 251
μDMA Read Example: 8-Bit Peripheral ................................................................ 260
μDMA Interrupt Assignments .............................................................................. 261
Channel Control Structure Offsets for Channel 30 ................................................ 262
Channel Control Word Configuration for Memory Transfer Example ...................... 262
Channel Control Structure Offsets for Channel 7 .................................................. 263
Channel Control Word Configuration for Peripheral Transmit Example .................. 264
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 265
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 266
μDMA Register Map .......................................................................................... 267
GPIO Pins With Non-Zero Reset Values .............................................................. 305
GPIO Pins and Alternate Functions (100LQFP) ................................................... 305
GPIO Pins and Alternate Functions (108BGA) ..................................................... 307
GPIO Pad Configuration Examples ..................................................................... 313
GPIO Interrupt Configuration Example ................................................................ 314
GPIO Pins With Non-Zero Reset Values .............................................................. 315
GPIO Register Map ........................................................................................... 316
GPIO Pins With Non-Zero Reset Values .............................................................. 328
GPIO Pins With Non-Zero Reset Values .............................................................. 334
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Table 9-10.
Table 9-11.
Table 9-12.
Table 10-1.
Table 10-2.
Table 10-3.
Table 10-4.
Table 10-5.
Table 10-6.
Table 10-7.
Table 10-8.
Table 11-1.
Table 11-2.
Table 11-3.
Table 11-4.
Table 11-5.
Table 12-1.
Table 13-1.
Table 13-2.
Table 13-3.
Table 13-4.
Table 13-5.
Table 14-1.
Table 14-2.
Table 14-3.
Table 14-4.
Table 15-1.
Table 15-2.
Table 15-3.
Table 16-1.
Table 16-2.
Table 16-3.
Table 16-4.
Table 16-5.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table 17-6.
Table 17-7.
Table 17-8.
Table 17-9.
Table 17-10.
Table 18-1.
Table 18-2.
Table 18-3.
Table 18-4.
GPIO Pins With Non-Zero Reset Values .............................................................. 336
GPIO Pins With Non-Zero Reset Values .............................................................. 339
GPIO Pins With Non-Zero Reset Values .............................................................. 346
Signals for External Peripheral Interface (100LQFP) ............................................ 362
Signals for External Peripheral Interface (108BGA) .............................................. 363
EPI SDRAM Signal Connections ......................................................................... 368
Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 372
EPI Host-Bus 8 Signal Connections .................................................................... 373
EPI Host-Bus 16 Signal Connections .................................................................. 374
EPI General Purpose Signal Connections ........................................................... 382
External Peripheral Interface (EPI) Register Map ................................................. 388
Available CCP Pins ............................................................................................ 434
Signals for General-Purpose Timers (100LQFP) .................................................. 435
Signals for General-Purpose Timers (108BGA) .................................................... 436
16-Bit Timer With Prescaler Configurations ......................................................... 440
Timers Register Map .......................................................................................... 449
Watchdog Timers Register Map .......................................................................... 484
Signals for ADC (100LQFP) ............................................................................... 508
Signals for ADC (108BGA) ................................................................................. 508
Samples and FIFO Depth of Sequencers ............................................................ 509
Differential Sampling Pairs ................................................................................. 515
ADC Register Map ............................................................................................. 524
Signals for UART (100LQFP) ............................................................................. 586
Signals for UART (108BGA) ............................................................................... 586
Flow Control Mode ............................................................................................. 591
UART Register Map ........................................................................................... 596
Signals for SSI (100LQFP) ................................................................................. 648
Signals for SSI (108BGA) ................................................................................... 648
SSI Register Map .............................................................................................. 659
Signals for I2C (100LQFP) ................................................................................. 689
Signals for I2C (108BGA) ................................................................................... 689
Examples of I2C Master Timer Period versus Speed Mode ................................... 693
Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 702
Write Field Decoding for I2CMCS[3:0] Field ......................................................... 708
Signals for I2S (100LQFP) ................................................................................. 727
Signals for I2S (108BGA) ................................................................................... 727
I2S Transmit FIFO Interface ................................................................................ 730
Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 731
Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 731
Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 732
Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 732
I2S Receive FIFO Interface ................................................................................. 734
Audio Formats Configuration .............................................................................. 736
Inter-Integrated Circuit Sound (I2S) Interface Register Map ................................... 737
Signals for Controller Area Network (100LQFP) ................................................... 764
Signals for Controller Area Network (108BGA) ..................................................... 764
Message Object Configurations .......................................................................... 770
CAN Protocol Ranges ........................................................................................ 777
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Table of Contents
Table 18-5.
Table 18-6.
Table 19-1.
Table 19-2.
Table 19-3.
Table 19-4.
Table 20-1.
Table 20-2.
Table 20-3.
Table 20-4.
Table 20-5.
Table 20-6.
Table 21-1.
Table 21-2.
Table 21-3.
Table 21-4.
Table 22-1.
Table 22-2.
Table 22-3.
Table 23-1.
Table 23-2.
Table 23-3.
Table 25-1.
Table 25-2.
Table 25-3.
Table 25-4.
Table 25-5.
Table 25-6.
Table 25-7.
Table 25-8.
Table 25-9.
Table 25-10.
Table 25-11.
Table 25-12.
Table 25-13.
Table 26-1.
Table 26-2.
Table 26-3.
Table 27-1.
Table 27-2.
Table 27-3.
Table 27-4.
Table 27-5.
Table 27-6.
Table 27-7.
Table 27-8.
Table 27-9.
Table 27-10.
CANBIT Register Values .................................................................................... 777
CAN Register Map ............................................................................................. 781
Signals for Ethernet (100LQFP) .......................................................................... 816
Signals for Ethernet (108BGA) ............................................................................ 816
TX & RX FIFO Organization ............................................................................... 819
Ethernet Register Map ....................................................................................... 826
Signals for USB (100LQFP) ................................................................................ 876
Signals for USB (108BGA) ................................................................................. 877
Remainder (RxMaxP/4) ...................................................................................... 889
Actual Bytes Read ............................................................................................. 889
Packet Sizes That Clear RXRDY ........................................................................ 889
Universal Serial Bus (USB) Controller Register Map ............................................ 891
Signals for Analog Comparators (100LQFP) ...................................................... 1015
Signals for Analog Comparators (108BGA) ........................................................ 1016
Internal Reference Voltage and ACREFCTL Field Values ................................... 1018
Analog Comparators Register Map ................................................................... 1019
Signals for PWM (100LQFP) ............................................................................ 1030
Signals for PWM (108BGA) .............................................................................. 1031
PWM Register Map .......................................................................................... 1039
Signals for QEI (100LQFP) ............................................................................... 1105
Signals for QEI (108BGA) ................................................................................. 1106
QEI Register Map ............................................................................................ 1109
GPIO Pins With Default Alternate Functions ...................................................... 1129
Signals by Pin Number ..................................................................................... 1130
Signals by Signal Name ................................................................................... 1141
Signals by Function, Except for GPIO ............................................................... 1151
GPIO Pins and Alternate Functions ................................................................... 1160
Possible Pin Assignments for Alternate Functions .............................................. 1163
Signals by Pin Number ..................................................................................... 1165
Signals by Signal Name ................................................................................... 1177
Signals by Function, Except for GPIO ............................................................... 1188
GPIO Pins and Alternate Functions ................................................................... 1197
Possible Pin Assignments for Alternate Functions .............................................. 1200
Connections for Unused Signals (100-pin LQFP) ............................................... 1202
Connections for Unused Signals, 108-pin BGA .................................................. 1203
Temperature Characteristics ............................................................................. 1204
Thermal Characteristics ................................................................................... 1204
ESD Absolute Maximum Ratings ...................................................................... 1204
Maximum Ratings ............................................................................................ 1205
Recommended DC Operating Conditions .......................................................... 1205
LDO Regulator Characteristics ......................................................................... 1206
Flash Memory Characteristics ........................................................................... 1206
GPIO Module DC Characteristics ...................................................................... 1206
USB Controller DC Characteristics .................................................................... 1207
Ethernet Controller DC Characteristics .............................................................. 1207
Preliminary Current Consumption ..................................................................... 1207
Phase Locked Loop (PLL) Characteristics ......................................................... 1208
Actual PLL Frequency ...................................................................................... 1208
16
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Table 27-11.
Table 27-12.
Table 27-13.
Table 27-14.
Table 27-15.
Table 27-16.
Table 27-17.
Table 27-18.
Table 27-19.
Table 27-20.
Table 27-21.
Table 27-22.
Table 27-23.
Table 27-24.
Table 27-25.
Table 27-26.
Table 27-27.
Table 27-28.
Table 27-29.
Table 27-30.
Table 27-31.
Table 27-32.
Table 27-33.
Table 27-34.
Table 27-35.
Table 27-36.
Table 27-37.
Table 27-38.
Table 27-39.
Table 27-40.
Table 27-41.
Table 27-42.
Table B-1.
PIOSC Clock Characteristics ............................................................................ 1209
30-kHz Clock Characteristics ............................................................................ 1209
Main Oscillator Clock Characteristics ................................................................ 1209
MOSC Oscillator Input Characteristics ............................................................... 1209
System Clock Characteristics with ADC Operation ............................................. 1210
JTAG Characteristics ....................................................................................... 1210
Reset Characteristics ....................................................................................... 1211
Sleep Modes AC Characteristics ....................................................................... 1213
GPIO Characteristics ....................................................................................... 1213
EPI SDRAM Characteristics ............................................................................. 1213
EPI SDRAM Interface Characteristics ............................................................... 1214
EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ................................. 1215
EPI General-Purpose Interface Characteristics .................................................. 1216
ADC Characteristics ......................................................................................... 1218
ADC Module External Reference Characteristics ............................................... 1219
ADC Module Internal Reference Characteristics ................................................ 1219
SSI Characteristics .......................................................................................... 1219
I2S Master Clock (Receive and Transmit) .......................................................... 1221
I2S Slave Clock (Receive and Transmit) ............................................................ 1221
I2S Master Mode .............................................................................................. 1222
I2S Slave Mode ................................................................................................ 1222
100BASE-TX Transmitter Characteristics .......................................................... 1223
100BASE-TX Transmitter Characteristics (informative) ....................................... 1223
100BASE-TX Receiver Characteristics .............................................................. 1223
10BASE-T Transmitter Characteristics .............................................................. 1224
10BASE-T Transmitter Characteristics (informative) ........................................... 1224
10BASE-T Receiver Characteristics .................................................................. 1224
Isolation Transformers ...................................................................................... 1224
Ethernet Reference Crystal .............................................................................. 1225
External XTLP Oscillator Characteristics ........................................................... 1225
Analog Comparator Characteristics ................................................................... 1226
Analog Comparator Voltage Reference Characteristics ...................................... 1226
Part Ordering Information ................................................................................. 1276
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Table of Contents
List of Registers
System Control ............................................................................................................................ 101
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Device Identification 0 (DID0), offset 0x000 ..................................................................... 118
Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 120
Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 121
Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 123
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 125
Reset Cause (RESC), offset 0x05C ................................................................................ 127
Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 129
XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 134
GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 135
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 137
Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 140
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 141
Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 143
I2S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 144
Device Identification 1 (DID1), offset 0x004 ..................................................................... 146
Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 148
Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 149
Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 152
Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 155
Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 158
Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 160
Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 162
Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 163
Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 167
Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 170
Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 172
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 173
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 176
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 179
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 181
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 185
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 189
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 193
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 196
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 199
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 202
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 204
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 207
Internal Memory ........................................................................................................................... 209
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Flash Memory Address (FMA), offset 0x000 .................................................................... 218
Flash Memory Data (FMD), offset 0x004 ......................................................................... 219
Flash Memory Control (FMC), offset 0x008 ..................................................................... 220
Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 222
Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 223
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Stellaris® LM3S9B95 Microcontroller
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 224
Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 225
Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 226
Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 227
Flash Control (FCTL), offset 0x0F8 ................................................................................. 228
ROM Control (RMCTL), offset 0x0F0 .............................................................................. 229
ROM Version Register (RMVER), offset 0x0F4 ................................................................ 230
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 231
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 232
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 233
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 236
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 237
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 238
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 239
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 240
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 241
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 242
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 243
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 244
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 245
Micro Direct Memory Access (μDMA) ........................................................................................ 246
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 269
DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 270
DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 271
DMA Status (DMASTAT), offset 0x000 ............................................................................ 276
DMA Configuration (DMACFG), offset 0x004 ................................................................... 278
DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 279
DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 280
DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 281
DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 282
DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 283
DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 284
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 285
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 286
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 287
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 288
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 289
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 290
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 291
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 292
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 293
DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 294
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 295
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 296
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 297
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 298
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 299
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 300
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Register 28:
Register 29:
Register 30:
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 301
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 302
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 303
General-Purpose Input/Outputs (GPIOs) ................................................................................... 304
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
GPIO Data (GPIODATA), offset 0x000 ............................................................................ 318
GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 319
GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 320
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 321
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 322
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 323
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 324
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 325
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 327
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 328
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 330
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 331
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 332
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 333
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 334
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 336
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 338
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 339
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 341
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 342
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 344
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 346
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 348
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 349
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 350
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 351
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 352
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 353
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 354
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 355
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 356
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 357
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 358
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 359
External Peripheral Interface (EPI) ............................................................................................. 360
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
EPI Configuration (EPICFG), offset 0x000 ....................................................................... 390
EPI Main Baud Rate (EPIBAUD), offset 0x004 ................................................................. 392
EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 .............................................. 394
EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ............................................... 396
EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ........................................... 400
EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................ 404
EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 .......................................... 409
EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ....................................... 411
EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ................................... 413
20
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Stellaris® LM3S9B95 Microcontroller
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
EPI Address Map (EPIADDRMAP), offset 0x01C .............................................................
EPI Read Size 0 (EPIRSIZE0), offset 0x020 ....................................................................
EPI Read Size 1 (EPIRSIZE1), offset 0x030 ....................................................................
EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................
EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................
EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 .............................................
EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 .............................................
EPI Status (EPISTAT), offset 0x060 ................................................................................
EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ......................................................
EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................
EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 ....................................................
EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 ....................................................
EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ...................................................
EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 ....................................................
EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 ....................................................
EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 ....................................................
EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ...................................................
EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................
EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ......................................................
EPI Interrupt Mask (EPIIM), offset 0x210 .........................................................................
EPI Raw Interrupt Status (EPIRIS), offset 0x214 ..............................................................
EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................
EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C ...........................................
414
416
416
417
417
418
418
420
422
423
423
423
423
423
423
423
423
424
426
427
428
430
431
General-Purpose Timers ............................................................................................................. 433
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 450
GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 451
GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 453
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 455
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 458
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 460
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 463
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 466
GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 468
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 469
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 470
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 471
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 472
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 473
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 474
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 475
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 476
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 477
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 479
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 480
Watchdog Timers ......................................................................................................................... 481
Register 1:
Register 2:
Register 3:
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 485
Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 486
Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 487
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Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 489
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 490
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 491
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 492
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 493
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 494
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 495
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 496
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 497
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 498
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 499
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 500
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 501
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 502
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 503
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 504
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 505
Analog-to-Digital Converter (ADC) ............................................................................................. 506
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 527
ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 528
ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 530
ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 532
ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 535
ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 537
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 542
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 543
ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 545
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 546
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 548
ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 549
ADC Control (ADCCTL), offset 0x038 ............................................................................. 551
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 552
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 554
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 557
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 557
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 557
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 557
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 558
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 558
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 558
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 558
ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 560
ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 562
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 564
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 564
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 565
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 565
ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 567
22
June 14, 2010
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Stellaris® LM3S9B95 Microcontroller
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 567
ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 568
ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 568
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 570
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 571
ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 572
ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 573
ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 574
ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 579
ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 579
ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 579
ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 579
ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 579
ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 579
ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 579
ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 579
ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 583
ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 583
ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 583
ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 583
ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 583
ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 583
ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 583
ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 583
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 584
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
UART Data (UARTDR), offset 0x000 ............................................................................... 598
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 600
UART Flag (UARTFR), offset 0x018 ................................................................................ 603
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 606
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 607
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 608
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 609
UART Control (UARTCTL), offset 0x030 ......................................................................... 611
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 615
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 617
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 621
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 625
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 628
UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 630
UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 631
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 632
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 633
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 634
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 635
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 636
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 637
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 638
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 639
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Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................
640
641
642
643
644
645
Synchronous Serial Interface (SSI) ............................................................................................ 646
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 661
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 663
SSI Data (SSIDR), offset 0x008 ...................................................................................... 665
SSI Status (SSISR), offset 0x00C ................................................................................... 666
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 668
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 669
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 670
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 672
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 674
SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 675
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 676
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 677
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 678
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 679
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 680
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 681
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 682
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 683
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 684
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 685
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 686
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 687
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 688
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 704
I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 705
I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 710
I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 711
I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 712
I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 713
I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 714
I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 715
I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 716
I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 717
I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 718
I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 720
I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 721
I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 722
I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 723
I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 724
24
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Stellaris® LM3S9B95 Microcontroller
Inter-Integrated Circuit Sound (I2S) Interface ............................................................................ 725
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
I2S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 738
I2S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 739
I2S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 740
I2S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 742
I2S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 743
I2S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 744
I2S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 745
I2S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 746
I2S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 747
I2S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 750
I2S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 751
I2S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 752
I2S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 753
I2S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 755
I2S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 757
I2S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 759
I2S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 761
Controller Area Network (CAN) Module ..................................................................................... 762
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
CAN Control (CANCTL), offset 0x000 ............................................................................. 783
CAN Status (CANSTS), offset 0x004 ............................................................................... 785
CAN Error Counter (CANERR), offset 0x008 ................................................................... 788
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 789
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 791
CAN Test (CANTST), offset 0x014 .................................................................................. 792
CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 794
CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 795
CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 795
CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 797
CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 797
CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 800
CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 800
CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 801
CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 801
CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 803
CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 803
CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 804
CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 804
CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 806
CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 806
CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 809
CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 809
CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 809
CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 809
CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 809
CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 809
CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 809
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Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 809
CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 810
CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 810
CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 811
CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 811
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 812
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 812
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 813
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 813
Ethernet Controller ...................................................................................................................... 814
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 829
Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 832
Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 834
Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 836
Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 838
Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 840
Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 841
Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 842
Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 844
Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 846
Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 847
Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 848
Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 849
Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 850
Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 851
Ethernet MAC LED Encoding (MACLED), offset 0x040 .................................................... 852
Ethernet PHY MDIX (MDIX), offset 0x044 ....................................................................... 854
Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 855
Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 857
Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 859
Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 860
Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 861
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 863
Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 865
Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 866
Ethernet PHY Management Register 17 – Mode Control/Status (MR17), address 0x11 ...... 867
Ethernet PHY Management Register 27 – Special Control/Status (MR27), address
0x1B ............................................................................................................................. 869
Ethernet PHY Management Register 29 – Interrupt Status (MR29), address 0x1D ............. 870
Ethernet PHY Management Register 30 – Interrupt Mask (MR30), address 0x1E ............... 872
Ethernet PHY Management Register 31 – PHY Special Control/Status (MR31), address
0x1F ............................................................................................................................. 874
Universal Serial Bus (USB) Controller ....................................................................................... 875
Register 1:
Register 2:
USB Device Functional Address (USBFADDR), offset 0x000 ............................................ 903
USB Power (USBPOWER), offset 0x001 ......................................................................... 904
26
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
USB Transmit Interrupt Status (USBTXIS), offset 0x002 ................................................... 907
USB Receive Interrupt Status (USBRXIS), offset 0x004 ................................................... 909
USB Transmit Interrupt Enable (USBTXIE), offset 0x006 .................................................. 911
USB Receive Interrupt Enable (USBRXIE), offset 0x008 .................................................. 913
USB General Interrupt Status (USBIS), offset 0x00A ........................................................ 915
USB Interrupt Enable (USBIE), offset 0x00B .................................................................... 918
USB Frame Value (USBFRAME), offset 0x00C ................................................................ 921
USB Endpoint Index (USBEPIDX), offset 0x00E .............................................................. 922
USB Test Mode (USBTEST), offset 0x00F ....................................................................... 923
USB FIFO Endpoint 0 (USBFIFO0), offset 0x020 ............................................................. 925
USB FIFO Endpoint 1 (USBFIFO1), offset 0x024 ............................................................. 925
USB FIFO Endpoint 2 (USBFIFO2), offset 0x028 ............................................................. 925
USB FIFO Endpoint 3 (USBFIFO3), offset 0x02C ............................................................ 925
USB FIFO Endpoint 4 (USBFIFO4), offset 0x030 ............................................................. 925
USB FIFO Endpoint 5 (USBFIFO5), offset 0x034 ............................................................. 925
USB FIFO Endpoint 6 (USBFIFO6), offset 0x038 ............................................................. 925
USB FIFO Endpoint 7 (USBFIFO7), offset 0x03C ............................................................ 925
USB FIFO Endpoint 8 (USBFIFO8), offset 0x040 ............................................................. 925
USB FIFO Endpoint 9 (USBFIFO9), offset 0x044 ............................................................. 925
USB FIFO Endpoint 10 (USBFIFO10), offset 0x048 ......................................................... 925
USB FIFO Endpoint 11 (USBFIFO11), offset 0x04C ......................................................... 925
USB FIFO Endpoint 12 (USBFIFO12), offset 0x050 ......................................................... 925
USB FIFO Endpoint 13 (USBFIFO13), offset 0x054 ......................................................... 925
USB FIFO Endpoint 14 (USBFIFO14), offset 0x058 ......................................................... 925
USB FIFO Endpoint 15 (USBFIFO15), offset 0x05C ......................................................... 925
USB Device Control (USBDEVCTL), offset 0x060 ............................................................ 927
USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ), offset 0x062 ................................. 929
USB Receive Dynamic FIFO Sizing (USBRXFIFOSZ), offset 0x063 .................................. 929
USB Transmit FIFO Start Address (USBTXFIFOADD), offset 0x064 ................................. 930
USB Receive FIFO Start Address (USBRXFIFOADD), offset 0x066 .................................. 930
USB Connect Timing (USBCONTIM), offset 0x07A .......................................................... 931
USB OTG VBUS Pulse Timing (USBVPLEN), offset 0x07B .............................................. 932
USB Full-Speed Last Transaction to End of Frame Timing (USBFSEOF), offset 0x07D ...... 933
USB Low-Speed Last Transaction to End of Frame Timing (USBLSEOF), offset 0x07E ...... 934
USB Transmit Functional Address Endpoint 0 (USBTXFUNCADDR0), offset 0x080 ........... 935
USB Transmit Functional Address Endpoint 1 (USBTXFUNCADDR1), offset 0x088 ........... 935
USB Transmit Functional Address Endpoint 2 (USBTXFUNCADDR2), offset 0x090 ........... 935
USB Transmit Functional Address Endpoint 3 (USBTXFUNCADDR3), offset 0x098 ........... 935
USB Transmit Functional Address Endpoint 4 (USBTXFUNCADDR4), offset 0x0A0 ........... 935
USB Transmit Functional Address Endpoint 5 (USBTXFUNCADDR5), offset 0x0A8 ........... 935
USB Transmit Functional Address Endpoint 6 (USBTXFUNCADDR6), offset 0x0B0 ........... 935
USB Transmit Functional Address Endpoint 7 (USBTXFUNCADDR7), offset 0x0B8 ........... 935
USB Transmit Functional Address Endpoint 8 (USBTXFUNCADDR8), offset 0x0C0 .......... 935
USB Transmit Functional Address Endpoint 9 (USBTXFUNCADDR9), offset 0x0C8 .......... 935
USB Transmit Functional Address Endpoint 10 (USBTXFUNCADDR10), offset 0x0D0 ....... 935
USB Transmit Functional Address Endpoint 11 (USBTXFUNCADDR11), offset 0x0D8 ....... 935
USB Transmit Functional Address Endpoint 12 (USBTXFUNCADDR12), offset 0x0E0 ....... 935
USB Transmit Functional Address Endpoint 13 (USBTXFUNCADDR13), offset 0x0E8 ....... 935
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Table of Contents
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
Register 88:
Register 89:
Register 90:
Register 91:
Register 92:
Register 93:
Register 94:
Register 95:
Register 96:
Register 97:
Register 98:
USB Transmit Functional Address Endpoint 14 (USBTXFUNCADDR14), offset 0x0F0 ....... 935
USB Transmit Functional Address Endpoint 15 (USBTXFUNCADDR15), offset 0x0F8 ....... 935
USB Transmit Hub Address Endpoint 0 (USBTXHUBADDR0), offset 0x082 ...................... 937
USB Transmit Hub Address Endpoint 1 (USBTXHUBADDR1), offset 0x08A ...................... 937
USB Transmit Hub Address Endpoint 2 (USBTXHUBADDR2), offset 0x092 ...................... 937
USB Transmit Hub Address Endpoint 3 (USBTXHUBADDR3), offset 0x09A ...................... 937
USB Transmit Hub Address Endpoint 4 (USBTXHUBADDR4), offset 0x0A2 ...................... 937
USB Transmit Hub Address Endpoint 5 (USBTXHUBADDR5), offset 0x0AA ...................... 937
USB Transmit Hub Address Endpoint 6 (USBTXHUBADDR6), offset 0x0B2 ...................... 937
USB Transmit Hub Address Endpoint 7 (USBTXHUBADDR7), offset 0x0BA ...................... 937
USB Transmit Hub Address Endpoint 8 (USBTXHUBADDR8), offset 0x0C2 ...................... 937
USB Transmit Hub Address Endpoint 9 (USBTXHUBADDR9), offset 0x0CA ..................... 937
USB Transmit Hub Address Endpoint 10 (USBTXHUBADDR10), offset 0x0D2 .................. 937
USB Transmit Hub Address Endpoint 11 (USBTXHUBADDR11), offset 0x0DA .................. 937
USB Transmit Hub Address Endpoint 12 (USBTXHUBADDR12), offset 0x0E2 .................. 937
USB Transmit Hub Address Endpoint 13 (USBTXHUBADDR13), offset 0x0EA .................. 937
USB Transmit Hub Address Endpoint 14 (USBTXHUBADDR14), offset 0x0F2 .................. 937
USB Transmit Hub Address Endpoint 15 (USBTXHUBADDR15), offset 0x0FA .................. 937
USB Transmit Hub Port Endpoint 0 (USBTXHUBPORT0), offset 0x083 ............................. 939
USB Transmit Hub Port Endpoint 1 (USBTXHUBPORT1), offset 0x08B ............................ 939
USB Transmit Hub Port Endpoint 2 (USBTXHUBPORT2), offset 0x093 ............................. 939
USB Transmit Hub Port Endpoint 3 (USBTXHUBPORT3), offset 0x09B ............................ 939
USB Transmit Hub Port Endpoint 4 (USBTXHUBPORT4), offset 0x0A3 ............................ 939
USB Transmit Hub Port Endpoint 5 (USBTXHUBPORT5), offset 0x0AB ............................ 939
USB Transmit Hub Port Endpoint 6 (USBTXHUBPORT6), offset 0x0B3 ............................ 939
USB Transmit Hub Port Endpoint 7 (USBTXHUBPORT7), offset 0x0BB ............................ 939
USB Transmit Hub Port Endpoint 8 (USBTXHUBPORT8), offset 0x0C3 ............................ 939
USB Transmit Hub Port Endpoint 9 (USBTXHUBPORT9), offset 0x0CB ............................ 939
USB Transmit Hub Port Endpoint 10 (USBTXHUBPORT10), offset 0x0D3 ........................ 939
USB Transmit Hub Port Endpoint 11 (USBTXHUBPORT11), offset 0x0DB ......................... 939
USB Transmit Hub Port Endpoint 12 (USBTXHUBPORT12), offset 0x0E3 ......................... 939
USB Transmit Hub Port Endpoint 13 (USBTXHUBPORT13), offset 0x0EB ........................ 939
USB Transmit Hub Port Endpoint 14 (USBTXHUBPORT14), offset 0x0F3 ......................... 939
USB Transmit Hub Port Endpoint 15 (USBTXHUBPORT15), offset 0x0FB ........................ 939
USB Receive Functional Address Endpoint 1 (USBRXFUNCADDR1), offset 0x08C ........... 941
USB Receive Functional Address Endpoint 2 (USBRXFUNCADDR2), offset 0x094 ........... 941
USB Receive Functional Address Endpoint 3 (USBRXFUNCADDR3), offset 0x09C ........... 941
USB Receive Functional Address Endpoint 4 (USBRXFUNCADDR4), offset 0x0A4 ........... 941
USB Receive Functional Address Endpoint 5 (USBRXFUNCADDR5), offset 0x0AC .......... 941
USB Receive Functional Address Endpoint 6 (USBRXFUNCADDR6), offset 0x0B4 ........... 941
USB Receive Functional Address Endpoint 7 (USBRXFUNCADDR7), offset 0x0BC .......... 941
USB Receive Functional Address Endpoint 8 (USBRXFUNCADDR8), offset 0x0C4 ........... 941
USB Receive Functional Address Endpoint 9 (USBRXFUNCADDR9), offset 0x0CC .......... 941
USB Receive Functional Address Endpoint 10 (USBRXFUNCADDR10), offset 0x0D4 ....... 941
USB Receive Functional Address Endpoint 11 (USBRXFUNCADDR11), offset 0x0DC ....... 941
USB Receive Functional Address Endpoint 12 (USBRXFUNCADDR12), offset 0x0E4 ....... 941
USB Receive Functional Address Endpoint 13 (USBRXFUNCADDR13), offset 0x0EC ....... 941
USB Receive Functional Address Endpoint 14 (USBRXFUNCADDR14), offset 0x0F4 ....... 941
28
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 99:
Register 100:
Register 101:
Register 102:
Register 103:
Register 104:
Register 105:
Register 106:
Register 107:
Register 108:
Register 109:
Register 110:
Register 111:
Register 112:
Register 113:
Register 114:
Register 115:
Register 116:
Register 117:
Register 118:
Register 119:
Register 120:
Register 121:
Register 122:
Register 123:
Register 124:
Register 125:
Register 126:
Register 127:
Register 128:
Register 129:
Register 130:
Register 131:
Register 132:
Register 133:
Register 134:
Register 135:
Register 136:
Register 137:
Register 138:
Register 139:
Register 140:
Register 141:
Register 142:
Register 143:
Register 144:
Register 145:
Register 146:
USB Receive Functional Address Endpoint 15 (USBRXFUNCADDR15), offset 0x0FC ....... 941
USB Receive Hub Address Endpoint 1 (USBRXHUBADDR1), offset 0x08E ...................... 943
USB Receive Hub Address Endpoint 2 (USBRXHUBADDR2), offset 0x096 ....................... 943
USB Receive Hub Address Endpoint 3 (USBRXHUBADDR3), offset 0x09E ...................... 943
USB Receive Hub Address Endpoint 4 (USBRXHUBADDR4), offset 0x0A6 ...................... 943
USB Receive Hub Address Endpoint 5 (USBRXHUBADDR5), offset 0x0AE ...................... 943
USB Receive Hub Address Endpoint 6 (USBRXHUBADDR6), offset 0x0B6 ...................... 943
USB Receive Hub Address Endpoint 7 (USBRXHUBADDR7), offset 0x0BE ...................... 943
USB Receive Hub Address Endpoint 8 (USBRXHUBADDR8), offset 0x0C6 ...................... 943
USB Receive Hub Address Endpoint 9 (USBRXHUBADDR9), offset 0x0CE ...................... 943
USB Receive Hub Address Endpoint 10 (USBRXHUBADDR10), offset 0x0D6 ................... 943
USB Receive Hub Address Endpoint 11 (USBRXHUBADDR11), offset 0x0DE ................... 943
USB Receive Hub Address Endpoint 12 (USBRXHUBADDR12), offset 0x0E6 ................... 943
USB Receive Hub Address Endpoint 13 (USBRXHUBADDR13), offset 0x0EE .................. 943
USB Receive Hub Address Endpoint 14 (USBRXHUBADDR14), offset 0x0F6 ................... 943
USB Receive Hub Address Endpoint 15 (USBRXHUBADDR15), offset 0x0FE ................... 943
USB Receive Hub Port Endpoint 1 (USBRXHUBPORT1), offset 0x08F ............................. 945
USB Receive Hub Port Endpoint 2 (USBRXHUBPORT2), offset 0x097 ............................. 945
USB Receive Hub Port Endpoint 3 (USBRXHUBPORT3), offset 0x09F ............................. 945
USB Receive Hub Port Endpoint 4 (USBRXHUBPORT4), offset 0x0A7 ............................. 945
USB Receive Hub Port Endpoint 5 (USBRXHUBPORT5), offset 0x0AF ............................. 945
USB Receive Hub Port Endpoint 6 (USBRXHUBPORT6), offset 0x0B7 ............................. 945
USB Receive Hub Port Endpoint 7 (USBRXHUBPORT7), offset 0x0BF ............................. 945
USB Receive Hub Port Endpoint 8 (USBRXHUBPORT8), offset 0x0C7 ............................. 945
USB Receive Hub Port Endpoint 9 (USBRXHUBPORT9), offset 0x0CF ............................ 945
USB Receive Hub Port Endpoint 10 (USBRXHUBPORT10), offset 0x0D7 ......................... 945
USB Receive Hub Port Endpoint 11 (USBRXHUBPORT11), offset 0x0DF ......................... 945
USB Receive Hub Port Endpoint 12 (USBRXHUBPORT12), offset 0x0E7 ......................... 945
USB Receive Hub Port Endpoint 13 (USBRXHUBPORT13), offset 0x0EF ......................... 945
USB Receive Hub Port Endpoint 14 (USBRXHUBPORT14), offset 0x0F7 ......................... 945
USB Receive Hub Port Endpoint 15 (USBRXHUBPORT15), offset 0x0FF ......................... 945
USB Maximum Transmit Data Endpoint 1 (USBTXMAXP1), offset 0x110 .......................... 947
USB Maximum Transmit Data Endpoint 2 (USBTXMAXP2), offset 0x120 .......................... 947
USB Maximum Transmit Data Endpoint 3 (USBTXMAXP3), offset 0x130 .......................... 947
USB Maximum Transmit Data Endpoint 4 (USBTXMAXP4), offset 0x140 .......................... 947
USB Maximum Transmit Data Endpoint 5 (USBTXMAXP5), offset 0x150 .......................... 947
USB Maximum Transmit Data Endpoint 6 (USBTXMAXP6), offset 0x160 .......................... 947
USB Maximum Transmit Data Endpoint 7 (USBTXMAXP7), offset 0x170 .......................... 947
USB Maximum Transmit Data Endpoint 8 (USBTXMAXP8), offset 0x180 .......................... 947
USB Maximum Transmit Data Endpoint 9 (USBTXMAXP9), offset 0x190 .......................... 947
USB Maximum Transmit Data Endpoint 10 (USBTXMAXP10), offset 0x1A0 ...................... 947
USB Maximum Transmit Data Endpoint 11 (USBTXMAXP11), offset 0x1B0 ....................... 947
USB Maximum Transmit Data Endpoint 12 (USBTXMAXP12), offset 0x1C0 ...................... 947
USB Maximum Transmit Data Endpoint 13 (USBTXMAXP13), offset 0x1D0 ...................... 947
USB Maximum Transmit Data Endpoint 14 (USBTXMAXP14), offset 0x1E0 ...................... 947
USB Maximum Transmit Data Endpoint 15 (USBTXMAXP15), offset 0x1F0 ...................... 947
USB Control and Status Endpoint 0 Low (USBCSRL0), offset 0x102 ................................. 949
USB Control and Status Endpoint 0 High (USBCSRH0), offset 0x103 ............................... 953
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Table of Contents
Register 147:
Register 148:
Register 149:
Register 150:
Register 151:
Register 152:
Register 153:
Register 154:
Register 155:
Register 156:
Register 157:
Register 158:
Register 159:
Register 160:
Register 161:
Register 162:
Register 163:
Register 164:
Register 165:
Register 166:
Register 167:
Register 168:
Register 169:
Register 170:
Register 171:
Register 172:
Register 173:
Register 174:
Register 175:
Register 176:
Register 177:
Register 178:
Register 179:
Register 180:
Register 181:
Register 182:
Register 183:
Register 184:
Register 185:
Register 186:
Register 187:
Register 188:
Register 189:
Register 190:
Register 191:
Register 192:
Register 193:
Register 194:
USB Receive Byte Count Endpoint 0 (USBCOUNT0), offset 0x108 ................................... 955
USB Type Endpoint 0 (USBTYPE0), offset 0x10A ............................................................ 956
USB NAK Limit (USBNAKLMT), offset 0x10B .................................................................. 957
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1), offset 0x112 ............... 958
USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2), offset 0x122 ............... 958
USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3), offset 0x132 ............... 958
USB Transmit Control and Status Endpoint 4 Low (USBTXCSRL4), offset 0x142 ............... 958
USB Transmit Control and Status Endpoint 5 Low (USBTXCSRL5), offset 0x152 ............... 958
USB Transmit Control and Status Endpoint 6 Low (USBTXCSRL6), offset 0x162 ............... 958
USB Transmit Control and Status Endpoint 7 Low (USBTXCSRL7), offset 0x172 ............... 958
USB Transmit Control and Status Endpoint 8 Low (USBTXCSRL8), offset 0x182 ............... 958
USB Transmit Control and Status Endpoint 9 Low (USBTXCSRL9), offset 0x192 ............... 958
USB Transmit Control and Status Endpoint 10 Low (USBTXCSRL10), offset 0x1A2 ........... 958
USB Transmit Control and Status Endpoint 11 Low (USBTXCSRL11), offset 0x1B2 ........... 958
USB Transmit Control and Status Endpoint 12 Low (USBTXCSRL12), offset 0x1C2 .......... 958
USB Transmit Control and Status Endpoint 13 Low (USBTXCSRL13), offset 0x1D2 .......... 958
USB Transmit Control and Status Endpoint 14 Low (USBTXCSRL14), offset 0x1E2 ........... 958
USB Transmit Control and Status Endpoint 15 Low (USBTXCSRL15), offset 0x1F2 ........... 958
USB Transmit Control and Status Endpoint 1 High (USBTXCSRH1), offset 0x113 .............. 963
USB Transmit Control and Status Endpoint 2 High (USBTXCSRH2), offset 0x123 ............. 963
USB Transmit Control and Status Endpoint 3 High (USBTXCSRH3), offset 0x133 ............. 963
USB Transmit Control and Status Endpoint 4 High (USBTXCSRH4), offset 0x143 ............. 963
USB Transmit Control and Status Endpoint 5 High (USBTXCSRH5), offset 0x153 ............. 963
USB Transmit Control and Status Endpoint 6 High (USBTXCSRH6), offset 0x163 ............. 963
USB Transmit Control and Status Endpoint 7 High (USBTXCSRH7), offset 0x173 ............. 963
USB Transmit Control and Status Endpoint 8 High (USBTXCSRH8), offset 0x183 ............. 963
USB Transmit Control and Status Endpoint 9 High (USBTXCSRH9), offset 0x193 ............. 963
USB Transmit Control and Status Endpoint 10 High (USBTXCSRH10), offset 0x1A3 ......... 963
USB Transmit Control and Status Endpoint 11 High (USBTXCSRH11), offset 0x1B3 .......... 963
USB Transmit Control and Status Endpoint 12 High (USBTXCSRH12), offset 0x1C3 ......... 963
USB Transmit Control and Status Endpoint 13 High (USBTXCSRH13), offset 0x1D3 ......... 963
USB Transmit Control and Status Endpoint 14 High (USBTXCSRH14), offset 0x1E3 ......... 963
USB Transmit Control and Status Endpoint 15 High (USBTXCSRH15), offset 0x1F3 ......... 963
USB Maximum Receive Data Endpoint 1 (USBRXMAXP1), offset 0x114 ........................... 967
USB Maximum Receive Data Endpoint 2 (USBRXMAXP2), offset 0x124 ........................... 967
USB Maximum Receive Data Endpoint 3 (USBRXMAXP3), offset 0x134 ........................... 967
USB Maximum Receive Data Endpoint 4 (USBRXMAXP4), offset 0x144 ........................... 967
USB Maximum Receive Data Endpoint 5 (USBRXMAXP5), offset 0x154 ........................... 967
USB Maximum Receive Data Endpoint 6 (USBRXMAXP6), offset 0x164 ........................... 967
USB Maximum Receive Data Endpoint 7 (USBRXMAXP7), offset 0x174 ........................... 967
USB Maximum Receive Data Endpoint 8 (USBRXMAXP8), offset 0x184 ........................... 967
USB Maximum Receive Data Endpoint 9 (USBRXMAXP9), offset 0x194 ........................... 967
USB Maximum Receive Data Endpoint 10 (USBRXMAXP10), offset 0x1A4 ....................... 967
USB Maximum Receive Data Endpoint 11 (USBRXMAXP11), offset 0x1B4 ....................... 967
USB Maximum Receive Data Endpoint 12 (USBRXMAXP12), offset 0x1C4 ...................... 967
USB Maximum Receive Data Endpoint 13 (USBRXMAXP13), offset 0x1D4 ...................... 967
USB Maximum Receive Data Endpoint 14 (USBRXMAXP14), offset 0x1E4 ....................... 967
USB Maximum Receive Data Endpoint 15 (USBRXMAXP15), offset 0x1F4 ....................... 967
30
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 195:
Register 196:
Register 197:
Register 198:
Register 199:
Register 200:
Register 201:
Register 202:
Register 203:
Register 204:
Register 205:
Register 206:
Register 207:
Register 208:
Register 209:
Register 210:
Register 211:
Register 212:
Register 213:
Register 214:
Register 215:
Register 216:
Register 217:
Register 218:
Register 219:
Register 220:
Register 221:
Register 222:
Register 223:
Register 224:
Register 225:
Register 226:
Register 227:
Register 228:
Register 229:
Register 230:
Register 231:
Register 232:
Register 233:
Register 234:
Register 235:
Register 236:
Register 237:
Register 238:
Register 239:
Register 240:
Register 241:
Register 242:
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1), offset 0x116 ............... 969
USB Receive Control and Status Endpoint 2 Low (USBRXCSRL2), offset 0x126 ............... 969
USB Receive Control and Status Endpoint 3 Low (USBRXCSRL3), offset 0x136 ............... 969
USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ............... 969
USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ............... 969
USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ............... 969
USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............... 969
USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 ............... 969
USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 ............... 969
USB Receive Control and Status Endpoint 10 Low (USBRXCSRL10), offset 0x1A6 ........... 969
USB Receive Control and Status Endpoint 11 Low (USBRXCSRL11), offset 0x1B6 ........... 969
USB Receive Control and Status Endpoint 12 Low (USBRXCSRL12), offset 0x1C6 ........... 969
USB Receive Control and Status Endpoint 13 Low (USBRXCSRL13), offset 0x1D6 ........... 969
USB Receive Control and Status Endpoint 14 Low (USBRXCSRL14), offset 0x1E6 ........... 969
USB Receive Control and Status Endpoint 15 Low (USBRXCSRL15), offset 0x1F6 ........... 969
USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 .............. 974
USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 .............. 974
USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 .............. 974
USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 .............. 974
USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 .............. 974
USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 .............. 974
USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 .............. 974
USB Receive Control and Status Endpoint 8 High (USBRXCSRH8), offset 0x187 .............. 974
USB Receive Control and Status Endpoint 9 High (USBRXCSRH9), offset 0x197 .............. 974
USB Receive Control and Status Endpoint 10 High (USBRXCSRH10), offset 0x1A7 .......... 974
USB Receive Control and Status Endpoint 11 High (USBRXCSRH11), offset 0x1B7 .......... 974
USB Receive Control and Status Endpoint 12 High (USBRXCSRH12), offset 0x1C7 ......... 974
USB Receive Control and Status Endpoint 13 High (USBRXCSRH13), offset 0x1D7 ......... 974
USB Receive Control and Status Endpoint 14 High (USBRXCSRH14), offset 0x1E7 .......... 974
USB Receive Control and Status Endpoint 15 High (USBRXCSRH15), offset 0x1F7 .......... 974
USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 979
USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 979
USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 979
USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 .............................. 979
USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 .............................. 979
USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 .............................. 979
USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 .............................. 979
USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset 0x188 .............................. 979
USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset 0x198 .............................. 979
USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset 0x1A8 .......................... 979
USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset 0x1B8 ........................... 979
USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset 0x1C8 .......................... 979
USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset 0x1D8 .......................... 979
USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset 0x1E8 .......................... 979
USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset 0x1F8 .......................... 979
USB Host Transmit Configure Type Endpoint 1 (USBTXTYPE1), offset 0x11A ................... 981
USB Host Transmit Configure Type Endpoint 2 (USBTXTYPE2), offset 0x12A ................... 981
USB Host Transmit Configure Type Endpoint 3 (USBTXTYPE3), offset 0x13A ................... 981
June 14, 2010
31
Texas Instruments-Advance Information
Table of Contents
Register 243:
Register 244:
Register 245:
Register 246:
Register 247:
Register 248:
Register 249:
Register 250:
Register 251:
Register 252:
Register 253:
Register 254:
Register 255:
Register 256:
Register 257:
Register 258:
Register 259:
Register 260:
Register 261:
Register 262:
Register 263:
Register 264:
Register 265:
Register 266:
Register 267:
Register 268:
Register 269:
Register 270:
Register 271:
Register 272:
Register 273:
Register 274:
Register 275:
Register 276:
Register 277:
Register 278:
Register 279:
Register 280:
Register 281:
Register 282:
Register 283:
Register 284:
Register 285:
Register 286:
Register 287:
Register 288:
Register 289:
Register 290:
USB Host Transmit Configure Type Endpoint 4 (USBTXTYPE4), offset 0x14A ................... 981
USB Host Transmit Configure Type Endpoint 5 (USBTXTYPE5), offset 0x15A ................... 981
USB Host Transmit Configure Type Endpoint 6 (USBTXTYPE6), offset 0x16A ................... 981
USB Host Transmit Configure Type Endpoint 7 (USBTXTYPE7), offset 0x17A ................... 981
USB Host Transmit Configure Type Endpoint 8 (USBTXTYPE8), offset 0x18A ................... 981
USB Host Transmit Configure Type Endpoint 9 (USBTXTYPE9), offset 0x19A ................... 981
USB Host Transmit Configure Type Endpoint 10 (USBTXTYPE10), offset 0x1AA ............... 981
USB Host Transmit Configure Type Endpoint 11 (USBTXTYPE11), offset 0x1BA ............... 981
USB Host Transmit Configure Type Endpoint 12 (USBTXTYPE12), offset 0x1CA .............. 981
USB Host Transmit Configure Type Endpoint 13 (USBTXTYPE13), offset 0x1DA .............. 981
USB Host Transmit Configure Type Endpoint 14 (USBTXTYPE14), offset 0x1EA ............... 981
USB Host Transmit Configure Type Endpoint 15 (USBTXTYPE15), offset 0x1FA ............... 981
USB Host Transmit Interval Endpoint 1 (USBTXINTERVAL1), offset 0x11B ....................... 983
USB Host Transmit Interval Endpoint 2 (USBTXINTERVAL2), offset 0x12B ....................... 983
USB Host Transmit Interval Endpoint 3 (USBTXINTERVAL3), offset 0x13B ....................... 983
USB Host Transmit Interval Endpoint 4 (USBTXINTERVAL4), offset 0x14B ....................... 983
USB Host Transmit Interval Endpoint 5 (USBTXINTERVAL5), offset 0x15B ....................... 983
USB Host Transmit Interval Endpoint 6 (USBTXINTERVAL6), offset 0x16B ....................... 983
USB Host Transmit Interval Endpoint 7 (USBTXINTERVAL7), offset 0x17B ....................... 983
USB Host Transmit Interval Endpoint 8 (USBTXINTERVAL8), offset 0x18B ....................... 983
USB Host Transmit Interval Endpoint 9 (USBTXINTERVAL9), offset 0x19B ....................... 983
USB Host Transmit Interval Endpoint 10 (USBTXINTERVAL10), offset 0x1AB ................... 983
USB Host Transmit Interval Endpoint 11 (USBTXINTERVAL11), offset 0x1BB ................... 983
USB Host Transmit Interval Endpoint 12 (USBTXINTERVAL12), offset 0x1CB ................... 983
USB Host Transmit Interval Endpoint 13 (USBTXINTERVAL13), offset 0x1DB ................... 983
USB Host Transmit Interval Endpoint 14 (USBTXINTERVAL14), offset 0x1EB ................... 983
USB Host Transmit Interval Endpoint 15 (USBTXINTERVAL15), offset 0x1FB ................... 983
USB Host Configure Receive Type Endpoint 1 (USBRXTYPE1), offset 0x11C ................... 985
USB Host Configure Receive Type Endpoint 2 (USBRXTYPE2), offset 0x12C ................... 985
USB Host Configure Receive Type Endpoint 3 (USBRXTYPE3), offset 0x13C ................... 985
USB Host Configure Receive Type Endpoint 4 (USBRXTYPE4), offset 0x14C ................... 985
USB Host Configure Receive Type Endpoint 5 (USBRXTYPE5), offset 0x15C ................... 985
USB Host Configure Receive Type Endpoint 6 (USBRXTYPE6), offset 0x16C ................... 985
USB Host Configure Receive Type Endpoint 7 (USBRXTYPE7), offset 0x17C ................... 985
USB Host Configure Receive Type Endpoint 8 (USBRXTYPE8), offset 0x18C ................... 985
USB Host Configure Receive Type Endpoint 9 (USBRXTYPE9), offset 0x19C ................... 985
USB Host Configure Receive Type Endpoint 10 (USBRXTYPE10), offset 0x1AC ............... 985
USB Host Configure Receive Type Endpoint 11 (USBRXTYPE11), offset 0x1BC ............... 985
USB Host Configure Receive Type Endpoint 12 (USBRXTYPE12), offset 0x1CC ............... 985
USB Host Configure Receive Type Endpoint 13 (USBRXTYPE13), offset 0x1DC ............... 985
USB Host Configure Receive Type Endpoint 14 (USBRXTYPE14), offset 0x1EC ............... 985
USB Host Configure Receive Type Endpoint 15 (USBRXTYPE15), offset 0x1FC ............... 985
USB Host Receive Polling Interval Endpoint 1 (USBRXINTERVAL1), offset 0x11D ............. 987
USB Host Receive Polling Interval Endpoint 2 (USBRXINTERVAL2), offset 0x12D ............ 987
USB Host Receive Polling Interval Endpoint 3 (USBRXINTERVAL3), offset 0x13D ............ 987
USB Host Receive Polling Interval Endpoint 4 (USBRXINTERVAL4), offset 0x14D ............ 987
USB Host Receive Polling Interval Endpoint 5 (USBRXINTERVAL5), offset 0x15D ............ 987
USB Host Receive Polling Interval Endpoint 6 (USBRXINTERVAL6), offset 0x16D ............ 987
32
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 291:
Register 292:
Register 293:
Register 294:
Register 295:
Register 296:
Register 297:
Register 298:
Register 299:
Register 300:
Register 301:
Register 302:
Register 303:
Register 304:
Register 305:
Register 306:
Register 307:
Register 308:
Register 309:
Register 310:
Register 311:
Register 312:
Register 313:
Register 314:
Register 315:
Register 316:
Register 317:
Register 318:
Register 319:
Register 320:
Register 321:
Register 322:
Register 323:
Register 324:
USB Host Receive Polling Interval Endpoint 7 (USBRXINTERVAL7), offset 0x17D ............ 987
USB Host Receive Polling Interval Endpoint 8 (USBRXINTERVAL8), offset 0x18D ............ 987
USB Host Receive Polling Interval Endpoint 9 (USBRXINTERVAL9), offset 0x19D ............ 987
USB Host Receive Polling Interval Endpoint 10 (USBRXINTERVAL10), offset 0x1AD ........ 987
USB Host Receive Polling Interval Endpoint 11 (USBRXINTERVAL11), offset 0x1BD ......... 987
USB Host Receive Polling Interval Endpoint 12 (USBRXINTERVAL12), offset 0x1CD ........ 987
USB Host Receive Polling Interval Endpoint 13 (USBRXINTERVAL13), offset 0x1DD ........ 987
USB Host Receive Polling Interval Endpoint 14 (USBRXINTERVAL14), offset 0x1ED ........ 987
USB Host Receive Polling Interval Endpoint 15 (USBRXINTERVAL15), offset 0x1FD ........ 987
USB Request Packet Count in Block Transfer Endpoint 1 (USBRQPKTCOUNT1), offset
0x304 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 2 (USBRQPKTCOUNT2), offset
0x308 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 3 (USBRQPKTCOUNT3), offset
0x30C ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 4 (USBRQPKTCOUNT4), offset
0x310 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 5 (USBRQPKTCOUNT5), offset
0x314 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 6 (USBRQPKTCOUNT6), offset
0x318 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 7 (USBRQPKTCOUNT7), offset
0x31C ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 8 (USBRQPKTCOUNT8), offset
0x320 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 9 (USBRQPKTCOUNT9), offset
0x324 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 10 (USBRQPKTCOUNT10), offset
0x328 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 11 (USBRQPKTCOUNT11), offset
0x32C ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 12 (USBRQPKTCOUNT12), offset
0x330 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 13 (USBRQPKTCOUNT13), offset
0x334 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 14 (USBRQPKTCOUNT14), offset
0x338 ........................................................................................................................... 989
USB Request Packet Count in Block Transfer Endpoint 15 (USBRQPKTCOUNT15), offset
0x33C ........................................................................................................................... 989
USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 991
USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 993
USB External Power Control (USBEPC), offset 0x400 ...................................................... 995
USB External Power Control Raw Interrupt Status (USBEPCRIS), offset 0x404 ................. 998
USB External Power Control Interrupt Mask (USBEPCIM), offset 0x408 ............................ 999
USB External Power Control Interrupt Status and Clear (USBEPCISC), offset 0x40C ....... 1000
USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 .......................... 1001
USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ..................................... 1002
USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................. 1003
USB General-Purpose Control and Status (USBGPCS), offset 0x41C ............................. 1004
June 14, 2010
33
Texas Instruments-Advance Information
Table of Contents
Register 325:
Register 326:
Register 327:
Register 328:
Register 329:
Register 330:
Register 331:
Register 332:
USB VBUS Droop Control (USBVDC), offset 0x430 ....................................................... 1005
USB VBUS Droop Control Raw Interrupt Status (USBVDCRIS), offset 0x434 .................. 1006
USB VBUS Droop Control Interrupt Mask (USBVDCIM), offset 0x438 ............................. 1007
USB VBUS Droop Control Interrupt Status and Clear (USBVDCISC), offset 0x43C .......... 1008
USB ID Valid Detect Raw Interrupt Status (USBIDVRIS), offset 0x444 ............................. 1009
USB ID Valid Detect Interrupt Mask (USBIDVIM), offset 0x448 ........................................ 1010
USB ID Valid Detect Interrupt Status and Clear (USBIDVISC), offset 0x44C .................... 1011
USB DMA Select (USBDMASEL), offset 0x450 .............................................................. 1012
Analog Comparators ................................................................................................................. 1014
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1020
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1021
Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1022
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ..................... 1023
Analog Comparator Status 0 (ACSTAT0), offset 0x020 ................................................... 1024
Analog Comparator Status 1 (ACSTAT1), offset 0x040 ................................................... 1024
Analog Comparator Status 2 (ACSTAT2), offset 0x060 ................................................... 1024
Analog Comparator Control 0 (ACCTL0), offset 0x024 ................................................... 1025
Analog Comparator Control 1 (ACCTL1), offset 0x044 ................................................... 1025
Analog Comparator Control 2 (ACCTL2), offset 0x064 ................................................... 1025
Pulse Width Modulator (PWM) .................................................................................................. 1027
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
PWM Master Control (PWMCTL), offset 0x000 .............................................................. 1042
PWM Time Base Sync (PWMSYNC), offset 0x004 ......................................................... 1044
PWM Output Enable (PWMENABLE), offset 0x008 ........................................................ 1045
PWM Output Inversion (PWMINVERT), offset 0x00C ..................................................... 1047
PWM Output Fault (PWMFAULT), offset 0x010 .............................................................. 1049
PWM Interrupt Enable (PWMINTEN), offset 0x014 ......................................................... 1051
PWM Raw Interrupt Status (PWMRIS), offset 0x018 ...................................................... 1053
PWM Interrupt Status and Clear (PWMISC), offset 0x01C .............................................. 1056
PWM Status (PWMSTATUS), offset 0x020 .................................................................... 1059
PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ........................................... 1061
PWM Enable Update (PWMENUPD), offset 0x028 ......................................................... 1063
PWM0 Control (PWM0CTL), offset 0x040 ..................................................................... 1067
PWM1 Control (PWM1CTL), offset 0x080 ..................................................................... 1067
PWM2 Control (PWM2CTL), offset 0x0C0 .................................................................... 1067
PWM3 Control (PWM3CTL), offset 0x100 ...................................................................... 1067
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................. 1072
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................. 1072
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................. 1072
PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104 ................................... 1072
PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................. 1075
PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................. 1075
PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................. 1075
PWM3 Raw Interrupt Status (PWM3RIS), offset 0x108 ................................................... 1075
PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ......................................... 1077
PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ......................................... 1077
PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ......................................... 1077
PWM3 Interrupt Status and Clear (PWM3ISC), offset 0x10C .......................................... 1077
PWM0 Load (PWM0LOAD), offset 0x050 ..................................................................... 1079
34
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Register 55:
Register 56:
Register 57:
Register 58:
Register 59:
Register 60:
Register 61:
Register 62:
Register 63:
Register 64:
Register 65:
Register 66:
Register 67:
Register 68:
Register 69:
Register 70:
Register 71:
Register 72:
Register 73:
Register 74:
Register 75:
Register 76:
PWM1 Load (PWM1LOAD), offset 0x090 ..................................................................... 1079
PWM2 Load (PWM2LOAD), offset 0x0D0 ..................................................................... 1079
PWM3 Load (PWM3LOAD), offset 0x110 ...................................................................... 1079
PWM0 Counter (PWM0COUNT), offset 0x054 .............................................................. 1080
PWM1 Counter (PWM1COUNT), offset 0x094 .............................................................. 1080
PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................. 1080
PWM3 Counter (PWM3COUNT), offset 0x114 ............................................................... 1080
PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................ 1081
PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................ 1081
PWM2 Compare A (PWM2CMPA), offset 0x0D8 ........................................................... 1081
PWM3 Compare A (PWM3CMPA), offset 0x118 ............................................................. 1081
PWM0 Compare B (PWM0CMPB), offset 0x05C ........................................................... 1082
PWM1 Compare B (PWM1CMPB), offset 0x09C ........................................................... 1082
PWM2 Compare B (PWM2CMPB), offset 0x0DC .......................................................... 1082
PWM3 Compare B (PWM3CMPB), offset 0x11C ............................................................ 1082
PWM0 Generator A Control (PWM0GENA), offset 0x060 .............................................. 1083
PWM1 Generator A Control (PWM1GENA), offset 0x0A0 .............................................. 1083
PWM2 Generator A Control (PWM2GENA), offset 0x0E0 .............................................. 1083
PWM3 Generator A Control (PWM3GENA), offset 0x120 ............................................... 1083
PWM0 Generator B Control (PWM0GENB), offset 0x064 .............................................. 1086
PWM1 Generator B Control (PWM1GENB), offset 0x0A4 .............................................. 1086
PWM2 Generator B Control (PWM2GENB), offset 0x0E4 .............................................. 1086
PWM3 Generator B Control (PWM3GENB), offset 0x124 ............................................... 1086
PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 .............................................. 1089
PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ............................................... 1089
PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 .............................................. 1089
PWM3 Dead-Band Control (PWM3DBCTL), offset 0x128 ............................................... 1089
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ........................... 1090
PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ........................... 1090
PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ........................... 1090
PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset 0x12C ............................ 1090
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ........................... 1091
PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ........................... 1091
PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ........................... 1091
PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset 0x130 ............................ 1091
PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074 .................................................. 1092
PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4 .................................................. 1092
PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4 .................................................. 1092
PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134 .................................................. 1092
PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078 .................................................. 1094
PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8 .................................................. 1094
PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8 .................................................. 1094
PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138 .................................................. 1094
PWM0 Minimum Fault Period (PWM0MINFLTPER), offset 0x07C ................................... 1097
PWM1 Minimum Fault Period (PWM1MINFLTPER), offset 0x0BC ................................... 1097
PWM2 Minimum Fault Period (PWM2MINFLTPER), offset 0x0FC ................................... 1097
PWM3 Minimum Fault Period (PWM3MINFLTPER), offset 0x13C ................................... 1097
PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800 .......................................... 1098
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Table of Contents
Register 77:
Register 78:
Register 79:
Register 80:
Register 81:
Register 82:
Register 83:
Register 84:
Register 85:
Register 86:
Register 87:
PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880 ..........................................
PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900 ..........................................
PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980 ..........................................
PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804 ...................................................
PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884 ...................................................
PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904 ...................................................
PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984 ...................................................
PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808 ...................................................
PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888 ...................................................
PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908 ...................................................
PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988 ...................................................
1098
1098
1098
1099
1099
1099
1099
1101
1101
1101
1101
Quadrature Encoder Interface (QEI) ........................................................................................ 1104
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
QEI Control (QEICTL), offset 0x000 ..............................................................................
QEI Status (QEISTAT), offset 0x004 ..............................................................................
QEI Position (QEIPOS), offset 0x008 ............................................................................
QEI Maximum Position (QEIMAXPOS), offset 0x00C .....................................................
QEI Timer Load (QEILOAD), offset 0x010 .....................................................................
QEI Timer (QEITIME), offset 0x014 ...............................................................................
QEI Velocity Counter (QEICOUNT), offset 0x018 ...........................................................
QEI Velocity (QEISPEED), offset 0x01C ........................................................................
QEI Interrupt Enable (QEIINTEN), offset 0x020 .............................................................
QEI Raw Interrupt Status (QEIRIS), offset 0x024 ...........................................................
QEI Interrupt Status and Clear (QEIISC), offset 0x028 ...................................................
36
1111
1114
1115
1116
1117
1118
1119
1120
1121
1123
1125
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S9B95
data sheet.
Table 1. Revision History
Date
Revision
June 2010
7299
May 2010
May 2010
March 2010
March 2010
7164
7101
6983
6912
Description
■
Changed memory map ending address for EPI0 mapped peripheral and RAM from 0xCFFF.FFFF
to 0xDFFF.FFFF.
■
Removed 4.194304-MHz crystal as a source for the system clock and PLL.
■
Summarized ROM contents descriptions in the "Internal Memory" chapter and removed various
ROM appendices.
■
Clarified DMA channel terminology: changed name of DMA Channel Alternate Select (DMACHALT)
register to DMA Channel Assignment (DMACHASGN) register, changed CHALT bit field to CHASGN,
and changed terminology from primary and alternate channels to primary and secondary channels.
■
Clarified EPI Main Baud Rate (EPIBAUD) equation.
■
In Signal Tables chapter, added table "Connections for Unused Signals."
■
In "Electrical Characteristics" chapter:
–
In "Reset Characteristics" table, corrected Supply voltage (VDD) rise time.
–
Clarified figure "SDRAM Initialization and Load Mode Register Timing".
–
Added BSEL0n/BSEL1n to EPI timing diagrams.
■
Removed 100-MHz from LM3S9B95 as that is no longer an orderable part. This device is only
available in 80-MHz.
■
Added data sheets for five new Stellaris® Tempest-class parts: LM3S1R26, LM3S1621, LM3S1B21,
LM3S9781, and LM3S9B81.
■
Additional minor data sheet clarifications and corrections.
■
Added pin table "Possible Pin Assignments for Alternate Functions", which lists the signals based
on number of possible pin assignments. This table can be used to plan how to configure the pins
for a particular functionality.
■
Additional minor data sheet clarifications and corrections.
■
Corrected reset for EPIHB8CFG, EPI_HB16CFG and EPIGPCFG registers.
■
Extended TBRL bit field in GPTMTBR register.
■
Additional minor data sheet clarifications and corrections.
■
Renamed the USER_DBG register to the BOOTCFG register in the Internal Memory chapter. Added
information on how to use a GPIO pin to force the ROM Boot Loader to execute on reset.
■
Added three figures to the ADC chapter on sample phase control.
■
Clarified configuration of USB0VBUS and USB0ID in OTG mode.
June 14, 2010
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Texas Instruments-Advance Information
Revision History
Table 1. Revision History (continued)
Date
Revision
February 2010
6790
Description
■
Added 108-ball BGA package.
■
In "System Control" chapter:
– Clarified functional description for external reset and brown-out reset.
– Clarified Debug Access Port operation after Sleep modes.
– Corrected the reset value of the Run-Mode Clock Configuration 2 (RCC2) register.
■
In "Internal Memory" chapter, clarified wording on Flash memory access errors and added a section
on interrupts to the Flash memory description.
■
In "External Peripheral Interface" chapter:
– Added clarification about byte selects and dual chip selects.
– Added timing diagrams for continuous-read mode (formerly SRAM mode).
– Corrected reset values of EPI Write FIFO Count (EPIWFIFOCNT) and EPI Raw Interrupt
Status (EPIRIS) registers.
■
Added clarification about timer operating modes and added register descriptions for the GPTM
Timer n Prescale Match (GPTMTnPMR) registers.
■
Clarified register descriptions for GPTM Timer A Value (GPTMTAV) and GPTM Timer B Value
(GPTMTBV) registers.
■
Corrected the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers.
■
Added ADC Sample Phase Control (ADCSPC) register at offset 0x24.
■
Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■
In the "Controller Area Network" chapter, added clarification about reading from the CAN FIFO
buffer and clarified packet timestamps functional description.
■
In the "Ethernet Controller" chapter:
– Corrected the reset value and the LED1 bit positions of the Ethernet MAC LED Encoding
(MACLED) register.
– Added clarification about the use of the NPR field in the Ethernet MAC Number of Packets
(MACNP) register.
– Corrected reset values for Ethernet PHY Management Register 0 – Control (MR0) and
Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5) registers.
■
Added Session Disconnect (DISCON) bit to the USB General Interrupt Status (USBIS) and
USB Interrupt Enable (USBIE) registers.
■
Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■
Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
– Modified the preliminary current consumption specification for Run mode 1 and Deep-Sleep
mode.
– Added table entry for VDD3ON power consumption to Table 27-8 on page 1207.
■
Added additional DriverLib functions to appendix.
38
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Stellaris® LM3S9B95 Microcontroller
Table 1. Revision History (continued)
Date
Revision
October 2009
6458
Description
®
■
Released new 1000, 3000, 5000 and 9000 series Stellaris devices.
■
The IDCODE value was corrected to be 0x4BA0.0477.
■
Clarified that the NMISET bit in the ICSR register in the NVIC is also a source for NMI.
■
Clarified the use of the LDO.
■
To clarify clock operation, reorganized clocking section, changed the USEFRACT bit to the DIV400
bit and the FRACT bit to the SYSDIV2LSB bit in the RCC2 register, added tables, and rewrote
descriptions.
■
Corrected bit description of the DSDIVORIDE field in the DSLPCLKCFG register.
■
Removed the DSFLASHCFG register at System Control offset 0x14C as it does not function correctly.
■
Removed the MAXADC1SPD and MAXADC0SPD fields from the DCGC0 as they have no function in
deep-sleep mode.
■
Corrected address offsets for the Flash Write Buffer (FWBn) registers.
■
Added Flash Control (FCTL) register at Internal memory offset 0x0F8 to help control frequent
power cycling when hibernation is not used.
■
Changed the name of the EPI channels for clarification: EPI0_TX became EPI0_WFIFO and EPI0_RX
became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions.
■
Removed the DMACHIS register at DMA module offset 0x504 as it does not function correctly.
■
Corrected alternate channel assignments for the µDMA controller.
■
Major improvements to the EPI chapter.
■
EPISDRAMCFG2 register was deleted as its function is not needed.
■
Clarified CAN bit timing and corrected examples.
■
Added pseudo-code for MDI/MDIX operation.
■
Corrected reset value of the MR1 register to 0x7809.
■
Clarified PWM source for ADC triggering
■
Corrected ADDR field in the USBTXFIFOADD register to be 9 bits instead of 13 bits.
■
Changed SSI set up and hold times to be expressed in system clocks, not ns.
■
Updated Electrical Characteristics chapter with latest data. Changes were made to ADC and EPI
content.
■
Additional minor data sheet clarifications and corrections.
June 14, 2010
39
Texas Instruments-Advance Information
Revision History
Table 1. Revision History (continued)
Date
Revision
July 2009
5930
Description
■
Added "Non-Blocking Read Cycle", "Normal Read Cycle", and "Write Cycle" sections to EPI chapter.
■
Corrected values for MAXADC0SPD and MAXADC1SPD bits in DC1, RCGC0, SCGC0, and DCGC0
registers.
■
Corrected figure "TI Synchronous Serial Frame Format (Single Transfer)".
■
Added description for Ethernet PHY power-saving modes.
■
Made a number of corrections to the Electrical Characteristics chapter:
–
Deleted VBAT and VREFA parameters from and added footnotes to Recommended DC Operating
Conditions table.
–
Deleted Nominal and Maximum Current Specifications section.
–
Modified EPI SDRAM Characteristics table:
•
Changed tEPIR to tSDRAMR and deleted values for 2-mA and 4-mA drive.
•
Changed tEPIF to tSDRAMF and deleted values for 2-mA and 4-mA drive.
–
Changed values for tCOV, tCOI, and tCOT parameters in EPI SDRAM Interface Characteristics
table.
–
Deleted SDRAM Read Command Timing, SDRAM Write Command Timing, SDRAM Write Burst
Timing, SDRAM Precharge Command Timing and SDRAM CAS Latency Timing figures and
replaced with SDRAM Read Timing and SDRAM Write Timing figures.
–
Modified Host-Bus 8/16 Mode Write Timing figure.
–
Modified General-Purpose Mode Read and Write Timing figure.
–
Modified values for tDV and tDI parameters, and deleted tOD parameter from EPI General-Purpose
Interface Characteristics figure.
–
Major changes to ADC Characteristics tables, including adding additonal tables and diagram.
■
Added missing ROM_I2SIntStatus function to ROM DriverLib Functions appendix.
■
Corrected ordering part numbers.
■
Additional minor data sheet clarifications and corrections.
40
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Table 1. Revision History (continued)
Date
Revision
June 2009
5779
May 2009
5285
Description
■
In System Control chapter, clarified power-on reset and external reset pin descriptions in "Reset
Sources" section.
■
Added missing comparator output pin bits to DC3 register; reset value changed as well.
■
Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■
Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0
registers.
■
In Request Type Support table in DMA chapter, corrected general-purpose timer row.
■
In General-Purpose Timers chapter, clarified DMA operation.
■
Added table "Preliminary Current Consumption" to Characteristics chapter.
■
Corrected Nom and Max values in EPI Characteristics table.
■
Added "CSn to output invalid" parameter to EPI table "EPI Host-Bus 8 and Host-Bus 16 Interface
Characteristics" and figure "Host-Bus 8/16 Mode Read Timing".
■
Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table.
■
Updated ROM DriverLib appendix with RevC0 functions.
■
Updated part ordering numbers.
■
Additional minor data sheet clarifications and corrections.
Started tracking revision history.
June 14, 2010
41
Texas Instruments-Advance Information
About This Document
About This Document
This data sheet provides reference information for the LM3S9B95 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
®
The following related documents are available on the documentation CD or from the Stellaris web
site at www.ti.com/stellaris:
■ Stellaris® Errata
■ ARM® Cortex™-M3 Errata
■ ARM® CoreSight Technical Reference Manual
■ ARM® Cortex™-M3 Technical Reference Manual
■ ARM® v7-M Architecture Application Level Reference Manual
■ Stellaris® Boot Loader User's Guide
■ Stellaris® Graphics Library User's Guide
■ Stellaris® Peripheral Driver Library User's Guide
■ Stellaris® ROM User’s Guide
■ Stellaris® USB Library User's Guide
The following related documents are also referenced:
■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
42
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Documentation Conventions
This document uses the conventions shown in Table 2 on page 43.
Table 2. Documentation Conventions
Notation
Meaning
General Register Notation
REGISTER
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
bit
A single bit in a register.
bit field
Two or more consecutive and related bits.
offset 0xnnn
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 83.
Register N
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
reserved
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
yy:xx
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
Register Bit/Field
Types
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
RC
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO
Software can read this field. Always write the chip reset value.
R/W
Software can read or write this field.
R/W1C
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
R/W1S
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
W1C
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
WO
Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field
Reset Value
This value in the register bit diagram shows the bit/field value after any reset, unless noted.
0
Bit cleared to 0 on chip reset.
1
Bit set to 1 on chip reset.
-
Nondeterministic.
Pin/Signal Notation
[]
Pin alternate function; a pin defaults to the signal without the brackets.
pin
Refers to the physical connection on the package.
signal
Refers to the electrical signal encoding of a pin.
June 14, 2010
43
Texas Instruments-Advance Information
About This Document
Table 2. Documentation Conventions (continued)
Notation
Meaning
assert a signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
deassert a signal
Change the value of the signal from the logically True state to the logically False state.
SIGNAL
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
SIGNAL
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
Numbers
X
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
44
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
1
Architectural Overview
Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM®
Cortex-M3™-based microcontrollers to the broadest reach of the microcontroller market. For current
®
users of 8- and 16-bit MCUs, Stellaris with Cortex-M3 offers a direct path to the strongest ecosystem
®
of development tools, software and knowledge in the industry. Designers who migrate to Stellaris
benefit from great tools, small code footprint and outstanding performance. Even more important,
designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to
®
1 GHz. For users of current 32-bit MCUs, the Stellaris family offers the industry’s first implementation
of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2
technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density
and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system
®
cost while delivering 25 percent better performance. The Texas Instruments Stellaris family of
microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit
computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver
customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package
with a small footprint.
The LM3S9B95 microcontroller has the following features:
■ ARM® Cortex™-M3 Processor Core
– 80-MHz operation; 100 DMIPS performance
– ARM Cortex SysTick Timer
– Nested Vectored Interrupt Controller (NVIC)
■ On-Chip Memory
– 256 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance
above 50 MHz
– 96 KB single-cycle SRAM
®
– Internal ROM loaded with StellarisWare software:
®
•
Stellaris Peripheral Driver Library
•
Stellaris Boot Loader
•
Advanced Encryption Standard (AES) cryptography tables
•
Cyclic Redundancy Check (CRC) error detection functionality
®
■ External Peripheral Interface (EPI)
– 8/16/32-bit dedicated parallel bus for external peripherals
– Supports SDRAM, SRAM/Flash memory, FPGAs, CPLDs
■ Advanced Serial Integration
– 10/100 Ethernet MAC and PHY with IEEE 1588 PTP hardware support
June 14, 2010
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Texas Instruments-Advance Information
Architectural Overview
– Two CAN 2.0 A/B controllers
– USB 2.0 OTG/Host/Device
– Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls)
– Two I2C modules
– Two Synchronous Serial Interface modules (SSI)
– Integrated Interchip Sound (I2S) module
■ System Integration
– Direct Memory Access Controller (DMA)
– System control and clocks including on-chip precision 16-MHz oscillator
– Four 32-bit timers (up to eight 16-bit)
– Eight Capture Compare PWM pins (CCP)
– Real-Time Clock
– Two Watchdog Timers
•
One timer runs off the main oscillator
•
One timer runs off the precision internal oscillator
– Up to 65 GPIOs, depending on configuration
•
Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
•
Independently configurable to 2, 4 or 8 mA drive capability
•
Up to 4 GPIOs can have 18 mA drive capability
■ Advanced Motion Control
– Eight advanced PWM outputs for motion and energy applications
– Four fault inputs to promote low-latency shutdown
– Two Quadrature Encoder Inputs (QEI)
■ Analog
– Two 10-bit Analog-to-Digital Converters (ADC) with sixteen analog input channels and sample
rate of one million samples/second
– Three analog comparators
– 16 digital comparators
– On-chip voltage regulator
46
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
■ JTAG and ARM Serial Wire Debug (SWD)
■ 100-pin LQFP and 108-ball BGA package
■ Industrial (-40°C to 85°C) Temperature Range
The LM3S9B95 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S9B95 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S9B95 microcontroller is code-compatible
®
to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
®
Information” on page 1276 for ordering information for Stellaris family devices.
1.1
Functional Overview
The following sections provide an overview of the features of the LM3S9B95 microcontroller. The
page number in parentheses indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 1276.
1.1.1
ARM Cortex™-M3
The following sections provide an overview of the ARM Cortex™-M3 processor core and instruction
set, the integrated System Timer (SysTick) and the Nested Vectored Interrupt Controller.
1.1.1.1
Processor Core (see page 70)
®
All members of the Stellaris product family, including the LM3S9B95 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
■ 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set, delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices; typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
June 14, 2010
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Texas Instruments-Advance Information
Architectural Overview
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast multiplier
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
■ 80-MHz operation
■ 1.25 DMIPS/MHz
“ARM Cortex-M3 Processor Core” on page 70 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.1.1.2
System Timer (SysTick) (see page 80)
ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter
■ A simple counter used to measure time to completion and time used
■ An internal clock-source control based on missing/meeting durations. The COUNTFLAG field in
the SysTick Control and Status register can be used to determine if an action completed within
a set duration, as part of a dynamic clock management control loop
1.1.1.3
Nested Vectored Interrupt Controller (NVIC) (see page 86)
The LM3S9B95 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC
and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is
automatically stored to the stack on an exception and automatically restored from the stack at the
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end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state
saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 53 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
“Interrupts” on page 86 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.1.2
On-Chip Memory
The following sections describe the on-chip memory modules.
1.1.2.1
SRAM (see page 210)
The LM3S9B95 microcontroller provides 96 KB of single-cycle on-chip SRAM. The internal SRAM
®
of the Stellaris devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
1.1.2.2
Flash Memory (see page 212)
The LM3S9B95 microcontroller provides 256 KB of single-cycle on-chip Flash memory (above 50
MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches
incur a one-cycle stall). The Flash memory is organized as a set of 2-KB blocks that can be
individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s.
These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can
be marked as read-only or execute-only, providing different levels of code protection. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified.
Execute-only blocks cannot be erased or programmed, and can only be read by the controller
instruction fetch mechanism, protecting the contents of those blocks from being read by either the
controller or by a debugger.
1.1.2.3
ROM (see page 210)
The LM3S9B95 ROM is preprogrammed with the following software and programs:
®
■ Stellaris Peripheral Driver Library
®
■ Stellaris Boot Loader
■ Advanced Encryption Standard (AES) cryptography tables
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■ Cyclic Redundancy Check (CRC) error-detection functionality
®
The Stellaris Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM® Cortex™-M3
core. No special pragmas or custom assembly code prologue/epilogue functions are required. For
®
applications that require in-field programmability, the royalty-free Stellaris Boot Loader can act as
an application loader and support in-field firmware updates.
The Advanced Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government. AES is a strong encryption method with reasonable performance and size. In
addition, it is fast in both hardware and software, is fairly easy to implement, and requires little
memory. The Texas Instruments encryption package is available with full source code, and is based
on lesser general public license (LGPL) source. An LGPL means that the code can be used within
an application without any copyleft implications for the application (the code does not automatically
become open source). Modifications to the package source, however, must be open source.
CRC (Cyclic Redundancy Check) is a technique to validate a span of data has the same contents
as when previously checked. This technique can be used to validate correct receipt of messages
(nothing lost or modified in transit), to validate data after decompression, to validate that Flash
memory contents have not been changed, and for other cases where the data needs to be validated.
A CRC is preferred over a simple checksum (e.g. XOR all bits) because it catches changes more
readily.
1.1.3
External Peripheral Interface (see page 360)
The External Peripheral Interface (EPI) provides access to external devices using a parallel path.
Unlike communications peripherals such as SSI, UART, and I2C, the EPI is designed to act like a
bus to external peripherals and memory.
The EPI has the following features:
■ 8/16/32-bit dedicated parallel bus for external peripherals and memory
■ Memory interface supports contiguous memory access independent of data bus width, thus
enabling code execution directly from SDRAM, SRAM and Flash memory
■ Blocking and non-blocking reads
■ Separates processor from timing details through use of an internal write FIFO
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for read and write
– Read channel request asserted by programmable levels on the internal non-blocking read
FIFO (NBRFIFO)
– Write channel request asserted by empty on the internal write FIFO (WFIFO)
The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory
(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also
provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same
way as a communication mechanism and is speed-controlled using clocking.
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■ Synchronous Dynamic Random Access Memory (SDRAM)
– Supports x16 (single data rate) SDRAM at up to 50 MHz
– Supports low-cost SDRAMs up to 64 MB (512 megabits)
– Includes automatic refresh and access to all banks/rows
– Includes a Sleep/Standby mode to keep contents active with minimal power draw
– Multiplexed address/data interface for reduced pin count
■ Host-bus
– Traditional x8 and x16 MCU bus interface capabilities
– Similar device compatibility options as PIC, ATmega, 8051, and others
– Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
no byte selects)
– Support of both muxed and de-muxed address and data
– Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
– Speed controlled, with read and write data wait-state counters
– Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn
– Manual chip-enable (or use extra address pins)
■ General Purpose
– Wide parallel interfaces for fast communications with CPLDs and FPGAs
– Data widths up to 32-bits
– Data rates up to 150 MB/second
– Optional “address” sizes from 4 bits to 20 bits
– Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input
■ General parallel GPIO
– 1 to 32 bits, FIFOed with speed control
– Useful for custom peripherals or for digital data acquisition and actuator controls
1.1.4
Serial Communications Peripherals
The LM3S9B95 controller supports both asynchronous and synchronous serial communications
with:
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■ 10/100 Ethernet MAC and PHY with IEEE 1588 PTP hardware support
■ Two CAN 2.0 A/B Controllers
■ USB 2.0 (full speed and low speed) OTG/Host/Device
■ Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls)
■ Two I2C modules
■ Two Synchronous Serial Interface modules (SSI)
■ Integrated Interchip Sound (I2S) Module
The following sections provide more detail on each of these communications functions.
1.1.4.1
Ethernet Controller (see page 814)
Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet
has been standardized as IEEE 802.3. This specification defines a number of wiring and signaling
standards for the physical layer, two means of network access at the Media Access Control
(MAC)/Data Link Layer, and a common addressing format.
®
The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and
network physical (PHY) interface and has the following features:
■ Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer
interface to the line
– 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler
– Full-featured auto-negotiation
■ Multiple operational modes
– Full- and half-duplex 100 Mbps
– Full- and half-duplex 10 Mbps
– Power-saving and power-down modes
■ Highly configurable
– Programmable MAC address
– LED activity selection
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
■ Physical media manipulation
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– MDI/MDI-X cross-over support through software assist
– Register-programmable transmit amplitude
– Automatic polarity correction and 10BASE-T signal reception
■ IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive channel request asserted on packet receipt
– Transmit channel request asserted on empty transmit FIFO
1.1.4.2
Controller Area Network (see page 762)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
environments and can utilize a differential balanced line like RS-485 or twisted-pair wire. Originally
created for automotive purposes, it is now used in many embedded control applications (for example,
industrial or medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters.
Decreased bit rates allow longer network distances (for example, 125 Kbps at 500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information.
The LM3S9B95 microcontroller includes two CAN units with the following features:
■ CAN protocol version 2.0 part A/B
■ Bit rates up to 1 Mbps
■ 32 message objects with individual identifier masks
■ Maskable interrupt
■ Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications
■ Programmable Loopback mode for self-test operation
■ Programmable FIFO mode enables storage of multiple message objects
■ Gluelessly attaches to an external CAN transceiver through the CANnTX and CANnRX signals
1.1.4.3
USB (see page 875)
Universal Serial Bus (USB) is a serial bus standard designed to allow peripherals to be connected
and disconnected using a standardized interface without rebooting the system.
The LM3S9B95 controller supports three configurations in USB 2.0 full and low speed: USB Device,
USB Host, and USB On-The-Go (negotiated on-the-go as host or device when connected to other
USB-enabled systems).
The USB module has the following features:
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■ Complies with USB-IF certification standards
■ USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
■ Integrated PHY
■ 4 transfer types: Control, Interrupt, Bulk, and Isochronous
■ 32 endpoints
– 1 dedicated control IN endpoint and 1 dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
■ 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-byte
isochronous packet size
■ VBUS droop and valid ID detection and interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive for up to three IN endpoints and three OUT
endpoints
– Channel requests asserted when FIFO contains required amount of data
1.1.4.4
UART (see page 584)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S9B95 controller includes three fully programmable 16C550-type UARTs. Although the
functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART
can generate individually masked interrupts from the Rx, Tx, modem status, and error conditions.
The module generates a single combined interrupt when any of the interrupts are asserted and are
unmasked.
The three UARTs have the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ False-start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
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– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Full modem handshake support (on UART1)
■ LIN protocol support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
1.1.4.5
I2C (see page 688)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
Each device on the I2C bus can be designated as either a master or a slave. Each I2C module
supports both sending and receiving data as either a master or a slave and can operate
simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts.
The LM3S9B95 controller includes two I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
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– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
1.1.4.6
SSI (see page 646)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The LM3S9B95 controller includes two SSI modules with the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
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– Transmit single request asserted when there is space in the FIFO; burst request asserted
when FIFO contains 4 entries
1.1.4.7
Inter-Integrated Circuit Sound (I2S) Interface (see page 725)
The I2S interface is a configurable serial audio core that contains a transmit module and a receive
module. The module is configurable for the I2S as well as Left-Justified and Right-Justified serial
audio formats. Data can be in one of four modes: Stereo, Mono, Compact 16-bit Stereo and Compact
8-Bit Stereo.
The transmit and receive modules each have an 8-entry audio-sample FIFO. An audio sample can
consist of a Left and Right Stereo sample, a Mono sample, or a Left and Right Compact Stereo
sample. In Compact 16-Bit Stereo, each FIFO entry contains both the 16-bit left and 16-bit right
samples, allowing efficient data transfers and requiring less memory space. In Compact 8-bit Stereo,
each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements
further.
Both the transmitter and receiver are capable of being a master or a slave.
®
The Stellaris I2S interface has the following features:
■ Configurable audio format supporting I2S, Left-justification, and Right-justification
■ Configurable sample size from 8 to 32 bits
■ Mono and Stereo support
■ 8-, 16-, and 32-bit FIFO interface for packing memory
■ Independent transmit and receive 8-entry FIFOs
■ Configurable FIFO-level interrupt and µDMA requests
■ Independent transmit and receive MCLK direction control
■ Transmit and receive internal MCLK sources
■ Independent transmit and receive control for serial clock and word select
■ MCLK and SCLK can be independently set to master or slave
■ Configurable transmit zero or last sample when FIFO empty
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Burst requests
– Channel requests asserted when FIFO contains required amount of data
1.1.5
System Integration
The LM3S9B95 controller provides a variety of standard system functions integrated into the device,
including:
■ Micro Direct Memory Access Controller (µDMA)
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■ System control and clocks including on-chip precision 16-MHz oscillator
■ ARM Cortex SysTick Timer
■ Four 32-bit timers (up to eight 16-bit)
■ Eight Capture Compare PWM pins (CCP)
■ Real-Time Clock
■ Two Watchdog Timers
■ Up to 65 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2, 4 or 8 mA drive capability
– Up to 4 GPIOs can have 18 mA drive capability
The following sections provide more detail on each of these functions.
1.1.5.1
Direct Memory Access (see page 246)
The LM3S9B95 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
■ ARM PrimeCell® 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules: GP Timer, USB, UART, Ethernet, ADC,
EPI, SSI, I2S
– Primary and secondary channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable bus arbitration scheme
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– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
1.1.5.2
System Control and Clocks (see page 101)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on
■ Power control
– On-chip fixed Low Drop-Out (LDO) voltage regulator
– Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating
– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Multiple clock sources for microcontroller system clock
– Precision Oscillator (PIOSC): on-chip resource providing a 16 MHz ±1% frequency at room
temperature
•
16 MHz ±3% across temperature
•
Software power down control for low power modes
– Main Oscillator (MOSC): a frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
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•
External oscillator used with or without on-chip PLL: select supported frequencies from 1
MHz to 16.384 MHz.
•
External crystal: from DC to maximum device speed
– Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during
power-saving modes
■ Flexible reset sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out reset (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– MOSC failure
1.1.5.3
Four Programmable Timers (see page 433)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently
as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time
Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions.
The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional
options:
■ Count up or down
■ 16- or 32-bit programmable one-shot timer
■ 16- or 32-bit programmable periodic timer
■ 16-bit general-purpose timer with an 8-bit prescaler
■ 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
■ Eight Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ ADC event trigger
■ User-enabled stalling when the controller asserts CPU Halt flag during debug (excluding RTC
mode)
■ 16-bit input-edge count- or time-capture modes
■ 16-bit PWM mode with software-programmable output inversion of the PWM signal
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine.
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■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.1.5.4
CCP Pins (see page 440)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The LM3S9B95 microcontroller includes eight Capture Compare PWM pins (CCP) that can be
programmed to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.1.5.5
Watchdog Timers (see page 481)
A watchdog timer is used to regain control when a system has failed due to a software error or to
®
the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer
can generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog
Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the controller on
its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer
has been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The LM3S9B95 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the
®
system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris
Watchdog Timer module has the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.1.5.6
Programmable GPIOs (see page 304)
®
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris
GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO
port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time
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Microcontrollers specification) and supports 0-65 programmable input/output pins. The number of
GPIOs available depends on the peripherals being used (see “Signal Tables” on page 1129 for the
signals available to each GPIO pin).
■ Up to 65 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant input/outputs
■ Fast toggle capable of a change every two clock cycles
■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility
with existing code
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
1.1.6
Advanced Motion Control
The LM3S9B95 controller provides motion control functions integrated into the device, including:
■ Eight advanced PWM outputs for motion and energy applications
■ Four fault input to promote low-latency shutdown
■ Two Quadrature Encoder Inputs (QEI)
The following provides more detail on these motion control functions.
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Stellaris® LM3S9B95 Microcontroller
1.1.6.1
PWM (see page 1027)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control. The LM3S9B95 PWM module consists of four PWM generator blocks and a
control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two
comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. PWM generator block has
the following features:
■ Four fault-condition handling input to quickly provide low-latency shutdown and prevent damage
to the motor being controlled
■ One 16-bit counter
– Runs in Down or Up/Down mode
– Output frequency controlled by a 16-bit load value
– Load value updates can be synchronized
– Produces output signals at zero and load value
■ Two PWM comparators
– Comparator value updates can be synchronized
– Produces output signals on match
■ PWM signal generator
– Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
– Produces two independent PWM signals
■ Dead-band generator
– Produces two PWM signals with programmable dead-band delays suitable for driving a half-H
bridge
– Can be bypassed, leaving input PWM signals unmodified
■ Can initiate an ADC sample sequence
The control block determines the polarity of the PWM signals and which signals are passed through
to the pins. The output of the PWM generation blocks are managed by the output control block
before being passed to the device pins. The PWM control block has the following options:
■ PWM output enable of each PWM signal
■ Optional output inversion of each PWM signal (polarity control)
■ Optional fault handling for each PWM signal
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■ Synchronization of timers in the PWM generator blocks
■ Synchronization of timer/comparator updates across the PWM generator blocks
■ Synchronization of PWM output enables across the PWM generator blocks
■ Interrupt status summary of the PWM generator blocks
■ Extended fault capabilities with multiple fault signals, programmable polarities, and filtering
■ PWM generators can be operated independently or synchronized with other generators
1.1.6.2
QEI (see page 1104)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
the position, direction of rotation, and speed can be tracked. In addition, a third channel, or index
®
signal, can be used to reset the position counter. The Stellaris quadrature encoder with index (QEI)
module interprets the code produced by a quadrature encoder wheel to integrate position over time
and determine direction of rotation. In addition, it can capture a running estimate of the velocity of
the encoder wheel. The input frequency of the QEI inputs may be as high as 1/4 of the processor
frequency (for example, 20 MHz for a 80-MHz system).
The LM3S9B95 microcontroller includes two QEI modules providing control of two motors at the
same time with the following features:
■ Position integrator that tracks the encoder position
■ Programmable noise filter on the inputs
■ Velocity capture using built-in timer
■ The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
■ Interrupt generation on:
– Index pulse
– Velocity-timer expiration
– Direction change
– Quadrature error detection
1.1.7
Analog
The LM3S9B95 controller provides analog functions integrated into the device, including:
■ Two 10-bit Analog-to-Digital Converters (ADC) with sixteen analog input channels and sample
rate of one million samples/second
■ Three analog comparators
■ 16 digital comparators
■ On-chip voltage regulator
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The following provides more detail on these analog functions.
1.1.7.1
ADC (see page 506)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
®
discrete digital number. The Stellaris ADC module features 10-bit conversion resolution and supports
sixteen input channels plus an internal temperature sensor. Four buffered sample sequencers allow
rapid sampling of up to eight analog input sources without controller intervention. Each sample
sequencer provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequencer priority. A digital comparator function is included that allows the conversion
value to be diverted to a comparison unit that provides 16 digital comparators.
The LM3S9B95 microcontroller provides two ADC modules with the following features:
■ Sixteen analog input channels
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Maximum sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– PWM
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
■ Digital comparison unit providing sixteen digital comparators
■ Converter uses an internal 3-V reference or an external reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
– ADC module uses burst requests for DMA
1.1.7.2
Analog Comparators (see page 1014)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The LM3S9B95 microcontroller provides three independent
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integrated analog comparators that can be configured to drive an output or generate an interrupt or
ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The LM3S9B95 microcontroller provides three independent integrated analog comparators with the
following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
1.1.8
JTAG and ARM Serial Wire Debug (see page 89)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial
Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG
debug ports into one module providing all the normal JTAG debug and test functionality plus real-time
access to system memory without halting the core or requiring any target resident code. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. The SWJ-DP interface
has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
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– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
1.1.9
Packaging and Temperature
■ Industrial-range 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2
Target Applications
®
The Stellaris family is positioned for cost-conscious applications requiring significant control
processing and connectivity capabilities such as:
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3
High-Level Block Diagram
®
Figure 1-1 depicts the features on the Stellaris LM3S9B95 microcontroller. Note that there are two
on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is
the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back
access performance than the APB bus.
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®
Figure 1-1. Stellaris LM3S9B95 Microcontroller High-Level Block Diagram
JTAG/SWD
ROM
ARM®
Cortex™-M3
System
Control and
Clocks
(w/ Precis. Osc.)
Boot Loader
DriverLib
AES & CRC
Flash
(256 KB)
DCode bus
(80 MHz)
ICode bus
NVIC
MPU
System Bus
LM3S9B95
Bus Matrix
SRAM
(96 KB)
SYSTEM PERIPHERALS
DMA
Watchdog
Timers
(2)
GPIOs
(65)
GeneralPurpose
Timers (4)
SSI
(2)
CAN
Controllers
(2)
SERIAL PERIPHERALS
Advanced Peripheral Bus (APB)
USB
(OTG)
Advanced High-Performance Bus (AHB)
External
Peripheral
Interface
UARTs
(3)
I2C
(2)
Ethernet
MAC/PHY
I2S
ANALOG PERIPHERALS
Analog
Comparators
(3)
ADC
Channels
(16)
MOTION CONTROL PERIPHERALS
PWM
(8)
QEI
(2)
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1.4
Additional Features
1.4.1
Memory Map (see page 83)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S9B95 controller can be found in “Memory Map” on page 83. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map. The
ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map.
1.4.2
Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 1127
■ “Signal Tables” on page 1129
■ “Operating Characteristics” on page 1204
■ “Electrical Characteristics” on page 1205
■ “Package Information” on page 1278
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2
ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
■ 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set, delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices; typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast multiplier
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
■ 80-MHz operation
■ 1.25 DMIPS/MHz
®
The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
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For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
2.1
Block Diagram
Figure 2-1. CPU Block Diagram
Nested
Vectored
Interrupt
Controller
Interrupts
Sleep
ARM
Cortex-M3
CM3 Core
Debug
Instructions
Data
Trace
Port
Interface
Unit
Memory
Protection
Unit
Flash
Patch and
Breakpoint
Instrumentation
Data
Watchpoint Trace Macrocell
and Trace
ROM
Table
Private Peripheral
Bus
(internal)
Adv. Peripheral
Bus
Bus
Matrix
Debug
Access Port
Serial Wire JTAG
Debug Port
2.2
Serial
Wire
Output
Trace
Port
(SWO)
I-code bus
D-code bus
System bus
Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
®
This section describes the Stellaris implementation.
Texas Instruments implements the ARM Cortex-M3 core as shown in Figure 2-1 on page 71. The
Cortex-M3 uses the entire 16-bit Thumb instruction set and the base Thumb-2 32-bit instruction set.
In addition, as noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3
components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the
MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the
sections that follow.
2.2.1
Programming Model
This section provides a brief overview of the programming model for the Cortex-M3 core. More
detailed information can be found in the ARM® Cortex™-M3 Technical Reference Manual.
■ Privileged access and user access - Code can execute as privileged or unprivileged. Unprivileged
execution limits or excludes access to some resources. Privileged execution has access to all
resources. Handler mode is always privileged. Thread mode can be privileged or unprivileged.
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Thread mode is privileged out of reset, but you can change it to user or unprivileged by setting
the CONTROL[0] bit using the MSR instruction. User access prevents:
– Use of some instructions such as CPS to set FAULTMASK and PRIMASK
– Access to most registers in System Control Space (SCS)
When Thread mode has been changed from privileged to user, it cannot change itself back to
privileged. Only a Handler can change the privilege of Thread mode. Handler mode is always
privileged.
■ Register set - The processor has the following 32-bit registers:
– 13 general-purpose registers, r0-r12
– Stack point alias of banked registers, SP_process and SP_main
– Link register, r14
– Program counter, r15
– One program status register, xPSR.
■ Data types - The processor supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
■ Memory formats - The processor views memory as a linear collection of bytes numbered in
ascending order from 0. For example, bytes 0-3 hold the first stored word and bytes 4-7 hold the
second stored word. The processor accesses code and data in little-endian format, which means
that the byte with the lowest address in a word is the least-significant byte of the word. The byte
with the highest address in a word is the most significant. The byte at address 0 of the memory
system connects to data lines 7-0.
■ Instruction set - The Cortex-M3 instruction set contains both 16 and 32-bit instructions. These
instructions are summarized in Table 2-1 on page 72 and Table 2-2 on page 74, respectively.
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary
Operation
Assembler
Add register value and C flag to register value
ADC <Rd>, <Rm>
Add immediate 3-bit value to register
ADD <Rd>, <Rn>, #<immed_3>
Add immediate 8-bit value to register
ADD <Rd>, #<immed_8>
Add low register value to low register value
ADD <Rd>, <Rn>, <Rm>
Add high register value to low or high register value
ADD <Rd>, <Rm>
Add 4* (immediate 8-bit value) with PC to register
ADD <Rd>, PC, #<immed_8> * 4
Add 4* (immediate 8-bit value) with SP to register
ADD <Rd>, SP, #<immed_8> * 4
Add 4* (immediate 7-bit value) to SP
ADD SP, #<immed_7> * 4
Bitwise AND register values
AND <Rd>, <Rm>
Arithmetic shift right by immediate number
ASR <Rd>, <Rm>, #<immed_5>
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Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Arithmetic shift right by number in register
ASR <Rd>, <Rs>
Branch conditional
B<cond> <target address>
Branch unconditional
B <target_address>
Bit clear
BIC <Rd>, <Rm>
Software breakpoint
BKPT <immed_8>
Branch with link
BL <Rm>
Branch with link and exchange
BLX <Rm>
Branch and exchange
BX <Rm>
Compare not zero and branch
CBNZ <Rn>,<label>
Compare zero and branch
CBZ <Rn>,<label>
Compare negation of register value with another register value
CMN <Rn>, <Rm>
Compare immediate 8-bit value
CMP <Rn>, #<immed_8>
Compare registers
CMP <Rn>, <Rm>
Compare high register to low or high register
CMP <Rn>, <Rm>
Change processor state
CPS <effect>, <iflags>
Copy high or low register value to another high or low register
CPY <Rd> <Rm>
Bitwise exclusive OR register values
EOR <Rd>, <Rm>
Condition the following instruction
IT <cond>
Condition the following two instructions
IT<x> <cond>
Condition the following three instructions
IT<x><y> <cond>
Condition the following four instructions
IT<x><y><z> <cond>
Multiple sequential memory word loads
LDMIA <Rn>!, <registers>
Load memory word from base register address + 5-bit immediate offset
LDR <Rd>, [<Rn>, #<immed_5> * 4]
Load memory word from base register address + register offset
LDR <Rd>, [<Rn>, <Rm>]
Load memory word from PC address + 8-bit immediate offset
LDR <Rd>, [PC, #<immed_8> * 4]
Load memory word from SP address + 8-bit immediate offset
LDR, <Rd>, [SP, #<immed_8> * 4]
Load memory byte [7:0] from register address + 5-bit immediate offset
LDRB <Rd>, [<Rn>, #<immed_5>]
Load memory byte [7:0] from register address + register offset
LDRB <Rd>, [<Rn>, <Rm>]
Load memory halfword [15:0] from register address + 5-bit immediate offset
LDRH <Rd>, [<Rn>, #<immed_5> * 2]
Load halfword [15:0] from register address + register offset
LDRH <Rd>, [<Rn>, <Rm>]
Load signed byte [7:0] from register address + register offset
LDRSB <Rd>, [<Rn>, <Rm>]
Load signed halfword [15:0] from register address + register offset
LDRSH <Rd>, [<Rn>, <Rm>]
Logical shift left by immediate number
LSL <Rd>, <Rm>, #<immed_5>
Logical shift left by number in register
LSL <Rd>, <Rs>
Logical shift right by immediate number
LSR <Rd>, <Rm>, #<immed_5>
Logical shift right by number in register
LSR <Rd>, <Rs>
Move immediate 8-bit value to register
MOV <Rd>, #<immed_8>
Move low register value to low register
MOV <Rd>, <Rn>
Move high or low register value to high or low register
MOV <Rd>, <Rm>
Multiply register values
MUL <Rd>, <Rm>
Move complement of register value to register
MVN <Rd>, <Rm>
Negate register value and store in register
NEG <Rd>, <Rm>
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Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
No operation
NOP <c>
Bitwise logical OR register values
ORR <Rd>, <Rm>
Pop registers from stack
POP <registers>
Pop registers and PC from stack
POP <registers, PC>
Push registers onto stack
PUSH <registers>
Push LR and registers onto stack
PUSH <registers, LR>
Reverse bytes in word and copy to register
REV <Rd>, <Rn>
Reverse bytes in two halfwords and copy to register
REV16 <Rd>, <Rn>
Reverse bytes in low halfword [15:0], sign-extend, and copy to register
REVSH <Rd>, <Rn>
Rotate right by amount in register
ROR <Rd>, <Rs>
Subtract register value and C flag from register value
SBC <Rd>, <Rm>
Send event
SEV <c>
Store multiple register words to sequential memory locations
STMIA <Rn>!, <registers>
Store register word to register address + 5-bit immediate offset
STR <Rd>, [<Rn>, #<immed_5> * 4]
Store register word to register address
STR <Rd>, [<Rn>, <Rm>]
Store register word to SP address + 8-bit immediate offset
STR <Rd>, [SP, #<immed_8> * 4]
Store register byte [7:0] to register address + 5-bit immediate offset
STRB <Rd>, [<Rn>, #<immed_5>]
Store register byte [7:0] to register address
STRB <Rd>, [<Rn>, <Rm>]
Store register halfword [15:0] to register address + 5-bit immediate offset
STRH <Rd>, [<Rn>, #<immed_5> * 2]
Store register halfword [15:0] to register address + register offset
STRH <Rd>, [<Rn>, <Rm>]
Subtract immediate 3-bit value from register
SUB <Rd>, <Rn>, #<immed_3>
Subtract immediate 8-bit value from register value
SUB <Rd>, #<immed_8>
Subtract register values
SUB <Rd>, <Rn>, <Rm>
Subtract 4 (immediate 7-bit value) from SP
SUB SP, #<immed_7> * 4
Operating system service call with 8-bit immediate call code
SVC <immed_8>
Extract byte [7:0] from register, move to register, and sign-extend to 32 bits
SXTB <Rd>, <Rm>
Extract halfword [15:0] from register, move to register, and sign-extend to 32 bits SXTH <Rd>, <Rm>
Test register value for set bits by ANDing it with another register value
TST <Rn>, <Rm>
Extract byte [7:0] from register, move to register, and zero-extend to 32 bits
UXTB <Rd>, <Rm>10
Extract halfword [15:0] from register, move to register, and zero-extend to 32
bits
UXTH <Rd>, <Rm>
Wait for event
WFE <c>
Wait for interrupt
WFI <c>
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary
Operation
Assembler
Add register value, immediate 12-bit value, and C bit
ADC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12>
Add register value, shifted register value, and C bit
ADC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Add register value and immediate 12-bit value
ADD{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Add register value and shifted register value
ADD{S}.W <Rd>, <Rm>{, <shift>}
Add register value and immediate 12-bit value
ADDW.W <Rd>, <Rn>, #<immed_12>
Bitwise AND register value with immediate 12-bit value
AND{S}.W <Rd>, <Rn>, #<modify_constant(immed_12>
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Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Bitwise AND register value with shifted register value
AND{S}.W <Rd>, <Rn>, Rm>{, <shift>}
Arithmetic shift right by number in register
ASR{S}.W <Rd>, <Rn>, <Rm>
Conditional branch
B{cond}.W <label>
Clear bit field
BFC.W <Rd>, #<lsb>, #<width>
Insert bit field from one register value into another
BFI.W <Rd>, <Rn>, #<lsb>, #<width>
Bitwise AND register value with complement of immediate 12-bit value
BIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Bitwise AND register value with complement of shifted register value
BIC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Branch with link
BL <label>
Branch with link (immediate)
BL<c> <label>
Unconditional branch
B.W <label>
Clear exclusive clears the local record of the executing processor that an
address has had a request for an exclusive access.
CLREX <c>
Return number of leading zeros in register value
CLZ.W <Rd>, <Rn>
Compare register value with two’s complement of immediate 12-bit value
CMN.W <Rn>, #<modify_constant(immed_12)>
Compare register value with two’s complement of shifted register value
CMN.W <Rn>, <Rm>{, <shift>}
Compare register value with immediate 12-bit value
CMP.W <Rn>, #<modify_constant(immed_12)>
Compare register value with shifted register value
CMP.W <Rn>, <Rm>{, <shift>}
Data memory barrier
DMB <c>
Data synchronization barrier
DSB <c>
Exclusive OR register value with immediate 12-bit value
EOR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Exclusive OR register value with shifted register value
EOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Instruction synchronization barrier
ISB <c>
Load multiple memory registers, increment after or decrement before
LDM{IA|DB}.W <Rn>{!}, <registers>
Memory word from base register address + immediate 12-bit offset
LDR.W <Rxf>, [<Rn>, #<offset_12>]
Memory word to PC from register address + immediate 12-bit offset
LDR.W PC, [<Rn>, #<offset_12>]
Memory word to PC from base register address immediate 8-bit offset,
postindexed
LDR.W PC, [Rn], #<+/-<offset_8>
Memory word from base register address immediate 8-bit offset, postindexed LDR.W <Rxf>, [<Rn>], #+/–<offset_8>
Memory word from base register address immediate 8-bit offset, preindexed LDR.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
LDRT.W <Rxf>, [<Rn>, #<offset_8>]
Memory word to PC from base register address immediate 8-bit offset,
preindexed
LDR.W PC, [<Rn>, #+/–<offset_8>]!
Memory word from register address shifted left by 0, 1, 2, or 3 places
LDR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word to PC from register address shifted left by 0, 1, 2, or 3 places LDR.W PC, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word from PC address immediate 12-bit offset
LDR.W <Rxf>, [PC, #+/–<offset_12>]
Memory word to PC from PC address immediate 12-bit offset
LDR.W PC, [PC, #+/–<offset_12>]
Memory byte [7:0] from base register address + immediate 12-bit offset
LDRB.W <Rxf>, [<Rn>, #<offset_12>]
Memory byte [7:0] from base register address immediate 8-bit offset,
postindexed
LDRB.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory byte [7:0] from register address shifted left by 0, 1, 2, or 3 places
LDRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory byte [7:0] from base register address immediate 8-bit offset,
preindexed
LDRB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory byte from PC address immediate 12-bit offset
LDRB.W <Rxf>, [PC, #+/–<offset_12>]
Memory doubleword from register address 8-bit offset 4, preindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
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Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Memory doubleword from register address 8-bit offset 4, postindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>], #+/–<offset_8> * 4
Load register exclusive calculates an address from a base register value and LDREX<c> <Rt>,[<Rn>{,#<imm>}]
an immediate offset, loads a word from memory, writes it to a register
Load register exclusive halfword calculates an address from a base register LDREXH<c> <Rt>,[<Rn>{,#<imm>}]
value and an immediate offset, loads a halfword from memory, writes it to a
register
Load register exclusive byte calculates an address from a base register value LDREXB<c> <Rt>,[<Rn>{,#<imm>}]
and an immediate offset, loads a byte from memory, writes it to a register
Memory halfword [15:0] from base register address + immediate 12-bit offset LDRH.W <Rxf>, [<Rn>, #<offset_12>]
Memory halfword [15:0] from base register address immediate 8-bit offset,
preindexed
LDRH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory halfword [15:0] from base register address immediate 8-bit offset,
postindexed
LDRH.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory halfword [15:0] from register address shifted left by 0, 1, 2, or 3 places LDRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory halfword from PC address immediate 12-bit offset
LDRH.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed byte [7:0] from base register address + immediate 12-bit offset LDRSB.W <Rxf>, [<Rn>, #<offset_12>]
Memory signed byte [7:0] from base register address immediate 8-bit offset, LDRSB.W <Rxf>. [<Rn>], #+/-<offset_8>
postindexed
Memory signed byte [7:0] from base register address immediate 8-bit offset, LDRSB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
preindexed
Memory signed byte [7:0] from register address shifted left by 0, 1, 2, or 3
places
LDRSB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory signed byte from PC address immediate 12-bit offset
LDRSB.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed halfword [15:0] from base register address + immediate 12-bit LDRSH.W <Rxf>, [<Rn>, #<offset_12>]
offset
Memory signed halfword [15:0] from base register address immediate 8-bit
offset, postindexed
LDRSH.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory signed halfword [15:0] from base register address immediate 8-bit
offset, preindexed
LDRSH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory signed halfword [15:0] from register address shifted left by 0, 1, 2,
or 3 places
LDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory signed halfword from PC address immediate 12-bit offset
LDRSH.W <Rxf>, [PC, #+/–<offset_12>]
Logical shift left register value by number in register
LSL{S}.W <Rd>, <Rn>, <Rm>
Logical shift right register value by number in register
LSR{S}.W <Rd>, <Rn>, <Rm>
Multiply two signed or unsigned register values and add the low 32 bits to a MLA.W <Rd>, <Rn>, <Rm>, <Racc>
register value
Multiply two signed or unsigned register values and subtract the low 32 bits MLS.W <Rd>, <Rn>, <Rm>, <Racc>
from a register value
Move immediate 12-bit value to register
MOV{S}.W <Rd>, #<modify_constant(immed_12)>
Move shifted register value to register
MOV{S}.W <Rd>, <Rm>{, <shift>}
Move immediate 16-bit value to top halfword [31:16] of register
MOVT.W <Rd>, #<immed_16>
Move immediate 16-bit value to bottom halfword [15:0] of register and clear MOVW.W <Rd>, #<immed_16>
top halfword [31:16]
Move to register from status
MRS<c> <Rd>, <psr>
Move to status register
MSR<c> <psr>_<fields>,<Rn>
Multiply two signed or unsigned register values
MUL.W <Rd>, <Rn>, <Rm>
No operation
NOP.W
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Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Logical OR NOT register value with immediate 12-bit value
ORN{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR NOT register value with shifted register value
ORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Logical OR register value with immediate 12-bit value
ORR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR register value with shifted register value
ORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Reverse bit order
RBIT.W <Rd>, <Rm>
Reverse bytes in word
REV.W <Rd>, <Rm>
Reverse bytes in each halfword
REV16.W <Rd>, <Rn>
Reverse bytes in bottom halfword and sign-extend
REVSH.W <Rd>, <Rn>
Rotate right by number in register
ROR{S}.W <Rd>, <Rn>, <Rm>
Rotate right with extend
RRX{S}.W <Rd>, <Rm>
Subtract a register value from an immediate 12-bit value
RSB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract a register value from a shifted register value
RSB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Subtract immediate 12-bit value and C bit from register value
SBC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract shifted register value and C bit from register value
SBC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Copy selected bits to register and sign-extend
SBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Signed divide
SDIV<c> <Rd>,<Rn>,<Rm>
Send event
SEV<c>
Multiply signed words and add signed-extended value to 2-register value
SMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Multiply two signed register values
SMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Signed saturate
SSAT.W <c> <Rd>, #<imm>, <Rn>{, <shift>}
Multiple register words to consecutive memory locations
STM{IA|DB}.W <Rn>{!}, <registers>
Register word to register address + immediate 12-bit offset
STR.W <Rxf>, [<Rn>, #<offset_12>]
Register word to register address immediate 8-bit offset, postindexed
STR.W <Rxf>, [<Rn>], #+/–<offset_8>
Register word to register address shifted by 0, 1, 2, or 3 places
STR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register word to register address immediate 8-bit offset, preindexed Store,
preindexed
STR.W <Rxf>, [<Rn>, #+/-<offset_8>]{!}
STRT.W <Rxf>, [<Rn>, #<offset_8>]
Register byte [7:0] to register address immediate 8-bit offset, preindexed
STRB{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
Register byte [7:0] to register address + immediate 12-bit offset
STRB.W <Rxf>, [<Rn>, #<offset_12>]
Register byte [7:0] to register address immediate 8-bit offset, postindexed
STRB.W <Rxf>, [<Rn>], #+/–<offset_8>
Register byte [7:0] to register address shifted by 0, 1, 2, or 3 places
STRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Store doubleword, preindexed
STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
Store doubleword, postindexed
STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]
Store register exclusive calculates an address from a base register value and STREX <c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
an immediate offset, and stores a word from a register to memory if the
executing processor has exclusive access to the memory addressed.
Store register exclusive byte derives an address from a base register value, STREXB <c> <Rd>,<Rt>,[<Rn>]
and stores a byte from a register to memory if the executing processor has
exclusive access to the memory addressed
Store register exclusive halfword derives an address from a base register
value, and stores a halfword from a register to memory if the executing
processor has exclusive access to the memory addressed.
STREXH <c> <Rd>,<Rt>,[<Rn>]
Register halfword [15:0] to register address + immediate 12-bit offset
STRH.W <Rxf>, [<Rn>, #<offset_12>]
Register halfword [15:0] to register address shifted by 0, 1, 2, or 3 places
STRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register halfword [15:0] to register address immediate 8-bit offset, preindexed STRH{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
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Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Register halfword [15:0] to register address immediate 8-bit offset, postindexed STRH.W <Rxf>, [<Rn>], #+/–<offset_8>
Subtract immediate 12-bit value from register value
SUB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract shifted register value from register value
SUB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Subtract immediate 12-bit value from register value
SUBW.W <Rd>, <Rn>, #<immed_12>
Sign extend byte to 32 bits
SXTB.W <Rd>, <Rm>{, <rotation>}
Sign extend halfword to 32 bits
SXTH.W <Rd>, <Rm>{, <rotation>}
Table branch byte
TBB [<Rn>, <Rm>]
Table branch halfword
TBH [<Rn>, <Rm>, LSL #1]
Exclusive OR register value with immediate 12-bit value
TEQ.W <Rn>, #<modify_constant(immed_12)>
Exclusive OR register value with shifted register value
TEQ.W <Rn>, <Rm>{, <shift}
Logical AND register value with 12-bit immediate value
TST.W <Rn>, #<modify_constant(immed_12)>
Logical AND register value with shifted register value
TST.W <Rn>, <Rm>{, <shift>}
Copy bit field from register value to register and zero-extend to 32 bits
UBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Unsigned divide
UDIV<c> <Rd>,<Rn>,<Rm>
Multiply two unsigned register values and add to a 2-register value
UMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Multiply two unsigned register values
UMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Unsigned saturate
USAT <c> <Rd>, #<imm>, <Rn>{, <shift>}
Copy unsigned byte to register and zero-extend to 32 bits
UXTB.W <Rd>, <Rm>{, <rotation>}
Copy unsigned halfword to register and zero-extend to 32 bits
UXTH.W <Rd>, <Rm>{, <rotation>}
Wait for event
WFE.W
Wait for interrupt
WFI.W
2.2.2
Serial Wire and JTAG Debug
Texas Instruments replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual
for details on SWJ-DP.
2.2.3
Embedded Trace Macrocell (ETM)
®
ETM is not implemented in the Stellaris devices. As a result, Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.4
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
®
Port Analyzer. Stellaris devices implement the TPIU as shown in Figure 2-2. This implementation
is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual,
however, SWJ-DP only provides the Serial Wire Viewer (SWV) output format for the TPIU.
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Figure 2-2. TPIU Block Diagram
2.2.5
Debug
ATB
Slave
Port
ATB
Interface
APB
Slave
Port
APB
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
ROM Table
The default ROM table is implemented as described in the ARM® Cortex™-M3 Technical Reference
Manual.
2.2.6
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S9B95 controller and supports the
standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full
support for protection regions, overlapping protection regions, access permissions, and exporting
memory attributes to the system.
2.2.7
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
by enabling the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
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2.2.7.1
Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S9B95 microcontroller supports 53 interrupts with eight priority
levels.
In addition to the peripheral interrupts, the system also provides for a non-maskable interrupt (NMI).
The NMI is generally used in safety critical applications where the immediate execution of an interrupt
handler is required. The NMI signal is available as an external signal so that it may be generated
by external circuitry. The NMI is also used internally as part of the main oscillator verification circuitry.
More information on the non-maskable interrupt is located in “Non-Maskable Interrupt” on page 106.
2.2.8
System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
2.2.8.1
Functional Description
The timer consists of three registers:
■ SysTick Control and Status Register - a control and status counter to configure its clock, enable
the counter, enable the SysTick interrupt, and determine counter status
■ SysTick Reload Value Register - the reload value for the counter, used to provide the counter's
wrap value
■ SysTick Current Value Register - the current value of the counter
®
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris devices.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the SysTick Reload Value register on the next clock edge, then decrements on
subsequent clocks. Clearing the SysTick Reload Value register disables the counter on the next
wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit
clears on reads.
Writing to the SysTick Current Value register clears the register and the COUNTFLAG status bit.
The write does not trigger the SysTick exception logic. On a read, the current value is the value of
the register at the time the register is accessed.
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If the core is in debug state (halted), the counter does not decrement. The timer is clocked with
respect to a reference clock, which can be either the core clock or an external clock source.
2.2.8.2
SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
Bit/Field
Name
Type
31:17
reserved
RO
16
COUNTFLAG
R/W
Reset Description
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Count Flag
When set, this bit indicates that the timer has counted to 0 since the last time
this register was read.
This bit is cleared by a read of the register.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
15:3
reserved
RO
2
CLKSOURCE
R/W
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Clock Source
Value Description
®
0
External reference clock. (Not implemented for Stellaris
microcontrollers.)
1
Core clock
Because an external reference clock is not supported, this bit must be set
in order for SysTick to operate.
1
TICKINT
R/W
0
Tick Interrupt
When set, this bit causes an interrupt to be generated to the NVIC when
SysTick counts to 0.
When clear, interrupt generation is disabled. Software can use the
COUNTFLAG to determine if the counter has ever reached 0.
0
ENABLE
R/W
0
Enable
When set, this bit enables SysTick to operate in a multi-shot way. That is,
the counter loads the Reload value and begins counting down. On reaching
0, the COUNTFLAG bit is set and an interrupt is generated if enabled by
TICKINT. The counter then loads the Reload value again and begins counting.
When this bit is clear, the counter is disabled.
2.2.8.3
SysTick Reload Value Register
The SysTick Reload Value Register specifies the start value to load into the SysTick Current Value
Register when the counter reaches 0. The start value can be between 1 and 0x00FF.FFFF. A start
value of 0 is possible but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
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When configuring SysTick as a single-shot timer, a new value is written on each tick interrupt, and
the actual count down value must be written. For example, if a tick is next required after 400 clock
pulses, 400 must be written into the RELOAD field.
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
23:0
RELOAD
R/W
-
Reload Value
Value to load into the SysTick Current Value Register when
the counter reaches 0.
2.2.8.4
SysTick Current Value Register
The SysTick Current Value Register contains the current value of the counter.
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:0
CURRENT
W1C
-
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register
to 0. Clearing this register also clears the COUNTFLAG bit of the
SysTick Control and Status Register.
2.2.8.5
SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
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3
Memory Map
The memory map for the LM3S9B95 controller is provided in Table 3-1.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Note that within the memory map, all reserved space returns a bus fault when read or written.
Table 3-1. Memory Map
Start
End
Description
For details,
see page ...
0x0000.0000
0x0003.FFFF
On-chip Flash
212
0x0004.0000
0x00FF.FFFF
Reserved
-
0x0100.0000
0x1FFF.FFFF
Reserved for ROM
210
0x2000.0000
0x2001.7FFF
Bit-banded on-chip SRAM
210
0x2001.8000
0x21FF.FFFF
Reserved
-
0x2200.0000
0x222F.FFFF
Bit-band alias of 0x2000.0000 through 0x200F.FFFF
210
0x2230.0000
0x3FFF.FFFF
Reserved
-
0x4000.0000
0x4000.0FFF
Watchdog timer 0
484
0x4000.1000
0x4000.1FFF
Watchdog timer 1
484
0x4000.2000
0x4000.3FFF
Reserved
-
0x4000.4000
0x4000.4FFF
GPIO Port A
317
0x4000.5000
0x4000.5FFF
GPIO Port B
317
0x4000.6000
0x4000.6FFF
GPIO Port C
317
0x4000.7000
0x4000.7FFF
GPIO Port D
317
0x4000.8000
0x4000.8FFF
SSI0
660
0x4000.9000
0x4000.9FFF
SSI1
660
0x4000.A000
0x4000.BFFF
Reserved
-
0x4000.C000
0x4000.CFFF
UART0
597
0x4000.D000
0x4000.DFFF
UART1
597
0x4000.E000
0x4000.EFFF
UART2
597
0x4000.F000
0x4001.FFFF
Reserved
-
0x4002.07FF
I2C Master 0
703
0x4002.0FFF
I2C
Slave 0
716
0x4002.1000
0x4002.17FF
I2C
Master 1
703
0x4002.1800
0x4002.1FFF
I2C Slave 1
716
0x4002.2000
0x4002.3FFF
Reserved
-
0x4002.4000
0x4002.4FFF
GPIO Port E
317
0x4002.5000
0x4002.5FFF
GPIO Port F
317
0x4002.6000
0x4002.6FFF
GPIO Port G
317
0x4002.7000
0x4002.7FFF
GPIO Port H
317
Memory
FiRM Peripherals
Peripherals
0x4002.0000
0x4002.0800
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Memory Map
Table 3-1. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4002.8000
0x4002.8FFF
PWM
1041
0x4002.9000
0x4002.BFFF
Reserved
-
0x4002.C000
0x4002.CFFF
QEI0
1110
0x4002.D000
0x4002.DFFF
QEI1
1110
0x4002.E000
0x4002.FFFF
Reserved
-
0x4003.0000
0x4003.0FFF
Timer 0
449
0x4003.1000
0x4003.1FFF
Timer 1
449
0x4003.2000
0x4003.2FFF
Timer 2
449
0x4003.3000
0x4003.3FFF
Timer 3
449
0x4003.4000
0x4003.7FFF
Reserved
-
0x4003.8000
0x4003.8FFF
ADC0
526
0x4003.9000
0x4003.9FFF
ADC1
526
0x4003.A000
0x4003.BFFF
Reserved
-
0x4003.C000
0x4003.CFFF
Analog Comparators
1014
0x4003.D000
0x4003.DFFF
GPIO Port J
317
0x4003.E000
0x4003.FFFF
Reserved
-
0x4004.0000
0x4004.0FFF
CAN0 Controller
782
0x4004.1000
0x4004.1FFF
CAN1 Controller
782
0x4004.2000
0x4004.7FFF
Reserved
-
0x4004.8000
0x4004.8FFF
Ethernet Controller
828
0x4004.9000
0x4004.FFFF
Reserved
-
0x4005.0000
0x4005.0FFF
USB
902
0x4005.1000
0x4005.3FFF
Reserved
-
0x4005.4000
0x4005.4FFF
I2S0
737
0x4005.5000
0x4005.7FFF
Reserved
-
0x4005.8000
0x4005.8FFF
GPIO Port A (AHB aperture)
317
0x4005.9000
0x4005.9FFF
GPIO Port B (AHB aperture)
317
0x4005.A000
0x4005.AFFF
GPIO Port C (AHB aperture)
317
0x4005.B000
0x4005.BFFF
GPIO Port D (AHB aperture)
317
0x4005.C000
0x4005.CFFF
GPIO Port E (AHB aperture)
317
0x4005.D000
0x4005.DFFF
GPIO Port F (AHB aperture)
317
0x4005.E000
0x4005.EFFF
GPIO Port G (AHB aperture)
317
0x4005.F000
0x4005.FFFF
GPIO Port H (AHB aperture)
317
0x4006.0000
0x4006.0FFF
GPIO Port J (AHB aperture)
317
0x4006.1000
0x400C.FFFF
Reserved
-
0x400D.0000
0x400D.0FFF
EPI0
389
0x400D.1000
0x400F.CFFF
Reserved
-
0x400F.D000
0x400F.DFFF
Flash memory control
217
0x400F.E000
0x400F.EFFF
System control
117
0x400F.F000
0x400F.FFFF
µDMA
267
0x4010.0000
0x41FF.FFFF
Reserved
-
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Table 3-1. Memory Map (continued)
Start
End
Description
For details,
see page ...
0x4200.0000
0x43FF.FFFF
Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
-
0x4400.0000
0x5FFF.FFFF
Reserved
-
0x6000.0000
0xDFFF.FFFF
EPI0 mapped peripheral and RAM
-
0xE000.0000
0xE000.0FFF
Instrumentation Trace Macrocell (ITM)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.1000
0xE000.1FFF
Data Watchpoint and Trace (DWT)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.2000
0xE000.2FFF
Flash Patch and Breakpoint (FPB)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.3000
0xE000.DFFF
Reserved
-
0xE000.E000
0xE000.EFFF
Nested Vectored Interrupt Controller (NVIC)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE000.F000
0xE003.FFFF
Reserved
-
0xE004.0000
0xE004.0FFF
Trace Port Interface Unit (TPIU)
ARM®
Cortex™-M3
Technical
Reference
Manual
0xE004.1000
0xFFFF.FFFF
Reserved
-
Private Peripheral Bus
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Interrupts
4
Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 4-1 on page 86 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 53 interrupts (listed in Table 4-2 on page 87).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. Priorities can be grouped by splitting priority levels into pre-emption priorities and
subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
Important: It may take several processor cycles after a write to clear an interrupt source for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
Exception Type
a
Vector
Number
Priority
Description
-
0
-
Stack top is loaded from the first entry of the vector table on reset.
Reset
1
-3 (highest)
This exception is invoked on power up and warm reset. On the first
instruction, Reset drops to the lowest priority (and then is called the
base level of activation). This exception is asynchronous.
Non-Maskable
Interrupt (NMI)
2
-2
This exception is caused by the assertion of the NMI signal or by using
the NVIC Interrupt Control State register and cannot be stopped or
preempted by any exception but Reset. This exception is asynchronous.
Hard Fault
3
-1
This exception is caused by all classes of Fault, when the fault cannot
activate due to priority or the configurable fault handler has been
disabled. This exception is synchronous.
Memory
Management
4
programmable
This exception is caused by an MPU mismatch, including access
violation and no match. This exception is synchronous.
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Table 4-1. Exception Types (continued)
Exception Type
a
Vector
Number
Priority
5
programmable
Bus Fault
Description
This exception is caused by a pre-fetch fault, memory access fault, and
other address/memory related faults. This exception is synchronous
when precise and asynchronous when imprecise.
This fault can be enabled or disabled.
Usage Fault
6
programmable
7-10
-
SVCall
11
programmable
This exception is caused by a system service call with an SVC
instruction. This exception is synchronous.
Debug Monitor
12
programmable
This exception is caused by the debug monitor (when not halting). This
exception is synchronous, but only active when enabled. This exception
does not activate if it is a lower priority than the current activation.
-
13
-
PendSV
14
programmable
This exception is caused by a pendable request for system service. This
exception is asynchronous and only pended by software.
SysTick
15
programmable
This exception is caused by the SysTick timer reaching 0, when it is
enabled to generate an interrupt. This exception is asynchronous.
16 and
above
programmable
This exception is caused by interrupts asserted from outside the ARM
Cortex-M3 core and fed through the NVIC (prioritized). These exceptions
are all asynchronous. Table 4-2 on page 87 lists the interrupts on the
LM3S9B95 controller.
-
Interrupts
This exception is caused by a usage fault, such as undefined instruction
executed or illegal state transition attempt. This exception is
synchronous.
Reserved.
Reserved.
a. 0 is the default priority for all the programmable priorities.
Table 4-2. Interrupts
Vector Number
Interrupt Number (Bit in
Interrupt Registers)
Description
0-15
-
Processor exceptions
16
0
GPIO Port A
17
1
GPIO Port B
18
2
GPIO Port C
19
3
GPIO Port D
20
4
GPIO Port E
21
5
UART0
22
6
UART1
23
7
SSI0
24
8
I2C0
25
9
PWM Fault
26
10
PWM Generator 0
27
11
PWM Generator 1
28
12
PWM Generator 2
29
13
QEI0
30
14
ADC0 Sequence 0
31
15
ADC0 Sequence 1
32
16
ADC0 Sequence 2
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Table 4-2. Interrupts (continued)
Vector Number
Interrupt Number (Bit in
Interrupt Registers)
Description
33
17
ADC0 Sequence 3
34
18
Watchdog Timers 0 and 1
35
19
Timer 0A
36
20
Timer 0B
37
21
Timer 1A
38
22
Timer 1B
39
23
Timer 2A
40
24
Timer 2B
41
25
Analog Comparator 0
42
26
Analog Comparator 1
43
27
Analog Comparator 2
44
28
System Control
45
29
Flash Memory Control
46
30
GPIO Port F
47
31
GPIO Port G
48
32
GPIO Port H
49
33
UART2
50
34
SSI1
51
35
Timer 3A
52
36
Timer 3B
53
37
I2C1
54
38
QEI1
55
39
CAN0
56
40
CAN1
57
41
Reserved
58
42
Ethernet Controller
59
43
Reserved
60
44
USB
61
45
PWM Generator 3
62
46
µDMA Software
63
47
µDMA Error
64
48
ADC1 Sequence 0
65
49
ADC1 Sequence 1
66
50
ADC1 Sequence 2
67
51
ADC1 Sequence 3
68
52
I2S0
69
53
EPI
70
54
GPIO Port J
71
55
Reserved
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5
JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into
the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
®
The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core
by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM
®
®
TDO output while Stellaris JTAG instructions select the Stellaris TDO output. The multiplexer is
®
controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM,
®
Stellaris , and unimplemented JTAG instructions.
®
The Stellaris JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
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JTAG Interface
5.1
Block Diagram
Figure 5-1. JTAG Module Block Diagram
TCK
TMS
TAP Controller
TDI
Instruction Register (IR)
BYPASS Data Register
TDO
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
Cortex-M3
Debug
Port
5.2
Signal Description
Table 5-1 on page 90 and Table 5-2 on page 91 list the external signals of the JTAG/SWD controller
and describe the function of each. The JTAG/SWD controller signals are alternate functions for
some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function.
The JTAG/SWD controller signals are under commit protection and require a special process to be
configured as GPIOs, see “Commit Control” on page 312. The column in the table below titled "Pin
Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL
bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 328) is set to choose the
JTAG/SWD function.The number in parentheses is the encoding that must be programmed into the
PMCn field in the GPIO Port Control (GPIOPCTL) register (page 346) to assign the JTAG/SWD
controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see
“General-Purpose Input/Outputs (GPIOs)” on page 304.
Table 5-1. Signals for JTAG_SWD_SWO (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
SWCLK
80
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWDIO
79
PC1 (3)
I/O
TTL
JTAG TMS and SWDIO.
SWO
77
PC3 (3)
O
TTL
JTAG TDO and SWO.
TCK
80
PC0 (3)
I
TTL
JTAG/SWD CLK.
TDI
78
PC2 (3)
I
TTL
JTAG TDI.
TDO
77
PC3 (3)
O
TTL
JTAG TDO and SWO.
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Table 5-1. Signals for JTAG_SWD_SWO (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
79
TMS
PC1 (3)
a
Pin Type
Buffer Type
I
TTL
Description
JTAG TMS and SWDIO.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 5-2. Signals for JTAG_SWD_SWO (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
A9
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWDIO
B9
PC1 (3)
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
PC3 (3)
O
TTL
JTAG TDO and SWO.
TCK
A9
PC0 (3)
I
TTL
JTAG/SWD CLK.
SWCLK
TDI
B8
PC2 (3)
I
TTL
JTAG TDI.
TDO
A10
PC3 (3)
O
TTL
JTAG TDO and SWO.
TMS
B9
PC1 (3)
I
TTL
JTAG TMS and SWDIO.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
5.3
Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 90. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-4 on page 97 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 1210 for JTAG timing diagrams.
Note:
5.3.1
Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST
input have any effect on the JTAG module. The pin configurations are reset by both the
RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset
Sources” on page 102 for more information on reset.
JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated state after a power-on reset or reset caused by the RST input are given in Table 5-3.
Detailed information on each pin follows. Refer to “General-Purpose Input/Outputs
(GPIOs)” on page 304 for information on how to reprogram the configuration of these pins.
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Table 5-3. JTAG Port Pins State after Power-On Reset or RST assertion
5.3.1.1
Pin Name
Data Direction
Internal Pull-Up
Internal Pull-Down
Drive Strength
Drive Value
TCK
Input
Enabled
Disabled
N/A
N/A
TMS
Input
Enabled
Disabled
N/A
N/A
TDI
Input
Enabled
Disabled
N/A
N/A
TDO
Output
Enabled
Disabled
2-mA driver
High-Z
Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks and to ensure that multiple JTAG TAP controllers that
are daisy-chained together can synchronously communicate serial test data between components.
During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When
necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0
or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data
Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking
occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors
can be turned off to save internal power as long as the TCK pin is constantly being driven by an
external source (see page 334 and page 336).
5.3.1.2
Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be
entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
module and associated registers are reset to their default values. This procedure should be performed
to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety
in Figure 5-2 on page 93.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost (see page 334).
5.3.1.3
Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled
on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost (see page 334).
5.3.1.4
Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
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chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin
remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states (see page 334 and page 336).
5.3.2
JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2. The TAP controller state machine
is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset
the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH
for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting
the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in
data, or idle during extended testing sequences. For detailed information on the function of the TAP
controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.
Figure 5-2. Test Access Port State Machine
Test Logic Reset
1
0
Run Test Idle
0
Select DR Scan
1
Select IR Scan
1
0
1
Capture DR
1
Capture IR
0
0
Shift DR
Shift IR
0
1
Exit 1 DR
Exit 1 IR
1
Pause IR
0
1
Exit 2 DR
0
1
0
Exit 2 IR
1
1
Update DR
5.3.3
1
0
Pause DR
1
0
1
0
0
1
0
Update IR
0
1
0
Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
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this information to be shifted out on TDO during the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 97.
5.3.4
Operational Considerations
Certain operational parameters must be considered when using the JTAG module. Because the
JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these
pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes is described below.
5.3.4.1
GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0]
set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0]
set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors
(PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the
alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWD pins. See page 328, page 334, page 336, and page 339.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of
the part. This issue can be avoided with a software routine that restores JTAG functionality based on
an external or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four
JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 328), GPIO Pull Up Select (GPIOPUR) register (see page 334),
GPIO Pull-Down Select (GPIOPDR) register (see page 336), and GPIO Digital Enable (GPIODEN)
register (see page 339) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 341) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 342) have been set.
5.3.4.2
Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
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5.3.4.3
Recovering a "Locked" Microcontroller
Note:
Performing the sequence below restores the nonvolatile registers discussed in “Nonvolatile
Register Programming” on page 215 to their factory default values. The mass erase of the
Flash memory caused by the sequence below occurs prior to the nonvolatile registers being
restored.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the microcontroller.
Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the
microcontroller in reset mass erases the Flash memory. The sequence to recover the microcontroller
is:
1. Assert and hold the RST signal.
2. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD
Switching” on page 96.
3. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG
Switching” on page 96.
4. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
5. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
6. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
7. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
8. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
9. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
10. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
11. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
12. Release the RST signal.
13. Wait 400 ms.
14. Power-cycle the microcontroller.
5.3.4.4
ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued
before the SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
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Stepping through this sequence of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one
where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to
the low probability of this sequence occurring during normal operation of the TAP controller, it should
not affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS
command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first.
This command can also be represented as 0xE79E when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset/idle states.
2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in SWD mode, the SWD goes into the line reset state before sending the switch sequence.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit TMS
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset/idle states.
2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS.
3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that if SWJ-DP was already
in JTAG mode, the JTAG goes into the Test Logic Reset state before sending the switch
sequence.
5.4
Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. To return the pins to their JTAG functions,
enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register.
In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (PC[3:0]) should be returned to their default settings.
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5.5
Register Descriptions
The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
5.5.1
Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated,
they are interpreted as the current instruction. The decode of the IR bits is shown in Table 5-4. A
detailed explanation of each instruction, along with its associated Data Register, follows.
Table 5-4. JTAG Instruction Register Commands
5.5.1.1
IR[3:0]
Instruction
Description
0x0
EXTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
0x1
INTEST
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
0x2
SAMPLE / PRELOAD
0x8
ABORT
Shifts data into the ARM Debug Port Abort Register.
0xA
DPACC
Shifts data into and out of the ARM DP Access Register.
0xB
APACC
Shifts data into and out of the ARM AC Access Register.
0xE
IDCODE
Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
0xF
BYPASS
Connects TDI to TDO through a single Shift Register chain.
All Others
Reserved
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
5.5.1.2
INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. Instead, the INTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. With tests that
drive known values into the controller, this instruction can be used for testing. It is important to note
that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable.
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While the INTEST instruction is present in the Instruction Register, the Boundary Scan Data Register
can be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
5.5.1.3
SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. See “Boundary Scan Data
Register” on page 99 for more information.
5.5.1.4
ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. See the “ABORT Data Register” on page 100 for more information.
5.5.1.5
DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. See “DPACC Data
Register” on page 100 for more information.
5.5.1.6
APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
See “APACC Data Register” on page 100 for more information.
5.5.1.7
IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure input and output data streams. IDCODE is the default instruction loaded into the JTAG
Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is
entered. See “IDCODE Data Register” on page 99 for more information.
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5.5.1.8
BYPASS Instruction
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 99 for more
information.
5.5.2
Data Registers
The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE,
BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.
5.5.2.1
IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3. The standard requires that every JTAG-compliant microcontroller implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
The major uses of the JTAG port are for manufacturer testing of component assembly and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically
configure themselves to work correctly with the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
31
TDI
5.5.2.2
28 27
Version
12 11
Part Number
1 0
Manufacturer ID
1
TDO
BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4. The standard requires that every JTAG-compliant microcontroller implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
Figure 5-4. BYPASS Register Format
0
TDI
5.5.2.3
0
TDO
Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5. Each GPIO pin, starting
with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each
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GPIO pin has three associated digital signals that are included in the chain. These signals are input,
output, and output enable, and are arranged in that order as shown in the figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. The EXTEST instruction forces data out of the controller,
and the INTEST instruction forces data into the controller.
Figure 5-5. Boundary Scan Register Format
TDI
I
N
O
U
T
O
E
...
O
U
T
mth GPIO
1st GPIO
5.5.2.4
I
N
O
E
I
N
O
U
T
O
E
(m+1)th GPIO
...
I
N
O
U
T
O
E
TDO
GPIO nth
APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.5.2.5
DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.5.2.6
ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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6
System Control
System control configures the overall operation of the device and provides information about the
device. Configurable features include reset control, NMI operation, power control, clock control, and
low-power modes.
6.1
Signal Description
Table 6-1 on page 101 and Table 6-2 on page 101 list the external signals of the System Control
module and describe the function of each. The NMI signal is the alternate function for the GPIO PB7
signal and functions as a GPIO after reset. PB7 is under commit protection and requires a special
process to be configured as the NMI signal or to subsequently return to the GPIO function, see
“Commit Control” on page 312. The column in the table below titled "Pin Mux/Pin Assignment" lists
the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 328) should be set to choose the NMI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 346) to assign the NMI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 304. The
remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin
assignment and function.
Table 6-1. Signals for System Control & Clocks (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
NMI
89
PB7 (4)
I
TTL
Non-maskable interrupt.
OSC0
48
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
49
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
64
fixed
I
TTL
System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 6-2. Signals for System Control & Clocks (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
NMI
A8
PB7 (4)
I
TTL
Non-maskable interrupt.
OSC0
L11
fixed
I
Analog
Main oscillator crystal input or an external clock
reference input.
OSC1
M11
fixed
O
Analog
Main oscillator crystal output. Leave unconnected
when using a single-ended clock source.
RST
H11
fixed
I
TTL
System reset input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
6.2
Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 102
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■ Local control, such as reset (see “Reset Control” on page 102), power (see “Power
Control” on page 107) and clock control (see “Clock Control” on page 107)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 114
6.2.1
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, Flash memory size, and other features. See the DID0 (page 118), DID1
(page 146), DC0-DC9 (page 148) and NVMSTAT (page 172) registers.
6.2.2
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.2.2.1
Reset Sources
The LM3S9B95 microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 103).
2. External reset input pin (RST) assertion (see page 103).
3. Internal brown-out (BOR) detector (see page 105).
4. Software-initiated reset (with the software reset registers) (see page 105).
5. A watchdog timer reset condition violation (see page 106).
6. MOSC failure (see page 106).
Table 6-3 provides a summary of results of the various reset operations.
Table 6-3. Reset Sources
Reset Source
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Power-On Reset
Yes
Yes
Yes
RST
Yes
Pin Config Only
Yes
Brown-Out Reset
Yes
No
Yes
a
No
Yes
Software System Request
Reset
Yes
Software Peripheral Reset
No
No
Yes
Watchdog Reset
Yes
No
Yes
MOSC Failure Reset
Yes
No
Yes
b
a. By using the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator.
A bit in the RESC register can be cleared by writing a 0.
At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM
Boot Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured
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in the Boot Configuration (BOOTCFG) register. If the ROM boot loader is not selected, code in
the ROM checks address 0x000.0004 to see if the Flash memory has a valid reset vector. If the
data at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not
yet been programmed, and the core executes the ROM Boot Loader.
For example, if the BOOTCFG register is written and committed with the value of 0x0000.3C01,
then PB7 is examined at reset to determine if the ROM boot loader should be executed. If PB7 is
Low, the core unconditionally begins executing the ROM boot loader. If PB7 is High, then the
application in Flash memory is executed if the reset vector at location 0x0000.0004 is not
0xFFFF.FFFF. Otherwise, the ROM boot loader is executed.
6.2.2.2
Power-On Reset (POR)
Note:
The power-on reset also resets the JTAG controller. An external reset does not.
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. For applications that require the use of an
external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input
may be used as discussed in “External RST Pin” on page 103.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 27-5 on page 1212.
6.2.2.3
External RST Pin
Note:
It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 6-1 on page 103.
Figure 6-1. Basic RST Configuration
VDD
Stellaris®
RPU
RST
RPU = 0 to 100 kΩ
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The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 89). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted
(see “Reset” on page 1211).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 6-2 on page 104.
Figure 6-2. External Circuitry to Extend Power-On Reset
VDD
Stellaris®
RPU
RST
C1
RPU = 1 kΩ to 100 kΩ
C1 = 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 6-3 on page 104 shows the
proper circuitry to use.
Figure 6-3. Reset Circuit Controlled by Switch
VDD
Stellaris®
RPU
RST
C1
RS
Typical RPU = 10 kΩ
Typical RS = 470 Ω
C1 = 10 nF
The RPU and C1 components define the power-on delay.
The external reset timing is shown in Figure 27-4 on page 1211.
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6.2.2.4
Brown-Out Reset (BOR)
The microcontroller provides a brown-out detection circuit that triggers if the power supply (VDD)
drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system
may generate an interrupt or a system reset. The default condition is to generate an interrupt, so
BOR must be enabled. Brown-out resets are controlled with the Power-On and Brown-Out Reset
Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out
condition to trigger a reset; if BORIOR is clear, an interrupt is generated. When a Brown-out condition
occurs during a Flash PROGRAM or ERASE operation, a full system reset is always triggered
without regard to the setting in the PBORCTL register.
The brown-out reset sequence is as follows:
1. When VDD drops below VBTH, an internal BOR condition is set.
2. If the BOR condition exists, an internal reset is asserted.
3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer,
the initial program counter, the first instruction designated by the program counter, and begins
execution.
4. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and
the reset is held active until the proper VDD level is restored. The RESC register can be examined
in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus
allowing software to determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 27-6 on page 1212.
6.2.2.5
Software Reset
Software can reset a specific peripheral or generate a reset to the entire microcontroller.
Peripherals can be individually reset by software via three registers that control reset signals to each
on-chip peripheral (see the SRCRn registers, page 202). If the bit position corresponding to a
peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers
is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see
“System Control” on page 114).
The entire microcontroller including the core can be reset by software by setting the SYSRESETREQ
bit in the Cortex-M3 Application Interrupt and Reset Control register. The software-initiated system
reset sequence is as follows:
1. A software microcontroller reset is initiated by setting the SYSRESETREQ bit in the ARM
Cortex-M3 Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The software-initiated system reset timing is shown in Figure 27-7 on page 1212.
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6.2.2.6
Watchdog Timer Reset
The Watchdog Timer module's function is to prevent system hangs. The LM3S9B95 microcontroller
has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run
off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module
operates in the same manner except that because the PIOSC watchdog timer module is in a different
clock domain, register accesses must have a time delay between them. The watchdog timer can
be configured to generate an interrupt to the microcontroller on its first time-out and to generate a
reset on its second time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal
has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog
timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
For more information on the Watchdog Timer module, see “Watchdog Timers” on page 481.
The watchdog reset timing is shown in Figure 27-8 on page 1212.
6.2.3
Non-Maskable Interrupt
The microcontroller has three sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal
■ A main oscillator verification error
■ The NMISET bit in the Interrupt Control and Status (ICSR) register in the Cortex-M3.
Software must check the cause of the interrupt in order to distinguish among the sources.
6.2.3.1
NMI Pin
The alternate function to GPIO port pin B7 is an NMI signal. The alternate function must be enabled
in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs
(GPIOs)” on page 304. Note that enabling the NMI alternate function requires the use of the GPIO
lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see
page 342. The active sense of the NMI signal is High; asserting the enabled NMI signal above VIH
initiates the NMI interrupt sequence.
6.2.3.2
Main Oscillator Verification Failure
The LM3S9B95 microcontroller provides a main oscillator verification circuit that generates an error
condition if the oscillator is running too fast or two slow. The main oscillator verification circuit can
be programmed to generate a reset event, at which time a Power-on Reset is generated and control
is transferred to the NMI handler. The NMI handler is used to address the main oscillator verification
failure because the necessary code can be removed from the general reset handler, speeding up
reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator
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Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator
fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit
action is described in more detail in “Main Oscillator Verification Circuit” on page 114.
6.2.4
Power Control
®
The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the microcontroller's internal logic. For power reduction, a non-programmable LDO
may be used to scale the microcontroller’s 3.3 V input voltage to 1.2V. The voltage output has a
minimum voltage of 1.08 V and a maximum of 1.35 V. The LDO delivers up to 60 ma.
Figure 6-4 shows the power architecture.
Note:
On the printed circuit board, use the LDO output as the source of VDDC input. In addition,
the LDO requires decoupling capacitors. See “On-Chip Low Drop-Out (LDO) Regulator
Characteristics” on page 1206.
Figure 6-4. Power Architecture
VDDC
Internal
Logic and PLL
VDDC
GND
GND
LDO
Low-Noise
LDO
+3.3V
VDD
GND
I/O Buffers
VDD
VDDA
VDDA
6.2.5
GND
Analog Circuits
(ADC, Analog
Comparators)
GNDA
GNDA
Clock Control
System control determines the control of clocks in this part.
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6.2.5.1
Fundamental Clock Sources
There are multiple clock sources for use in the microcontroller:
■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock
source that is the clock source the microcontroller uses during and following POR. It does not
require the use of any external components and provides a clock that is 16 MHz ±1% at room
temperature and ±3% across temperature. The PIOSC allows for a reduced system cost in
applications that require an accurate clock source. If the main oscillator is required, software
must enable the main oscillator following reset and allow the main oscillator to stabilize before
changing the clock reference.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 16.384 MHz. The single-ended clock source range is from DC
through the specified speed of the microcontroller. The supported crystals are listed in the XTAL
bit field in the RCC register (see page 129). Note that the MOSC must have a clock source for
the USB PLL.
■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator provides an operational frequency of
30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings
mode benefits from reduced internal switching and also allows the MOSC and PIOSC to be
powered down.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%).
The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz
(inclusive). Table 6-4 on page 108 shows how the various clock sources can be used in a system.
Table 6-4. Clock Source Options
6.2.5.2
Clock Source
Drive PLL?
Precision Internal Oscillator
Yes
Used as SysClk?
BYPASS = 0, OSCSRC =
0x1
Yes
BYPASS = 1, OSCSRC = 0x1
Precision Internal Oscillator divide No
by 4 (4 MHz ± 1%)
BYPASS = 1
Yes
BYPASS = 1, OSCSRC = 0x2
Main Oscillator
Yes
BYPASS = 0, OSCSRC =
0x0
Yes
BYPASS = 1, OSCSRC = 0x0
Internal 30-kHz Oscillator
No
BYPASS = 1
Yes
BYPASS = 1, OSCSRC = 0x3
Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
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■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 6-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. The ADC clock signal is automatically divided
down to 16 MHz for proper ADC operation. The PWM clock signal is a synchronous divide of the
system clock to provide the PWM circuit with more range (set with PWMDIV in RCC).
Note:
When the ADC module is in operation, the system clock must be at least 16 MHz.
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Figure 6-5. Main Clock Tree
XTALa
USBPWRDN c
USB PLL
(240 MHz)
÷4
USB Clock
RXINT
RXFRAC
I2S Receive MCLK
TXINT
TXFRAC
I2S Transmit MCLK
USEPWMDIV a
PWMDW a
PWM Clock
XTALa
PWRDN b
MOSCDIS a
PLL
(400 MHz)
Main OSC
USESYSDIV a,d
DIV400 c
÷2
IOSCDIS
a
System Clock
Precision
Internal OSC
(16 MHz)
SYSDIV e
÷4
BYPASS
Internal OSC
(30 kHz)
Hibernation
OSC
(32.768 kHz)
b,d
PWRDN
ADC Clock
OSCSRC b,d
÷ 25
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or
[SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
Note:
The figure above shows all features available on all Stellaris® Tempest-class microcontrollers.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 6-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 6-4 on page 108.
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Table 6-5. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
Divisor
a
Frequency (BYPASS=0) Frequency (BYPASS=1)
StellarisWare Parameter
b
0x0
/1
reserved
Clock source frequency/2
SYSCTL_SYSDIV_1
0x1
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x2
/3
66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x3
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
0x4
/5
40 MHz
Clock source frequency/5
SYSCTL_SYSDIV_5
0x5
/6
33.33 MHz
Clock source frequency/6
SYSCTL_SYSDIV_6
0x6
/7
28.57 MHz
Clock source frequency/7
SYSCTL_SYSDIV_7
0x7
/8
25 MHz
Clock source frequency/8
SYSCTL_SYSDIV_8
0x8
/9
22.22 MHz
Clock source frequency/9
SYSCTL_SYSDIV_9
0x9
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
0xA
/11
18.18 MHz
Clock source frequency/11
SYSCTL_SYSDIV_11
0xB
/12
16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
0xC
/13
15.38 MHz
Clock source frequency/13
SYSCTL_SYSDIV_13
0xD
/14
14.29 MHz
Clock source frequency/14
SYSCTL_SYSDIV_14
0xE
/15
13.33 MHz
Clock source frequency/15
SYSCTL_SYSDIV_15
0xF
/16
12.5 MHz (default)
Clock source frequency/16
SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 6-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 6-4 on page 108.
Table 6-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
SYSDIV2
Divisor
a
Frequency
(BYPASS2=0)
Frequency (BYPASS2=1)
StellarisWare Parameter
b
0x00
/1
reserved
Clock source frequency/2
SYSCTL_SYSDIV_1
0x01
/2
reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x02
/3
66.67 MHz
Clock source frequency/3
SYSCTL_SYSDIV_3
0x03
/4
50 MHz
Clock source frequency/4
SYSCTL_SYSDIV_4
...
...
...
...
...
0x09
/10
20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
...
...
...
...
...
0x3F
/64
3.125 MHz
Clock source frequency/64
SYSCTL_SYSDIV_64
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along
with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In
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this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus
one. Table 6-7 shows the frequency choices when DIV400 is set. When the DIV400 bit is clear,
SYSDIV2LSB is ignored, and the system clock frequency is determined as shown in Table
6-6 on page 111.
Table 6-7. Examples of Possible System Clock Frequencies with DIV400=1
b
StellarisWare Parameter
/2
reserved
-
0
/3
reserved
-
1
/4
reserved
-
0
/5
80 MHz
SYSCTL_SYSDIV_2_5
1
/6
66.67 MHz
SYSCTL_SYSDIV_3
0
/7
reserved
-
1
/8
50 MHz
SYSCTL_SYSDIV_4
0
/9
44.44 MHz
SYSCTL_SYSDIV_4_5
1
/10
40 MHz
SYSCTL_SYSDIV_5
...
...
...
...
...
0x3F
0
/127
3.15 MHz
SYSCTL_SYSDIV_63_5
1
/128
3.125 MHz
SYSCTL_SYSDIV_64
SYSDIV2LSB
0x00
reserved
0x01
0x02
0x03
0x04
Divisor
a
Frequency (BYPASS2=0)
SYSDIV2
a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
6.2.5.3
Precision Internal Oscillator Operation (PIOSC)
The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC
can be powered down by setting the IOSCDIS bit in the RCC register.
The PIOSC generates a 16 MHz clock with a ±1% accuracy at room temperatures. Across the
extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at
room temperature, however, the frequency can be trimmed for other voltage or temperature conditions
using software in one of two ways:
■ Default calibration: clear the UTEN bit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.
6.2.5.4
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise,
the range of supported crystals is 1 to 16.384 MHz.
The XTAL bit in the RCC register (see page 129) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
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6.2.5.5
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor.
To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the
Run-Mode Clock Configuration 2 (RCC2) register to be 0x1.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 134). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 27-10 on page 1208 shows the actual PLL frequency and error
for a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 129)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
6.2.5.6
USB PLL Frequency Configuration
The USB PLL is disabled by default during power-on reset and is enabled later by software. The
USB PLL must be enabled and running for proper USB function. The main oscillator is the only clock
reference for the USB PLL. The USB PLL is enabled by clearing the USBPWRDN bit of the RCC2
register. The XTAL bit field (Crystal Value) of the RCC register describes the available crystal choices.
The main oscillator must be connected to one of the following crystal values in order to correctly
generate the USB clock: 4, 5, 6, 8, 10, 12, or 16 MHz. Only these crystals provide the necessary
USB PLL VCO frequency to conform with the USB timing specifications.
6.2.5.7
PLL Modes
Both PLLs have two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 129 and page 137).
6.2.5.8
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is TREADY (see Table
27-9 on page 1208). During the relock time, the affected PLL is not usable as a clock reference.
Either PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter is defined to measure the TREADY requirement. The counter is clocked by the main
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). When the XTAL value is
greater than 0x0F, the down counter is set to 0x2400 to maintain the required lock time on higher
frequency crystal inputs. Hardware is provided to keep the PLL from being used as a system clock
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until the TREADY condition is met after one of the two changes above. It is the user's responsibility
to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched
to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
The USB PLL is not protected during the lock time (TREADY), and software should ensure that the
USB PLL has locked before using the interface. Software can use many methods to ensure the
TREADY period has passed, including periodically polling the USBPLLLRIS bit in the Raw Interrupt
Status (RIS) register, and enabling the USB PLL Lock interrupt.
6.2.5.9
Main Oscillator Verification Circuit
The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, the following sequence is performed by the
hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. If the internal oscillator (PIOSC) is disabled, it is enabled.
3. The system clock is switched from the main oscillator to the PIOSC.
4. An internal power-on reset is initiated that lasts for 32 PIOSC periods.
5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
6.2.6
System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and
Deep-Sleep mode, respectively. The DC1 , DC2 and DC4 registers act as a write mask for the
RCGCn , SCGCn, and DCGCn registers.
There are three levels of operation for the microcontroller defined as:
■ Run Mode. In Run mode, the microcontroller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.
■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction.
Any properly configured interrupt event in the system brings the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
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Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the microcontroller to Run mode from one of the sleep modes; the
sleep modes are entered on request from the code. Deep-Sleep mode is entered by first writing
the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing
a WFI instruction. Any properly configured interrupt event in the system brings the processor
back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical
Reference Manual for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used, the internal
oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is
running at the time of the WFI instruction, hardware powers the PLL down and overrides the
SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in
the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event
occurs, hardware brings the system clock back to the source and frequency it had at the onset
of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration. If the PIOSC is used as the PLL reference clock source, it may continue to provide the
clock during Deep-Sleep. See page 141.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode configuration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
6.3
Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a “raw” clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
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3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
6.4
Register Map
Table 6-8 on page 116 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note:
Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 209.
Table 6-8. System Control Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
DID0
RO
-
Device Identification 0
118
0x004
DID1
RO
-
Device Identification 1
146
0x008
DC0
RO
0x017F.007F
Device Capabilities 0
148
0x010
DC1
RO
-
Device Capabilities 1
149
0x014
DC2
RO
0x570F.5337
Device Capabilities 2
152
0x018
DC3
RO
0xBFFF.FFFF
Device Capabilities 3
155
0x01C
DC4
RO
0x5100.F1FF
Device Capabilities 4
158
0x020
DC5
RO
0x0F30.00FF
Device Capabilities 5
160
0x024
DC6
RO
0x0000.0013
Device Capabilities 6
162
0x028
DC7
RO
0xFFFF.FFFF
Device Capabilities 7
163
0x02C
DC8
RO
0xFFFF.FFFF
Device Capabilities 8 ADC Channels
167
0x030
PBORCTL
R/W
0x0000.7FFD
Brown-Out Reset Control
120
0x040
SRCR0
R/W
0x00000000
Software Reset Control 0
202
0x044
SRCR1
R/W
0x00000000
Software Reset Control 1
204
0x048
SRCR2
R/W
0x00000000
Software Reset Control 2
207
0x050
RIS
RO
0x0000.0000
Raw Interrupt Status
121
0x054
IMC
R/W
0x0000.0000
Interrupt Mask Control
123
0x058
MISC
R/W1C
0x0000.0000
Masked Interrupt Status and Clear
125
0x05C
RESC
R/W
-
Reset Cause
127
0x060
RCC
R/W
0x078E.3AD1
Run-Mode Clock Configuration
129
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Table 6-8. System Control Register Map (continued)
Offset
Name
Type
Reset
0x064
PLLCFG
RO
-
0x06C
GPIOHBCTL
R/W
0x070
RCC2
0x07C
Description
See
page
XTAL to PLL Translation
134
0x0000.0000
GPIO High-Performance Bus Control
135
R/W
0x07C0.6810
Run-Mode Clock Configuration 2
137
MOSCCTL
R/W
0x0000.0000
Main Oscillator Control
140
0x100
RCGC0
R/W
0x00000040
Run Mode Clock Gating Control Register 0
173
0x104
RCGC1
R/W
0x00000000
Run Mode Clock Gating Control Register 1
181
0x108
RCGC2
R/W
0x00000000
Run Mode Clock Gating Control Register 2
193
0x110
SCGC0
R/W
0x00000040
Sleep Mode Clock Gating Control Register 0
176
0x114
SCGC1
R/W
0x00000000
Sleep Mode Clock Gating Control Register 1
185
0x118
SCGC2
R/W
0x00000000
Sleep Mode Clock Gating Control Register 2
196
0x120
DCGC0
R/W
0x00000040
Deep Sleep Mode Clock Gating Control Register 0
179
0x124
DCGC1
R/W
0x00000000
Deep-Sleep Mode Clock Gating Control Register 1
189
0x128
DCGC2
R/W
0x00000000
Deep Sleep Mode Clock Gating Control Register 2
199
0x144
DSLPCLKCFG
R/W
0x0780.0000
Deep Sleep Clock Configuration
141
0x150
PIOSCCAL
R/W
0x0000.0000
Precision Internal Oscillator Calibration
143
0x170
I2SMCLKCFG
R/W
0x0000.0000
I2S MCLK Configuration
144
0x190
DC9
RO
0x00FF.00FF
Device Capabilities 9 ADC Digital Comparators
170
0x1A0
NVMSTAT
RO
0x0000.0001
Non-Volatile Memory Information
172
6.5
Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
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Texas Instruments-Advance Information
System Control
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the microcontroller.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset 31
30
28
27
26
VER
reserved
Type
Reset
29
25
24
23
22
21
20
reserved
18
17
16
CLASS
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
MAJOR
Type
Reset
19
MINOR
Bit/Field
Name
Type
Reset
31
reserved
RO
0
30:28
VER
RO
0x1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1
Second version of the DID0 register format.
27:24
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23:16
CLASS
RO
0x04
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all microcontrollers in a particular product line.
The CLASS field value is changed for new product lines, for changes in
fab process (for example, a remap or shrink), or any case where the
MAJOR or MINOR fields require differentiation from prior microcontrollers.
The value of the CLASS field is encoded as follows (all other encodings
are reserved):
Value Description
0x04 Stellaris® Tempest-class microcontrollers
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
15:8
MAJOR
RO
-
Description
Major Revision
This field specifies the major revision number of the microcontroller.
The major revision reflects changes to base layers of the design. The
major revision number is indicated in the part number as a letter (A for
first revision, B for second, and so on). This field is encoded as follows:
Value Description
0x0
Revision A (initial device)
0x1
Revision B (first base layer revision)
0x2
Revision C (second base layer revision)
and so on.
7:0
MINOR
RO
-
Minor Revision
This field specifies the minor revision number of the microcontroller.
The minor revision reflects changes to the metal layers of the design.
The MINOR field value is reset when the MAJOR field is changed. This
field is numeric and is encoded as follows:
Value Description
0x0
Initial device, or a major revision update.
0x1
First metal layer change.
0x2
Second metal layer change.
and so on.
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System Control
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
BORIOR
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
BORIOR
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
BOR Interrupt or Reset
Value Description
0
reserved
RO
0
0
A Brown Out Event causes an interrupt to be generated to the
interrupt controller.
1
A Brown Out Event causes a reset of the microcontroller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Register 3: Raw Interrupt Status (RIS), offset 0x050
This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt
controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1
to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt
status bit.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
BORRIS
reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPRIS USBPLLLRIS
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
MOSCPUPRIS
RO
0
RO
0
RO
0
PLLLRIS
RO
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Power Up Raw Interrupt Status
Value Description
1
Sufficient time has passed for the MOSC to reach the expected
frequency. The value for this power-up time is indicated by
TMOSC_SETTLE.
0
Sufficient time has not passed for the MOSC to reach the
expected frequency.
This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC
register.
7
USBPLLLRIS
RO
0
USB PLL Lock Raw Interrupt Status
Value Description
1
The USB PLL timer has reached TREADY indicating that sufficient
time has passed for the USB PLL to lock.
0
The USB PLL timer has not reached TREADY.
This bit is cleared by writing a 1 to the USBPLLLMIS bit in the MISC
register.
6
PLLLRIS
RO
0
PLL Lock Raw Interrupt Status
Value Description
1
The PLL timer has reached TREADY indicating that sufficient time
has passed for the PLL to lock.
0
The PLL timer has not reached TREADY.
This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register.
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System Control
Bit/Field
Name
Type
Reset
5:2
reserved
RO
0x0
1
BORRIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Brown-Out Reset Raw Interrupt Status
Value Description
1
A brown-out condition is currently active.
0
A brown-out condition is not currently active.
Note the BORIOR bit in the PBORCTL register must be cleared to cause
an interrupt due to a Brown Out Event.
This bit is cleared by writing a 1 to the BORMIS bit in the MISC register.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 4: Interrupt Mask Control (IMC), offset 0x054
This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by
a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the
corresponding bit in this register is set.
Interrupt Mask Control (IMC)
Base 0x400F.E000
Offset 0x054
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
BORIM
reserved
RO
0
RO
0
RO
0
RO
0
R/W
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPIM USBPLLLIM
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
MOSCPUPIM
R/W
0
R/W
0
R/W
0
PLLLIM
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Power Up Interrupt Mask
Value Description
7
USBPLLLIM
R/W
0
1
An interrupt is sent to the interrupt controller when the
MOSCPUPRIS bit in the RIS register is set.
0
The MOSCPUPRIS interrupt is suppressed and not sent to the
interrupt controller.
USB PLL Lock Interrupt Mask
Value Description
6
PLLLIM
R/W
0
1
An interrupt is sent to the interrupt controller when the
USBPLLLRIS bit in the RIS register is set.
0
The USBPLLLRIS interrupt is suppressed and not sent to the
interrupt controller.
PLL Lock Interrupt Mask
Value Description
5:2
reserved
RO
0x0
1
An interrupt is sent to the interrupt controller when the PLLLRIS
bit in the RIS register is set.
0
The PLLLRIS interrupt is suppressed and not sent to the
interrupt controller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
1
BORIM
R/W
0
Description
Brown-Out Reset Interrupt Mask
Value Description
0
reserved
RO
0
1
An interrupt is sent to the interrupt controller when the BORRIS
bit in the RIS register is set.
0
The BORRIS interrupt is suppressed and not sent to the interrupt
controller.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt in the
Raw Interrupt Status (RIS) register. All of the bits are R/W1C, thus writing a 1 to a bit clears the
corresponding raw interrupt bit in the RIS register (see page 121).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
BORMIS
reserved
RO
0
RO
0
RO
0
RO
0
R/W1C
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
MOSCPUPMIS USBPLLLMIS
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.00
8
MOSCPUPMIS
R/W1C
0
R/W1C
0
R/W1C
0
PLLLMIS
R/W1C
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Power Up Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the MOSC PLL
to lock.
Writing a 1 to this bit clears it and also the MOSCPUPRIS bit in
the RIS register.
0
When read, a 0 indicates that sufficient time has not passed for
the MOSC PLL to lock.
A write of 0 has no effect on the state of this bit.
7
USBPLLLMIS
R/W1C
0
USB PLL Lock Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the USB PLL
to lock.
Writing a 1 to this bit clears it and also the USBPLLLRIS bit in
the RIS register.
0
When read, a 0 indicates that sufficient time has not passed for
the USB PLL to lock.
A write of 0 has no effect on the state of this bit.
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
6
PLLLMIS
R/W1C
0
Description
PLL Lock Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because sufficient time has passed for the PLL to lock.
Writing a 1 to this bit clears it and also the PLLLRIS bit in the
RIS register.
0
When read, a 0 indicates that sufficient time has not passed for
the PLL to lock.
A write of 0 has no effect on the state of this bit.
5:2
reserved
RO
0x0
1
BORMIS
R/W1C
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
BOR Masked Interrupt Status
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because of a brown-out condition.
Writing a 1 to this bit clears it and also the BORRIS bit in the
RIS register.
0
When read, a 0 indicates that a brown-out condition has not
occurred.
A write of 0 has no effect on the state of this bit.
0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 6: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset 31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
-
9
8
7
6
5
4
3
2
1
0
WDT1
SW
WDT0
BOR
POR
EXT
RO
0
RO
0
RO
0
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
MOSCFAIL
reserved
Type
Reset
RO
0
16
Bit/Field
Name
Type
Reset
Description
31:17
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
MOSCFAIL
R/W
-
MOSC Failure Reset
Value Description
1
When read, this bit indicates that the MOSC circuit was enabled
for clock validation and failed, generating a reset event.
0
When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
15:6
reserved
RO
0x00
5
WDT1
R/W
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Watchdog Timer 1 Reset
Value Description
1
When read, this bit indicates that Watchdog Timer 1 timed out
and generated a reset.
0
When read, this bit indicates that Watchdog Timer 1 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
4
SW
R/W
-
Description
Software Reset
Value Description
1
When read, this bit indicates that a software reset has caused
a reset event.
0
When read, this bit indicates that a software reset has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
3
WDT0
R/W
-
Watchdog Timer 0 Reset
Value Description
1
When read, this bit indicates that Watchdog Timer 0 timed out
and generated a reset.
0
When read, this bit indicates that Watchdog Timer 0 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
2
BOR
R/W
-
Brown-Out Reset
Value Description
1
When read, this bit indicates that a brown-out reset has caused
a reset event.
0
When read, this bit indicates that a brown-out reset has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
1
POR
R/W
-
Power-On Reset
Value Description
1
When read, this bit indicates that a power-on reset has caused
a reset event.
0
When read, this bit indicates that a power-on reset has not
generated a reset.
Writing a 0 to this bit clears it.
0
EXT
R/W
-
External Reset
Value Description
1
When read, this bit indicates that an external reset (RST
assertion) has caused a reset event.
0
When read, this bit indicates that an external reset (RST
assertion) has not caused a reset event since the previous
power-on reset.
Writing a 0 to this bit clears it.
128
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060
The bits in this register configure the system clock and oscillators.
Run-Mode Clock Configuration (RCC)
Base 0x400F.E000
Offset 0x060
Type R/W, reset 0x078E.3AD1
31
30
29
28
26
25
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
1
15
14
13
12
11
PWRDN
reserved
BYPASS
R/W
1
RO
1
R/W
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
27
24
23
R/W
1
R/W
1
R/W
1
10
9
8
R/W
0
R/W
1
ACG
22
21
20
USESYSDIV
reserved
USEPWMDIV
R/W
0
RO
0
R/W
0
R/W
1
R/W
1
R/W
1
RO
0
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
0
R/W
1
RO
0
SYSDIV
XTAL
Bit/Field
Name
Type
Reset
31:28
reserved
RO
0x0
27
ACG
R/W
0
R/W
0
OSCSRC
19
18
17
PWMDIV
reserved
RO
0
16
reserved
IOSCDIS MOSCDIS
R/W
0
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Auto Clock Gating
This bit specifies whether the system uses the Sleep-Mode Clock
Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock
Gating Control (DCGCn) registers if the microcontroller enters a Sleep
or Deep-Sleep mode (respectively).
Value Description
1
The SCGCn or DCGCn registers are used to control the clocks
distributed to the peripherals when the microcontroller is in a
sleep mode. The SCGCn and DCGCn registers allow unused
peripherals to consume less power when the microcontroller is
in a sleep mode.
0
The Run-Mode Clock Gating Control (RCGCn) registers are
used when the microcontroller enters a sleep mode.
The RCGCn registers are always used to control the clocks in Run
mode.
26:23
SYSDIV
R/W
0xF
System Clock Divisor
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS
bit in this register is configured). See Table 6-5 on page 111 for bit
encodings.
If the SYSDIV value is less than MINSYSDIV (see page 149), and the
PLL is being used, then the MINSYSDIV value is used as the divisor.
If the PLL is not being used, the SYSDIV value can be less than
MINSYSDIV.
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
22
USESYSDIV
R/W
0
Description
Enable System Clock Divider
Value Description
1
The system clock divider is the source for the system clock. The
system clock divider is forced to be used when the PLL is
selected as the source.
If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2
field in the RCC2 register is used as the system clock divider
rather than the SYSDIV field in this register.
0
The system clock is used undivided.
21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
USEPWMDIV
R/W
0
Enable PWM Clock Divisor
Value Description
19:17
PWMDIV
R/W
0x7
1
The PWM clock divider is the source for the PWM clock.
0
The system clock is the source for the PWM clock.
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. The rising
edge of this clock is synchronous with the system clock.
Value Divisor
16:14
reserved
RO
0x0
13
PWRDN
R/W
1
0x0
/2
0x1
/4
0x2
/8
0x3
/16
0x4
/32
0x5
/64
0x6
/64
0x7
/64 (default)
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Power Down
Value Description
1
The PLL is powered down. Care must be taken to ensure that
another clock source is functioning and that the BYPASS bit is
set before setting this bit.
0
The PLL is operating normally.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
12
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS
R/W
1
PLL Bypass
Value Description
1
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV.
0
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV.
See Table 6-5 on page 111 for programming guidelines.
Note:
The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
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System Control
Bit/Field
Name
Type
Reset
Description
10:6
XTAL
R/W
0x0B
Crystal Value
This field specifies the crystal value attached to the main oscillator. The
encoding for this field is provided below. Depending on the crystal used,
the PLL frequency may not be exactly 400 MHz, see Table
27-10 on page 1208 for more information.
Frequencies that may be used with the USB interface are indicated in
the table. To function within the clocking requirements of the USB
specification, a crystal of 4, 5, 6, 8, 10, 12, or 16 MHz must be used.
Value Crystal Frequency (MHz) Not Crystal Frequency (MHz) Using
Using the PLL
the PLL
0x00
1.000
reserved
0x01
1.8432
reserved
0x02
2.000
reserved
0x03
2.4576
reserved
0x04
3.579545 MHz
0x05
3.6864 MHz
0x06
4 MHz (USB)
0x07
4.096 MHz
0x08
4.9152 MHz
0x09
5 MHz (USB)
0x0A
5.12 MHz
0x0B
6 MHz (reset value)(USB)
0x0C
6.144 MHz
0x0D
7.3728 MHz
0x0E
8 MHz (USB)
0x0F
8.192 MHz
0x10
10.0 MHz (USB)
0x11
12.0 MHz (USB)
0x12
12.288 MHz
0x13
13.56 MHz
0x14
14.31818 MHz
0x15
16.0 MHz (USB)
0x16
16.384 MHz
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
5:4
OSCSRC
R/W
0x1
Description
Oscillator Source
Selects the input source for the OSC. The values are:
Value Input Source
0x0
MOSC
Main oscillator
0x1
PIOSC
Precision internal oscillator
(default)
0x2
PIOSC/4
Precision internal oscillator / 4
0x3
30 kHz
30-kHz internal oscillator
For additional oscillator sources, see the RCC2 register.
3:2
reserved
RO
0x0
1
IOSCDIS
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Precision Internal Oscillator Disable
Value Description
0
MOSCDIS
R/W
1
1
The precision internal oscillator (PIOSC) is disabled.
0
The precision internal oscillator is enabled.
Main Oscillator Disable
Value Description
1
The main oscillator is disabled (default).
0
The main oscillator is enabled.
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System Control
Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 129).
The PLL frequency is calculated using the PLLCFG field values, as follows:
PLLFreq = OSCFreq * F / (R + 1)
XTAL to PLL Translation (PLLCFG)
Base 0x400F.E000
Offset 0x064
Type RO, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
-
RO
-
RO
-
RO
-
RO
-
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
RO
0
F
Bit/Field
Name
Type
Reset
31:14
reserved
RO
0x0000.0
13:5
F
RO
-
R
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL F Value
This field specifies the value supplied to the PLL’s F input.
4:0
R
RO
-
PLL R Value
This field specifies the value supplied to the PLL’s R input.
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Stellaris® LM3S9B95 Microcontroller
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C
This register controls which internal bus is used to access each GPIO port. When a bit is clear, the
corresponding GPIO port is accessed across the legacy Advanced Peripheral Bus (APB) bus and
through the APB memory aperture. When a bit is set, the corresponding port is accessed across
the Advanced High-Performance Bus (AHB) bus and through the AHB memory aperture. Each
GPIO port can be individually configured to use AHB or APB, but may be accessed only through
one aperture. The AHB bus provides better back-to-back access performance than the APB bus.
The address aperture in the memory map changes for the ports that are enabled for AHB access
(see Table 9-7 on page 316).
GPIO High-Performance Bus Control (GPIOHBCTL)
Base 0x400F.E000
Offset 0x06C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:9
reserved
RO
0x0000.0
8
PORTJ
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port J Advanced High-Performance Bus
This bit defines the memory aperture for Port J.
Value Description
7
PORTH
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port H Advanced High-Performance Bus
This bit defines the memory aperture for Port H.
Value Description
6
PORTG
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port G Advanced High-Performance Bus
This bit defines the memory aperture for Port G.
Value Description
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
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System Control
Bit/Field
Name
Type
Reset
5
PORTF
R/W
0
Description
Port F Advanced High-Performance Bus
This bit defines the memory aperture for Port F.
Value Description
4
PORTE
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port E Advanced High-Performance Bus
This bit defines the memory aperture for Port E.
Value Description
3
PORTD
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port D Advanced High-Performance Bus
This bit defines the memory aperture for Port D.
Value Description
2
PORTC
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port C Advanced High-Performance Bus
This bit defines the memory aperture for Port C.
Value Description
1
PORTB
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port B Advanced High-Performance Bus
This bit defines the memory aperture for Port B.
Value Description
0
PORTA
R/W
0
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
Port A Advanced High-Performance Bus
This bit defines the memory aperture for Port A.
Value Description
1
Advanced High-Performance Bus (AHB)
0
Advanced Peripheral Bus (APB). This bus is the legacy bus.
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Stellaris® LM3S9B95 Microcontroller
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070
This register overrides the RCC equivalent register fields, as shown in Table 6-9, when the USERCC2
bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a
means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC
field is located at the same LSB bit position; however, some RCC2 fields are larger than the
corresponding RCC field.
Table 6-9. RCC2 Fields that Override RCC fields
RCC2 Field...
Overrides RCC Field
SYSDIV2, bits[28:23]
SYSDIV, bits[26:23]
PWRDN2, bit[13]
PWRDN, bit[13]
BYPASS2, bit[11]
BYPASS, bit[11]
OSCSRC2, bits[6:4]
OSCSRC, bits[5:4]
Run-Mode Clock Configuration 2 (RCC2)
Base 0x400F.E000
Offset 0x070
Type R/W, reset 0x07C0.6810
31
30
USERCC2 DIV400
Type
Reset
Type
Reset
R/W
0
R/W
0
29
28
27
26
25
24
23
SYSDIV2
reserved
RO
0
R/W
0
22
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
10
9
8
7
6
15
14
13
12
11
reserved
USBPWRDN
PWRDN2
reserved
BYPASS2
RO
0
R/W
1
R/W
1
RO
0
R/W
1
reserved
RO
0
21
20
19
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31
USERCC2
R/W
0
Use RCC2
R/W
0
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
RO
0
RO
0
OSCSRC2
RO
0
18
reserved
SYSDIV2LSB
R/W
0
reserved
R/W
1
RO
0
RO
0
Value Description
30
DIV400
R/W
0
1
The RCC2 register fields override the RCC register fields.
0
The RCC register fields are used, and the fields in RCC2 are
ignored.
Divide PLL as 400 MHz vs. 200 MHz
This bit, along with the SYSDIV2LSB bit, allows additional frequency
choices.
Value Description
29
reserved
RO
0x0
1
Append the SYSDIV2LSB bit to the SYSDIV2 field to create a
7 bit divisor using the 400 MHz PLL output, see Table
6-7 on page 112.
0
Use SYSDIV2 as is and apply to 200 MHz predivided PLL
output. See Table 6-6 on page 111 for programming guidelines.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
Description
28:23
SYSDIV2
R/W
0x0F
System Clock Divisor 2
Specifies which divisor is used to generate the system clock from either
the PLL output or the oscillator source (depending on how the BYPASS2
bit is configured). SYSDIV2 is used for the divisor when both the
USESYSDIV bit in the RCC register and the USERCC2 bit in this register
are set. See Table 6-6 on page 111 for programming guidelines.
22
SYSDIV2LSB
R/W
1
Additional LSB for SYSDIV2
When DIV400 is set, this bit becomes the LSB of SYSDIV2. If DIV400
is clear, this bit is not used. See Table 6-6 on page 111 for programming
guidelines.
This bit can only be set or cleared when DIV400 is set.
21:15
reserved
RO
0x0
14
USBPWRDN
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Power-Down USB PLL
Value Description
13
PWRDN2
R/W
1
1
The USB PLL is powered down.
0
The USB PLL operates normally.
Power-Down PLL 2
Value Description
1
The PLL is powered down.
0
The PLL operates normally.
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11
BYPASS2
R/W
1
PLL Bypass 2
Value Description
1
The system clock is derived from the OSC source and divided
by the divisor specified by SYSDIV2.
0
The system clock is the PLL output clock divided by the divisor
specified by SYSDIV2.
See Table 6-6 on page 111 for programming guidelines.
Note:
10:7
reserved
RO
0x0
The ADC must be clocked from the PLL or directly from a
16-MHz clock source to operate properly.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
6:4
OSCSRC2
R/W
0x1
Description
Oscillator Source 2
Selects the input source for the OSC. The values are:
Value
Description
0x0
MOSC
Main oscillator
0x1
PIOSC
Precision internal oscillator
0x2
PIOSC/4
Precision internal oscillator / 4
0x3
30 kHz
30-kHz internal oscillator
0x4-0x7 Reserved
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C
This register provides the ability to enable the MOSC clock verification circuit. When enabled, this
circuit monitors the frequency of the MOSC to verify that the oscillator is operating within specified
limits. If the clock goes invalid after being enabled, the microcontroller issues a power-on reset and
reboots to the NMI handler.
Main Oscillator Control (MOSCCTL)
Base 0x400F.E000
Offset 0x07C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
CVAL
R/W
0
RO
0
CVAL
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Validation for MOSC
Value Description
1
The MOSC monitor circuit is enabled.
0
The MOSC monitor circuit is disabled.
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Stellaris® LM3S9B95 Microcontroller
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144
This register provides configuration information for the hardware control of Deep Sleep Mode.
Deep Sleep Clock Configuration (DSLPCLKCFG)
Base 0x400F.E000
Offset 0x144
Type R/W, reset 0x0780.0000
31
30
29
28
27
26
reserved
Type
Reset
25
24
23
22
21
20
DSDIVORIDE
18
17
16
reserved
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
19
RO
0
DSOSCSRC
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28:23
DSDIVORIDE
R/W
0x0F
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Divider Field Override
If Deep-Sleep mode is enabled when the PLL is running, the PLL is
disabled. This 6-bit field contains a system divider field that overrides
the SYSDIV field in the RCC register or the SYSDIV2 field in the RCC2
register during Deep Sleep. This divider is applied to the source selected
by the DSOSCSRC field.
Value Description
0x0
/1
0x1
/2
0x2
/3
0x3
/4
...
...
0x3F /64
22:7
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Bit/Field
Name
Type
Reset
6:4
DSOSCSRC
R/W
0x0
Description
Clock Source
Specifies the clock source during Deep-Sleep mode.
Value
Description
0x0
MOSC
Use the main oscillator as the source.
Note:
0x1
If the PIOSC is being used as the clock reference
for the PLL, the PIOSC is the clock source instead
of MOSC in Deep-Sleep mode.
PIOSC
Use the precision internal 16-MHz oscillator as the source.
0x2
Reserved
0x3
30 kHz
Use the 30-kHz internal oscillator as the source.
0x4-0x7 Reserved
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150
This register provides the ability to update or recalibrate the precision internal oscillator.
Precision Internal Oscillator Calibration (PIOSCCAL)
Base 0x400F.E000
Offset 0x150
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
22
21
20
19
18
17
16
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
UPDATE
reserved
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
UTEN
Type
Reset
reserved
reserved
Type
Reset
23
RO
0
Bit/Field
Name
Type
Reset
31
UTEN
R/W
0
UT
Description
Use User Trim Value
Value Description
30:9
reserved
RO
0x0000
8
UPDATE
R/W
0
1
The trim value in bits[6:0] of this register are used for any update
trim operation.
0
The factory calibration value is used for an update trim operation.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Update Trim
Value Description
1
Updates the PIOSC trim value with the UT bit or the DT bit in
the PIOSCSTAT register. Used with UTEN.
0
No action.
This bit is auto-cleared after the update.
7
reserved
RO
0
6:0
UT
R/W
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
User Trim Value
User trim value that can be loaded into the PIOSC.
Refer to “Main PLL Frequency Configuration” on page 113 for more
information on calibrating the PIOSC.
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System Control
Register 14: I2S MCLK Configuration (I2SMCLKCFG), offset 0x170
This register configures the receive and transmit fractional clock dividers for the for the I2S master
transmit and receive clocks (I2S0TXMCLK and I2S0RXMCLK) . Varying the integer and fractional
inputs for the clocks allows greater accuracy in hitting the target I2S clock frequencies. Refer to
“Clock Control” on page 730 for combinations of the TXI and TXF bits and the RXI and RXF bits that
provide MCLK frequencies within acceptable error limits.
I2S MCLK Configuration (I2SMCLKCFG)
Base 0x400F.E000
Offset 0x170
Type R/W, reset 0x0000.0000
Type
Reset
Type
Reset
31
30
RXEN
reserved
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
13
12
11
10
9
15
14
TXEN
reserved
R/W
0
RO
0
29
28
27
26
25
24
23
22
21
20
19
18
RXI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
8
7
6
5
4
3
2
TXI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31
RXEN
R/W
0
17
16
R/W
0
R/W
0
1
0
R/W
0
R/W
0
RXF
TXF
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
RX Clock Enable
Value Description
1
The I2S receive clock generator is enabled.
0
The I2S receive clock generator is disabled.
If the RXSLV bit in the I2S Module Configuration (I2SCFG)
register is set, then the I2S0RXMCLK must be externally
generated.
30
reserved
RO
0
29:20
RXI
R/W
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RX Clock Integer Input
This field contains the integer input for the receive clock generator.
19:16
RXF
R/W
0x0
RX Clock Fractional Input
This field contains the fractional input for the receive clock generator.
15
TXEN
R/W
0
TX Clock Enable
Value Description
1
The I2S transmit clock generator is enabled.
0
The I2S transmit clock generator is disabled.
If the TXSLV bit in the I2S Module Configuration (I2SCFG)
register is set, then the I2S0TXMCLK must be externally
generated.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
14
reserved
RO
0
13:4
TXI
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
TX Clock Integer Input
This field contains the integer input for the transmit clock generator.
3:0
TXF
R/W
0x0
TX Clock Fractional Input
This field contains the fractional input for the transmit clock generator.
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System Control
Register 15: Device Identification 1 (DID1), offset 0x004
This register identifies the device family, part number, temperature range, and package type.
Device Identification 1 (DID1)
Base 0x400F.E000
Offset 0x004
Type RO, reset 31
30
29
28
27
26
RO
0
15
25
24
23
22
21
20
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
14
13
12
11
10
9
8
7
6
5
4
RO
0
RO
0
RO
0
RO
0
RO
0
RO
-
RO
-
RO
-
VER
Type
Reset
FAM
PINCOUNT
Type
Reset
RO
0
RO
1
18
17
16
RO
1
RO
1
RO
1
RO
0
3
2
1
0
PARTNO
reserved
RO
0
19
TEMP
Bit/Field
Name
Type
Reset
31:28
VER
RO
0x1
RO
-
PKG
ROHS
RO
-
RO
1
QUAL
RO
-
RO
-
Description
DID1 Version
This field defines the DID1 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
Value Description
0x1
27:24
FAM
RO
0x0
Second version of the DID1 register format.
Family
This field provides the family identification of the device within the
Luminary Micro product portfolio. The value is encoded as follows (all
other encodings are reserved):
Value Description
0x0
23:16
PARTNO
RO
0x6E
Stellaris family of microcontollers, that is, all devices with
external part numbers starting with LM3S.
Part Number
This field provides the part number of the device within the family. The
value is encoded as follows (all other encodings are reserved):
Value Description
0x6E LM3S9B95
15:13
PINCOUNT
RO
0x2
Package Pin Count
This field specifies the number of pins on the device package. The value
is encoded as follows (all other encodings are reserved):
Value Description
0x2
100-pin package
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
12:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:5
TEMP
RO
-
Temperature Range
This field specifies the temperature rating of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
4:3
PKG
RO
-
0x0
Commercial temperature range (0°C to 70°C)
0x1
Industrial temperature range (-40°C to 85°C)
0x2
Extended temperature range (-40°C to 105°C)
Package Type
This field specifies the package type. The value is encoded as follows
(all other encodings are reserved):
Value Description
2
ROHS
RO
1
0x0
SOIC package
0x1
LQFP package
0x2
BGA package
RoHS-Compliance
This bit specifies whether the device is RoHS-compliant. A 1 indicates
the part is RoHS-compliant.
1:0
QUAL
RO
-
Qualification Status
This field specifies the qualification status of the device. The value is
encoded as follows (all other encodings are reserved):
Value Description
0x0
Engineering Sample (unqualified)
0x1
Pilot Production (unqualified)
0x2
Fully Qualified
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System Control
Register 16: Device Capabilities 0 (DC0), offset 0x008
This register is predefined by the part and can be used to verify features.
Device Capabilities 0 (DC0)
Base 0x400F.E000
Offset 0x008
Type RO, reset 0x017F.007F
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
SRAMSZ
Type
Reset
FLASHSZ
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
Description
31:16
SRAMSZ
RO
0x017F
SRAM Size
Indicates the size of the on-chip SRAM memory.
Value
Description
0x017F 96 KB of SRAM
15:0
FLASHSZ
RO
0x007F
Flash Size
Indicates the size of the on-chip flash memory.
Value
Description
0x007F 256 KB of Flash
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Stellaris® LM3S9B95 Microcontroller
Register 17: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 31
30
29
reserved
Type
Reset
28
WDT1
26
24
23
22
21
19
16
CAN1
CAN0
ADC1
ADC0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MPU
reserved
TEMPSNS
PLL
WDT0
SWO
SWD
JTAG
RO
-
RO
-
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
MAXADC0SPD
RO
1
RO
1
RO
1
RO
1
reserved
17
RO
1
MAXADC1SPD
PWM
18
RO
0
RO
-
reserved
20
RO
0
RO
-
reserved
25
RO
0
MINSYSDIV
Type
Reset
27
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
RO
1
Watchdog Timer1 Present
When set, indicates that watchdog timer 1 is present.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
RO
1
CAN Module 1 Present
When set, indicates that CAN unit 1 is present.
24
CAN0
RO
1
CAN Module 0 Present
When set, indicates that CAN unit 0 is present.
23:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
RO
1
PWM Module Present
When set, indicates that the PWM module is present.
19:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
RO
1
ADC Module 1 Present
When set, indicates that ADC module 1 is present.
16
ADC0
RO
1
ADC Module 0 Present
When set, indicates that ADC module 0 is present
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System Control
Bit/Field
Name
Type
Reset
15:12
MINSYSDIV
RO
-
Description
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
11:10
MAXADC1SPD
RO
0x3
0x1
Divide VCO (400MHZ) by 5 minimum
0x2
Divide VCO (400MHZ) by 2*2 + 2 = 6 minimum
0x3
Specifies a 50-MHz CPU clock with a PLL divider of 4.
0x7
Specifies a 25-MHz clock with a PLL divider of 8.
0x9
Specifies a 20-MHz clock with a PLL divider of 10.
Max ADC1 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
0x3
9:8
MAXADC0SPD
RO
0x3
1M samples/second
Max ADC0 Speed
This field indicates the maximum rate at which the ADC samples data.
Value Description
0x3
7
MPU
RO
1
1M samples/second
MPU Present
When set, indicates that the Cortex-M3 Memory Protection Unit (MPU)
module is present. See the ARM Cortex-M3 Technical Reference Manual
for details on the MPU.
6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
TEMPSNS
RO
1
Temp Sensor Present
When set, indicates that the on-chip temperature sensor is present.
4
PLL
RO
1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
3
WDT0
RO
1
Watchdog Timer 0 Present
When set, indicates that watchdog timer 0 is present.
2
SWO
RO
1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1
SWD
RO
1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
0
JTAG
RO
1
Description
JTAG Present
When set, indicates that the JTAG debugger interface is present.
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System Control
Register 18: Device Capabilities 2 (DC2), offset 0x014
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 2 (DC2)
Base 0x400F.E000
Offset 0x014
Type RO, reset 0x570F.5337
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
RO
1
RO
0
RO
1
RO
0
RO
1
RO
1
15
14
13
12
11
10
reserved
I2C1
reserved
I2C0
RO
0
RO
1
RO
0
RO
1
reserved
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
1
RO
0
RO
0
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
RO
1
RO
1
RO
1
RO
1
9
8
7
6
5
4
3
2
1
0
QEI1
QEI0
RO
1
RO
1
SSI1
SSI0
reserved
UART2
UART1
UART0
RO
1
RO
1
RO
0
RO
1
RO
1
RO
1
reserved
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
RO
1
EPI Module 0 Present
When set, indicates that EPI module 0 is present.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
RO
1
I2S Module 0 Present
When set, indicates that I2S module 0 is present.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
COMP2
RO
1
Analog Comparator 2 Present
When set, indicates that analog comparator 2 is present.
25
COMP1
RO
1
Analog Comparator 1 Present
When set, indicates that analog comparator 1 is present.
24
COMP0
RO
1
Analog Comparator 0 Present
When set, indicates that analog comparator 0 is present.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
RO
1
Timer Module 3 Present
When set, indicates that General-Purpose Timer module 3 is present.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
18
TIMER2
RO
1
Description
Timer Module 2 Present
When set, indicates that General-Purpose Timer module 2 is present.
17
TIMER1
RO
1
Timer Module 1 Present
When set, indicates that General-Purpose Timer module 1 is present.
16
TIMER0
RO
1
Timer Module 0 Present
When set, indicates that General-Purpose Timer module 0 is present.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
RO
1
I2C Module 1 Present
When set, indicates that I2C module 1 is present.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
RO
1
I2C Module 0 Present
When set, indicates that I2C module 0 is present.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
QEI1
RO
1
QEI Module 1 Present
When set, indicates that QEI module 1 is present.
8
QEI0
RO
1
QEI Module 0 Present
When set, indicates that QEI module 0 is present.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
RO
1
SSI Module 1 Present
When set, indicates that SSI module 1 is present.
4
SSI0
RO
1
SSI Module 0 Present
When set, indicates that SSI module 0 is present.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
RO
1
UART Module 2 Present
When set, indicates that UART module 2 is present.
1
UART1
RO
1
UART Module 1 Present
When set, indicates that UART module 1 is present.
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System Control
Bit/Field
Name
Type
Reset
0
UART0
RO
1
Description
UART Module 0 Present
When set, indicates that UART module 0 is present.
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Stellaris® LM3S9B95 Microcontroller
Register 19: Device Capabilities 3 (DC3), offset 0x018
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 3 (DC3)
Base 0x400F.E000
Offset 0x018
Type RO, reset 0xBFFF.FFFF
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
32KHZ
reserved
CCP5
CCP4
CCP3
CCP2
CCP1
CCP0
RO
1
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWMFAULT
C2O
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
C2PLUS C2MINUS
RO
1
RO
1
C1O
C1PLUS C1MINUS
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31
32KHZ
RO
1
C0O
RO
1
23
22
21
20
19
18
17
16
ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0
C0PLUS C0MINUS
RO
1
RO
1
Description
32KHz Input Clock Available
When set, indicates an even CCP pin is present and can be used as a
32-KHz input clock.
30
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
29
CCP5
RO
1
CCP5 Pin Present
When set, indicates that Capture/Compare/PWM pin 5 is present.
28
CCP4
RO
1
CCP4 Pin Present
When set, indicates that Capture/Compare/PWM pin 4 is present.
27
CCP3
RO
1
CCP3 Pin Present
When set, indicates that Capture/Compare/PWM pin 3 is present.
26
CCP2
RO
1
CCP2 Pin Present
When set, indicates that Capture/Compare/PWM pin 2 is present.
25
CCP1
RO
1
CCP1 Pin Present
When set, indicates that Capture/Compare/PWM pin 1 is present.
24
CCP0
RO
1
CCP0 Pin Present
When set, indicates that Capture/Compare/PWM pin 0 is present.
23
ADC0AIN7
RO
1
ADC Module 0 AIN7 Pin Present
When set, indicates that ADC module 0 input pin 7 is present.
22
ADC0AIN6
RO
1
ADC Module 0 AIN6 Pin Present
When set, indicates that ADC module 0 input pin 6 is present.
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System Control
Bit/Field
Name
Type
Reset
21
ADC0AIN5
RO
1
Description
ADC Module 0 AIN5 Pin Present
When set, indicates that ADC module 0 input pin 5 is present.
20
ADC0AIN4
RO
1
ADC Module 0 AIN4 Pin Present
When set, indicates that ADC module 0 input pin 4 is present.
19
ADC0AIN3
RO
1
ADC Module 0 AIN3 Pin Present
When set, indicates that ADC module 0 input pin 3 is present.
18
ADC0AIN2
RO
1
ADC Module 0 AIN2 Pin Present
When set, indicates that ADC module 0 input pin 2 is present.
17
ADC0AIN1
RO
1
ADC Module 0 AIN1 Pin Present
When set, indicates that ADC module 0 input pin 1 is present.
16
ADC0AIN0
RO
1
ADC Module 0 AIN0 Pin Present
When set, indicates that ADC module 0 input pin 0 is present.
15
PWMFAULT
RO
1
PWM Fault Pin Present
When set, indicates that a PWM Fault pin is present. See DC5 for
specific Fault pins on this device.
14
C2O
RO
1
C2o Pin Present
When set, indicates that the analog comparator 2 output pin is present.
13
C2PLUS
RO
1
C2+ Pin Present
When set, indicates that the analog comparator 2 (+) input pin is present.
12
C2MINUS
RO
1
C2- Pin Present
When set, indicates that the analog comparator 2 (-) input pin is present.
11
C1O
RO
1
C1o Pin Present
When set, indicates that the analog comparator 1 output pin is present.
10
C1PLUS
RO
1
C1+ Pin Present
When set, indicates that the analog comparator 1 (+) input pin is present.
9
C1MINUS
RO
1
C1- Pin Present
When set, indicates that the analog comparator 1 (-) input pin is present.
8
C0O
RO
1
C0o Pin Present
When set, indicates that the analog comparator 0 output pin is present.
7
C0PLUS
RO
1
C0+ Pin Present
When set, indicates that the analog comparator 0 (+) input pin is present.
6
C0MINUS
RO
1
C0- Pin Present
When set, indicates that the analog comparator 0 (-) input pin is present.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
5
PWM5
RO
1
Description
PWM5 Pin Present
When set, indicates that the PWM pin 5 is present.
4
PWM4
RO
1
PWM4 Pin Present
When set, indicates that the PWM pin 4 is present.
3
PWM3
RO
1
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
2
PWM2
RO
1
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
1
PWM1
RO
1
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
0
PWM0
RO
1
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
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System Control
Register 20: Device Capabilities 4 (DC4), offset 0x01C
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 4 (DC4)
Base 0x400F.E000
Offset 0x01C
Type RO, reset 0x5100.F1FF
Type
Reset
Type
Reset
31
30
29
28
27
26
25
reserved
EPHY0
reserved
EMAC0
RO
0
RO
1
RO
0
RO
1
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
CCP7
CCP6
UDMA
ROM
RO
1
RO
1
RO
1
RO
1
reserved
RO
0
23
22
21
20
18
17
16
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
RO
1
RO
1
RO
1
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
E1588
reserved
RO
0
24
RO
0
19
reserved
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
RO
1
Ethernet PHY Layer 0 Present
When set, indicates that Ethernet PHY layer 0 is present.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
RO
1
Ethernet MAC Layer 0 Present
When set, indicates that Ethernet MAC layer 0 is present.
27:25
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
24
E1588
RO
1
1588 Capable
When set, indicates that that Ethernet MAC layer 0 is 1588 capable.
23:16
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15
CCP7
RO
1
CCP7 Pin Present
When set, indicates that Capture/Compare/PWM pin 7 is present.
14
CCP6
RO
1
CCP6 Pin Present
When set, indicates that Capture/Compare/PWM pin 6 is present.
13
UDMA
RO
1
Micro-DMA Module Present
When set, indicates that the micro-DMA module present.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
12
ROM
RO
1
Description
Internal Code ROM Present
When set, indicates that internal code ROM is present.
11:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
RO
1
GPIO Port J Present
When set, indicates that GPIO Port J is present.
7
GPIOH
RO
1
GPIO Port H Present
When set, indicates that GPIO Port H is present.
6
GPIOG
RO
1
GPIO Port G Present
When set, indicates that GPIO Port G is present.
5
GPIOF
RO
1
GPIO Port F Present
When set, indicates that GPIO Port F is present.
4
GPIOE
RO
1
GPIO Port E Present
When set, indicates that GPIO Port E is present.
3
GPIOD
RO
1
GPIO Port D Present
When set, indicates that GPIO Port D is present.
2
GPIOC
RO
1
GPIO Port C Present
When set, indicates that GPIO Port C is present.
1
GPIOB
RO
1
GPIO Port B Present
When set, indicates that GPIO Port B is present.
0
GPIOA
RO
1
GPIO Port A Present
When set, indicates that GPIO Port A is present.
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System Control
Register 21: Device Capabilities 5 (DC5), offset 0x020
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 5 (DC5)
Base 0x400F.E000
Offset 0x020
Type RO, reset 0x0F30.00FF
31
30
29
28
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
1
15
14
13
12
11
10
9
8
7
6
PWM7
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
27
26
25
24
RO
0
22
19
18
RO
1
RO
0
RO
0
RO
0
RO
0
5
4
3
2
1
0
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
reserved
PWMFAULT3 PWMFAULT2 PWMFAULT1 PWMFAULT0
reserved
Type
Reset
23
21
20
PWMEFLT PWMESYNC
17
16
reserved
Bit/Field
Name
Type
Reset
Description
31:28
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
27
PWMFAULT3
RO
1
PWM Fault 3 Pin Present
When set, indicates that the PWM Fault 3 pin is present.
26
PWMFAULT2
RO
1
PWM Fault 2 Pin Present
When set, indicates that the PWM Fault 2 pin is present.
25
PWMFAULT1
RO
1
PWM Fault 1 Pin Present
When set, indicates that the PWM Fault 1 pin is present.
24
PWMFAULT0
RO
1
PWM Fault 0 Pin Present
When set, indicates that the PWM Fault 0 pin is present.
23:22
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
21
PWMEFLT
RO
1
PWM Extended Fault Active
When set, indicates that the PWM Extended Fault feature is active.
20
PWMESYNC
RO
1
PWM Extended SYNC Active
When set, indicates that the PWM Extended SYNC feature is active.
19:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
PWM7
RO
1
PWM7 Pin Present
When set, indicates that the PWM pin 7 is present.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
6
PWM6
RO
1
Description
PWM6 Pin Present
When set, indicates that the PWM pin 6 is present.
5
PWM5
RO
1
PWM5 Pin Present
When set, indicates that the PWM pin 5 is present.
4
PWM4
RO
1
PWM4 Pin Present
When set, indicates that the PWM pin 4 is present.
3
PWM3
RO
1
PWM3 Pin Present
When set, indicates that the PWM pin 3 is present.
2
PWM2
RO
1
PWM2 Pin Present
When set, indicates that the PWM pin 2 is present.
1
PWM1
RO
1
PWM1 Pin Present
When set, indicates that the PWM pin 1 is present.
0
PWM0
RO
1
PWM0 Pin Present
When set, indicates that the PWM pin 0 is present.
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System Control
Register 22: Device Capabilities 6 (DC6), offset 0x024
This register is predefined by the part and can be used to verify features. If any bit is clear in this
register, the module is not present. The corresponding bit in the RCGC0, SCGC0, and DCGC0
registers cannot be set.
Device Capabilities 6 (DC6)
Base 0x400F.E000
Offset 0x024
Type RO, reset 0x0000.0013
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
USB0PHY
RO
1
reserved
RO
0
USB0
RO
1
Bit/Field
Name
Type
Reset
Description
31:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
USB0PHY
RO
1
USB Module 0 PHY Present
When set, indicates that the USB module 0 PHY is present.
3:2
reserved
RO
0
1:0
USB0
RO
0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB Module 0 Present
Thie field indicates that USB module 0 is present and specifies its
capability.
Value Description
0x3
USB0 is OTG.
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Stellaris® LM3S9B95 Microcontroller
Register 23: Device Capabilities 7 (DC7), offset 0x028
This register is predefined by the part and can be used to verify uDMA channel features. A 1 indicates
the channel is available on this device; a 0 that the channel is only available on other devices in the
family. Most channels have primary and secondary assignments. If the primary function is not
available on this microcontroller, the secondary function becomes the primary function. If the
secondary function is not available, the primary function is the only option.
Device Capabilities 7 (DC7)
Base 0x400F.E000
Offset 0x028
Type RO, reset 0xFFFF.FFFF
31
reserved
Type
Reset
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMACH30 DMACH29 DMACH28 DMACH27 DMACH26 DMACH25 DMACH24 DMACH23 DMACH22 DMACH21 DMACH20 DMACH19 DMACH18 DMACH17 DMACH16
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMACH15 DMACH14 DMACH13 DMACH12 DMACH11 DMACH10 DMACH9 DMACH8 DMACH7 DMACH6 DMACH5 DMACH4 DMACH3 DMACH2 DMACH1 DMACH0
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31
reserved
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
Reserved
Reserved for uDMA channel 31.
30
DMACH30
RO
1
SW
When set, indicates uDMA channel 30 is available for software transfers.
29
DMACH29
RO
1
I2S0_TX / CAN1_TX
When set, indicates uDMA channel 29 is available and connected to
the transmit path of I2S module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 1 transmit.
28
DMACH28
RO
1
I2S0_RX / CAN1_RX
When set, indicates uDMA channel 28 is available and connected to
the receive path of I2S module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 1 receive.
27
DMACH27
RO
1
CAN1_TX / ADC1_SS3
When set, indicates uDMA channel 27 is available and connected to
the transmit path of CAN module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
3.
26
DMACH26
RO
1
CAN1_RX / ADC1_SS2
When set, indicates uDMA channel 26 is available and connected to
the receive path of CAN module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
2.
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System Control
Bit/Field
Name
Type
Reset
25
DMACH25
RO
1
Description
SSI1_TX / ADC1_SS1
When set, indicates uDMA channel 25 is available and connected to
the transmit path of SSI module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
1.
24
DMACH24
RO
1
SSI1_RX / ADC1_SS0
When set, indicates uDMA channel 24 is available and connected to
the receive path of SSI module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of ADC module 1 Sample Sequencer
0.
23
DMACH23
RO
1
UART1_TX / CAN2_TX
When set, indicates uDMA channel 23 is available and connected to
the transmit path of UART module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 2 transmit.
22
DMACH22
RO
1
UART1_RX / CAN2_RX
When set, indicates uDMA channel 22 is available and connected to
the receive path of UART module 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of CAN module 2 receive.
21
DMACH21
RO
1
Timer1B / EPI0_WFIFO
When set, indicates uDMA channel 21 is available and connected to
Timer 1B.If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of EPI module write FIFO (WRIFO).
20
DMACH20
RO
1
Timer1A / EPI0_NBRFIFO
When set, indicates uDMA channel 20 is available and connected to
Timer 1A. If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of EPI module 0 non-blocking read FIFO (NBRFIFO).
19
DMACH19
RO
1
Timer0B / Timer1B
When set, indicates uDMA channel 19 is available and connected to
Timer 0B. If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of Timer 1B.
18
DMACH18
RO
1
Timer0A / Timer1A
When set, indicates uDMA channel 18 is available and connected to
Timer 0A. If the corresponding bit in the DMACHASGN register is set,
the channel is connected instead to the secondary channel assignment
of Timer 1A.
17
DMACH17
RO
1
ADC0_SS3
When set, indicates uDMA channel 17 is available and connected to
ADC module 0 Sample Sequencer 3.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
16
DMACH16
RO
1
ADC0_SS2
When set, indicates uDMA channel 16 is available and connected to
ADC module 0 Sample Sequencer 2.
15
DMACH15
RO
1
ADC0_SS1 / Timer2B
When set, indicates uDMA channel 15 is available and connected to
ADC module 0 Sample Sequencer 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2B.
14
DMACH14
RO
1
ADC0_SS0 / Timer2A
When set, indicates uDMA channel 14 is available and connected to
ADC module 0 Sample Sequencer 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2A.
13
DMACH13
RO
1
CAN0_TX / UART2_TX
When set, indicates uDMA channel 13 is available and connected to
the transmit path of CAN module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 transmit.
12
DMACH12
RO
1
CAN0_RX / UART2_RX
When set, indicates uDMA channel 12 is available and connected to
the receive path of CAN module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 receive.
11
DMACH11
RO
1
SSI0_TX / SSI1_TX
When set, indicates uDMA channel 11 is available and connected to
the transmit path of SSI module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of SSI module 1 transmit.
10
DMACH10
RO
1
SSI0_RX / SSI1_RX
When set, indicates uDMA channel 10 is available and connected to
the receive path of SSI module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of SSI module 1 receive.
9
DMACH9
RO
1
UART0_TX / UART1_TX
When set, indicates uDMA channel 9 is available and connected to the
transmit path of UART module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
seondary channel assignment of UART module 1 transmit.
8
DMACH8
RO
1
UART0_RX / UART1_RX
When set, indicates uDMA channel 8 is available and connected to the
receive path of UART module 0. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 1 receive.
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System Control
Bit/Field
Name
Type
Reset
7
DMACH7
RO
1
Description
ETH_TX / Timer2B
When set, indicates uDMA channel 7 is available and connected to the
transmit path of the Ethernet module. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2B.
6
DMACH6
RO
1
ETH_RX / Timer2A
When set, indicates uDMA channel 6 is available and connected to the
receive path of the Ethernet module. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2A.
5
DMACH5
RO
1
USB_EP3_TX / Timer2B
When set, indicates uDMA channel 5 is available and connected to the
transmit path of USB endpoint 3. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2B.
4
DMACH4
RO
1
USB_EP3_RX / Timer2A
When set, indicates uDMA channel 4 is available and connected to the
receive path of USB endpoint 3. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 2A.
3
DMACH3
RO
1
USB_EP2_TX / Timer3B
When set, indicates uDMA channel 3 is available and connected to the
transmit path of USB endpoint 2. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 3B.
2
DMACH2
RO
1
USB_EP2_RX / Timer3A
When set, indicates uDMA channel 2 is available and connected to the
receive path of USB endpoint 2. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of Timer 3A.
1
DMACH1
RO
1
USB_EP1_TX / UART2_TX
When set, indicates uDMA channel 1 is available and connected to the
transmit path of USB endpoint 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 transmit.
0
DMACH0
RO
1
USB_EP1_RX / UART2_RX
When set, indicates uDMA channel 0 is available and connected to the
receive path of USB endpoint 1. If the corresponding bit in the
DMACHASGN register is set, the channel is connected instead to the
secondary channel assignment of UART module 2 receive.
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Stellaris® LM3S9B95 Microcontroller
Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C
This register is predefined by the part and can be used to verify features.
Device Capabilities 8 ADC Channels (DC8)
Base 0x400F.E000
Offset 0x02C
Type RO, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADC1AIN15 ADC1AIN14 ADC1AIN13 ADC1AIN12 ADC1AIN11 ADC1AIN10 ADC1AIN9 ADC1AIN8 ADC1AIN7 ADC1AIN6 ADC1AIN5 ADC1AIN4 ADC1AIN3 ADC1AIN2 ADC1AIN1 ADC1AIN0
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC0AIN15 ADC0AIN14 ADC0AIN13 ADC0AIN12 ADC0AIN11 ADC0AIN10 ADC0AIN9 ADC0AIN8 ADC0AIN7 ADC0AIN6 ADC0AIN5 ADC0AIN4 ADC0AIN3 ADC0AIN2 ADC0AIN1 ADC0AIN0
Type
Reset
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
31
ADC1AIN15
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Description
ADC Module 1 AIN15 Pin Present
When set, indicates that ADC module 1 input pin 15 is present.
30
ADC1AIN14
RO
1
ADC Module 1 AIN14 Pin Present
When set, indicates that ADC module 1 input pin 14 is present.
29
ADC1AIN13
RO
1
ADC Module 1 AIN13 Pin Present
When set, indicates that ADC module 1 input pin 13 is present.
28
ADC1AIN12
RO
1
ADC Module 1 AIN12 Pin Present
When set, indicates that ADC module 1 input pin 12 is present.
27
ADC1AIN11
RO
1
ADC Module 1 AIN11 Pin Present
When set, indicates that ADC module 1 input pin 11 is present.
26
ADC1AIN10
RO
1
ADC Module 1 AIN10 Pin Present
When set, indicates that ADC module 1 input pin 10 is present.
25
ADC1AIN9
RO
1
ADC Module 1 AIN9 Pin Present
When set, indicates that ADC module 1 input pin 9 is present.
24
ADC1AIN8
RO
1
ADC Module 1 AIN8 Pin Present
When set, indicates that ADC module 1 input pin 8 is present.
23
ADC1AIN7
RO
1
ADC Module 1 AIN7 Pin Present
When set, indicates that ADC module 1 input pin 7 is present.
22
ADC1AIN6
RO
1
ADC Module 1 AIN6 Pin Present
When set, indicates that ADC module 1 input pin 6 is present.
21
ADC1AIN5
RO
1
ADC Module 1 AIN5 Pin Present
When set, indicates that ADC module 1 input pin 5 is present.
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System Control
Bit/Field
Name
Type
Reset
20
ADC1AIN4
RO
1
Description
ADC Module 1 AIN4 Pin Present
When set, indicates that ADC module 1 input pin 4 is present.
19
ADC1AIN3
RO
1
ADC Module 1 AIN3 Pin Present
When set, indicates that ADC module 1 input pin 3 is present.
18
ADC1AIN2
RO
1
ADC Module 1 AIN2 Pin Present
When set, indicates that ADC module 1 input pin 2 is present.
17
ADC1AIN1
RO
1
ADC Module 1 AIN1 Pin Present
When set, indicates that ADC module 1 input pin 1 is present.
16
ADC1AIN0
RO
1
ADC Module 1 AIN0 Pin Present
When set, indicates that ADC module 1 input pin 0 is present.
15
ADC0AIN15
RO
1
ADC Module 0 AIN15 Pin Present
When set, indicates that ADC module 0 input pin 15 is present.
14
ADC0AIN14
RO
1
ADC Module 0 AIN14 Pin Present
When set, indicates that ADC module 0 input pin 14 is present.
13
ADC0AIN13
RO
1
ADC Module 0 AIN13 Pin Present
When set, indicates that ADC module 0 input pin 13 is present.
12
ADC0AIN12
RO
1
ADC Module 0 AIN12 Pin Present
When set, indicates that ADC module 0 input pin 12 is present.
11
ADC0AIN11
RO
1
ADC Module 0 AIN11 Pin Present
When set, indicates that ADC module 0 input pin 11 is present.
10
ADC0AIN10
RO
1
ADC Module 0 AIN10 Pin Present
When set, indicates that ADC module 0 input pin 10 is present.
9
ADC0AIN9
RO
1
ADC Module 0 AIN9 Pin Present
When set, indicates that ADC module 0 input pin 9 is present.
8
ADC0AIN8
RO
1
ADC Module 0 AIN8 Pin Present
When set, indicates that ADC module 0 input pin 8 is present.
7
ADC0AIN7
RO
1
ADC Module 0 AIN7 Pin Present
When set, indicates that ADC module 0 input pin 7 is present.
6
ADC0AIN6
RO
1
ADC Module 0 AIN6 Pin Present
When set, indicates that ADC module 0 input pin 6 is present.
5
ADC0AIN5
RO
1
ADC Module 0 AIN5 Pin Present
When set, indicates that ADC module 0 input pin 5 is present.
4
ADC0AIN4
RO
1
ADC Module 0 AIN4 Pin Present
When set, indicates that ADC module 0 input pin 4 is present.
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June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
3
ADC0AIN3
RO
1
Description
ADC Module 0 AIN3 Pin Present
When set, indicates that ADC module 0 input pin 3 is present.
2
ADC0AIN2
RO
1
ADC Module 0 AIN2 Pin Present
When set, indicates that ADC module 0 input pin 2 is present.
1
ADC0AIN1
RO
1
ADC Module 0 AIN1 Pin Present
When set, indicates that ADC module 0 input pin 1 is present.
0
ADC0AIN0
RO
1
ADC Module 0 AIN0 Pin Present
When set, indicates that ADC module 0 input pin 0 is present.
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Texas Instruments-Advance Information
System Control
Register 25: Device Capabilities 9 ADC Digital Comparators (DC9), offset
0x190
This register is predefined by the part and can be used to verify features.
Device Capabilities 9 ADC Digital Comparators (DC9)
Base 0x400F.E000
Offset 0x190
Type RO, reset 0x00FF.00FF
31
30
29
28
27
26
25
24
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
ADC1DC7 ADC1DC6 ADC1DC5 ADC1DC4 ADC1DC3 ADC1DC2 ADC1DC1 ADC1DC0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
1
0
ADC0DC7 ADC0DC6 ADC0DC5 ADC0DC4 ADC0DC3 ADC0DC2 ADC0DC1 ADC0DC0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
23
ADC1DC7
RO
1
ADC1 DC7 Present
When set, indicates that ADC module 1 Digital Comparator 7 is present.
22
ADC1DC6
RO
1
ADC1 DC6 Present
When set, indicates that ADC module 1 Digital Comparator 6 is present.
21
ADC1DC5
RO
1
ADC1 DC5 Present
When set, indicates that ADC module 1 Digital Comparator 5 is present.
20
ADC1DC4
RO
1
ADC1 DC4 Present
When set, indicates that ADC module 1 Digital Comparator 4 is present.
19
ADC1DC3
RO
1
ADC1 DC3 Present
When set, indicates that ADC module 1 Digital Comparator 3 is present.
18
ADC1DC2
RO
1
ADC1 DC2 Present
When set, indicates that ADC module 1 Digital Comparator 2 is present.
17
ADC1DC1
RO
1
ADC1 DC1 Present
When set, indicates that ADC module 1 Digital Comparator 1 is present.
16
ADC1DC0
RO
1
ADC1 DC0 Present
When set, indicates that ADC module 1 Digital Comparator 0 is present.
15:8
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7
ADC0DC7
RO
1
ADC0 DC7 Present
When set, indicates that ADC module 0 Digital Comparator 7 is present.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
6
ADC0DC6
RO
1
Description
ADC0 DC6 Present
When set, indicates that ADC module 0 Digital Comparator 6 is present.
5
ADC0DC5
RO
1
ADC0 DC5 Present
When set, indicates that ADC module 0 Digital Comparator 5 is present.
4
ADC0DC4
RO
1
ADC0 DC4 Present
When set, indicates that ADC module 0 Digital Comparator 4 is present.
3
ADC0DC3
RO
1
ADC0 DC3 Present
When set, indicates that ADC module 0 Digital Comparator 3 is present.
2
ADC0DC2
RO
1
ADC0 DC2 Present
When set, indicates that ADC module 0 Digital Comparator 2 is present.
1
ADC0DC1
RO
1
ADC0 DC1 Present
When set, indicates that ADC module 0 Digital Comparator 1 is present.
0
ADC0DC0
RO
1
ADC0 DC0 Present
When set, indicates that ADC module 0 Digital Comparator 0 is present.
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Texas Instruments-Advance Information
System Control
Register 26: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0
This register is predefined by the part and can be used to verify features.
Non-Volatile Memory Information (NVMSTAT)
Base 0x400F.E000
Offset 0x1A0
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
FWB
RO
1
Bit/Field
Name
Type
Reset
Description
31:1
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FWB
RO
1
32 Word Flash Write Buffer Active
When set, indicates that the 32 word Flash memory write buffer feature
is active.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Run Mode Clock Gating Control Register 0 (RCGC0)
Base 0x400F.E000
Offset 0x100
Type R/W, reset 0x00000040
31
30
29
reserved
Type
Reset
28
WDT1
26
24
23
22
21
19
16
CAN1
CAN0
ADC1
ADC0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
RO
0
RO
0
RO
0
RO
1
MAXADC0SPD
R/W
0
R/W
0
R/W
0
R/W
0
reserved
RO
0
RO
0
reserved
17
R/W
0
MAXADC1SPD
PWM
18
RO
0
RO
0
reserved
20
RO
0
RO
0
reserved
25
RO
0
reserved
Type
Reset
27
WDT0
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
Description
23:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
19:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
R/W
0
ADC1 Clock Gating Control
This bit controls the clock gating for SAR ADC module 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
16
ADC0
R/W
0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10
MAXADC1SPD
R/W
0
ADC1 Sample Speed
This field sets the rate at which ADC module 1 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC1SPD bit as follows (all other encodings are
reserved):
Value Description
9:8
MAXADC0SPD
R/W
0
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
ADC0 Sample Speed
This field sets the rate at which ADC0 samples data. You cannot set
the rate higher than the maximum rate. You can set the sample rate by
setting the MAXADC0SPD bit as follows (all other encodings are reserved):
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
System Control
Register 28: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
reserved
Type
Reset
28
WDT1
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
27
26
reserved
RO
0
RO
0
11
10
25
24
CAN1
CAN0
R/W
0
R/W
0
9
8
MAXADC1SPD
MAXADC0SPD
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
reserved
RO
0
20
RO
0
RO
0
R/W
0
5
4
7
6
reserved
reserved
RO
0
RO
1
19
PWM
reserved
RO
0
RO
0
18
reserved
RO
0
RO
0
3
2
WDT0
R/W
0
17
16
ADC1
ADC0
R/W
0
R/W
0
1
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Clock Gating Control
This bit controls the clock gating for Watchdog Timer module 1. If set,
the module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
23:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
19:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
R/W
0
ADC1 Clock Gating Control
This bit controls the clock gating for ADC module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
16
ADC0
R/W
0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
11:10
MAXADC1SPD
R/W
0
ADC1 Sample Speed
This field sets the rate at which ADC module 1 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC1SPD bit as follows (all other encodings are
reserved):
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
9:8
MAXADC0SPD
R/W
0
Description
ADC0 Sample Speed
This field sets the rate at which ADC module 0 samples data. You cannot
set the rate higher than the maximum rate. You can set the sample rate
by setting the MAXADC0SPD bit as follows (all other encodings are
reserved):
Value Description
0x3
1M samples/second
0x2
500K samples/second
0x1
250K samples/second
0x0
125K samples/second
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
31
30
29
reserved
Type
Reset
28
WDT1
RO
0
RO
0
RO
0
R/W
0
15
14
13
12
27
26
reserved
25
24
CAN1
CAN0
23
RO
0
RO
0
R/W
0
R/W
0
RO
0
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
22
RO
0
RO
0
RO
0
20
RO
0
R/W
0
6
5
4
RO
1
19
PWM
RO
0
reserved
RO
0
21
reserved
reserved
RO
0
RO
0
18
reserved
RO
0
RO
0
3
2
WDT0
R/W
0
17
16
ADC1
ADC0
R/W
0
R/W
0
1
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 1. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Clock Gating Control
This bit controls the clock gating for CAN module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
24
CAN0
R/W
0
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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System Control
Bit/Field
Name
Type
Reset
Description
23:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Clock Gating Control
This bit controls the clock gating for the PWM module. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
19:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
ADC1
R/W
0
ADC1 Clock Gating Control
This bit controls the clock gating for ADC module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
16
ADC0
R/W
0
ADC0 Clock Gating Control
This bit controls the clock gating for ADC module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
reserved
RO
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Clock Gating Control
This bit controls the clock gating for the Watchdog Timer module 0. If
set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Run Mode Clock Gating Control Register 1 (RCGC1)
Base 0x400F.E000
Offset 0x104
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
reserved
RO
0
RO
0
23
22
21
20
19
18
17
16
R/W
0
RO
0
RO
0
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
7
6
5
4
3
2
1
0
QEI1
QEI0
R/W
0
R/W
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Clock Gating
This bit controls the clock gating for EPI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Clock Gating
This bit controls the clock gating for I2S module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 14, 2010
181
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System Control
Bit/Field
Name
Type
Reset
26
COMP2
R/W
0
Description
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
QEI1
R/W
0
QEI1 Clock Gating Control
This bit controls the clock gating for QEI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
8
QEI0
R/W
0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
1
UART1
R/W
0
Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Stellaris® LM3S9B95 Microcontroller
Register 31: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset
0x114
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Sleep Mode Clock Gating Control Register 1 (SCGC1)
Base 0x400F.E000
Offset 0x114
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
11
10
7
6
15
14
13
12
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
reserved
RO
0
RO
0
9
8
QEI1
QEI0
R/W
0
R/W
0
23
22
21
20
reserved
reserved
RO
0
RO
0
RO
0
RO
0
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Clock Gating
This bit controls the clock gating for EPI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Clock Gating
This bit controls the clock gating for I2S module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 14, 2010
185
Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
26
COMP2
R/W
0
Description
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
QEI1
R/W
0
QEI1 Clock Gating Control
This bit controls the clock gating for QEI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
8
QEI0
R/W
0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
June 14, 2010
187
Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
1
UART1
R/W
0
Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 32: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1),
offset 0x124
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC1 is the clock configuration register for
running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1)
Base 0x400F.E000
Offset 0x124
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
11
10
7
6
15
14
13
12
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
reserved
RO
0
RO
0
9
8
QEI1
QEI0
R/W
0
R/W
0
23
22
21
20
reserved
reserved
RO
0
RO
0
RO
0
RO
0
19
18
17
16
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
5
4
3
2
1
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Clock Gating
This bit controls the clock gating for EPI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Clock Gating
This bit controls the clock gating for I2S module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 14, 2010
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
26
COMP2
R/W
0
Description
Analog Comparator 2 Clock Gating
This bit controls the clock gating for analog comparator 2. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
25
COMP1
R/W
0
Analog Comparator 1 Clock Gating
This bit controls the clock gating for analog comparator 1. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
24
COMP0
R/W
0
Analog Comparator 0 Clock Gating
This bit controls the clock gating for analog comparator 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 3.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
18
TIMER2
R/W
0
Timer 2 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 2.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
17
TIMER1
R/W
0
Timer 1 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 1.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
16
TIMER0
R/W
0
Timer 0 Clock Gating Control
This bit controls the clock gating for General-Purpose Timer module 0.
If set, the module receives a clock and functions. Otherwise, the module
is unclocked and disabled. If the module is unclocked, a read or write
to the module generates a bus fault.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Clock Gating Control
This bit controls the clock gating for I2C module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Clock Gating Control
This bit controls the clock gating for I2C module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
QEI1
R/W
0
QEI1 Clock Gating Control
This bit controls the clock gating for QEI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
8
QEI0
R/W
0
QEI0 Clock Gating Control
This bit controls the clock gating for QEI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Clock Gating Control
This bit controls the clock gating for SSI module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
4
SSI0
R/W
0
SSI0 Clock Gating Control
This bit controls the clock gating for SSI module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Clock Gating Control
This bit controls the clock gating for UART module 2. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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System Control
Bit/Field
Name
Type
Reset
1
UART1
R/W
0
Description
UART1 Clock Gating Control
This bit controls the clock gating for UART module 1. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
0
UART0
R/W
0
UART0 Clock Gating Control
This bit controls the clock gating for UART module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
15
14
13
reserved
Type
Reset
RO
0
RO
0
27
26
25
24
23
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
RO
0
RO
0
UDMA
R/W
0
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
reserved
RO
0
RO
0
16
USB0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
System Control
Bit/Field
Name
Type
Reset
16
USB0
R/W
0
Description
USB0 Clock Gating Control
This bit controls the clock gating for USB module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Clock Gating Control
This bit controls the clock gating for Port J. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
7
GPIOH
R/W
0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
6
GPIOG
R/W
0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
2
GPIOC
R/W
0
Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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Texas Instruments-Advance Information
System Control
Register 34: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset
0x118
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Sleep Mode Clock Gating Control Register 2 (SCGC2)
Base 0x400F.E000
Offset 0x118
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
UDMA
R/W
0
27
26
25
23
22
21
20
19
18
17
reserved
reserved
RO
0
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
16
USB0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
8
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
16
USB0
R/W
0
Description
USB0 Clock Gating Control
This bit controls the clock gating for USB module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Clock Gating Control
This bit controls the clock gating for Port J. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
7
GPIOH
R/W
0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
6
GPIOG
R/W
0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
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System Control
Bit/Field
Name
Type
Reset
2
GPIOC
R/W
0
Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 35: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2),
offset 0x128
This register controls the clock gating logic in Deep-Sleep mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2)
Base 0x400F.E000
Offset 0x128
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
R/W
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
UDMA
R/W
0
27
26
25
23
22
21
20
19
18
17
reserved
reserved
RO
0
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
16
USB0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
8
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Clock Gating Control
This bit controls the clock gating for Ethernet PHY layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Clock Gating Control
This bit controls the clock gating for Ethernet MAC layer 0. If set, the
module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 14, 2010
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System Control
Bit/Field
Name
Type
Reset
16
USB0
R/W
0
Description
USB0 Clock Gating Control
This bit controls the clock gating for USB module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Clock Gating Control
This bit controls the clock gating for Port J. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
7
GPIOH
R/W
0
Port H Clock Gating Control
This bit controls the clock gating for Port H. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
6
GPIOG
R/W
0
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
5
GPIOF
R/W
0
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
4
GPIOE
R/W
0
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
3
GPIOD
R/W
0
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
2
GPIOC
R/W
0
Description
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
1
GPIOB
R/W
0
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
0
GPIOA
R/W
0
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
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Texas Instruments-Advance Information
System Control
Register 36: Software Reset Control 0 (SRCR0), offset 0x040
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
reserved
Type
Reset
28
WDT1
27
26
reserved
25
24
23
22
21
reserved
20
PWM
18
reserved
17
16
CAN1
CAN0
ADC1
ADC0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
19
WDT0
R/W
0
reserved
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
WDT1
R/W
0
WDT1 Reset Control
When this bit is set, Watchdog Timer module 1 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
27:26
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
25
CAN1
R/W
0
CAN1 Reset Control
When this bit is set, CAN module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
24
CAN0
R/W
0
CAN0 Reset Control
When this bit is set, CAN module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
23:21
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20
PWM
R/W
0
PWM Reset Control
When this bit is set, PWM module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
19:18
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Bit/Field
Name
Type
Reset
17
ADC1
R/W
0
Description
ADC1 Reset Control
When this bit is set, ADC module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
16
ADC0
R/W
0
ADC0 Reset Control
When this bit is set, ADC module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
15:4
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3
WDT0
R/W
0
WDT0 Reset Control
When this bit is set, Watchdog Timer module 0 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
2:0
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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System Control
Register 37: Software Reset Control 1 (SRCR1), offset 0x044
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 2 (DC2) register.
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
Type
Reset
Type
Reset
31
30
29
28
27
26
25
24
reserved
EPI0
reserved
I2S0
reserved
COMP2
COMP1
COMP0
RO
0
R/W
0
RO
0
R/W
0
RO
0
R/W
0
R/W
0
15
14
13
12
11
10
reserved
I2C1
reserved
I2C0
RO
0
R/W
0
RO
0
R/W
0
reserved
RO
0
RO
0
23
22
21
20
19
18
17
16
R/W
0
RO
0
RO
0
RO
0
RO
0
TIMER3
TIMER2
TIMER1
TIMER0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
7
6
5
4
3
2
1
0
QEI1
QEI0
R/W
0
R/W
0
SSI1
SSI0
reserved
UART2
UART1
UART0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
reserved
reserved
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPI0
R/W
0
EPI0 Reset Control
When this bit is set, EPI module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
I2S0
R/W
0
I2S0 Reset Control
When this bit is set, I2S module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
27
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
26
COMP2
R/W
0
Analog Comp 2 Reset Control
When this bit is set, Analog Comparator module 2 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
25
COMP1
R/W
0
Analog Comp 1 Reset Control
When this bit is set, Analog Comparator module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
24
COMP0
R/W
0
Analog Comp 0 Reset Control
When this bit is set, Analog Comparator module 0 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
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Bit/Field
Name
Type
Reset
Description
23:20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
TIMER3
R/W
0
Timer 3 Reset Control
Timer 3 Reset Control. When this bit is set, General-Purpose Timer
module 3 is reset. All internal data is lost and the registers are returned
to their reset states. This bit must be manually cleared after being set.
18
TIMER2
R/W
0
Timer 2 Reset Control
When this bit is set, General-Purpose Timer module 2 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
17
TIMER1
R/W
0
Timer 1 Reset Control
When this bit is set, General-Purpose Timer module 1 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
16
TIMER0
R/W
0
Timer 0 Reset Control
When this bit is set, General-Purpose Timer module 0 is reset. All internal
data is lost and the registers are returned to their reset states. This bit
must be manually cleared after being set.
15
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
14
I2C1
R/W
0
I2C1 Reset Control
When this bit is set, I2C module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
13
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
12
I2C0
R/W
0
I2C0 Reset Control
When this bit is set, I2C module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
11:10
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
9
QEI1
R/W
0
QEI1 Reset Control
When this bit is set, QEI module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
8
QEI0
R/W
0
QEI0 Reset Control
When this bit is set, QEI module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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System Control
Bit/Field
Name
Type
Reset
Description
7:6
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
SSI1
R/W
0
SSI1 Reset Control
When this bit is set, SSI module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
4
SSI0
R/W
0
SSI0 Reset Control
When this bit is set, SSI module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
UART2
R/W
0
UART2 Reset Control
When this bit is set, UART module 2 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
1
UART1
R/W
0
UART1 Reset Control
When this bit is set, UART module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
0
UART0
R/W
0
UART0 Reset Control
When this bit is set, UART module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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Register 38: Software Reset Control 2 (SRCR2), offset 0x048
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
Type
Reset
31
30
29
28
reserved
EPHY0
reserved
EMAC0
RO
0
R/W
0
RO
0
15
14
13
reserved
Type
Reset
RO
0
RO
0
27
26
25
24
23
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
12
11
10
9
8
RO
0
RO
0
UDMA
R/W
0
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
7
6
5
4
3
2
1
0
GPIOJ
GPIOH
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
reserved
RO
0
RO
0
16
USB0
Bit/Field
Name
Type
Reset
Description
31
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
30
EPHY0
R/W
0
PHY0 Reset Control
When this bit is set, Ethernet PHY layer 0 is reset. All internal data is
lost and the registers are returned to their reset states. This bit must be
manually cleared after being set.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
EMAC0
R/W
0
MAC0 Reset Control
When this bit is set, Ethernet MAC layer 0 is reset. All internal data is
lost and the registers are returned to their reset states. This bit must be
manually cleared after being set.
27:17
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
16
USB0
R/W
0
USB0 Reset Control
When this bit is set, USB module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
15:14
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
13
UDMA
R/W
0
Micro-DMA Reset Control
When this bit is set, uDMA module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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System Control
Bit/Field
Name
Type
Reset
Description
12:9
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
8
GPIOJ
R/W
0
Port J Reset Control
When this bit is set, Port J module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
7
GPIOH
R/W
0
Port H Reset Control
When this bit is set, Port H module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
6
GPIOG
R/W
0
Port G Reset Control
When this bit is set, Port G module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
5
GPIOF
R/W
0
Port F Reset Control
When this bit is set, Port F module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
4
GPIOE
R/W
0
Port E Reset Control
When this bit is set, Port E module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
3
GPIOD
R/W
0
Port D Reset Control
When this bit is set, Port D module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
2
GPIOC
R/W
0
Port C Reset Control
When this bit is set, Port C module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
1
GPIOB
R/W
0
Port B Reset Control
When this bit is set, Port B module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
0
GPIOA
R/W
0
Port A Reset Control
When this bit is set, Port A module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
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7
Internal Memory
The LM3S9B95 microcontroller comes with 96 KB of bit-banded SRAM, internal ROM, and 256 KB
of Flash memory. The Flash memory controller provides a user-friendly interface, making Flash
memory programming a simple task. Flash memory protection can be applied to the Flash memory
on a 2-KB block basis.
7.1
Block Diagram
Figure 7-1 on page 209 illustrates the internal memory blocks and control logic. The dashed boxes
in the figure indicate registers residing in the System Control module.
Figure 7-1. Internal Memory Block Diagram
ROM Control
ROM Array
RMCTL
RMVER
Icode Bus
Flash Control
Cortex-M3
Dcode Bus
FMA
FMD
FMC
FCRIS
FCIM
FCMISC
Flash Array
System
Bus
Flash Write Buffer
FMC2
FWBVAL
FWBn
32 words
Flash Protection
Bridge
FMPREn
FMPRE
FMPPEn
FMPPE
User
Registers
Flash
Timing
BOOTCFG
USECRL
USER_REG0
USER_REG1
USER_REG2
USER_REG3
SRAM Array
7.2
Functional Description
This section describes the functionality of the SRAM, ROM, and Flash memories.
Note:
The μDMA controller can transfer data to and from the on-chip SRAM. However, because
the Flash memory and ROM are located on a separate internal bus, it is not possible to
transfer data from the Flash memory or ROM with the μDMA controller.
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Internal Memory
7.2.1
SRAM
Note:
The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays).
The banks are partitioned such that one bank contains all even words (the even bank) and
the other contains all odd words (the odd bank). A write access that is followed immediately
by a read access to the same bank incurs a stall of a single clock cycle. However, a write
to one bank followed by a read of the other bank can occur in successive clock cycles
without incurring any delay.
®
The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory
map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has
introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor,
certain regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:
bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)
For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C
allows direct access to only bit 3 of the byte at address 0x2000.1000.
For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3
Technical Reference Manual.
7.2.2
ROM
®
The internal ROM of the Stellaris device is located at address 0x0100.0000 of the device memory
map. The ROM contains the following components:
®
■ Stellaris Boot Loader and vector table
®
■ Stellaris Peripheral Driver Library (DriverLib) release for product-specific peripherals and
interfaces
■ Advanced Encryption Standard (AES) cryptography tables
■ Cyclic Redundancy Check (CRC) error detection functionality
The boot loader is used as an initial program loader (when the Flash memory is empty) as well as
an application-initiated firmware upgrade mechanism (by calling back to the boot loader). The
Peripheral Driver Library APIs in ROM can be called by applications, reducing Flash memory
requirements and freeing the Flash memory to be used for other purposes (such as additional
features in the application). Advance Encryption Standard (AES) is a publicly defined encryption
standard used by the U.S. Government and Cyclic Redundancy Check (CRC) is a technique to
validate a span of data has the same contents as when previously checked.
7.2.2.1
Boot Loader Overview
®
The Stellaris Boot Loader is executed from the ROM when the Flash memory is empty and is used
to download code to the Flash memory of a device without the use of a debug interface. At any
reset that resets the core, the user has the opportunity to direct the core to execute the ROM Boot
Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured in
the Boot Configuration (BOOTCFG) register. If the ROM boot loader is not selected, code in the
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ROM checks address 0x000.0004 to see if the Flash memory has a valid reset vector. If the data
at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not yet
been programmed, and the core executes the ROM Boot Loader.
The boot loader uses a simple packet interface to provide synchronous communication with the
device. The speed of the boot loader is determined by the internal oscillator (PIOSC) frequency as
it does not enable the PLL. The following serial interfaces can be used:
■ UART0
■ SSI0
■ I2C0
■ Ethernet
For simplicity, both the data format and communication protocol are identical for all serial interfaces.
Note:
The Flash-memory-resident version of the Boot Loader also supports CAN and USB.
See the Stellaris® Boot Loader User's Guide for information on the boot loader software.
7.2.2.2
®
Stellaris Peripheral Driver Library
®
The Stellaris Peripheral Driver Library contains a file called driverlib/rom.h that assists with
calling the peripheral driver library functions in the ROM. The detailed description of each function
is available in the Stellaris® ROM User’s Guide. See the "Using the ROM" chapter of the Stellaris®
Peripheral Driver Library User's Guide for more details on calling the ROM functions and using
driverlib/rom.h.
A table at the beginning of the ROM points to the entry points for the APIs that are provided in the
ROM. Accessing the API through these tables provides scalability; while the API locations may
change in future versions of the ROM, the API tables will not. The tables are split into two levels;
the main table contains one pointer per peripheral which points to a secondary table that contains
one pointer per API that is associated with that peripheral. The main table is located at 0x0100.0010,
right after the Cortex-M3 vector table in the ROM.
DriverLib functions are described in detail in the Stellaris® Peripheral Driver Library User's Guide.
Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The
®
Stellaris Graphics Library provides a set of graphics primitives and a widget set for creating graphical
®
user interfaces on Stellaris microcontroller-based boards that have a graphical display (for more
®
information, see the Stellaris® Graphics Library User's Guide). The Stellaris USB Library is a set
of data types and functions for creating USB Device, Host or On-The-Go (OTG) applications on
Stellaris microcontroller-based boards (for more information, see the Stellaris® USB Library User's
Guide).
7.2.2.3
Advanced Encryption Standard (AES) Cryptography Tables
AES is a strong encryption method with reasonable performance and size. AES is fast in both
hardware and software, is fairly easy to implement, and requires little memory. AES is ideal for
applications that can use pre-arranged keys, such as setup during manufacturing or configuration.
Four data tables used by the XySSL AES implementation are provided in the ROM. The first is the
forward S-box substitution table, the second is the reverse S-box substitution table, the third is the
forward polynomial table, and the final is the reverse polynomial table. See the Stellaris® ROM
User’s Guide for more information on AES.
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7.2.2.4
Cyclic Redundancy Check (CRC) Error Detection
The CRC technique can be used to validate correct receipt of messages (nothing lost or modified
in transit), to validate data after decompression, to validate that Flash memory contents have not
been changed, and for other cases where the data needs to be validated. A CRC is preferred over
a simple checksum (e.g. XOR all bits) because it catches changes more readily. See the Stellaris®
ROM User’s Guide for more information on CRC.
7.2.3
Flash Memory
At system clock speeds of 50 MHz and below, the Flash memory is read in a single cycle. The Flash
memory is organized as a set of 1-KB blocks that can be individually erased. An individual 32-bit
word can be programmed to change bits from 1 to 0. In addition, a write buffer provides the ability
to concurrently program 32 continuous words in Flash memory. Erasing a block causes the entire
contents of the block to be reset to all 1s. The 1-KB blocks are paired into sets of 2-KB blocks that
can be individually protected. The protection allows blocks to be marked as read-only or execute-only,
providing different levels of code protection. Read-only blocks cannot be erased or programmed,
protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased
or programmed and can only be read by the controller instruction fetch mechanism, protecting the
contents of those blocks from being read by either the controller or by a debugger.
Caution – In systems where the microcontroller is frequently powered for less than five minutes, power
should be removed from the microcontroller in a controlled manner to ensure proper operation. Software
should request permission to power down the part using the USDREQ bit in the Flash Control (FCTL)
register and wait to receive an acknowledge from the USDACK bit prior to removing power.
7.2.3.1
Prefetch Buffer
The Flash memory controller has a prefetch buffer that is automatically used when the CPU frequency
is greater than 50 MHz. In this mode, the Flash memory operates at half of the system clock. The
prefetch buffer fetches two 32-bit words per clock allowing instructions to be fetched with no wait
states while code is executing linearly. The fetch buffer includes a branch speculation mechanism
that recognizes a branch and avoids extra wait states by not reading the next word pair. Also, short
loop branches often stay in the buffer. As a result, some branches can be executed with no wait
states. Other branches incur a single wait state.
7.2.3.2
Flash Memory Protection
The user is provided two forms of Flash memory protection per 2-KB Flash memory block in four
pairs of 32-bit wide registers. The policy for each protection form is controlled by individual bits (per
policy per block) in the FMPPEn and FMPREn registers.
■ Flash Memory Protection Program Enable (FMPPEn): If a bit is set, the corresponding block
may be programmed (written) or erased. If a bit is cleared, the corresponding block may not be
changed.
■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may
be executed or read by software or debuggers. If a bit is cleared, the corresponding block may
only be executed, and contents of the memory block are prohibited from being read as data.
The policies may be combined as shown in Table 7-1 on page 213.
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Table 7-1. Flash Memory Protection Policy Combinations
FMPPEn
FMPREn
Protection
0
0
Execute-only protection. The block may only be executed and may not be written or erased.
This mode is used to protect code.
1
0
The block may be written, erased or executed, but not read. This combination is unlikely to
be used.
0
1
Read-only protection. The block may be read or executed but may not be written or erased.
This mode is used to lock the block from further modification while allowing any read or
execute access.
1
1
No protection. The block may be written, erased, executed or read.
A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited
and generates a bus fault. A Flash memory access that attempts to program or erase a
program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt
(by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software
developers of poorly behaving software during the development and debug phases.
The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented
banks. These settings create a policy of open access and programmability. The register bits may
be changed by clearing the specific register bit. The changes are not permanent until the register
is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a
0 and not committed, it may be restored by executing a power-on reset sequence. The changes
are committed using the Flash Memory Control (FMC) register. Details on programming these bits
are discussed in “Nonvolatile Register Programming” on page 215.
7.2.3.3
Interrupts
The Flash memory controller can generate interrupts when the following conditions are observed:
■ Programming Interrupt - signals when a program or erase action is complete.
■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block
of memory that is protected by its corresponding FMPPEn bit.
The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller
Masked Interrupt Status (FCMIS) register (see page 223) by setting the corresponding MASK bits.
If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw
Interrupt Status (FCRIS) register (see page 222).
Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the
corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register
(see page 224).
7.3
Flash Memory Initialization and Configuration
7.3.1
Flash Memory Programming
®
The Stellaris devices provide a user-friendly interface for Flash memory programming. All
erase/program operations are handled via three registers: Flash Memory Address (FMA), Flash
Memory Data (FMD), and Flash Memory Control (FMC). Note that if the debug capabilities of the
microcontroller have been deactivated, resulting in a "locked" state, a recovery sequence must be
performed in order to reactivate the debug module. See “Recovering a "Locked"
Microcontroller” on page 95.
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Caution – The Flash memory is divided into sectors of electrically separated address ranges of 4 KB
each, aligned on 4 KB boundaries. Erase/program operations on a 1-KB page have an electrical effect
on the other three 1-KB pages within the sector. A specific 1-KB page must be erased after 6 total
erase/program cycles occur to the other pages within it’s 4-KB sector. The following sequence of
operations on a 4-KB sector of Flash memory (Page 0..3) provides an example:
■ Page 3 is erase and programmed with values.
■ Page 0, Page 1, and Page 2 are erased and then programmed with values. At this point Page 3 has
been affected by 3 erase/program cycles.
■ Page 0, Page 1, and Page 2 are again erased and then programmed with values. At this point Page
3 has been affected by 6 erase/program cycles.
■ If the contents of Page 3 must continue to be valid, Page 3 must be erased and reprogrammed before
any other page in this sector has another erase or program operation.
7.3.1.1
To program a 32-bit word
1. Write source data to the FMD register.
2. Write the target address to the FMA register.
3. Write the Flash memory write key and the WRITE bit (a value of 0xA442.0001) to the FMC
register.
4. Poll the FMC register until the WRITE bit is cleared.
Important: To ensure proper operation, two writes to the same word must be separated by an
ERASE. The following two sequences are allowed:
■ ERASE -> PROGRAM value -> PROGRAM 0x0000.0000
■ ERASE -> PROGRAM value -> ERASE
The following sequence is NOT allowed:
■ ERASE -> PROGRAM value -> PROGRAM value
7.3.1.2
To perform an erase of a 1-KB page
1. Write the page address to the FMA register.
2. Write the Flash memory write key and the ERASE bit (a value of 0xA442.0002) to the FMC
register.
3. Poll the FMC register until the ERASE bit is cleared.
7.3.1.3
To perform a mass erase of the Flash memory
1. Write the Flash memory write key and the MERASE bit (a value of 0xA442.0004) to the FMC
register.
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2. Poll the FMC register until the MERASE bit is cleared.
7.3.2
32-Word Flash Memory Write Buffer
A 32-word write buffer provides the capability to perform faster write accesses to the Flash memory
by concurrently programing 32 words with a single buffered Flash memory write operation. The
buffered Flash memory write operation takes the same amount of time as the single word write
operation controlled by bit 0 in the FMC register. The data for the buffered write is written to the
Flash Write Buffer (FWBn) registers.
The registers are 32-word aligned with Flash memory, and therefore the register FWB0 corresponds
with the address in FMA where bits [6:0] of FMA are all 0. FWB1 corresponds with the address in
FMA + 0x4 and so on. Only the FWBn registers that have been updated since the previous buffered
Flash memory write operation are written. The Flash Write Buffer Valid (FWBVAL) register shows
which registers have been written since the last buffered Flash memory write operation. This register
contains a bit for each of the 32 FWBn registers, where bit[n] of FWBVAL corresponds to FWBn.
The FWBn register has been updated if the corresponding bit in the FWBVAL register is set.
7.3.2.1
To program 32 words with a single buffered Flash memory write operation
1. Write the source data to the FWBn registers.
2. Write the target address to the FMA register. This must be a 32-word aligned address (that is,
bits [6:0] in FMA must be 0s).
3. Write the Flash memory write key and the WRBUF bit (a value of 0xA442.0001) to the FMC2
register.
4. Poll the FMC2 register until the WRBUF bit is cleared.
7.3.3
Nonvolatile Register Programming
This section discusses how to update registers that are resident within the Flash memory itself.
These registers exist in a separate space from the main Flash memory array and are not affected
by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0
with a write operation. The register contents are unaffected by any reset condition except power-on
reset, which returns the register contents to 0xFFFF.FFFF. By committing the register values using
the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained
following power cycling. Once the register contents are committed, the only way to restore the factory
default values is to perform the sequence described in “Recovering a "Locked"
Microcontroller” on page 95.
With the exception of the Boot Configuration (BOOTCFG) register, the settings in these registers
can be tested before committing them to Flash memory. For the BOOTCFG register, the data to be
written is loaded into the FMD register before it is committed. The FMD register is read only and
does not allow the BOOTCFG operation to be tried before committing it to nonvolatile memory.
Important: The Flash memory resident registers can only have bits changed from 1 to 0 by user
programming and can only be committed once. After being committed, these registers
can only be restored to their factory default values only by performing the sequence
described in “Recovering a "Locked" Microcontroller” on page 95. The mass erase of
the main Flash memory array caused by the sequence is performed prior to restoring
these registers.
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In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and BOOTCFG registers
each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be
changed from 1 to 0. Table 7-2 on page 216 provides the FMA address required for commitment of
each of the registers and the source of the data to be written when the FMC register is written with
a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for
the commit operation to complete.
Table 7-2. User-Programmable Flash Memory Resident Registers
Register to be Committed
7.4
FMA Value
Data Source
FMPRE0
0x0000.0000
FMPRE0
FMPRE1
0x0000.0002
FMPRE1
FMPRE2
0x0000.0004
FMPRE2
FMPRE3
0x0000.0006
FMPRE3
FMPPE0
0x0000.0001
FMPPE0
FMPPE1
0x0000.0003
FMPPE1
FMPPE2
0x0000.0005
FMPPE2
FMPPE3
0x0000.0007
FMPPE3
USER_REG0
0x8000.0000
USER_REG0
USER_REG1
0x8000.0001
USER_REG1
USER_REG2
0x8000.0002
USER_REG2
USER_REG3
0x8000.0003
USER_REG3
BOOTCFG
0x7510.0000
FMD
Register Map
Table 7-3 on page 216 lists the ROM Controller register and the Flash memory and control registers.
The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS,
FCIM, FCMISC, FMC2, FWBVAL, and FWBn register offsets are relative to the Flash memory
control base address of 0x400F.D000. The ROM and Flash memory protection register offsets are
relative to the System Control base address of 0x400F.E000.
Table 7-3. Flash Register Map
Offset
Name
Type
Reset
See
page
Description
Flash Memory Registers (Flash Control Offset)
0x000
FMA
R/W
0x0000.0000
Flash Memory Address
218
0x004
FMD
R/W
0x0000.0000
Flash Memory Data
219
0x008
FMC
R/W
0x0000.0000
Flash Memory Control
220
0x00C
FCRIS
RO
0x0000.0000
Flash Controller Raw Interrupt Status
222
0x010
FCIM
R/W
0x0000.0000
Flash Controller Interrupt Mask
223
0x014
FCMISC
R/W1C
0x0000.0000
Flash Controller Masked Interrupt Status and Clear
224
0x020
FMC2
R/W
0x0000.0000
Flash Memory Control 2
225
0x030
FWBVAL
R/W
0x0000.0000
Flash Write Buffer Valid
226
0x0F8
FCTL
R/W
0x0000.0000
Flash Control
228
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Table 7-3. Flash Register Map (continued)
Offset
Name
Type
Reset
0x100 0x17C
FWBn
R/W
0x0000.0000
Description
See
page
Flash Write Buffer n
227
ROM Control
229
Memory Registers (System Control Offset)
0x0F0
RMCTL
R/W1C
-
0x0F4
RMVER
RO
0x0202.5400
ROM Version Register
230
0x130
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
231
0x200
FMPRE0
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 0
231
0x134
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
232
0x400
FMPPE0
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 0
232
0x1D0
BOOTCFG
R/W
0xFFFF.FFFE
Boot Configuration
233
0x1E0
USER_REG0
R/W
0xFFFF.FFFF
User Register 0
236
0x1E4
USER_REG1
R/W
0xFFFF.FFFF
User Register 1
237
0x1E8
USER_REG2
R/W
0xFFFF.FFFF
User Register 2
238
0x1EC
USER_REG3
R/W
0xFFFF.FFFF
User Register 3
239
0x204
FMPRE1
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 1
240
0x208
FMPRE2
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 2
241
0x20C
FMPRE3
R/W
0xFFFF.FFFF
Flash Memory Protection Read Enable 3
242
0x404
FMPPE1
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 1
243
0x408
FMPPE2
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 2
244
0x40C
FMPPE3
R/W
0xFFFF.FFFF
Flash Memory Protection Program Enable 3
245
7.5
Flash Memory Register Descriptions (Flash Control Offset)
This section lists and describes the Flash Memory registers, in numerical order by address offset.
Registers in this section are relative to the Flash control base address of 0x400F.D000.
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Internal Memory
Register 1: Flash Memory Address (FMA), offset 0x000
During a write operation, this register contains a 4-byte-aligned address and specifies where the
data is written. During erase operations, this register contains a 1 KB-aligned address and specifies
which page is erased. Note that the alignment requirements must be met by software or the results
of the operation are unpredictable.
Flash Memory Address (FMA)
Base 0x400F.D000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
24
23
22
21
20
19
18
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
16
OFFSET
OFFSET
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:18
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17:0
OFFSET
R/W
0x0
Address Offset
Address offset in Flash memory where operation is performed, except
for nonvolatile registers (see “Nonvolatile Register
Programming” on page 215 for details on values for this field).
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Register 2: Flash Memory Data (FMD), offset 0x004
This register contains the data to be written during the programming cycle or read during the read
cycle. Note that the contents of this register are undefined for a read access of an execute-only
block. This register is not used during erase cycles.
Flash Memory Data (FMD)
Base 0x400F.D000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
31:0
DATA
R/W
Reset
Description
0x0000.0000 Data Value
Data value for write operation.
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Internal Memory
Register 3: Flash Memory Control (FMC), offset 0x008
When this register is written, the Flash memory controller initiates the appropriate access cycle for
the location specified by the Flash Memory Address (FMA) register (see page 218). If the access
is a write access, the data contained in the Flash Memory Data (FMD) register (see page 219) is
written to the specified address.
This register must be the final register written and initiates the memory operation. The four control
bits in the lower byte of this register are used to initiate memory operations.
Care must be taken not to set multiple control bits as the results of such an operation are
unpredictable.
Flash Memory Control (FMC)
Base 0x400F.D000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
COMT
MERASE
ERASE
WRITE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
WRKEY
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:16
WRKEY
WO
0x0000
Description
Flash Memory Write Key
This field contains a write key, which is used to minimize the incidence
of accidental Flash memory writes. The value 0xA442 must be written
into this field for a Flash memory write to occur. Writes to the FMC
register without this WRKEY value are ignored. A read of this field returns
the value 0.
15:4
reserved
RO
0x000
3
COMT
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Commit Register Value
This bit is used to commit writes to Flash-memory-resident registers
and to monitor the progress of that process.
Value Description
1
Set this bit to commit (write) the register value to a
Flash-memory-resident register.
When read, a 1 indicates that the previous commit access is
not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous commit access is
complete.
A commit can take up to 50 μs.
See “Nonvolatile Register Programming” on page 215 for more information
on programming Flash-memory-resident registers.
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Bit/Field
Name
Type
Reset
2
MERASE
R/W
0
Description
Mass Erase Flash Memory
This bit is used to mass erase the Flash main memory and to monitor
the progress of that process.
Value Description
1
Set this bit to erase the Flash main memory.
When read, a 1 indicates that the previous mass erase access
is not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous mass erase access
is complete.
A mass erase can take up to 16 ms.
1
ERASE
R/W
0
Erase a Page of Flash Memory
This bit is used to erase a page of Flash memory and to monitor the
progress of that process.
Value Description
1
Set this bit to erase the Flash memory page specified by the
contents of the FMA register.
When read, a 1 indicates that the previous page erase access
is not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous page erase access
is complete.
A page erase can take up to 25 ms.
0
WRITE
R/W
0
Write a Word into Flash Memory
This bit is used to write a word into Flash memory and to monitor the
progress of that process.
Value Description
1
Set this bit to write the data stored in the FMD register into the
Flash memory location specified by the contents of the FMA
register.
When read, a 1 indicates that the write update access is not
complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous write update access
is complete.
Writing a single word can take up to 50 µs.
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Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the Flash memory controller has an interrupt condition. An interrupt is
sent to the interrupt controller only if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F.D000
Offset 0x00C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PRIS
ARIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
PRIS
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or erase
actions generated through the FMC or FMC2 register bits (see page 220
and page 225).
Value Description
1
The programming cycle has completed.
0
The programming cycle has not completed.
This status is sent to the interrupt controller when the PMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register.
0
ARIS
RO
0
Access Raw Interrupt Status
Value Description
1
A program or erase action was attempted on a block of Flash
memory that contradicts the protection policy for that block as
set in the FMPPEn registers.
0
No access has tried to improperly program or erase the Flash
memory.
This status is sent to the interrupt controller when the AMASK bit in the
FCIM register is set.
This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
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Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the Flash memory controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F.D000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
PMASK
AMASK
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
PMASK
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt status
to the interrupt controller.
Value Description
0
AMASK
R/W
0
1
An interrupt is sent to the interrupt controller when the PRIS bit
is set.
0
The PRIS interrupt is suppressed and not sent to the interrupt
controller.
Access Interrupt Mask
This bit controls the reporting of the access raw interrupt status to the
interrupt controller.
Value Description
1
An interrupt is sent to the interrupt controller when the ARIS bit
is set.
0
The ARIS interrupt is suppressed and not sent to the interrupt
controller.
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Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC),
offset 0x014
This register provides two functions. First, it reports the cause of an interrupt by indicating which
interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the
interrupt reporting.
Flash Controller Masked Interrupt Status and Clear (FCMISC)
Base 0x400F.D000
Offset 0x014
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
PMISC
R/W1C
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
1
0
PMISC
AMISC
R/W1C
0
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Programming Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
Writing a 1 to this bit clears PMISC and also the PRIS bit in the
FCRIS register (see page 222).
0
When read, a 0 indicates that a programming cycle complete
interrupt has not occurred.
A write of 0 has no effect on the state of this bit.
0
AMISC
R/W1C
0
Access Masked Interrupt Status and Clear
Value Description
1
When read, a 1 indicates that an unmasked interrupt was
signaled because a program or erase action was attempted on
a block of Flash memory that contradicts the protection policy
for that block as set in the FMPPEn registers.
Writing a 1 to this bit clears AMISC and also the ARIS bit in the
FCRIS register (see page 222).
0
When read, a 0 indicates that no improper accesses have
occurred.
A write of 0 has no effect on the state of this bit.
224
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 7: Flash Memory Control 2 (FMC2), offset 0x020
When this register is written, the Flash memory controller initiates the appropriate access cycle for
the location specified by the Flash Memory Address (FMA) register (see page 218). If the access
is a write access, the data contained in the Flash Write Buffer (FWB) registers is written.
This register must be the final register written as it initiates the memory operation.
Flash Memory Control 2 (FMC2)
Base 0x400F.D000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
8
7
6
5
4
3
2
1
WRKEY
Type
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
15
14
13
12
11
10
9
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:16
WRKEY
WO
0x0000
RO
0
0
WRBUF
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
Description
Flash Memory Write Key
This field contains a write key, which is used to minimize the incidence
of accidental Flash memory writes. The value 0xA442 must be written
into this field for a write to occur. Writes to the FMC2 register without
this WRKEY value are ignored. A read of this field returns the value 0.
15:1
reserved
RO
0x000
0
WRBUF
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Buffered Flash Memory Write
This bit is used to start a buffered write to Flash memory.
Value Description
1
Set this bit to write the data stored in the FWBn registers to the
location specified by the contents of the FMA register.
When read, a 1 indicates that the previous buffered Flash
memory write access is not complete.
0
A write of 0 has no effect on the state of this bit.
When read, a 0 indicates that the previous buffered Flash
memory write access is complete.
A buffered Flash memory write can take up to 4 ms.
June 14, 2010
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Texas Instruments-Advance Information
Internal Memory
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030
This register provides a bitwise status of which FWBn registers have been written by the processor
since the last write of the Flash memory write buffer. The entries with a 1 are written on the next
write of the Flash memory write buffer. This register is cleared after the write operation by hardware.
A protection violation on the write operation also clears this status.
Software can program the same 32 words to various Flash memory locations by setting the FWB[n]
bits after they are cleared by the write operation. The next write operation then uses the same data
as the previous one. In addition, if a FWBn register change should not be written to Flash memory,
software can clear the corresponding FWB[n] bit to preserve the existing data when the next write
operation occurs.
Flash Write Buffer Valid (FWBVAL)
Base 0x400F.D000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FWB[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
FWB[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:0
FWB[n]
R/W
0x0
R/W
0
Description
Flash Memory Write Buffer
Value Description
1
The corresponding FWBn register has been updated since the
last buffer write operation and is ready to be written to Flash
memory.
0
The corresponding FWBn register has no new data to be written.
Bit 0 corresponds to FWB0, offset 0x100, and bit 31 corresponds to
FWB31, offset 0x13C.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 9: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C
These 32 registers hold the contents of the data to be written into the Flash memory on a buffered
Flash memory write operation. The offset selects one of the 32-bit registers. Only FWBn registers
that have been updated since the preceding buffered Flash memory write operation are written into
the Flash memory, so it is not necessary to write the entire bank of registers in order to write 1 or
2 words. The FWBn registers are written into the Flash memory with the FWB0 register corresponding
to the address contained in FMA. FWB1 is written to the address FMA+0x4 etc. Note that only data
bits that are 0 result in the Flash memory being modified. A data bit that is 1 leaves the content of
the Flash memory bit at its previous value.
Flash Write Buffer n (FWBn)
Base 0x400F.D000
Offset 0x100 - 0x17C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
31:0
DATA
R/W
Reset
Description
0x0000.0000 Data
Data to be written into the Flash memory.
June 14, 2010
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Texas Instruments-Advance Information
Internal Memory
Register 10: Flash Control (FCTL), offset 0x0F8
This register is used to ensure that the microcontroller is powered down in a controlled fashion in
systems where power is cycled more frequently than once every five minutes. The USDREQ bit
should be set to indicate that power is going to be turned off. Software should poll the USDACK bit
to determine when it is acceptable to power down.
Flash Control (FCTL)
Base 0x400F.D000
Offset 0x0F8
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1
USDACK
RO
0
USDACK USDREQ
RO
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
User Shut Down Acknowledge
Value Description
1
The microcontroller can be powered down.
0
The microcontroller cannot yet be powered down.
This bit should be set within 50 ms of setting the USDREQ bit.
0
USDREQ
R/W
0
User Shut Down Request
Value Description
7.6
1
Requests permission to power down the microcontroller.
0
No effect.
Memory Register Descriptions (System Control Offset)
The remainder of this section lists and describes the registers that reside in Flash memory, in
numerical order by address offset. Registers in this section are relative to the System Control base
address of 0x400F.E000.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 11: ROM Control (RMCTL), offset 0x0F0
This register provides control of the ROM controller state. This register offset is relative to the System
Control base address of 0x400F.E000.
ROM Control (RMCTL)
Base 0x400F.E000
Offset 0x0F0
Type R/W1C, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
-
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
BA
R/W1C
-
RO
0
BA
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Boot Alias
At reset, the user has the opportunity to direct the core to execute the
ROM Boot Loader or the application in Flash memory by using any
GPIO signal as configured in the BOOTCFG register. If the ROM boot
loader is not selected, the system control module checks address
0x000.0004 to see if the Flash memory has a valid reset vector. If the
data at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that
the Flash memory has not yet been programmed, and this bit is then
set by hardware so that the on-chip ROM appears at address 0x0.
Value Description
1
The microcontroller's ROM appears at address 0x0. This bit is
set automatically if the data at address 0x0000.0004 is
0xFFFF.FFFF.
0
The Flash memory is at address 0x0.
This bit is cleared by writing a 1 to this bit position.
June 14, 2010
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Texas Instruments-Advance Information
Internal Memory
Register 12: ROM Version Register (RMVER), offset 0x0F4
Note:
Offset is relative to System Control base address of 0x400FE000.
A 32-bit read-only register containing the ROM content version information.
ROM Version Register (RMVER)
Base 0x400F.E000
Offset 0x0F4
Type RO, reset 0x0202.5400
31
30
29
28
27
26
25
24
23
22
21
20
CONT
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
5
4
VER
Type
Reset
RO
0
RO
1
RO
0
RO
1
19
18
17
16
RO
0
RO
0
RO
1
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
SIZE
REV
RO
0
RO
1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:24
CONT
RO
0x02
ROM Contents
RO
0
RO
0
RO
0
Value Description
0x02 Stellaris Boot Loader & DriverLib with AES and Ethernet
23:16
SIZE
RO
0x02
ROM Size of Contents
This field encodes the size of the ROM.
Value Description
0x02 Stellaris Boot Loader & DriverLib with AES and Ethernet
15:8
VER
RO
0x54
ROM Version
7:0
REV
RO
0x0
ROM Revision
230
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 13: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130
and 0x200
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For
additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Read Enable 0 (FMPRE0)
Base 0x400F.E000
Offset 0x130 and 0x200
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in the table “Flash Protection Policy
Combinations”.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
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Texas Instruments-Advance Information
Internal Memory
Register 14: Flash Memory Protection Program Enable 0 (FMPPE0), offset
0x134 and 0x400
Note:
This register is aliased for backwards compatability.
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. For
additional information, see the "Flash Memory Protection" section.
Flash Memory Protection Program Enable 0 (FMPPE0)
Base 0x400F.E000
Offset 0x134 and 0x400
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Configures 2-KB flash blocks to be execute only. The policies may be
combined as shown in the table “Flash Protection Policy Combinations”.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory up to the total of 64 KB.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 15: Boot Configuration (BOOTCFG), offset 0x1D0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides configuration of a GPIO pin to enable the ROM Boot Loader as well as a
write-once mechanism to disable external debugger access to the device. Upon reset, the user has
the opportunity to direct the core to execute the ROM Boot Loader or the application in Flash memory
by using any GPIO signal from Ports A-H as configured by the bits in this register. If the EN bit is
set or the specified pin does not have the required polarity, the system control module checks
address 0x000.0004 to see if the Flash memory has a valid reset vector. If the data at address
0x0000.0004 is 0xFFFF.FFFF, then it is assumed that the Flash memory has not yet been
programmed, and the core executes the ROM Boot Loader. The DBG0 bit (bit 0) is set to 0 from
the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Clearing the
DBG1 bit disables any external debugger access to the device permanently, starting with the next
power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been
committed and is controlled through hardware to ensure that the register is only committed once.
Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies
to power-on reset; any other type of reset does not affect this register. The only way to restore the
factory default value of this register is to perform the "Recover Locked Device" sequence detailed
in the JTAG chapter.
Boot Configuration (BOOTCFG)
Base 0x400F.E000
Offset 0x1D0
Type R/W, reset 0xFFFF.FFFE
31
30
29
28
27
26
25
24
NW
Type
Reset
R/W
1
15
RO
1
RO
1
RO
1
14
13
12
PORT
Type
Reset
R/W
1
23
22
21
20
19
18
17
16
RO
1
RO
1
reserved
R/W
1
RO
1
RO
1
11
10
PIN
R/W
1
R/W
1
R/W
1
R/W
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
RO
1
7
6
5
4
3
2
9
8
POL
EN
R/W
1
R/W
1
reserved
RO
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
RO
1
RO
1
RO
1
RO
1
RO
1
1
0
DBG1
DBG0
R/W
1
R/W
0
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:16
reserved
RO
0x7FFF
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 14, 2010
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Texas Instruments-Advance Information
Internal Memory
Bit/Field
Name
Type
Reset
15:13
PORT
R/W
0x7
Description
Boot GPIO Port
This field selects the port of the GPIO port pin that enables the ROM
boot loader at reset.
Value Description
12:10
PIN
R/W
0x7
0x0
Port A
0x1
Port B
0x2
Port C
0x3
Port D
0x4
Port E
0x5
Port F
0x6
Port G
0x7
Port H
Boot GPIO Pin
This field selects the pin number of the GPIO port pin that enables the
ROM boot loader at reset.
Value Description
9
POL
R/W
0x1
0x0
Pin 0
0x1
Pin 1
0x2
Pin 2
0x3
Pin 3
0x4
Pin 4
0x5
Pin 5
0x6
Pin 6
0x7
Pin 7
Boot GPIO Polarity
When set, this bit selects a high level for the GPIO port pin to enable
the ROM boot loader at reset. When clear, this bit selects a low level
for the GPIO port pin.
8
EN
R/W
0x1
Boot GPIO Enable
Clearing this bit enables the use of a GPIO pin to enable the ROM Boot
Loader at reset. When this bit is set, the contents of address
0x0000.0004 are checked to see if the Flash memory has been
programmed. If the contents are not 0xFFFF.FFFF, the core executes
out of Flash memory. If the Flash has not been programmed, the core
executes out of ROM.
7:2
reserved
RO
0x3F
1
DBG1
R/W
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Debug Control 1
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
0
DBG0
R/W
0x0
Description
Debug Control 0
The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available.
June 14, 2010
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Internal Memory
Register 16: User Register 0 (USER_REG0), offset 0x1E0
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be committed
once. Bit 31 indicates that the register is available to be committed and is controlled through hardware
to ensure that the register is only committed once. Prior to being committed, bits can only be changed
from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not
affect this register. The write-once characteristics of this register are useful for keeping static
information like communication addresses that need to be unique per part and would otherwise
require an external EEPROM or other non-volatile device. The only way to restore the factory default
value of this register is to perform the "Recover Locked Device" sequence detailed in the JTAG
section.
User Register 0 (USER_REG0)
Base 0x400F.E000
Offset 0x1E0
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Stellaris® LM3S9B95 Microcontroller
Register 17: User Register 1 (USER_REG1), offset 0x1E4
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 1 (USER_REG1)
Base 0x400F.E000
Offset 0x1E4
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Internal Memory
Register 18: User Register 2 (USER_REG2), offset 0x1E8
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 2 (USER_REG2)
Base 0x400F.E000
Offset 0x1E8
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
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Stellaris® LM3S9B95 Microcontroller
Register 19: User Register 3 (USER_REG3), offset 0x1EC
Note:
Offset is relative to System Control base address of 0x400FE000.
This register provides 31 bits of user-defined data that is non-volatile and can only be written once.
Bit 31 indicates that the register is available to be written and is controlled through hardware to
ensure that the register is only written once. The write-once characteristics of this register are useful
for keeping static information like communication addresses that need to be unique per part and
would otherwise require an external EEPROM or other non-volatile device.
User Register 3 (USER_REG3)
Base 0x400F.E000
Offset 0x1EC
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
NW
Type
Reset
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
DATA
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
DATA
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31
NW
R/W
1
Not Written
When set, this bit indicates that this 32-bit register has not been
committed. When clear, this bit specifies that this register has been
committed and may not be committed again.
30:0
DATA
R/W
0x7FFFFFFF User Data
Contains the user data value. This field is initialized to all 1s and can
only be committed once.
June 14, 2010
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Texas Instruments-Advance Information
Internal Memory
Register 20: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the
Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Read Enable 1 (FMPRE1)
Base 0x400F.E000
Offset 0x204
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in the table “Flash Protection Policy
Combinations”.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
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Stellaris® LM3S9B95 Microcontroller
Register 21: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the
Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Read Enable 2 (FMPRE2)
Base 0x400F.E000
Offset 0x208
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in the table “Flash Protection Policy
Combinations”.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 129 to 192 KB.
June 14, 2010
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Internal Memory
Register 22: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the
Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Read Enable 3 (FMPRE3)
Base 0x400F.E000
Offset 0x20C
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
8
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
READ_ENABLE
Type
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit/Field
Name
Type
31:0
READ_ENABLE
R/W
R/W
1
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Read Enable
Configures 2-KB flash blocks to be read or executed only. The policies
may be combined as shown in the table “Flash Protection Policy
Combinations”.
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 193 to 256 KB.
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Stellaris® LM3S9B95 Microcontroller
Register 23: Flash Memory Protection Program Enable 1 (FMPPE1), offset
0x404
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the
Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Program Enable 1 (FMPPE1)
Base 0x400F.E000
Offset 0x404
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in memory range from 65 to 128 KB.
June 14, 2010
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Internal Memory
Register 24: Flash Memory Protection Program Enable 2 (FMPPE2), offset
0x408
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the
Flash memory size on the device is less than 128 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Program Enable 2 (FMPPE2)
Base 0x400F.E000
Offset 0x408
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 129 to 192 KB.
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Stellaris® LM3S9B95 Microcontroller
Register 25: Flash Memory Protection Program Enable 3 (FMPPE3), offset
0x40C
Note:
Offset is relative to System Control base address of 0x400FE000.
This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the
execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn
registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on
reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for
all implemented banks. This achieves a policy of open access and programmability. The register
bits may be changed by writing the specific register bit. However, this register is R/W0; the user can
only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are
not permanent until the register is committed (saved), at which point the bit change is permanent.
If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on
reset sequence. The reset value shown only applies to power-on reset; any other type of reset does
not affect this register. Once committed, the only way to restore the factory default value of this
register is to perform the "Recover Locked Device" sequence detailed in the JTAG chapter. If the
Flash memory size on the device is less than 192 KB, this register usually reads as zeroes, but
software should not rely on these bits to be zero. For additional information, see the "Flash Memory
Protection" section.
Flash Memory Protection Program Enable 3 (FMPPE3)
Base 0x400F.E000
Offset 0x40C
Type R/W, reset 0xFFFF.FFFF
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
PROG_ENABLE
Type
Reset
PROG_ENABLE
Type
Reset
Bit/Field
Name
Type
31:0
PROG_ENABLE
R/W
Reset
R/W
1
R/W
1
Description
0xFFFFFFFF Flash Programming Enable
Value
Description
0xFFFFFFFF Bits [31:0] each enable protection on a 2-KB block of
Flash memory in the range from 193 to 256 KB.
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8
Micro Direct Memory Access (μDMA)
The LM3S9B95 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
■ ARM PrimeCell® 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules: GP Timer, USB, UART, Ethernet, ADC,
EPI, SSI, I2S
– Primary and secondary channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable bus arbitration scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
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■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
8.1
Block Diagram
Figure 8-1. μDMA Block Diagram
uDMA
Controller
DMA error
System Memory
CH Control Table
Peripheral
DMA Channel 0
•
•
•
Peripheral
DMA Channel N-1
Nested
Vectored
Interrupt
Controller
(NVIC)
IRQ
General
Peripheral N
Registers
request
done
request
done
request
done
DMASTAT
DMACFG
DMACTLBASE
DMAALTBASE
DMAWAITSTAT
DMASWREQ
DMAUSEBURSTSET
DMAUSEBURSTCLR
DMAREQMASKSET
DMAREQMASKCLR
DMAENASET
DMAENACLR
DMAALTSET
DMAALTCLR
DMAPRIOSET
DMAPRIOCLR
DMAERRCLR
DMACHASGN
DMASRCENDP
DMADSTENDP
DMACHCTRL
•
•
•
DMASRCENDP
DMADSTENDP
DMACHCTRL
Transfer Buffers
Used by µDMA
ARM
Cortex-M3
8.2
Functional Description
The μDMA controller is a flexible and highly configurable DMA controller designed to work efficiently
with the microcontroller's Cortex-M3 processor core. It supports multiple data sizes and address
increment schemes, multiple levels of priority among DMA channels, and several transfer modes
to allow for sophisticated programmed data transfers. The μDMA controller's usage of the bus is
always subordinate to the processor core, so it never holds up a bus transaction by the processor.
Because the μDMA controller is only using otherwise-idle bus cycles, the data transfer bandwidth
it provides is essentially free, with no impact on the rest of the system. The bus architecture has
been optimized to greatly enhance the ability of the processor core and the μDMA controller to
efficiently share the on-chip bus, thus improving performance. The optimizations include RAM
striping and peripheral bus segmentation, which in many cases allow both the processor core and
the μDMA controller to access the bus and perform simultaneous data transfers.
The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data from the
Flash memory or ROM with the μDMA controller.
Each peripheral function that is supported has a dedicated channel on the μDMA controller that can
be configured independently. The μDMA controller implements a unique configuration method using
channel control structures that are maintained in system memory by the processor. While simple
transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that
allow the μDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part
of a single transfer request. The μDMA controller also supports the use of ping-pong buffering to
accommodate constant streaming of data to or from a peripheral.
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Each channel also has a configurable arbitration size. The arbitration size is the number of items
that are transferred in a burst before the μDMA controller rearbitrates for channel priority. Using the
arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral
each time it makes a μDMA service request.
8.2.1
Channel Assignments
μDMA channels 0-31 are assigned to peripherals according to the following table. The DMA Channel
Assignment (DMACHASGN) register (see page 294) can be used to specify the primary or secondary
assignment. If the primary function is not available on this microcontroller, the secondary function
becomes the primary function. If the secondary function is not available, the primary function is the
only option.
Note:
Channels noted in the table as "Available for software" may be assigned to peripherals in
the future. However, they are currently available for software use. Channel 30 is dedicated
for software use.
The USB endpoints mapped to μDMA channels 0-3 can be changed with the USBDMASEL
register (see page 1012).
If a channel is marked with "*" below and is configured to transfer data with a software
request using the DMASWREQ register, this channel must also be enabled in the
DMAENASET register.
Table 8-1. μDMA Channel Assignments
μDMA Channel
Primary Assignment
Secondary Assignment
0
USB Endpoint 1 Receive
UART2 Receive*
1
USB Endpoint 1 Transmit
UART2 Transmit*
2
USB Endpoint 2 Receive
General-Purpose Timer 3A*
3
USB Endpoint 2 Transmit
General-Purpose Timer 3B*
4
USB Endpoint 3 Receive
General-Purpose Timer 2A*
5
USB Endpoint 3 Transmit
General-Purpose Timer 2B*
6
Ethernet Receive
General-Purpose Timer 2A*
7
Ethernet Transmit
General-Purpose Timer 2B*
8
UART0 Receive
UART1 Receive
9
UART0 Transmit
UART1 Transmit
10
SSI0 Receive
SSI1 Receive
11
SSI0 Transmit
SSI1 Transmit
12
Available for software
UART2 Receive*
13
Available for software
UART2 Transmit*
14
ADC0 Sample Sequencer 0
General-Purpose Timer 2A*
15
ADC0 Sample Sequencer 1
General-Purpose Timer 2B*
16
ADC0 Sample Sequencer 2
Available for software
17
ADC0 Sample Sequencer 3
Available for software
18
General-Purpose Timer 0A
General-Purpose Timer 1A
19
General-Purpose Timer 0B
General-Purpose Timer 1B
20
General-Purpose Timer 1A
EPI0 NBRFIFO*
21
General-Purpose Timer 1B
EPI0 WFIFO*
22
UART1 Receive
Available for software
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Table 8-1. μDMA Channel Assignments (continued)
μDMA Channel
8.2.2
Primary Assignment
Secondary Assignment
23
UART1 Transmit
Available for software
24
SSI1 Receive
ADC1 Sample Sequencer 0*
25
SSI1 Transmit
ADC1 Sample Sequencer 1*
26
Available for software
ADC1 Sample Sequencer 2*
27
Available for software
ADC1 Sample Sequencer 3*
28
I2S0 Receive
Available for software
29
I2S0
Available for software
30
Dedicated for software use
31
Reserved
Transmit
Priority
The μDMA controller assigns priority to each channel based on the channel number and the priority
level bit for the channel. Channel number 0 has the highest priority and as the channel number
increases, the priority of a channel decreases. Each channel has a priority level bit to provide two
levels of priority: default priority and high priority. If the priority level bit is set, then that channel has
higher priority than all other channels at default priority. If multiple channels are set for high priority,
then the channel number is used to determine relative priority among all the high priority channels.
The priority bit for a channel can be set using the DMA Channel Priority Set (DMAPRIOSET)
register and cleared with the DMA Channel Priority Clear (DMAPRIOCLR) register.
8.2.3
Arbitration Size
When a μDMA channel requests a transfer, the μDMA controller arbitrates among all the channels
making a request and services the μDMA channel with the highest priority. Once a transfer begins,
it continues for a selectable number of transfers before rearbitrating among the requesting channels
again. The arbitration size can be configured for each channel, ranging from 1 to 1024 item transfers.
After the μDMA controller transfers the number of items specified by the arbitration size, it then
checks among all the channels making a request and services the channel with the highest priority.
If a lower priority μDMA channel uses a large arbitration size, the latency for higher priority channels
is increased because the μDMA controller completes the lower priority burst before checking for
higher priority requests. Therefore, lower priority channels should not use a large arbitration size
for best response on high priority channels.
The arbitration size can also be thought of as a burst size. It is the maximum number of items that
are transferred at any one time in a burst. Here, the term arbitration refers to determination of μDMA
channel priority, not arbitration for the bus. When the μDMA controller arbitrates for the bus, the
processor always takes priority. Furthermore, the μDMA controller is held off whenever the processor
must perform a bus transaction on the same bus, even in the middle of a burst transfer.
8.2.4
Request Types
The μDMA controller responds to two types of requests from a peripheral: single or burst. Each
peripheral may support either or both types of requests. A single request means that the peripheral
is ready to transfer one item, while a burst request means that the peripheral is ready to transfer
multiple items.
The μDMA controller responds differently depending on whether the peripheral is making a single
request or a burst request. If both are asserted, and the μDMA channel has been set up for a burst
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transfer, then the burst request takes precedence. See Table 8-2, which shows how each peripheral
supports the two request types.
Table 8-2. Request Type Support
Peripheral
8.2.4.1
Single Request Signal
Burst Request Signal
USB TX
None
FIFO TXRDY
USB RX
None
FIFO RXRDY
Ethernet TX
TX FIFO empty
None
Ethernet RX
RX packet received
None
UART TX
TX FIFO Not Full
TX FIFO Level (configurable)
UART RX
RX FIFO Not Empty
RX FIFO Level (configurable)
SSI TX
TX FIFO Not Full
TX FIFO Level (fixed at 4)
SSI RX
RX FIFO Not Empty
RX FIFO Level (fixed at 4)
ADC
None
Sequencer IE bit
General-Purpose Timer
None
Raw interrupt pulse
I2S TX
None
FIFO service request
I2S RX
None
FIFO service request
EPI WFIFO
None
WFIFO Level (configurable)
EPI NBRFIFO
None
NBRFIFO Level (configurable)
Single Request
When a single request is detected, and not a burst request, the μDMA controller transfers one item
and then stops to wait for another request.
8.2.4.2
Burst Request
When a burst request is detected, the μDMA controller transfers the number of items that is the
lesser of the arbitration size or the number of items remaining in the transfer. Therefore, the arbitration
size should be the same as the number of data items that the peripheral can accommodate when
making a burst request. For example, the UART generates a burst request based on the FIFO trigger
level. In this case, the arbitration size should be set to the amount of data that the FIFO can transfer
when the trigger level is reached. A burst transfer runs to completion once it is started, and cannot
be interrupted, even by a higher priority channel. Burst transfers complete in a shorter time than the
same number of non-burst transfers.
It may be desirable to use only burst transfers and not allow single transfers. For example, perhaps
the nature of the data is such that it only makes sense when transferred together as a single unit
rather than one piece at a time. The single request can be disabled by using the DMA Channel
Useburst Set (DMAUSEBURSTSET) register. By setting the bit for a channel in this register, the
μDMA controller only responds to burst requests for that channel.
8.2.5
Channel Configuration
The μDMA controller uses an area of system memory to store a set of channel control structures
in a table. The control table may have one or two entries for each μDMA channel. Each entry in the
table structure contains source and destination pointers, transfer size, and transfer mode. The
control table can be located anywhere in system memory, but it must be contiguous and aligned on
a 1024-byte boundary.
Table 8-3 on page 251 shows the layout in memory of the channel control table. Each channel may
have one or two control structures in the control table: a primary control structure and an optional
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alternate control structure. The table is organized so that all of the primary entries are in the first
half of the table, and all the alternate structures are in the second half of the table. The primary entry
is used for simple transfer modes where transfers can be reconfigured and restarted after each
transfer is complete. In this case, the alternate control structures are not used and therefore only
the first half of the table must be allocated in memory; the second half of the control table is not
necessary, and that memory can be used for something else. If a more complex transfer mode is
used such as ping-pong or scatter-gather, then the alternate control structure is also used and
memory space should be allocated for the entire table.
Any unused memory in the control table may be used by the application. This includes the control
structures for any channels that are unused by the application as well as the unused control word
for each channel.
Table 8-3. Control Structure Memory Map
Offset
Channel
0x0
0, Primary
0x10
1, Primary
...
...
0x1F0
31, Primary
0x200
0, Alternate
0x210
1, Alternate
...
...
0x3F0
31, Alternate
Table 8-4 shows an individual control structure entry in the control table. Each entry is aligned on
a 16-byte boundary. The entry contains four long words: the source end pointer, the destination end
pointer, the control word, and an unused entry. The end pointers point to the ending address of the
transfer and are inclusive. If the source or destination is non-incrementing (as for a peripheral
register), then the pointer should point to the transfer address.
Table 8-4. Channel Control Structure
Offset
Description
0x000
Source End Pointer
0x004
Destination End Pointer
0x008
Control Word
0x00C
Unused
The control word contains the following fields:
■ Source and destination data sizes
■ Source and destination address increment size
■ Number of transfers before bus arbitration
■ Total number of items to transfer
■ Useburst flag
■ Transfer mode
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The control word and each field are described in detail in “μDMA Channel Control
Structure” on page 268. The μDMA controller updates the transfer size and transfer mode fields as
the transfer is performed. At the end of a transfer, the transfer size indicates 0, and the transfer
mode indicates "stopped." Because the control word is modified by the μDMA controller, it must be
reconfigured before each new transfer. The source and destination end pointers are not modified,
so they can be left unchanged if the source or destination addresses remain the same.
Prior to starting a transfer, a μDMA channel must be enabled by setting the appropriate bit in the
DMA Channel Enable Set (DMAENASET) register. A channel can be disabled by setting the
channel bit in the DMA Channel Enable Clear (DMAENACLR) register. At the end of a complete
μDMA transfer, the controller automatically disables the channel.
8.2.6
Transfer Modes
The μDMA controller supports several transfer modes. Two of the modes support simple one-time
transfers. Several complex modes support a continuous flow of data.
8.2.6.1
Stop Mode
While Stop is not actually a transfer mode, it is a valid value for the mode field of the control word.
When the mode field has this value, the μDMA controller does not perform any transfers and disables
the channel if it is enabled. At the end of a transfer, the μDMA controller updates the control word
to set the mode to Stop.
8.2.6.2
Basic Mode
In Basic mode, the μDMA controller performs transfers as long as there are more items to transfer,
and a transfer request is present. This mode is used with peripherals that assert a μDMA request
signal whenever the peripheral is ready for a data transfer. Basic mode should not be used in any
situation where the request is momentary even though the entire transfer should be completed. For
example, a software-initiated transfer creates a momentary request, and in Basic mode, only the
number of transfers specified by the ARBSIZE field in the DMA Channel Control Word (DMACHCTL)
register is transferred on a software request, even if there is more data to transfer.
When all of the items have been transferred using Basic mode, the μDMA controller sets the mode
for that channel to Stop.
8.2.6.3
Auto Mode
Auto mode is similar to Basic mode, except that once a transfer request is received, the transfer
runs to completion, even if the μDMA request is removed. This mode is suitable for software-triggered
transfers. Generally, Auto mode is not used with a peripheral.
When all the items have been transferred using Auto mode, the μDMA controller sets the mode for
that channel to Stop.
8.2.6.4
Ping-Pong
Ping-Pong mode is used to support a continuous data flow to or from a peripheral. To use Ping-Pong
mode, both the primary and alternate data structures must be implemented. Both structures are set
up by the processor for data transfer between memory and a peripheral. The transfer is started
using the primary control structure. When the transfer using the primary control structure is complete,
the μDMA controller reads the alternate control structure for that channel to continue the transfer.
Each time this happens, an interrupt is generated, and the processor can reload the control structure
for the just-completed transfer. Data flow can continue indefinitely this way, using the primary and
alternate control structures to switch back and forth between buffers as the data flows to or from
the peripheral.
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Refer to Figure 8-2 for an example showing operation in Ping-Pong mode.
Figure 8-2. Example of Ping-Pong μDMA Transaction
µDMA Controller
SOURCE
DEST
CONTROL
Unused
transfers using BUFFER A
transfer continues using alternate
Primary Structure
Cortex-M3 Processor
SOURCE
DEST
CONTROL
Unused
Pe
rip
he
ral
/µD
M
AI
nte
Time
transfers using BUFFER B
SOURCE
DEST
CONTROL
Unused
Alternate Structure
8.2.6.5
SOURCE
DEST
CONTROL
Unused
BUFFER B
· Process data in BUFFER A
· Reload primary structure
Pe
rip
he
ral
/µD
M
AI
nte
r
transfers using BUFFER A
rup
t
BUFFER A
· Process data in BUFFER B
· Reload alternate structure
transfer continues using alternate
Primary Structure
rru
p
t
transfer continues using primary
Alternate Structure
BUFFER A
Pe
rip
he
ral
/µD
M
AI
nte
transfers using BUFFER B
rru
pt
BUFFER B
· Process data in BUFFER B
· Reload alternate structure
Memory Scatter-Gather
Memory Scatter-Gather mode is a complex mode used when data must be transferred to or from
varied locations in memory instead of a set of contiguous locations in a memory buffer. For example,
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a gather μDMA operation could be used to selectively read the payload of several stored packets
of a communication protocol and store them together in sequence in a memory buffer.
In Memory Scatter-Gather mode, the primary control structure is used to program the alternate
control structure from a table in memory. The table is set up by the processor software and contains
a list of control structures, each containing the source and destination end pointers, and the control
word for a specific transfer. The mode of each control word must be set to Scatter-Gather mode.
Each entry in the table is copied in turn to the alternate structure where it is then executed. The
μDMA controller alternates between using the primary control structure to copy the next transfer
instruction from the list and then executing the new transfer instruction. The end of the list is marked
by programming the control word for the last entry to use Basic transfer mode. Once the last transfer
is performed using Basic mode, the μDMA controller stops. A completion interrupt is generated only
after the last transfer. It is possible to loop the list by having the last entry copy the primary control
structure to point back to the beginning of the list (or to a new list). It is also possible to trigger a set
of other channels to perform a transfer, either directly, by programming a write to the software trigger
for another channel, or indirectly, by causing a peripheral action that results in a μDMA request.
By programming the μDMA controller using this method, a set of arbitrary transfers can be performed
based on a single μDMA request.
Refer to Figure 8-3 on page 255 and Figure 8-4 on page 256, which show an example of operation
in Memory Scatter-Gather mode. This example shows a gather operation, where data in three
separate buffers in memory is copied together into one buffer. Figure 8-3 on page 255 shows how
the application sets up a μDMA task list in memory that is used by the controller to perform three
sets of copy operations from different locations in memory. The primary control structure for the
channel that is used for the operation is configured to copy from the task list to the alternate control
structure.
Figure 8-4 on page 256 shows the sequence as the μDMA controller performs the three sets of copy
operations. First, using the primary control structure, the μDMA controller loads the alternate control
structure with task A. It then performs the copy operation specified by task A, copying the data from
the source buffer A to the destination buffer. Next, the μDMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
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Figure 8-3. Memory Scatter-Gather, Setup and Configuration
1
2
3
Source and Destination
Buffer in Memory
Task List in Memory
Channel Control
Table in Memory
4 WORDS (SRC A)
SRC
A
DST
ITEMS=4
16 WORDS (SRC B)
SRC
Unused
DST
SRC
ITEMS=12
DST
B
“TASK” A
ITEMS=16
Channel Primary
Control Structure
“TASK” B
Unused
SRC
DST
ITEMS=1
“TASK” C
Unused
SRC
DST
Channel Alternate
Control Structure
ITEMS=n
1 WORD (SRC C)
C
4 (DEST A)
16 (DEST B)
1 (DEST C)
NOTES:
1. Application has a need to copy data items from three separate locations in memory into one combined buffer.
2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three
µDMA copy “tasks.”
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it is executed by the µDMA controller.
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Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
COPIED
DST
TASK A
TASK B
SRC
SRC C
ALT
COPIED
DST
TASK C
DEST A
DEST B
DEST C
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer A to
the destination buffer.
Using the channel’s primary control structure, the µDMA
controller copies task A configuration to the channel’s
alternate control structure.
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC B
SRC
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
COPIED
ALT
COPIED
DST
DEST A
DEST B
DEST C
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer B to
the destination buffer.
Using the channel’s primary control structure, the µDMA
controller copies task B configuration to the channel’s
alternate control structure.
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
ALT
DST
DEST A
COPIED
COPIED
DEST B
DEST C
Using the channel’s primary control structure, the µDMA
controller copies task C configuration to the channel’s
alternate control structure.
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer C to
the destination buffer.
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8.2.6.6
Peripheral Scatter-Gather
Peripheral Scatter-Gather mode is very similar to Memory Scatter-Gather, except that the transfers
are controlled by a peripheral making a μDMA request. Upon detecting a request from the peripheral,
the μDMA controller uses the primary control structure to copy one entry from the list to the alternate
control structure and then performs the transfer. At the end of this transfer, the next transfer is started
only if the peripheral again asserts a μDMA request. The μDMA controller continues to perform
transfers from the list only when the peripheral is making a request, until the last transfer is complete.
A completion interrupt is generated only after the last transfer.
By using this method, the μDMA controller can transfer data to or from a peripheral from a set of
arbitrary locations whenever the peripheral is ready to transfer data.
Refer to Figure 8-5 on page 258 and Figure 8-6 on page 259, which show an example of operation
in Peripheral Scatter-Gather mode. This example shows a gather operation, where data from three
separate buffers in memory is copied to a single peripheral data register. Figure 8-5 on page 258
shows how the application sets up a µDMA task list in memory that is used by the controller to
perform three sets of copy operations from different locations in memory. The primary control
structure for the channel that is used for the operation is configured to copy from the task list to the
alternate control structure.
Figure 8-6 on page 259 shows the sequence as the µDMA controller performs the three sets of copy
operations. First, using the primary control structure, the µDMA controller loads the alternate control
structure with task A. It then performs the copy operation specified by task A, copying the data from
the source buffer A to the peripheral data register. Next, the µDMA controller again uses the primary
control structure to load task B into the alternate control structure, and then performs the B operation
with the alternate control structure. The process is repeated for task C.
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Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration
1
2
3
Source Buffer
in Memory
Task List in Memory
Channel Control
Table in Memory
4 WORDS (SRC A)
SRC
A
DST
ITEMS=4
16 WORDS (SRC B)
SRC
DST
SRC
ITEMS=12
DST
B
“TASK” A
Unused
ITEMS=16
Channel Primary
Control Structure
“TASK” B
Unused
SRC
DST
ITEMS=1
“TASK” C
Unused
SRC
DST
Channel Alternate
Control Structure
ITEMS=n
1 WORD (SRC C)
C
Peripheral Data
Register
DEST
NOTES:
1. Application has a need to copy data items from three separate locations in memory into a peripheral data
register.
2. Application sets up µDMA “task list” in memory, which contains the pointers and control configuration for three
µDMA copy “tasks.”
3. Application sets up the channel primary control structure to copy each task configuration, one at a time, to the
alternate control structure, where it is executed by the µDMA controller.
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Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence
Task List
in Memory
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
COPIED
DST
TASK A
TASK B
SRC
SRC C
ALT
COPIED
DST
TASK C
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer A to
the peripheral data register.
Using the channel’s primary control structure, the µDMA
controller copies task A configuration to the channel’s
alternate control structure.
Task List
in Memory
Peripheral
Data
Register
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
COPIED
ALT
COPIED
DST
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer B to
the peripheral data register.
Using the channel’s primary control structure, the µDMA
controller copies task B configuration to the channel’s
alternate control structure.
Task List
in Memory
Peripheral
Data
Register
Buffers
in Memory
µDMA Control Table
in Memory
SRC A
SRC
SRC B
PRI
DST
TASK A
SRC
TASK B
TASK C
SRC C
ALT
DST
COPIED
COPIED
Peripheral
Data
Register
Using the channel’s primary control structure, the µDMA
controller copies task C configuration to the channel’s
alternate control structure.
Then, using the channel’s alternate control structure, the
µDMA controller copies data from the source buffer C to
the peripheral data register.
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8.2.7
Transfer Size and Increment
The μDMA controller supports transfer data sizes of 8, 16, or 32 bits. The source and destination
data size must be the same for any given transfer. The source and destination address can be
auto-incremented by bytes, half-words, or words, or can be set to no increment. The source and
destination address increment values can be set independently, and it is not necessary for the
address increment to match the data size as long as the increment is the same or larger than the
data size. For example, it is possible to perform a transfer using 8-bit data size, but using an address
increment of full words (4 bytes). The data to be transferred must be aligned in memory according
to the data size (8, 16, or 32 bits).
Table 8-5 shows the configuration to read from a peripheral that supplies 8-bit data.
Table 8-5. μDMA Read Example: 8-Bit Peripheral
8.2.8
Field
Configuration
Source data size
8 bits
Destination data size
8 bits
Source address increment
No increment
Destination address increment
Byte
Source end pointer
Peripheral read FIFO register
Destination end pointer
End of the data buffer in memory
Peripheral Interface
Each peripheral that supports μDMA has a single request and/or burst request signal that is asserted
when the peripheral is ready to transfer data (see Table 8-2 on page 250). The request signal can
be disabled or enabled using the DMA Channel Request Mask Set (DMAREQMASKSET) and
DMA Channel Request Mask Clear (DMAREQMASKCLR) registers. The μDMA request signal
is disabled, or masked, when the channel request mask bit is set. When the request is not masked,
the μDMA channel is configured correctly and enabled, and the peripheral asserts the request signal,
the μDMA controller begins the transfer.
When a μDMA transfer is complete, the μDMA controller generates an interrupt, see “Interrupts and
Errors” on page 261 for more information.
For more information on how a specific peripheral interacts with the μDMA controller, refer to the
DMA Operation section in the chapter that discusses that peripheral.
8.2.9
Software Request
One μDMA channel is dedicated to software-initiated transfers. This channel also has a dedicated
interrupt to signal completion of a μDMA transfer. A transfer is initiated by software by first configuring
and enabling the transfer, and then issuing a software request using the DMA Channel Software
Request (DMASWREQ) register. For software-based transfers, the Auto transfer mode should be
used.
It is possible to initiate a transfer on any channel using the DMASWREQ register. If a request is
initiated by software using a peripheral μDMA channel, then the completion interrupt occurs on the
interrupt vector for the peripheral instead of the software interrupt vector. Any channel may be used
for software requests as long as the corresponding peripheral is not using μDMA for data transfer.
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8.2.10
Interrupts and Errors
When a μDMA transfer is complete, the μDMA controller generates a completion interrupt on the
interrupt vector of the peripheral. Therefore, if μDMA is used to transfer data for a peripheral and
interrupts are used, then the interrupt handler for that peripheral must be designed to handle the
μDMA transfer completion interrupt. If the transfer uses the software μDMA channel, then the
completion interrupt occurs on the dedicated software μDMA interrupt vector (see Table 8-6).
When μDMA is enabled for a peripheral, the μDMA controller stops the normal transfer interrupts
for a peripheral from reaching the interrupt controller (the interrupts are still reported in the peripheral's
interrupt registers). Thus, when a large amount of data is transferred using μDMA, instead of receiving
multiple interrupts from the peripheral as data flows, the interrupt controller receives only one interrupt
when the transfer is complete. Unmasked peripheral error interrupts continue to be sent to the
interrupt controller.
If the μDMA controller encounters a bus or memory protection error as it attempts to perform a data
transfer, it disables the μDMA channel that caused the error and generates an interrupt on the μDMA
error interrupt vector. The processor can read the DMA Bus Error Clear (DMAERRCLR) register
to determine if an error is pending. The ERRCLR bit is set if an error occurred. The error can be
cleared by writing a 1 to the ERRCLR bit.
Table 8-6 shows the dedicated interrupt assignments for the μDMA controller.
Table 8-6. μDMA Interrupt Assignments
Interrupt
Assignment
46
μDMA Software Channel Transfer
47
μDMA Error
8.3
Initialization and Configuration
8.3.1
Module Initialization
Before the μDMA controller can be used, it must be enabled in the System Control block and in the
peripheral. The location of the channel control structure must also be programmed.
The following steps should be performed one time during system initialization:
1. The μDMA peripheral must be enabled in the System Control block. To do this, set the UDMA
bit of the System Control RCGC2 register (see page 193).
2. Enable the μDMA controller by setting the MASTEREN bit of the DMA Configuration (DMACFG)
register.
3. Program the location of the channel control table by writing the base address of the table to the
DMA Channel Control Base Pointer (DMACTLBASE) register. The base address must be
aligned on a 1024-byte boundary.
8.3.2
Configuring a Memory-to-Memory Transfer
μDMA channel 30 is dedicated for software-initiated transfers. However, any channel can be used
for software-initiated, memory-to-memory transfer if the associated peripheral is not being used.
8.3.2.1
Configure the Channel Attributes
First, configure the channel attributes:
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1. Program bit 30 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 30 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 30 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 30 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
8.3.2.2
Configure the Channel Control Structure
Now the channel control structure must be configured.
This example transfers 256 words from one memory buffer to another. Channel 30 is used for a
software transfer, and the control structure for channel 30 is at offset 0x1E0 of the channel control
table. The channel control structure for channel 30 is located at the offsets shown in Table 8-7.
Table 8-7. Channel Control Structure Offsets for Channel 30
Offset
Description
Control Table Base + 0x1E0
Channel 30 Source End Pointer
Control Table Base + 0x1E4
Channel 30 Destination End Pointer
Control Table Base + 0x1E8
Channel 30 Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
1. Program the source end pointer at offset 0x1E0 to the address of the source buffer + 0x3FC.
2. Program the destination end pointer at offset 0x1E4 to the address of the destination buffer +
0x3FC.
The control word at offset 0x1E8 must be programmed according to Table 8-8.
Table 8-8. Channel Control Word Configuration for Memory Transfer Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
2
32-bit destination address increment
DSTSIZE
29:28
2
32-bit destination data size
SRCINC
27:26
2
32-bit source address increment
SRCSIZE
25:24
2
32-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
3
Arbitrates after 8 transfers
XFERSIZE
13:4
255
3
0
N/A for this transfer type
2:0
2
Use Auto-request transfer mode
NXTUSEBURST
XFERMODE
8.3.2.3
Description
Transfer 256 items
Start the Transfer
Now the channel is configured and is ready to start.
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1. Enable the channel by setting bit 30 of the DMA Channel Enable Set (DMAENASET) register.
2. Issue a transfer request by setting bit 30 of the DMA Channel Software Request (DMASWREQ)
register.
The μDMA transfer begins. If the interrupt is enabled, then the processor is notified by interrupt
when the transfer is complete. If needed, the status can be checked by reading bit 30 of the
DMAENASET register. This bit is automatically cleared when the transfer is complete. The status
can also be checked by reading the XFERMODE field of the channel control word at offset 0x1E8.
This field is automatically cleared at the end of the transfer.
8.3.3
Configuring a Peripheral for Simple Transmit
This example configures the μDMA controller to transmit a buffer of data to a peripheral. The
peripheral has a transmit FIFO with a trigger level of 4. The example peripheral uses μDMA channel
7.
8.3.3.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Configure bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
8.3.3.2
Configure the Channel Control Structure
This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register
using μDMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control
table. The channel control structure for channel 7 is located at the offsets shown in Table 8-9.
Table 8-9. Channel Control Structure Offsets for Channel 7
Offset
Description
Control Table Base + 0x070
Channel 7 Source End Pointer
Control Table Base + 0x074
Channel 7 Destination End Pointer
Control Table Base + 0x078
Channel 7 Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
1. Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F.
2. Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit
FIFO register.
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The control word at offset 0x078 must be programmed according to Table 8-10.
Table 8-10. Channel Control Word Configuration for Peripheral Transmit Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
3
Destination address does not increment
DSTSIZE
29:28
0
8-bit destination data size
SRCINC
27:26
0
8-bit source address increment
SRCSIZE
25:24
0
8-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
2
Arbitrates after 4 transfers
XFERSIZE
13:4
63
Transfer 64 items
3
0
N/A for this transfer type
2:0
1
Use Basic transfer mode
NXTUSEBURST
XFERMODE
Note:
8.3.3.3
Description
In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 4, the arbitration size is set to
4. If the peripheral does make a burst request, then 4 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any space
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[7] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
Start the Transfer
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 7 of the DMA Channel Enable Set (DMAENASET) register.
The μDMA controller is now configured for transfer on channel 7. The controller makes transfers to
the peripheral whenever the peripheral asserts a μDMA request. The transfers continue until the
entire buffer of 64 bytes has been transferred. When that happens, the μDMA controller disables
the channel and sets the XFERMODE field of the channel control word to 0 (Stopped). The status of
the transfer can be checked by reading bit 7 of the DMA Channel Enable Set (DMAENASET)
register. This bit is automatically cleared when the transfer is complete. The status can also be
checked by reading the XFERMODE field of the channel control word at offset 0x078. This field is
automatically cleared at the end of the transfer.
If peripheral interrupts are enabled, then the peripheral interrupt handler receives an interrupt when
the entire transfer is complete.
8.3.4
Configuring a Peripheral for Ping-Pong Receive
This example configures the μDMA controller to continuously receive 8-bit data from a peripheral
into a pair of 64-byte buffers. The peripheral has a receive FIFO with a trigger level of 8. The example
peripheral uses μDMA channel 8.
8.3.4.1
Configure the Channel Attributes
First, configure the channel attributes:
1. Configure bit 8 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority
Clear (DMAPRIOCLR) registers to set the channel to High priority or Default priority.
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2. Set bit 8 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the
primary channel control structure for this transfer.
3. Set bit 8 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the
μDMA controller to respond to single and burst requests.
4. Set bit 8 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow
the μDMA controller to recognize requests for this channel.
8.3.4.2
Configure the Channel Control Structure
This example transfers bytes from the peripheral's receive FIFO register into two memory buffers
of 64 bytes each. As data is received, when one buffer is full, the μDMA controller switches to use
the other.
To use Ping-Pong buffering, both primary and alternate channel control structures must be used.
The primary control structure for channel 8 is at offset 0x080 of the channel control table, and the
alternate channel control structure is at offset 0x280. The channel control structures for channel 8
are located at the offsets shown in Table 8-11.
Table 8-11. Primary and Alternate Channel Control Structure Offsets for Channel 8
Offset
Description
Control Table Base + 0x080
Channel 8 Primary Source End Pointer
Control Table Base + 0x084
Channel 8 Primary Destination End Pointer
Control Table Base + 0x088
Channel 8 Primary Control Word
Control Table Base + 0x280
Channel 8 Alternate Source End Pointer
Control Table Base + 0x284
Channel 8 Alternate Destination End Pointer
Control Table Base + 0x288
Channel 8 Alternate Control Word
Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
Both the primary and alternate sets of pointers must be configured.
1. Program the primary source end pointer at offset 0x080 to the address of the peripheral's receive
buffer.
2. Program the primary destination end pointer at offset 0x084 to the address of ping-pong buffer
A + 0x3F.
3. Program the alternate source end pointer at offset 0x280 to the address of the peripheral's
receive buffer.
4. Program the alternate destination end pointer at offset 0x284 to the address of ping-pong buffer
B + 0x3F.
The primary control word at offset 0x088 and the alternate control word at offset 0x288 are initially
programmed the same way.
1. Program the primary channel control word at offset 0x088 according to Table 8-12.
2. Program the alternate channel control word at offset 0x288 according to Table 8-12.
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Table 8-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive Example
Field in DMACHCTL
Bits
Value
DSTINC
31:30
0
8-bit destination address increment
DSTSIZE
29:28
0
8-bit destination data size
SRCINC
27:26
3
Source address does not increment
SRCSIZE
25:24
0
8-bit source data size
reserved
23:18
0
Reserved
ARBSIZE
17:14
3
Arbitrates after 8 transfers
XFERSIZE
13:4
63
Transfer 64 items
3
0
N/A for this transfer type
2:0
3
Use Ping-Pong transfer mode
NXTUSEBURST
XFERMODE
Note:
8.3.4.3
Description
In this example, it is not important if the peripheral makes a single request or a burst request.
Because the peripheral has a FIFO that triggers at a level of 8, the arbitration size is set to
8. If the peripheral does make a burst request, then 8 bytes are transferred, which is what
the FIFO can accommodate. If the peripheral makes a single request (if there is any data
in the FIFO), then one byte is transferred at a time. If it is important to the application that
transfers only be made in bursts, then the Channel Useburst SET[8] bit should be set in
the DMA Channel Useburst Set (DMAUSEBURSTSET) register.
Configure the Peripheral Interrupt
An interrupt handler should be configured when using μDMA Ping-Pong mode, it is best to use an
interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling.
The interrupt handler is triggered after each buffer is complete.
1. Configure and enable an interrupt handler for the peripheral.
8.3.4.4
Enable the μDMA Channel
Now the channel is configured and is ready to start.
1. Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register.
8.3.4.5
Process Interrupts
The μDMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the μDMA request signal, the μDMA controller makes transfers into buffer A using the primary
channel control structure. When the primary transfer to buffer A is complete, it switches to the
alternate channel control structure and makes transfers into buffer B. At the same time, the primary
channel control word mode field is configured to indicate Stopped, and an interrupt is
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and
process the data or set a flag that the data must be processed by non-interrupt buffer processing
code. Then the next buffer transfer must be set up.
In the interrupt handler:
1. Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the
field is 0, this means buffer A is complete. If buffer A is complete, then:
a. Process the newly received data in buffer A or signal the buffer processing code that buffer
A has data available.
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b. Reprogram the primary channel control word at offset 0x88 according to Table
8-12 on page 266.
2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the
field is 0, this means buffer B is complete. If buffer B is complete, then:
a. Process the newly received data in buffer B or signal the buffer processing code that buffer
B has data available.
b. Reprogram the alternate channel control word at offset 0x288 according to Table
8-12 on page 266.
8.3.5
Configuring Channel Assignments
Channel assignments for each μDMA channel can be changed using the DMACHASGN register.
Each bit represents a μDMA channel. If the bit is set, then the secondary function is used for the
channel.
Refer to Table 8-1 on page 248 for channel assignments.
For example, to use SSI1 Receive on channel 8 instead of UART0, set bit 8 of the DMACHASGN
register.
8.4
Register Map
Table 8-13 on page 267 lists the μDMA channel control structures and registers. The channel control
structure shows the layout of one entry in the channel control table. The channel control table is
located in system memory, and the location is determined by the application, that is, the base
address is n/a (not applicable). In the table below, the offset for the channel control structures is the
offset from the entry in the channel control table. See “Channel Configuration” on page 250 and Table
8-3 on page 251 for a description of how the entries in the channel control table are located in memory.
The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base
address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers
can be programmed (see page 193).
Table 8-13. μDMA Register Map
Offset
Name
Type
Reset
Description
See
page
μDMA Channel Control Structure (Offset from Channel Control Table Base)
0x000
DMASRCENDP
R/W
-
DMA Channel Source Address End Pointer
269
0x004
DMADSTENDP
R/W
-
DMA Channel Destination Address End Pointer
270
0x008
DMACHCTL
R/W
-
DMA Channel Control Word
271
DMA Status
276
DMA Configuration
278
μDMA Registers (Offset from μDMA Base Address)
0x000
DMASTAT
RO
0x001F.0000
0x004
DMACFG
WO
-
0x008
DMACTLBASE
R/W
0x0000.0000
DMA Channel Control Base Pointer
279
0x00C
DMAALTBASE
RO
0x0000.0200
DMA Alternate Channel Control Base Pointer
280
0x010
DMAWAITSTAT
RO
0x0000.0000
DMA Channel Wait-on-Request Status
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Table 8-13. μDMA Register Map (continued)
Offset
Name
Type
Reset
0x014
DMASWREQ
WO
-
0x018
DMAUSEBURSTSET
R/W
0x0000.0000
0x01C
DMAUSEBURSTCLR
WO
-
0x020
DMAREQMASKSET
R/W
0x0000.0000
0x024
DMAREQMASKCLR
WO
-
0x028
DMAENASET
R/W
0x0000.0000
0x02C
DMAENACLR
WO
-
0x030
DMAALTSET
R/W
0x0000.0000
0x034
DMAALTCLR
WO
-
0x038
DMAPRIOSET
R/W
0x0000.0000
0x03C
DMAPRIOCLR
WO
-
0x04C
DMAERRCLR
R/W
0x500
DMACHASGN
0xFD0
Description
See
page
DMA Channel Software Request
282
DMA Channel Useburst Set
283
DMA Channel Useburst Clear
284
DMA Channel Request Mask Set
285
DMA Channel Request Mask Clear
286
DMA Channel Enable Set
287
DMA Channel Enable Clear
288
DMA Channel Primary Alternate Set
289
DMA Channel Primary Alternate Clear
290
DMA Channel Priority Set
291
DMA Channel Priority Clear
292
0x0000.0000
DMA Bus Error Clear
293
R/W
0x0000.0000
DMA Channel Assignment
294
DMAPeriphID4
RO
0x0000.0004
DMA Peripheral Identification 4
299
0xFE0
DMAPeriphID0
RO
0x0000.0030
DMA Peripheral Identification 0
295
0xFE4
DMAPeriphID1
RO
0x0000.00B2
DMA Peripheral Identification 1
296
0xFE8
DMAPeriphID2
RO
0x0000.000B
DMA Peripheral Identification 2
297
0xFEC
DMAPeriphID3
RO
0x0000.0000
DMA Peripheral Identification 3
298
0xFF0
DMAPCellID0
RO
0x0000.000D
DMA PrimeCell Identification 0
300
0xFF4
DMAPCellID1
RO
0x0000.00F0
DMA PrimeCell Identification 1
301
0xFF8
DMAPCellID2
RO
0x0000.0005
DMA PrimeCell Identification 2
302
0xFFC
DMAPCellID3
RO
0x0000.00B1
DMA PrimeCell Identification 3
303
8.5
μDMA Channel Control Structure
The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel
has two control structures, which are located in a table in system memory. Refer to “Channel
Configuration” on page 250 for an explanation of the Channel Control Table and the Channel Control
Structure.
The channel control structure is one entry in the channel control table. Each channel has a primary
and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and
so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on.
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Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset
0x000
DMA Channel Source Address End Pointer (DMASRCENDP) is part of the Channel Control
Structure and is used to specify the source address for a μDMA transfer.
The μDMA controller can transfer data to and from the on-chip SRAM. However, because the Flash
memory and ROM are located on a separate internal bus, it is not possible to transfer data from the
Flash memory or ROM with the μDMA controller.
Note:
The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Source Address End Pointer (DMASRCENDP)
Base n/a
Offset 0x000
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
ADDR
Type
Reset
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
R/W
-
Description
Source Address End Pointer
This field points to the last address of the μDMA transfer source
(inclusive). If the source address is not incrementing (the SRCINC field
in the DMACHCTL register is 0x3), then this field points at the source
location itself (such as a peripheral data register).
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Micro Direct Memory Access (μDMA)
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP),
offset 0x004
DMA Channel Destination Address End Pointer (DMADSTENDP) is part of the Channel Control
Structure and is used to specify the destination address for a μDMA transfer.
Note:
The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Destination Address End Pointer (DMADSTENDP)
Base n/a
Offset 0x004
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
ADDR
Type
Reset
ADDR
Type
Reset
Bit/Field
Name
Type
Reset
31:0
ADDR
R/W
-
Description
Destination Address End Pointer
This field points to the last address of the μDMA transfer destination
(inclusive). If the destination address is not incrementing (the DSTINC
field in the DMACHCTL register is 0x3), then this field points at the
destination location itself (such as a peripheral data register).
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Stellaris® LM3S9B95 Microcontroller
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used
to specify parameters of a μDMA transfer.
Note:
The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Control Word (DMACHCTL)
Base n/a
Offset 0x008
Type R/W, reset 31
30
DSTINC
Type
Reset
29
28
27
DSTSIZE
26
24
23
22
21
SRCSIZE
20
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
7
6
5
4
R/W
-
XFERSIZE
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
Bit/Field
Name
Type
Reset
31:30
DSTINC
R/W
-
18
17
R/W
-
R/W
-
3
2
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
1
0
XFERMODE
NXTUSEBURST
R/W
-
16
ARBSIZE
R/W
-
R/W
-
19
reserved
R/W
-
ARBSIZE
Type
Reset
25
SRCINC
R/W
-
R/W
-
R/W
-
Description
Destination Address Increment
This field configures the destination address increment.
The address increment value must be equal or greater than the value
of the destination size (DSTSIZE).
Value Description
0x0
Byte
Increment by 8-bit locations
0x1
Half-word
Increment by 16-bit locations
0x2
Word
Increment by 32-bit locations
0x3
No increment
Address remains set to the value of the Destination Address
End Pointer (DMADSTENDP) for the channel
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Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
29:28
DSTSIZE
R/W
-
Description
Destination Data Size
This field configures the destination item data size.
Note:
DSTSIZE must be the same as SRCSIZE.
Value Description
0x0
Byte
8-bit data size
0x1
Half-word
16-bit data size
0x2
Word
32-bit data size
0x3
27:26
SRCINC
R/W
-
Reserved
Source Address Increment
This field configures the source address increment.
The address increment value must be equal or greater than the value
of the source size (SRCSIZE).
Value Description
0x0
Byte
Increment by 8-bit locations
0x1
Half-word
Increment by 16-bit locations
0x2
Word
Increment by 32-bit locations
0x3
No increment
Address remains set to the value of the Source Address End
Pointer (DMASRCENDP) for the channel
25:24
SRCSIZE
R/W
-
Source Data Size
This field configures the source item data size.
Note:
DSTSIZE must be the same as SRCSIZE.
Value Description
0x0
Byte
8-bit data size.
0x1
Half-word
16-bit data size.
0x2
Word
32-bit data size.
0x3
Reserved
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
23:18
reserved
R/W
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17:14
ARBSIZE
R/W
-
Arbitration Size
This field configures the number of transfers that can occur before the
μDMA controller re-arbitrates. The possible arbitration rate configurations
represent powers of 2 and are shown below.
Value
Description
0x0
1 Transfer
Arbitrates after each μDMA transfer
0x1
2 Transfers
0x2
4 Transfers
0x3
8 Transfers
0x4
16 Transfers
0x5
32 Transfers
0x6
64 Transfers
0x7
128 Transfers
0x8
256 Transfers
0x9
512 Transfers
0xA-0xF 1024 Transfers
In this configuration, no arbitration occurs during the μDMA
transfer because the maximum transfer size is 1024.
13:4
XFERSIZE
R/W
-
Transfer Size (minus 1)
This field configures the total number of items to transfer. The value of
this field is 1 less than the number to transfer (value 0 means transfer
1 item). The maximum value for this 10-bit field is 1023 which represents
a transfer size of 1024 items.
The transfer size is the number of items, not the number of bytes. If the
data size is 32 bits, then this value is the number of 32-bit words to
transfer.
The μDMA controller updates this field immediately prior to entering the
arbitration process, so it contains the number of outstanding items that
is necessary to complete the μDMA cycle.
3
NXTUSEBURST
R/W
-
Next Useburst
This field controls whether the Useburst SET[n] bit is automatically set
for the last transfer of a peripheral scatter-gather operation. Normally,
for the last transfer, if the number of remaining items to transfer is less
than the arbitration size, the μDMA controller uses single transfers to
complete the transaction. If this bit is set, then the controller uses a burst
transfer to complete the last transfer.
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Micro Direct Memory Access (μDMA)
Bit/Field
Name
Type
Reset
2:0
XFERMODE
R/W
-
Description
μDMA Transfer Mode
This field configures the operating mode of the μDMA cycle. Refer to
“Transfer Modes” on page 252 for a detailed explanation of transfer
modes.
Because this register is in system RAM, it has no reset value. Therefore,
this field should be initialized to 0 before the channel is enabled.
Value Description
0x0
Stop
0x1
Basic
0x2
Auto-Request
0x3
Ping-Pong
0x4
Memory Scatter-Gather
0x5
Alternate Memory Scatter-Gather
0x6
Peripheral Scatter-Gather
0x7
Alternate Peripheral Scatter-Gather
XFERMODE Bit Field Values.
Stop
Channel is stopped or configuration data is invalid. No more transfers can occur.
Basic
For each trigger (whether from a peripheral or a software request), the μDMA controller performs
the number of transfers specified by the ARBSIZE field.
Auto-Request
The initial request (software- or peripheral-initiated) is sufficient to complete the entire transfer
of XFERSIZE items without any further requests.
Ping-Pong
This mode uses both the primary and alternate control structures for this channel. When the
number of transfers specified by the XFERSIZE field have completed for the current control
structure (primary or alternate), the µDMA controller switches to the other one. These switches
continue until one of the control structures is not set to ping-pong mode. At that point, the µDMA
controller stops. An interrupt is generated on completion of the transfers configured by each
control structure. See “Ping-Pong” on page 252.
Memory Scatter-Gather
When using this mode, the primary control structure for the channel is configured to allow a list
of operations (tasks) to be performed. The source address pointer specifies the start of a table
of tasks to be copied to the alternate control structure for this channel. The XFERMODE field for
the alternate control structure should be configured to 0x5 (Alternate memory scatter-gather)
to perform the task. When the task completes, the µDMA switches back to the primary channel
control structure, which then copies the next task to the alternate control structure. This process
continues until the table of tasks is empty. The last task must have an XFERMODE value other
than 0x5. Note that for continuous operation, the last task can update the primary channel control
structure back to the start of the list or to another list. See “Memory Scatter-Gather” on page 253.
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Stellaris® LM3S9B95 Microcontroller
Alternate Memory Scatter-Gather
This value must be used in the alternate channel control data structure when the μDMA controller
operates in Memory Scatter-Gather mode.
Peripheral Scatter-Gather
This value must be used in the primary channel control data structure when the μDMA controller
operates in Peripheral Scatter-Gather mode. In this mode, the μDMA controller operates exactly
the same as in Memory Scatter-Gather mode, except that instead of performing the number of
transfers specified by the XFERSIZE field in the alternate control structure at one time, the
μDMA controller only performs the number of transfers specified by the ARBSIZE field per
trigger; see Basic mode for details. See “Peripheral Scatter-Gather” on page 257.
Alternate Peripheral Scatter-Gather
This value must be used in the alternate channel control data structure when the μDMA controller
operates in Peripheral Scatter-Gather mode.
8.6
μDMA Register Descriptions
The register addresses given are relative to the μDMA base address of 0x400F.F000.
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Micro Direct Memory Access (μDMA)
Register 4: DMA Status (DMASTAT), offset 0x000
The DMA Status (DMASTAT) register returns the status of the μDMA controller. You cannot read
this register when the μDMA controller is in the reset state.
DMA Status (DMASTAT)
Base 0x400F.F000
Offset 0x000
Type RO, reset 0x001F.0000
31
30
29
28
27
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
RO
0
RO
0
RO
0
RO
0
26
25
24
23
22
21
20
19
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
10
9
8
7
6
5
4
3
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
STATE
RO
0
17
16
RO
1
RO
1
RO
1
2
1
0
DMACHANS
reserved
Type
Reset
18
reserved
RO
0
MASTEN
RO
0
RO
0
Bit/Field
Name
Type
Reset
Description
31:21
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
20:16
DMACHANS
RO
0x1F
Available μDMA Channels Minus 1
This field contains a value equal to the number of μDMA channels the
μDMA controller is configured to use, minus one. The value of 0x1F
corresponds to 32 μDMA channels.
15:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:4
STATE
RO
0x0
Control State Machine Status
This field shows the current status of the control state machine. Status
can be one of the following.
Value
Description
0x0
Idle
0x1
Reading channel controller data.
0x2
Reading source end pointer.
0x3
Reading destination end pointer.
0x4
Reading source data.
0x5
Writing destination data.
0x6
Waiting for µDMA request to clear.
0x7
Writing channel controller data.
0x8
Stalled
0x9
Done
0xA-0xF Undefined
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
0
MASTEN
RO
0
Description
Master Enable Status
Value Description
0
The μDMA controller is disabled.
1
The μDMA controller is enabled.
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Micro Direct Memory Access (μDMA)
Register 5: DMA Configuration (DMACFG), offset 0x004
The DMACFG register controls the configuration of the μDMA controller.
DMA Configuration (DMACFG)
Base 0x400F.F000
Offset 0x004
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
reserved
Type
Reset
reserved
Type
Reset
WO
-
MASTEN
WO
-
Bit/Field
Name
Type
Reset
Description
31:1
reserved
WO
-
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
MASTEN
WO
-
Controller Master Enable
Value Description
0
Disables the μDMA controller.
1
Enables μDMA controller.
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Stellaris® LM3S9B95 Microcontroller
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008
The DMACTLBASE register must be configured so that the base pointer points to a location in
system memory.
The amount of system memory that must be assigned to the μDMA controller depends on the
number of μDMA channels used and whether the alternate channel control data structure is used.
See “Channel Configuration” on page 250 for details about the Channel Control Table. The base
address must be aligned on a 1024-byte boundary. This register cannot be read when the μDMA
controller is in the reset state.
DMA Channel Control Base Pointer (DMACTLBASE)
Base 0x400F.F000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR
Type
Reset
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
ADDR
Type
Reset
R/W
0
R/W
0
R/W
0
reserved
R/W
0
R/W
0
R/W
0
RO
0
Bit/Field
Name
Type
Reset
31:10
ADDR
R/W
0x0000.00
RO
0
RO
0
RO
0
RO
0
Description
Channel Control Base Address
This field contains the pointer to the base address of the channel control
table. The base address must be 1024-byte aligned.
9:0
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Micro Direct Memory Access (μDMA)
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE),
offset 0x00C
The DMAALTBASE register returns the base address of the alternate channel control data. This
register removes the necessity for application software to calculate the base address of the alternate
channel control structures. This register cannot be read when the μDMA controller is in the reset
state.
DMA Alternate Channel Control Base Pointer (DMAALTBASE)
Base 0x400F.F000
Offset 0x00C
Type RO, reset 0x0000.0200
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
ADDR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
ADDR
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:0
ADDR
RO
RO
1
Reset
RO
0
Description
0x0000.0200 Alternate Channel Address Pointer
This field provides the base address of the alternate channel control
structures.
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Stellaris® LM3S9B95 Microcontroller
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset
0x010
This read-only register indicates that the μDMA channel is waiting on a request. A peripheral can
hold off the μDMA from performing a single request until the peripheral is ready for a burst request
to enhance the μDMA performance. The use of this feature is dependent on the design of the
peripheral and is not controllable by software in any way. This register cannot be read when the
μDMA controller is in the reset state.
DMA Channel Wait-on-Request Status (DMAWAITSTAT)
Base 0x400F.F000
Offset 0x010
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WAITREQ[n]
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
WAITREQ[n]
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
31:0
WAITREQ[n]
RO
RO
0
Reset
RO
0
RO
0
Description
0x0000.0000 Channel [n] Wait Status
These bits provide the channel wait-on-request status. Bit 0 corresponds
to channel 0.
Value Description
1
The corresponding channel is waiting on a request.
0
The corresponding channel is not waiting on a request.
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Micro Direct Memory Access (μDMA)
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014
Each bit of the DMASWREQ register represents the corresponding μDMA channel. Setting a bit
generates a request for the specified μDMA channel.
DMA Channel Software Request (DMASWREQ)
Base 0x400F.F000
Offset 0x014
Type WO, reset 31
30
29
28
27
26
25
24
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
SWREQ[n]
Type
Reset
SWREQ[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
SWREQ[n]
WO
-
WO
-
Description
Channel [n] Software Request
These bits generate software requests. Bit 0 corresponds to channel 0.
Value Description
1
Generate a software request for the corresponding channel.
0
No request generated.
These bits are automatically cleared when the software request has
been completed.
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Stellaris® LM3S9B95 Microcontroller
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018
Each bit of the DMAUSEBURSTSET register represents the corresponding μDMA channel. Setting
a bit disables the channel's single request input from generating requests, configuring the channel
to only accept burst requests. Reading the register returns the status of USEBURST.
If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n]
bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than
the arbitration (burst) size, the μDMA controller automatically clears the corresponding SET[n] bit,
allowing the remaining items to transfer using single requests. In order to resume transfers using
burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding
peripheral does not support the burst request model.
Refer to “Request Types” on page 249 for more details about request types.
DMA Channel Useburst Set (DMAUSEBURSTSET)
Base 0x400F.F000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Useburst Set
Value Description
0
μDMA channel [n] responds to single or burst requests.
1
μDMA channel [n] responds only to burst requests.
Bit 0 corresponds to channel 0. This bit is automatically cleared as
described above. A bit can also be manually cleared by setting the
corresponding CLR[n] bit in the DMAUSEBURSTCLR register.
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Micro Direct Memory Access (μDMA)
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C
Each bit of the DMAUSEBURSTCLR register represents the corresponding μDMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register.
DMA Channel Useburst Clear (DMAUSEBURSTCLR)
Base 0x400F.F000
Offset 0x01C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Useburst Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAUSEBURSTSET register meaning that µDMA channel [n]
responds to single and burst requests.
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Stellaris® LM3S9B95 Microcontroller
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset
0x020
Each bit of the DMAREQMASKSET register represents the corresponding μDMA channel. Setting
a bit disables μDMA requests for the channel. Reading the register returns the request mask status.
When a μDMA channel's request is masked, that means the peripheral can no longer request μDMA
transfers. The channel can then be used for software-initiated transfers.
DMA Channel Request Mask Set (DMAREQMASKSET)
Base 0x400F.F000
Offset 0x020
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SET[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
SET[n]
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0000 Channel [n] Request Mask Set
Value Description
0
The peripheral associated with channel [n] is enabled to request
μDMA transfers.
1
The peripheral associated with channel [n] is not able to request
μDMA transfers. Channel [n] may be used for software-initiated
transfers.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAREQMASKCLR register.
June 14, 2010
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Micro Direct Memory Access (μDMA)
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset
0x024
Each bit of the DMAREQMASKCLR register represents the corresponding μDMA channel. Setting
a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register.
DMA Channel Request Mask Clear (DMAREQMASKCLR)
Base 0x400F.F000
Offset 0x024
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
WO
-
Description
Channel [n] Request Mask Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAREQMASKSET register meaning that the peripheral
associated with channel [n] is enabled to request μDMA
transfers.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028
Each bit of the DMAENASET register represents the corresponding µDMA channel. Setting a bit
enables the corresponding µDMA channel. Reading the register returns the enable status of the
channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the
channel can be used for software-initiated transfers.
DMA Channel Enable Set (DMAENASET)
Base 0x400F.F000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Enable Set
Value Description
0
µDMA Channel [n] is disabled.
1
µDMA Channel [n] is enabled.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAENACLR register.
June 14, 2010
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Micro Direct Memory Access (μDMA)
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C
Each bit of the DMAENACLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAENASET register.
DMA Channel Enable Clear (DMAENACLR)
Base 0x400F.F000
Offset 0x02C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Clear Channel [n] Enable Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAENASET register meaning that channel [n] is disabled for
μDMA transfers.
Note:
The controller disables a channel when it completes the μDMA
cycle.
288
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030
Each bit of the DMAALTSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to use the alternate control data structure. Reading the register returns
the status of which control data structure is in use for the corresponding µDMA channel.
DMA Channel Primary Alternate Set (DMAALTSET)
Base 0x400F.F000
Offset 0x030
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Alternate Set
Value Description
0
µDMA channel [n] is using the primary control structure.
1
µDMA channel [n] is using the alternate control structure.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAALTCLR register.
Note:
For Ping-Pong and Scatter-Gather cycle types, the µDMA
controller automatically sets these bits to select the alternate
channel control data structure.
June 14, 2010
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Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset
0x034
Each bit of the DMAALTCLR register represents the corresponding μDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAALTSET register.
DMA Channel Primary Alternate Clear (DMAALTCLR)
Base 0x400F.F000
Offset 0x034
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
CLR[n]
Type
Reset
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
WO
-
Description
Channel [n] Alternate Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAALTSET register meaning that channel [n] is using the
primary control structure.
Note:
For Ping-Pong and Scatter-Gather cycle types, the µDMA
controller automatically sets these bits to select the alternate
channel control data structure.
290
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038
Each bit of the DMAPRIOSET register represents the corresponding µDMA channel. Setting a bit
configures the µDMA channel to have a high priority level. Reading the register returns the status
of the channel priority mask.
DMA Channel Priority Set (DMAPRIOSET)
Base 0x400F.F000
Offset 0x038
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SET[n]
Type
Reset
SET[n]
Type
Reset
Bit/Field
Name
Type
31:0
SET[n]
R/W
Reset
Description
0x0000.0000 Channel [n] Priority Set
Value Description
0
µDMA channel [n] is using the default priority level.
1
µDMA channel [n] is using a high priority level.
Bit 0 corresponds to channel 0. A bit can only be cleared by setting the
corresponding CLR[n] bit in the DMAPRIOCLR register.
June 14, 2010
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Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C
Each bit of the DMAPRIOCLR register represents the corresponding µDMA channel. Setting a bit
clears the corresponding SET[n] bit in the DMAPRIOSET register.
DMA Channel Priority Clear (DMAPRIOCLR)
Base 0x400F.F000
Offset 0x03C
Type WO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
WO
-
CLR[n]
Type
Reset
CLR[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CLR[n]
WO
-
Description
Channel [n] Priority Clear
Value Description
0
No effect.
1
Setting a bit clears the corresponding SET[n] bit in the
DMAPRIOSET register meaning that channel [n] is using the
default priority level.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C
The DMAERRCLR register is used to read and clear the µDMA bus error status. The error status
is set if the μDMA controller encountered a bus error while performing a transfer. If a bus error
occurs on a channel, that channel is automatically disabled by the μDMA controller. The other
channels are unaffected.
DMA Bus Error Clear (DMAERRCLR)
Base 0x400F.F000
Offset 0x04C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
Bit/Field
Name
Type
Reset
31:1
reserved
RO
0x0000.000
0
ERRCLR
R/W1C
0
RO
0
ERRCLR
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Bus Error Status
Value Description
0
No bus error is pending.
1
A bus error is pending.
This bit is cleared by writing a 1 to it.
June 14, 2010
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Micro Direct Memory Access (μDMA)
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500
Each bit of the DMACHASGN register represents the corresponding µDMA channel. Setting a bit
selects the secondary channel assignment as specified in Table 8-1 on page 248.
DMA Channel Assignment (DMACHASGN)
Base 0x400F.F000
Offset 0x500
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
15
14
13
12
11
10
9
8
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
23
22
21
20
19
18
17
16
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
7
6
5
4
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
CHASGN[n]
Type
Reset
CHASGN[n]
Type
Reset
Bit/Field
Name
Type
Reset
31:0
CHASGN[n]
R/W
-
R/W
-
Description
Channel [n] Assignment Select
Value Description
0
Use the primary channel assignment.
1
Use the secondary channel assignment.
294
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 22: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 0 (DMAPeriphID0)
Base 0x400F.F000
Offset 0xFE0
Type RO, reset 0x0000.0030
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x30
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
June 14, 2010
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Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)
Register 23: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 1 (DMAPeriphID1)
Base 0x400F.F000
Offset 0xFE4
Type RO, reset 0x0000.00B2
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
1
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0xB2
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
296
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 24: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 2 (DMAPeriphID2)
Base 0x400F.F000
Offset 0xFE8
Type RO, reset 0x0000.000B
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
RO
1
reserved
Type
Reset
reserved
Type
Reset
PID2
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x0B
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
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Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)
Register 25: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC
The DMAPeriphIDn registers are hard-coded and the fields within the registers determine the reset
values.
DMA Peripheral Identification 3 (DMAPeriphID3)
Base 0x400F.F000
Offset 0xFEC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID3
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
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Stellaris® LM3S9B95 Microcontroller
Register 26: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0
The DMAPeriphIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA Peripheral Identification 4 (DMAPeriphID4)
Base 0x400F.F000
Offset 0xFD0
Type RO, reset 0x0000.0004
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
PID4
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x04
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA Peripheral ID Register
Can be used by software to identify the presence of this peripheral.
June 14, 2010
299
Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)
Register 27: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 0 (DMAPCellID0)
Base 0x400F.F000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
300
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 28: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 1 (DMAPCellID1)
Base 0x400F.F000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
CID1
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
μDMA PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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301
Texas Instruments-Advance Information
Micro Direct Memory Access (μDMA)
Register 29: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 2 (DMAPCellID2)
Base 0x400F.F000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID2
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID2
RO
0x05
μDMA PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 30: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC
The DMAPCellIDn registers are hard-coded, and the fields within the registers determine the reset
values.
DMA PrimeCell Identification 3 (DMAPCellID3)
Base 0x400F.F000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
1
RO
0
RO
1
RO
1
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
CID3
RO
0
Bit/Field
Name
Type
Reset
Description
31:8
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
7:0
CID3
RO
0xB1
μDMA PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
9
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of nine physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H, Port J). The GPIO module
supports up to 65 programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ Up to 65 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant input/outputs
■ Fast toggle capable of a change every two clock cycles
■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility
with existing code
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
9.1
Signal Description
GPIO signals have alternate hardware functions. Table 9-2 on page 305 and Table 9-3 on page 307
list the GPIO pins and their analog and digital alternate functions. The AINx and VREFA analog
signals are not 5-V tolerant and go through an isolation circuit before reaching their circuitry. These
signals are configured by clearing the corresponding DEN bit in the GPIO Digital Enable (GPIODEN)
register and setting the corresponding AMSEL bit in the GPIO Analog Mode Select (GPIOAMSEL)
register. Other analog signals are 5-V tolerant and are connected directly to their circuitry (C0-,
304
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
C0+, C1-, C1+, C2-, C2+, USB0VBUS, USB0ID). These signals are configured by clearing the DEN
bit in the GPIO Digital Enable (GPIODEN) register. The digital alternate hardware functions are
enabled by setting the appropriate bit in the GPIO Alternate Function Select (GPIOAFSEL) and
GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control (GPIOPCTL)
register to the numeric enoding shown in the table below. Table entries that are shaded gray are
the default values for the corresponding GPIO pin.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-1. GPIO Pins With Non-Zero Reset Values
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
GPIOPCTL
0
0x1
PA[5:2]
SSI0
1
1
0
0
0x1
PB[3:2]
I2C0
1
1
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
Table 9-2. GPIO Pins and Alternate Functions (100LQFP)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PA0 26
-
U0Rx
-
-
-
-
-
-
I2C1SCL
U1Rx
-
-
PA1 27
-
U0Tx
-
-
-
-
-
-
I2C1SDA
U1Tx
-
-
PA2 28
-
SSI0Clk
-
-
PWM4
-
-
-
-
I2S0RXSD
-
-
PA3 29
-
SSI0Fss
-
-
PWM5
-
-
-
-
I2S0RXMCLK
-
-
PA4 30
-
SSI0Rx
-
-
PWM6
CAN0Rx
-
-
-
I2S0TXSCK
-
-
PA5 31
-
SSI0Tx
-
-
PWM7
CAN0Tx
-
-
-
I2S0TXWS
-
-
PA6 34
-
I2C1SCL
CCP1
-
PWM0
PWM4
CAN0Rx
-
USB0EPEN
U1CTS
-
-
PA7 35
-
I2C1SDA
CCP4
-
PWM1
PWM5
CAN0Tx
CCP3
USB0PFLT
U1DCD
-
-
PB0 66
USB0ID
CCP0
PWM2
-
-
U1Rx
-
-
-
-
-
-
CCP2
PWM3
-
CCP1
U1Tx
-
-
-
-
-
-
PB2 72
PB1 67 USB0VBUS
-
I2C0SCL
IDX0
-
CCP3
CCP0
-
-
USB0EPEN
-
-
-
PB3 65
-
I2C0SDA Fault0
-
Fault3
-
-
-
USB0PFLT
-
-
-
PB4 92
AIN10
C0-
-
-
-
U2Rx
CAN0Rx
IDX0
U1Rx
EPI0S23
-
-
-
PB5 91
AIN11
C1-
C0o
CCP5
CCP6
CCP0
CAN0Tx
CCP2
U1Tx
EPI0S22
-
-
-
PB6 90
VREFA
C0+
CCP1
CCP7
C0o
Fault1
IDX0
CCP5
-
-
I2S0TXSCK
-
-
PB7 89
-
-
-
-
NMI
-
-
-
-
-
-
-
PC0 80
-
-
-
TCK
SWCLK
-
-
-
-
-
-
-
-
PC1 79
-
-
-
TMS
SWDIO
-
-
-
-
-
-
-
-
PC2 78
-
-
-
TDI
-
-
-
-
-
-
-
-
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Table 9-2. GPIO Pins and Alternate Functions (100LQFP) (continued)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PC3 77
-
-
-
TDO SWO
-
-
-
-
-
-
-
-
PC4 25
-
CCP5
PhA0
-
PWM6
CCP2
CCP4
-
EPI0S2
CCP1
-
-
PC5 24
C1+
CCP1
C1o
C0o
Fault2
CCP3
USB0EPEN
-
EPI0S3
-
-
-
PC6 23
C2+
CCP3
PhB0
C2o
PWM7
U1Rx
CCP0
USB0PFLT EPI0S4
-
-
-
PC7 22
C2-
CCP4
PhB0
-
CCP0
U1Tx
USB0PFLT
C1o
-
-
-
PD0 10
AIN15
PWM0
CAN0Rx
IDX0
U2Rx
U1Rx
CCP6
-
I2S0RXSCK U1CTS
-
-
PD1 11
AIN14
PWM1
CAN0Tx
PhA0
U2Tx
U1Tx
CCP7
-
I2S0RXWS
U1DCD
CCP2
PhB1
PD2 12
AIN13
U1Rx
CCP6
PWM2
CCP5
-
-
-
EPI0S20
-
-
-
PD3 13
AIN12
U1Tx
CCP7
PWM3
CCP0
-
-
-
EPI0S21
-
-
-
PD4 97
AIN7
CCP0
CCP3
-
-
-
-
-
I2S0RXSD
U1RI
EPI0S19
-
PD5 98
AIN6
CCP2
CCP4
-
-
-
-
-
I2S0RXMCLK
U2Rx
EPI0S28
-
PD6 99
AIN5
Fault0
-
-
-
-
-
-
I2S0TXSCK
U2Tx
EPI0S29
-
PD7 100
AIN4
IDX0
C0o
CCP1
-
-
-
-
I2S0TXWS
U1DTR
EPI0S30
-
PE0 74
-
PWM4
SSI1Clk
CCP3
-
-
-
-
EPI0S8 USB0PFLT
-
-
PE1 75
-
PWM5
SSI1Fss Fault0
CCP2
CCP6
-
-
EPI0S9
-
-
-
PE2 95
AIN9
CCP4
SSI1Rx
PhB1
PhA0
CCP2
-
-
EPI0S24
-
-
-
PE3 96
AIN8
CCP1
SSI1Tx
PhA1
PhB0
CCP7
-
-
EPI0S25
-
-
-
PE4
6
AIN3
CCP3
-
-
Fault0
U2Tx
CCP2
-
-
I2S0TXWS
-
-
PE5
5
AIN2
CCP5
-
-
-
-
-
-
-
I2S0TXSD
-
-
PE6
2
AIN1
PWM4
C1o
-
-
-
-
-
-
U1CTS
-
-
PE7
1
AIN0
PWM5
C2o
-
-
-
-
-
-
U1DCD
-
-
PF0 47
-
CAN1Rx
PhB0
PWM0
-
-
-
-
I2S0TXSD
U1DSR
-
-
PF1 61
-
CAN1Tx
IDX1
PWM1
-
-
-
-
I2S0TXMCLK U1RTS
CCP3
-
PF2 60
-
LED1
PWM4
-
PWM2
-
-
-
-
SSI1Clk
-
-
PF3 59
-
LED0
PWM5
-
PWM3
-
-
-
-
SSI1Fss
-
-
PF4 42
-
CCP0
C0o
-
Fault0
-
-
-
EPI0S12 SSI1Rx
-
-
PF5 41
-
CCP2
C1o
-
-
-
-
-
EPI0S15 SSI1Tx
-
-
PG0 19
-
U2Rx
PWM0
I2C1SCL
PWM4
-
-
-
-
-
PG1 18
-
U2Tx
PWM1
I2C1SDA
PWM5
-
-
-
EPI0S14
-
-
-
PG7 36
-
PhB1
-
-
PWM7
-
-
-
CCP5
EPI0S31
-
-
PH0 86
-
CCP6
PWM2
-
-
-
-
-
EPI0S6
PWM4
-
-
PH1 85
-
CCP7
PWM3
-
-
-
-
-
EPI0S7
PWM5
-
-
PH2 84
-
IDX1
C1o
-
Fault3
-
-
-
EPI0S1
-
-
-
PH3 83
-
PhB0
Fault0
-
USB0EPEN
-
-
-
EPI0S0
-
-
-
PH4 76
-
-
-
-
USB0PFLT
-
-
-
EPI0S10
-
-
SSI1Clk
PH5 63
-
-
-
-
-
-
-
-
EPI0S11
-
PH6 62
-
-
-
-
-
-
-
-
EPI0S26
-
PWM4
PH7 15
-
-
-
-
-
-
-
-
EPI0S27
-
PWM5
SSI1Tx
PJ0 14
-
-
-
-
-
-
-
-
EPI0S16
-
PWM0
I2C1SCL
PJ1 87
-
-
-
-
-
-
-
-
EPI0S17 USB0PFLT
PWM1
I2C1SDA
EPI0S5
USB0EPEN EPI0S13
306
Fault2 SSI1Fss
SSI1Rx
June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Table 9-2. GPIO Pins and Alternate Functions (100LQFP) (continued)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PJ2 39
-
-
-
-
-
-
-
-
EPI0S18
CCP0
Fault0
-
PJ3 50
-
-
-
-
-
-
-
-
EPI0S19
U1CTS
CCP6
-
PJ4 52
-
-
-
-
-
-
-
-
EPI0S28
U1DCD
CCP4
-
PJ5 53
-
-
-
-
-
-
-
-
EPI0S29
U1DSR
CCP2
-
PJ6 54
-
-
-
-
-
-
-
-
EPI0S30
U1RTS
CCP1
-
PJ7 55
-
-
-
-
-
-
-
-
-
U1DTR
CCP0
-
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.
Table 9-3. GPIO Pins and Alternate Functions (108BGA)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PA0 L3
-
U0Rx
-
-
-
-
-
-
I2C1SCL
U1Rx
-
-
PA1 M3
-
U0Tx
-
-
-
-
-
-
I2C1SDA
U1Tx
-
-
PA2 M4
-
SSI0Clk
-
-
PWM4
-
-
-
-
I2S0RXSD
-
-
PA3 L4
-
SSI0Fss
-
-
PWM5
-
-
-
-
I2S0RXMCLK
-
-
PA4 L5
-
SSI0Rx
-
-
PWM6
CAN0Rx
-
-
-
I2S0TXSCK
-
-
PA5 M5
-
SSI0Tx
-
-
PWM7
CAN0Tx
-
-
-
I2S0TXWS
-
-
PA6 L6
-
I2C1SCL
CCP1
-
PWM0
PWM4
CAN0Rx
-
USB0EPEN
U1CTS
-
-
PA7 M6
-
I2C1SDA
CCP4
-
PWM1
PWM5
CAN0Tx
CCP3
USB0PFLT
U1DCD
-
-
PB0 E12 USB0ID
CCP0
PWM2
-
-
U1Rx
-
-
-
-
-
-
PB1 D12 USB0VBUS
CCP2
PWM3
-
CCP1
U1Tx
-
-
-
-
-
-
IDX0
-
CCP3
CCP0
-
-
USB0EPEN
-
-
-
-
Fault3
-
-
-
USB0PFLT
-
-
-
PB2 A11
-
I2C0SCL
PB3 E11
-
I2C0SDA Fault0
PB4 A6
AIN10
C0-
-
-
-
U2Rx
CAN0Rx
IDX0
U1Rx
EPI0S23
-
-
-
PB5 B7
AIN11
C1-
C0o
CCP5
CCP6
CCP0
CAN0Tx
CCP2
U1Tx
EPI0S22
-
-
-
PB6 A7
VREFA
C0+
CCP1
CCP7
C0o
Fault1
IDX0
CCP5
-
-
I2S0TXSCK
-
-
PB7 A8
-
-
-
-
NMI
-
-
-
-
-
-
-
PC0 A9
-
-
-
TCK
SWCLK
-
-
-
-
-
-
-
-
PC1 B9
-
-
-
TMS
SWDIO
-
-
-
-
-
-
-
-
PC2 B8
-
-
-
TDI
-
-
-
-
-
-
-
-
PC3 A10
-
-
-
TDO SWO
-
-
-
-
-
-
-
-
PC4 L1
-
CCP5
PhA0
-
PWM6
CCP2
CCP4
-
EPI0S2
CCP1
-
-
PC5 M1
C1+
CCP1
C1o
C0o
Fault2
CCP3
USB0EPEN
-
EPI0S3
-
-
-
USB0PFLT EPI0S4
-
-
-
-
-
-
PC6 M2
C2+
CCP3
PhB0
C2o
PWM7
U1Rx
CCP0
PC7 L2
C2-
CCP4
PhB0
-
CCP0
U1Tx
USB0PFLT
C1o
PD0 G1
AIN15
PWM0
CAN0Rx
IDX0
U2Rx
U1Rx
CCP6
-
I2S0RXSCK U1CTS
PD1 G2
AIN14
PWM1
CAN0Tx
PhA0
U2Tx
U1Tx
CCP7
-
I2S0RXWS
June 14, 2010
EPI0S5
U1DCD
-
-
CCP2
PhB1
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General-Purpose Input/Outputs (GPIOs)
Table 9-3. GPIO Pins and Alternate Functions (108BGA) (continued)
IO
Pin Analog
Function
a
Digital Function (GPIOPCTL PMCx Bit Field Encoding)
1
2
3
4
5
6
7
8
9
10
11
PD2 H2
AIN13
U1Rx
CCP6
PWM2
CCP5
-
-
-
EPI0S20
-
-
-
PD3 H1
AIN12
U1Tx
CCP7
PWM3
CCP0
-
-
-
EPI0S21
-
-
-
PD4 B5
AIN7
CCP0
CCP3
-
-
-
-
-
I2S0RXSD
U1RI
EPI0S19
-
PD5 C6
AIN6
CCP2
CCP4
-
-
-
-
-
I2S0RXMCLK
U2Rx
EPI0S28
-
PD6 A3
AIN5
Fault0
-
-
-
-
-
-
I2S0TXSCK
U2Tx
EPI0S29
-
PD7 A2
AIN4
IDX0
C0o
CCP1
-
-
-
-
I2S0TXWS
U1DTR
EPI0S30
-
PE0 B11
-
PWM4
SSI1Clk
CCP3
-
-
-
-
EPI0S8 USB0PFLT
-
-
PE1 A12
-
PWM5
SSI1Fss Fault0
CCP2
CCP6
-
-
EPI0S9
-
-
-
PE2 A4
AIN9
CCP4
SSI1Rx
PhB1
PhA0
CCP2
-
-
EPI0S24
-
-
-
PE3 B4
AIN8
CCP1
SSI1Tx
PhA1
PhB0
CCP7
-
-
EPI0S25
-
-
-
PE4 B2
AIN3
CCP3
-
-
Fault0
U2Tx
CCP2
-
-
I2S0TXWS
-
-
PE5 B3
AIN2
CCP5
-
-
-
-
-
-
-
I2S0TXSD
-
-
PE6 A1
AIN1
PWM4
C1o
-
-
-
-
-
-
U1CTS
-
-
PE7 B1
AIN0
PWM5
C2o
-
-
-
-
-
-
U1DCD
-
-
PF0 M9
-
CAN1Rx
PhB0
PWM0
-
-
-
-
I2S0TXSD
U1DSR
PF1 H12
-
CAN1Tx
IDX1
PWM1
-
-
-
-
I2S0TXMCLK U1RTS
PF2 J11
-
LED1
PWM4
-
PWM2
-
-
-
PF3 J12
-
LED0
PWM5
-
PWM3
-
-
-
PF4 K4
-
CCP0
C0o
-
Fault0
-
-
-
PF5 K3
-
CCP2
C1o
-
-
-
-
-
EPI0S15 SSI1Tx
PG0 K1
-
U2Rx
PWM0
I2C1SCL
PWM4
-
-
PG1 K2
-
U2Tx
PWM1
I2C1SDA
PWM5
-
-
-
PG7 C10
-
PhB1
-
-
PWM7
-
-
PH0 C9
-
CCP6
PWM2
-
-
-
-
PH1 C8
-
CCP7
PWM3
-
-
-
PH2 D11
-
IDX1
C1o
-
Fault3
PH3 D10
-
PhB0
Fault0
-
USB0EPEN
PH4 B10
-
-
-
-
PH5 F10
-
-
-
-
PH6 G3
-
-
-
PH7 H3
-
-
PJ0 F3
-
-
PJ1 B6
-
PJ2 K6
-
PJ3 M10
-
-
CCP3
-
-
SSI1Clk
-
-
-
SSI1Fss
-
-
EPI0S12 SSI1Rx
-
-
-
-
-
-
-
EPI0S14
-
-
-
-
CCP5
EPI0S31
-
-
-
EPI0S6
PWM4
-
-
-
-
EPI0S7
PWM5
-
-
-
-
-
EPI0S1
-
-
-
-
-
-
EPI0S0
-
-
-
USB0PFLT
-
-
-
EPI0S10
-
-
SSI1Clk
-
-
-
-
EPI0S11
-
-
-
-
-
-
EPI0S26
-
PWM4
-
-
-
-
-
-
EPI0S27
-
PWM5
SSI1Tx
-
-
-
-
-
-
EPI0S16
-
PWM0
I2C1SCL
-
-
-
-
-
-
-
EPI0S17 USB0PFLT
PWM1
I2C1SDA
-
-
-
-
-
-
-
EPI0S18
CCP0
Fault0
-
-
-
-
-
-
-
-
-
EPI0S19
U1CTS
CCP6
-
PJ4 K11
-
-
-
-
-
-
-
-
EPI0S28
U1DCD
CCP4
-
PJ5 K12
-
-
-
-
-
-
-
-
EPI0S29
U1DSR
CCP2
-
PJ6 L10
-
-
-
-
-
-
-
-
EPI0S30
U1RTS
CCP1
-
PJ7 L12
-
-
-
-
-
-
-
-
-
U1DTR
CCP0
-
USB0EPEN EPI0S13
Fault2 SSI1Fss
SSI1Rx
a. The digital signals that are shaded gray are the power-on default values for the corresponding GPIO pin.
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Stellaris® LM3S9B95 Microcontroller
9.2
Functional Description
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 309 and Figure 9-2 on page 310). The LM3S9B95 microcontroller contains nine ports
and thus nine of these physical GPIO blocks. Note that not all pins may be implemented on every
block. Some GPIO pins can function as I/O signals for the on-chip peripheral modules. For information
on which GPIO pins are used for alternate hardware functions, refer to Table 25-5 on page 1160.
Figure 9-1. Digital I/O Pads
Commit
Control
GPIOLOCK
GPIOCR
Port
Control
GPIOPCTL
Mode
Control
GPIOAFSEL
Periph 1
DEMUX
Alternate Input
Alternate Output
Alternate Output Enable
MUX
Periph 0
Pad Input
Periph n
GPIO Output
GPIO Output Enable
Interrupt
Control
Pad
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
MUX
GPIODATA
GPIODIR
Interrupt
MUX
GPIO Input
Data
Control
Pad Output
Digital
I/O
Pad
Package I/O Pin
Pad Output
Enable
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
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General-Purpose Input/Outputs (GPIOs)
Figure 9-2. Analog/Digital I/O Pads
Commit
Control
GPIOLOCK
GPIOCR
Port
Control
GPIOPCTL
Mode
Control
GPIOAFSEL
Periph 1
DEMUX
Alternate Input
Alternate Output
Alternate Output Enable
MUX
Periph 0
Pad Input
Periph n
MUX
MUX
Data
Control
Pad Output
Pad Output Enable
Analog/Digital
I/O Pad
Package I/O Pin
GPIO Input
GPIO Output
GPIODATA
GPIODIR
Interrupt
GPIO Output Enable
Interrupt
Control
GPIOIS
GPIOIBE
GPIOIEV
GPIOIM
GPIORIS
GPIOMIS
GPIOICR
Pad
Control
GPIODR2R
GPIODR4R
GPIODR8R
GPIOSLR
GPIOPUR
GPIOPDR
GPIOODR
GPIODEN
GPIOAMSEL
Analog Circuitry
Identification Registers
GPIOPeriphID0
GPIOPeriphID1
GPIOPeriphID2
GPIOPeriphID3
9.2.1
GPIOPeriphID4
GPIOPeriphID5
GPIOPeriphID6
GPIOPeriphID7
GPIOPCellID0
GPIOPCellID1
GPIOPCellID2
GPIOPCellID3
ADC
(for GPIO pins that
connect to the ADC
input MUX)
Isolation
Circuit
Data Control
The data control registers allow software to configure the operational modes of the GPIOs. The data
direction register configures the GPIO as an input or an output while the data register either captures
incoming data or drives it out to the pads.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of
the part. This issue can be avoided with a software routine that restores JTAG functionality based on
an external or software trigger.
9.2.1.1
Data Direction Operation
The GPIO Direction (GPIODIR) register (see page 319) is used to configure each individual pin as
an input or output. When the data direction bit is cleared, the GPIO is configured as an input, and
the corresponding data register bit captures and stores the value on the GPIO port. When the data
direction bit is set, the GPIO is configured as an output, and the corresponding data register bit is
driven out on the GPIO port.
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Stellaris® LM3S9B95 Microcontroller
9.2.1.2
Data Register Operation
To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the
GPIO Data (GPIODATA) register (see page 318) by using bits [9:2] of the address bus as a mask.
In this manner, software drivers can modify individual GPIO pins in a single instruction without
affecting the state of the other pins. This method is more efficient than the conventional method of
performing a read-modify-write operation to set or clear an individual GPIO pin. To implement this
feature, the GPIODATA register covers 256 locations in the memory map.
During a write, if the address bit associated with that data bit is set, the value of the GPIODATA
register is altered. If the address bit is cleared, the data bit is left unchanged.
For example, writing a value of 0xEB to the address GPIODATA + 0x098 has the results shown in
Figure 9-3, where u indicates that data is unchanged by the write.
Figure 9-3. GPIODATA Write Example
ADDR[9:2]
0x098
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
0
0
0
0xEB
1
1
1
0
1
0
1
1
GPIODATA
u
u
1
u
u
0
1
u
7
6
5
4
3
2
1
0
During a read, if the address bit associated with the data bit is set, the value is read. If the address
bit associated with the data bit is cleared, the data bit is read as a zero, regardless of its actual
value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-4.
Figure 9-4. GPIODATA Read Example
9.2.2
ADDR[9:2]
0x0C4
9
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
1
0
0
GPIODATA
1
0
1
1
1
1
1
0
Returned Value
0
0
1
1
0
0
0
0
7
6
5
4
3
2
1
0
Interrupt Control
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. These registers
are used to select the source of the interrupt, its polarity, and the edge properties. When one or
more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for
the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any
further interrupts. For a level-sensitive interrupt, the external source must hold the level constant
for the interrupt to be recognized by the controller.
Three registers define the edge or sense that causes interrupts:
■ GPIO Interrupt Sense (GPIOIS) register (see page 320)
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 321)
■ GPIO Interrupt Event (GPIOIEV) register (see page 322)
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 323).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers
(see page 324 and page 325). As the name implies, the GPIOMIS register only shows interrupt
conditions that are allowed to be passed to the interrupt controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
interrupt controller.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt
for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion
is initiated. See page 537.
If no other Port B pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the Port B interrupts,
and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt
handler must ignore and clear interrupts on PB4 and wait for the ADC interrupt, or the ADC interrupt
must be disabled in the SETNA register and the Port B interrupt handler must poll the ADC registers
until the conversion is completed. See the ARM® Cortex™-M3 Technical Reference Manual for
more information.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 327).
When programming the interrupt control registers (GPIOIS, GPIOIBE, or GPIOIEV), the interrupts
should be masked (GPIOIM cleared). Writing any value to an interrupt control register can generate
a spurious interrupt if the corresponding bits are enabled.
9.2.3
Mode Control
The GPIO pins can be controlled by either software or hardware. Software control is the default for
most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read
or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 328), the pin state is controlled by its alternate function
(that is, the peripheral).
Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which
selects one of several peripheral functions for each GPIO. For information on the configuration
options, refer to Table 25-5 on page 1160.
Note:
9.2.4
If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register
must be set to disable the analog isolation circuit.
Commit Control
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four
JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 328), GPIO Pull Up Select (GPIOPUR) register (see page 334),
GPIO Pull-Down Select (GPIOPDR) register (see page 336), and GPIO Digital Enable (GPIODEN)
register (see page 339) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
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Stellaris® LM3S9B95 Microcontroller
(see page 341) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 342) have been set.
9.2.5
Pad Control
The pad control registers allow software to configure the GPIO pads based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable
for each GPIO.
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
9.2.6
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
9.3
Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the
®
Advanced Peripheral Bus (APB), is backwards-compatible with previous Stellaris parts. The other
aperture, the Advanced High-Performance Bus (AHB), offers the same register map but provides
better back-to-back access performance than the APB bus. These apertures are mutually exclusive.
The aperture enabled for a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL
register (see page 135).
To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the
appropriate GPIO Port bit field (GPIOn) in the RCGC2 register (see page 193).
On reset, all GPIO pins are configured out of reset to be undriven (tristate): GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, and GPIOPUR=0, except for the pins shown in Table 9-1 on page 305.
Table 9-4 on page 313 shows all possible configurations of the GPIO pads and the control register
settings required to achieve them. Table 9-5 on page 314 shows how a rising edge interrupt is
configured for pin 2 of a GPIO port.
Table 9-4. GPIO Pad Configuration Examples
Configuration
a
GPIO Register Bit Value
AFSEL
DIR
ODR
DEN
PUR
PDR
DR2R
DR4R
DR8R
SLR
Digital Input (GPIO)
0
0
0
1
?
?
X
X
X
X
Digital Output (GPIO)
0
1
0
1
?
?
?
?
?
?
Open Drain Output
(GPIO)
0
1
1
1
X
X
?
?
?
?
Open Drain
Input/Output (I2C)
1
X
1
1
X
X
?
?
?
?
Digital Input (Timer
CCP)
1
X
0
1
?
?
X
X
X
X
June 14, 2010
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General-Purpose Input/Outputs (GPIOs)
Table 9-4. GPIO Pad Configuration Examples (continued)
a
Configuration
GPIO Register Bit Value
AFSEL
Digital Input (QEI)
DIR
1
ODR
X
DEN
0
PUR
1
PDR
?
DR2R
DR4R
DR8R
X
X
X
?
SLR
X
Digital Output (PWM)
1
X
0
1
?
?
?
?
?
?
Digital Output (Timer
PWM)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(SSI)
1
X
0
1
?
?
?
?
?
?
Digital Input/Output
(UART)
1
X
0
1
?
?
?
?
?
?
Analog Input
(Comparator)
0
0
0
0
0
0
X
X
X
X
Digital Output
(Comparator)
1
X
0
1
?
?
?
?
?
?
a. X=Ignored (don’t care bit)
?=Can be either 0 or 1, depending on the configuration
Table 9-5. GPIO Interrupt Configuration Example
Register
GPIOIS
Desired
Interrupt
Event
Trigger
a
Pin 2 Bit Value
7
0=edge
6
5
4
3
2
1
0
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
X
0
0
0
0
0
1
0
0
1=level
GPIOIBE
0=single
edge
1=both
edges
GPIOIEV
0=Low level,
or falling
edge
1=High level,
or rising
edge
GPIOIM
0=masked
1=not
masked
a. X=Ignored (don’t care bit)
9.4
Register Map
Table 9-7 on page 316 lists the GPIO registers. Each GPIO port can be accessed through one of
two bus apertures. The legacy aperture, the Advanced Peripheral Bus (APB), is backwards-compatible
®
with previous Stellaris parts. The other aperture, the Advanced High-Performance Bus (AHB),
offers the same register map but provides better back-to-back access performance than the APB
bus.
Important: The GPIO registers in this chapter are duplicated in each GPIO block; however,
depending on the block, all eight bits may not be connected to a GPIO pad. In those
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cases, writing to unconnected bits has no effect, and reading unconnected bits returns
no meaningful data.
The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s
base address:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
GPIO Port A (APB): 0x4000.4000
GPIO Port A (AHB): 0x4005.8000
GPIO Port B (APB): 0x4000.5000
GPIO Port B (AHB): 0x4005.9000
GPIO Port C (APB): 0x4000.6000
GPIO Port C (AHB): 0x4005.A000
GPIO Port D (APB): 0x4000.7000
GPIO Port D (AHB): 0x4005.B000
GPIO Port E (APB): 0x4002.4000
GPIO Port E (AHB): 0x4005.C000
GPIO Port F (APB): 0x4002.5000
GPIO Port F (AHB): 0x4005.D000
GPIO Port G (APB): 0x4002.6000
GPIO Port G (AHB): 0x4005.E000
GPIO Port H (APB): 0x4002.7000
GPIO Port H (AHB): 0x4005.F000
GPIO Port J (APB): 0x4003.D000
GPIO Port J (AHB): 0x4006.0000
Note that each GPIO module clock must be enabled before the registers can be programmed (see
page 193).
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-6. GPIO Pins With Non-Zero Reset Values
Note:
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
GPIOPCTL
0x1
PA[5:2]
SSI0
1
1
0
0
0x1
PB[3:2]
I2C0
1
1
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The default register type for the GPIOCR register is RO for all GPIO pins with the exception
of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). These five pins are
currently the only GPIOs that are protected by the GPIOCR register. Because of this, the
register type for GPIO Port B7 and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the NMI pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To ensure that
the JTAG port is not accidentally programmed as a GPIO, these four pins default to
non-committable. To ensure that the NMI pin is not accidentally programmed as the
non-maskable interrupt pin, it defaults to non-committable. Because of this, the default reset
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value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR
for Port C is 0x0000.00F0.
Table 9-7. GPIO Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
GPIODATA
R/W
0x0000.0000
GPIO Data
318
0x400
GPIODIR
R/W
0x0000.0000
GPIO Direction
319
0x404
GPIOIS
R/W
0x0000.0000
GPIO Interrupt Sense
320
0x408
GPIOIBE
R/W
0x0000.0000
GPIO Interrupt Both Edges
321
0x40C
GPIOIEV
R/W
0x0000.0000
GPIO Interrupt Event
322
0x410
GPIOIM
R/W
0x0000.0000
GPIO Interrupt Mask
323
0x414
GPIORIS
RO
0x0000.0000
GPIO Raw Interrupt Status
324
0x418
GPIOMIS
RO
0x0000.0000
GPIO Masked Interrupt Status
325
0x41C
GPIOICR
W1C
0x0000.0000
GPIO Interrupt Clear
327
0x420
GPIOAFSEL
R/W
-
GPIO Alternate Function Select
328
0x500
GPIODR2R
R/W
0x0000.00FF
GPIO 2-mA Drive Select
330
0x504
GPIODR4R
R/W
0x0000.0000
GPIO 4-mA Drive Select
331
0x508
GPIODR8R
R/W
0x0000.0000
GPIO 8-mA Drive Select
332
0x50C
GPIOODR
R/W
0x0000.0000
GPIO Open Drain Select
333
0x510
GPIOPUR
R/W
-
GPIO Pull-Up Select
334
0x514
GPIOPDR
R/W
0x0000.0000
GPIO Pull-Down Select
336
0x518
GPIOSLR
R/W
0x0000.0000
GPIO Slew Rate Control Select
338
0x51C
GPIODEN
R/W
-
GPIO Digital Enable
339
0x520
GPIOLOCK
R/W
0x0000.0001
GPIO Lock
341
0x524
GPIOCR
-
-
GPIO Commit
342
0x528
GPIOAMSEL
R/W
0x0000.0000
GPIO Analog Mode Select
344
0x52C
GPIOPCTL
R/W
-
GPIO Port Control
346
0xFD0
GPIOPeriphID4
RO
0x0000.0000
GPIO Peripheral Identification 4
348
0xFD4
GPIOPeriphID5
RO
0x0000.0000
GPIO Peripheral Identification 5
349
0xFD8
GPIOPeriphID6
RO
0x0000.0000
GPIO Peripheral Identification 6
350
0xFDC
GPIOPeriphID7
RO
0x0000.0000
GPIO Peripheral Identification 7
351
0xFE0
GPIOPeriphID0
RO
0x0000.0061
GPIO Peripheral Identification 0
352
0xFE4
GPIOPeriphID1
RO
0x0000.0000
GPIO Peripheral Identification 1
353
0xFE8
GPIOPeriphID2
RO
0x0000.0018
GPIO Peripheral Identification 2
354
0xFEC
GPIOPeriphID3
RO
0x0000.0001
GPIO Peripheral Identification 3
355
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Table 9-7. GPIO Register Map (continued)
Offset
Name
0xFF0
Reset
GPIOPCellID0
RO
0x0000.000D
GPIO PrimeCell Identification 0
356
0xFF4
GPIOPCellID1
RO
0x0000.00F0
GPIO PrimeCell Identification 1
357
0xFF8
GPIOPCellID2
RO
0x0000.0005
GPIO PrimeCell Identification 2
358
0xFFC
GPIOPCellID3
RO
0x0000.00B1
GPIO PrimeCell Identification 3
359
9.5
Description
See
page
Type
Register Descriptions
The remainder of this section lists and describes the GPIO registers, in numerical order by address
offset.
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General-Purpose Input/Outputs (GPIOs)
Register 1: GPIO Data (GPIODATA), offset 0x000
The GPIODATA register is the data register. In software control mode, values written in the
GPIODATA register are transferred onto the GPIO port pins if the respective pins have been
configured as outputs through the GPIO Direction (GPIODIR) register (see page 319).
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus
bits [9:2], must be set. Otherwise, the bit values remain unchanged by the write.
Similarly, the values read from this register are determined for each bit by the mask bit derived from
the address used to access the data register, bits [9:2]. Bits that are set in the address mask cause
the corresponding bits in GPIODATA to be read, and bits that are clear in the address mask cause
the corresponding bits in GPIODATA to be read as 0, regardless of their value.
A read from GPIODATA returns the last bit value written if the respective pins are configured as
outputs, or it returns the value on the corresponding input pin when these are configured as inputs.
All bits are cleared by a reset.
GPIO Data (GPIODATA)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
DATA
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DATA
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Data
This register is virtually mapped to 256 locations in the address space.
To facilitate the reading and writing of data to these registers by
independent drivers, the data read from and written to the registers are
masked by the eight address lines [9:2]. Reads from this register return
its current state. Writes to this register only affect bits that are not masked
by ADDR[9:2] and are configured as outputs. See “Data Register
Operation” on page 311 for examples of reads and writes.
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Register 2: GPIO Direction (GPIODIR), offset 0x400
The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures
the corresponding pin to be an output, while clearing a bit configures the corresponding pin to be
an input. All bits are cleared by a reset, meaning all GPIO pins are inputs by default.
GPIO Direction (GPIODIR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x400
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DIR
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DIR
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Data Direction
Value Description
0
Corresponding pin is an input.
1
Corresponding pins is an output.
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Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404
The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures
the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect
edges. All bits are cleared by a reset.
GPIO Interrupt Sense (GPIOIS)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x404
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IS
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Sense
Value Description
0
The edge on the corresponding pin is detected (edge-sensitive).
1
The level on the corresponding pin is detected (level-sensitive).
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Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408
The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the
GPIO Interrupt Sense (GPIOIS) register (see page 320) is set to detect edges, setting a bit in the
GPIOIBE register configures the corresponding pin to detect both rising and falling edges, regardless
of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 322). Clearing
a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset.
GPIO Interrupt Both Edges (GPIOIBE)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x408
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IBE
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IBE
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Both Edges
Value Description
0
Interrupt generation is controlled by the GPIO Interrupt Event
(GPIOIEV) register (see page 322).
1
Both edges on the corresponding pin trigger an interrupt.
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Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C
The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures
the corresponding pin to detect rising edges or high levels, depending on the corresponding bit
value in the GPIO Interrupt Sense (GPIOIS) register (see page 320). Clearing a bit configures the
pin to detect falling edges or low levels, depending on the corresponding bit value in the GPIOIS
register. All bits are cleared by a reset.
GPIO Interrupt Event (GPIOIEV)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x40C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IEV
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IEV
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Event
Value Description
0
A falling edge or a Low level on the corresponding pin triggers
an interrupt.
1
A rising edge or a High level on the corresponding pin triggers
an interrupt.
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Stellaris® LM3S9B95 Microcontroller
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410
The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows
interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the
combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being
sent to the interrupt controller. All bits are cleared by a reset.
GPIO Interrupt Mask (GPIOIM)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x410
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IME
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IME
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Mask Enable
Value Description
0
The interrupt from the corresponding pin is masked.
1
The interrupt from the corresponding pin is sent to the interrupt
controller.
June 14, 2010
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General-Purpose Input/Outputs (GPIOs)
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414
The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt
condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt
Mask (GPIOIM) register (see page 323) is set, the interrupt is sent to the interrupt controller. Bits
read as zero indicate that corresponding input pins have not initiated an interrupt. A bit in this register
can be cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR)
register.
GPIO Raw Interrupt Status (GPIORIS)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x414
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
RIS
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Raw Status
Value Description
1
An interrupt condition has occurred on the corresponding pin.
0
An interrupt condition has not occurred on the corresponding
pin.
A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR
register.
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Stellaris® LM3S9B95 Microcontroller
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the
corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either
no interrupt has been generated, or the interrupt is masked.
In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set), an interrupt
for Port B is generated, and an external trigger signal is sent to the ADC. If the ADC Event
Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion
is initiated. See page 537.
If no other Port B pins are being used to generate interrupts, the ARM Integrated Nested Vectored
Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the Port B interrupts,
and the ADC interrupt can be used to read back the converted data. Otherwise, the Port B interrupt
handler must ignore and clear interrupts on PB4 and wait for the ADC interrupt, or the ADC interrupt
must be disabled in the SETNA register and the Port B interrupt handler must poll the ADC registers
until the conversion is completed. See the ARM® Cortex™-M3 Technical Reference Manual for
more information.
GPIOMIS is the state of the interrupt after masking.
GPIO Masked Interrupt Status (GPIOMIS)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x418
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
MIS
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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General-Purpose Input/Outputs (GPIOs)
Bit/Field
Name
Type
Reset
Description
7:0
MIS
RO
0x00
GPIO Masked Interrupt Status
Value Description
1
An interrupt condition on the corresponding pin has triggered
an interrupt to the interrupt controller.
0
An interrupt condition on the corresponding pin is masked or
has not occurred.
A bit is cleared by writing a 1 to the corresponding bit in the GPIOICR
register.
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June 14, 2010
Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect.
GPIO Interrupt Clear (GPIOICR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x41C
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
W1C
0
W1C
0
W1C
0
W1C
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
IC
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
IC
W1C
0x00
RO
0
W1C
0
W1C
0
W1C
0
W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Clear
Value Description
1
The corresponding interrupt is cleared.
0
The corresponding interrupt is unaffected.
June 14, 2010
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420
The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a
GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the
corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral
functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to
select one of the possible functions. Table 25-5 on page 1160 details which functions are muxed on
each GPIO pin. The reset value for this register is 0x0000.0000 for GPIO ports that are not listed
in the table below.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-8. GPIO Pins With Non-Zero Reset Values
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
GPIOPCTL
0x1
PA[5:2]
SSI0
1
1
0
0
0x1
PB[3:2]
I2C0
1
1
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of
the part. This issue can be avoided with a software routine that restores JTAG functionality based on
an external or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four
JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 328), GPIO Pull Up Select (GPIOPUR) register (see page 334),
GPIO Pull-Down Select (GPIOPDR) register (see page 336), and GPIO Digital Enable (GPIODEN)
register (see page 339) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 341) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 342) have been set.
When using the I2C module, in addition to setting the GPIOAFSEL register bits for the I2C clock
and data pins, the pins should be set to open drain using the GPIO Open Drain Select (GPIOODR)
register (see examples in “Initialization and Configuration” on page 313).
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Stellaris® LM3S9B95 Microcontroller
GPIO Alternate Function Select (GPIOAFSEL)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x420
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
AFSEL
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
AFSEL
R/W
-
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Alternate Function Select
Value Description
0
The associated pin functions as a GPIO and is controlled by
the GPIO registers.
1
The associated pin functions as a peripheral signal and is
controlled by the alternate hardware function.
The reset value for this register is 0x0000.0000 for GPIO ports
that are not listed in Table 9-1 on page 305.
June 14, 2010
329
Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500
The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal,
the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are
automatically cleared by hardware. By default, all GPIO pins have 2-mA drive.
GPIO 2-mA Drive Select (GPIODR2R)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x500
Type R/W, reset 0x0000.00FF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DRV2
R/W
0xFF
RO
0
R/W
1
R/W
1
R/W
1
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad 2-mA Drive Enable
Value Description
1
The corresponding GPIO pin has 2-mA drive.
0
The drive for the corresponding GPIO pin is controlled by the
GPIODR4R or GPIODR8R register.
Setting a bit in either the GPIODR4 register or the GPIODR8 register
clears the corresponding 2-mA enable bit. The change is effective on
the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the
next clock cycle.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504
The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal,
the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are
automatically cleared by hardware.
GPIO 4-mA Drive Select (GPIODR4R)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x504
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV4
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DRV4
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad 4-mA Drive Enable
Value Description
1
The corresponding GPIO pin has 4-mA drive.
0
The drive for the corresponding GPIO pin is controlled by the
GPIODR2R or GPIODR8R register.
Setting a bit in either the GPIODR2 register or the GPIODR8 register
clears the corresponding 4-mA enable bit. The change is effective on
the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the
next clock cycle.
June 14, 2010
331
Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508
The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be
individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal,
the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are
automatically cleared by hardware. The 8-mA setting is also used for high-current operation.
Note:
There is no configuration difference between 8-mA and high-current operation. The additional
current capacity results from a shift in the VOH/VOL levels. See “Recommended DC Operating
Conditions” on page 1205 for further information.
GPIO 8-mA Drive Select (GPIODR8R)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x508
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DRV8
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DRV8
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad 8-mA Drive Enable
Value Description
1
The corresponding GPIO pin has 8-mA drive.
0
The drive for the corresponding GPIO pin is controlled by the
GPIODR2R or GPIODR4R register.
Setting a bit in either the GPIODR2 register or the GPIODR4 register
clears the corresponding 8-mA enable bit. The change is effective on
the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the
next clock cycle.
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Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C
The GPIOODR register is the open drain control register. Setting a bit in this register enables the
open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled, the
corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see
page 339). Corresponding bits in the drive strength and slew rate control registers (GPIODR2R,
GPIODR4R, GPIODR8R, and GPIOSLR) can be set to achieve the desired rise and fall times. The
GPIO acts as an open-drain input if the corresponding bit in the GPIODIR register is cleared. If open
drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the
open-drain selection has no effect until the GPIO is changed to an output.
When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate
Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set (see
examples in “Initialization and Configuration” on page 313).
GPIO Open Drain Select (GPIOODR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x50C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
ODE
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
ODE
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Output Pad Open Drain Enable
Value Description
1
The corresponding pin is configured as open drain.
0
The corresponding pin is not configured as open drain.
June 14, 2010
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General-Purpose Input/Outputs (GPIOs)
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510
The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on
the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the
corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 336). Write access
to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes
to the equivalent bit in this register.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-9. GPIO Pins With Non-Zero Reset Values
Note:
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
GPIOPCTL
0x1
PA[5:2]
SSI0
1
1
0
0
0x1
PB[3:2]
I2C0
1
1
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is currently provided for the NMI
pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 328), GPIO Pull Up Select
(GPIOPUR) register (see page 334), GPIO Pull-Down Select (GPIOPDR) register (see
page 336), and GPIO Digital Enable (GPIODEN) register (see page 339) are not committed
to storage unless the GPIO Lock (GPIOLOCK) register (see page 341) has been unlocked
and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 342) have been
set.
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GPIO Pull-Up Select (GPIOPUR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x510
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PUE
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PUE
R/W
-
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Pad Weak Pull-Up Enable
Value Description
1
The corresponding pin has a weak pull-up resistor.
0
The corresponding pin is not affected.
Setting a bit in the GPIOPDR register clears the corresponding bit in
the GPIOPUR register. The change is effective on the second clock
cycle after the write if accessing GPIO via the APB memory aperture.
If using AHB access, the change is effective on the next clock cycle.
The reset value for this register is 0x0000.0000 for GPIO ports that are
not listed in Table 9-1 on page 305.
June 14, 2010
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General-Purpose Input/Outputs (GPIOs)
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514
The GPIOPDR register is the pull-down control register. When a bit is set, a weak pull-down resistor
on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the
corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 334).
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-10. GPIO Pins With Non-Zero Reset Values
Note:
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
GPIOPCTL
0
0x1
PA[5:2]
SSI0
1
1
0
0
0x1
PB[3:2]
I2C0
1
1
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is currently provided for the NMI
pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 328), GPIO Pull Up Select
(GPIOPUR) register (see page 334), GPIO Pull-Down Select (GPIOPDR) register (see
page 336), and GPIO Digital Enable (GPIODEN) register (see page 339) are not committed
to storage unless the GPIO Lock (GPIOLOCK) register (see page 341) has been unlocked
and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 342) have been
set.
GPIO Pull-Down Select (GPIOPDR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x514
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
PDE
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PDE
R/W
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Pad Weak Pull-Down Enable
Value Description
1
The corresponding pin has a weak pull-down resistor.
0
The corresponding pin is not affected.
Setting a bit in the GPIOPUR register clears the corresponding bit in
the GPIOPDR register. The change is effective on the second clock
cycle after the write if accessing GPIO via the APB memory aperture.
If using AHB access, the change is effective on the next clock cycle.
June 14, 2010
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General-Purpose Input/Outputs (GPIOs)
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518
The GPIOSLR register is the slew rate control register. Slew rate control is only available when
using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see
page 332).
GPIO Slew Rate Control Select (GPIOSLR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x518
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
SRL
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
SRL
R/W
0x00
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Slew Rate Limit Enable (8-mA drive only)
Value Description
1
Slew rate control is enabled for the corresponding pin.
0
Slew rate control is disabled for the corresponding pin.
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Stellaris® LM3S9B95 Microcontroller
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note:
Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed
below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do
not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To
use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIODEN
bit must be set.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-11. GPIO Pins With Non-Zero Reset Values
Note:
GPIO Pins
Default State
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
GPIOPCTL
PA[1:0]
UART0
1
1
0
0
0x1
PA[5:2]
SSI0
1
1
0
0
0x1
PB[3:2]
I2C0
1
1
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is currently provided for the NMI
pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 328), GPIO Pull Up Select
(GPIOPUR) register (see page 334), GPIO Pull-Down Select (GPIOPDR) register (see
page 336), and GPIO Digital Enable (GPIODEN) register (see page 339) are not committed
to storage unless the GPIO Lock (GPIOLOCK) register (see page 341) has been unlocked
and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 342) have been
set.
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General-Purpose Input/Outputs (GPIOs)
GPIO Digital Enable (GPIODEN)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x51C
Type R/W, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
R/W
-
R/W
-
R/W
-
R/W
-
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
DEN
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
DEN
R/W
-
RO
0
R/W
-
R/W
-
R/W
-
R/W
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Digital Enable
Value Description
0
The digital functions for the corresponding pin are disabled.
1
The digital functions for the corresponding pin are enabled.
The reset value for this register is 0x0000.0000 for GPIO ports
that are not listed in Table 9-1 on page 305.
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Register 19: GPIO Lock (GPIOLOCK), offset 0x520
The GPIOLOCK register enables write access to the GPIOCR register (see page 342). Writing
0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to
the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the
lock status rather than the 32-bit value that was previously written. Therefore, when write accesses
are disabled, or locked, reading the GPIOLOCK register returns 0x0000.0001. When write accesses
are enabled, or unlocked, reading the GPIOLOCK register returns 0x0000.0000.
GPIO Lock (GPIOLOCK)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x520
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
LOCK
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
LOCK
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
31:0
LOCK
R/W
R/W
0
Reset
R/W
0
Description
0x0000.0001 GPIO Lock
A write of the value 0x4C4F.434B unlocks the GPIO Commit (GPIOCR)
register for write access.A write of any other value or a write to the
GPIOCR register reapplies the lock, preventing any register updates.
A read of this register returns the following values:
Value
Description
0x0000.0001 The GPIOCR register is locked and may not be modified.
0x0000.0000 The GPIOCR register is unlocked and may be modified.
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General-Purpose Input/Outputs (GPIOs)
Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN registers are committed when a
write to these registers is performed. If a bit in the GPIOCR register is cleared, the data being written
to the corresponding bit in the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers cannot
be committed and retains its previous value. If a bit in the GPIOCR register is set, the data being
written to the corresponding bit of the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers
is committed to the register and reflects the new value.
The contents of the GPIOCR register can only be modified if the status in the GPIOLOCK register
is unlocked. Writes to the GPIOCR register are ignored if the status in the GPIOLOCK register is
locked.
Important: This register is designed to prevent accidental programming of the registers that control
connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the
GPIOCR register to 0 for PB7 and PC[3:0], the NMI and JTAG/SWD debug port can
only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK,
GPIOCR, and the corresponding registers.
Because this protection is currently only implemented on the NMI and JTAG/SWD pins
on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written
with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit
new values to the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN register bits of
these other pins.
GPIO Commit (GPIOCR)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x524
Type -, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
-
-
-
-
-
-
-
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
CR
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CR
-
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Commit
Value Description
1
The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or
GPIODEN bits can be written.
0
The corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or
GPIODEN bits cannot be written.
Note:
The default register type for the GPIOCR register is RO for
all GPIO pins with the exception of the NMI pin and the four
JTAG/SWD pins (PB7 and PC[3:0]). These five pins are
currently the only GPIOs that are protected by the GPIOCR
register. Because of this, the register type for GPIO Port B7
and GPIO Port C[3:0] is R/W.
The default reset value for the GPIOCR register is
0x0000.00FF for all GPIO pins, with the exception of the NMI
pin and the four JTAG/SWD pins (PB7 and PC[3:0]). To
ensure that the JTAG port is not accidentally programmed as
a GPIO, these four pins default to non-committable. To ensure
that the NMI pin is not accidentally programmed as the
non-maskable interrupt pin, it defaults to non-committable.
Because of this, the default reset value of GPIOCR for GPIO
Port B is 0x0000.007F while the default reset value of
GPIOCR for Port C is 0x0000.00F0.
June 14, 2010
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528
Important: This register is only valid for ports D and E; the corresponding base addresses for the
remaining ports are not valid.
If any pin is to be used as an ADC input, the appropriate bit in GPIOAMSEL must be
set to disable the analog isolation circuit.
The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because
the GPIOs may be driven by a 5-V source and affect analog operation, analog circuitry requires
isolation from the pins when they are not used in their analog function.
Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. For
information on which GPIO pins can be used for ADC functions, refer to Table 25-5 on page 1160.
GPIO Analog Mode Select (GPIOAMSEL)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x528
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
GPIOAMSEL
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
R/W
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
7:4
GPIOAMSEL
R/W
0x0
Description
GPIO Analog Mode Select
Value Description
1
The analog function of the pin is enabled, the isolation is
disabled, and the pin is capable of analog functions.
0
The analog function of the pin is disabled, the isolation is
enabled, and the pin is capable of digital functions as specified
by the other GPIO configuration registers.
Note:
This register and bits are only valid for GPIO signals that
share analog function through a unified I/O pad.
The reset state of this register is 0 for all signals.
3:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C
The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific
peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the
GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by
default. When a bit is set in the GPIOAFSEL register, the corresponding GPIO signal is controlled
by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions
for each GPIO, providing additional flexibility in signal definition. For information on the defined
encodings for the bit fields in this register, refer to Table 25-5 on page 1160. The reset value for this
register is 0x0000.0000 for GPIO ports that are not listed in the table below.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-12. GPIO Pins With Non-Zero Reset Values
GPIO Pins
Default State
PA[1:0]
UART0
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
GPIOPCTL
0
0x1
PA[5:2]
SSI0
1
1
0
0
0x1
PB[3:2]
I2C0
1
1
0
0
0x1
PC[3:0]
JTAG/SWD
1
1
0
1
0x3
GPIO Port Control (GPIOPCTL)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0x52C
Type R/W, reset 31
30
29
28
27
26
PMC7
Type
Reset
R/W
-
R/W
-
15
14
R/W
-
R/W
-
R/W
-
R/W
-
13
12
11
10
PMC3
Type
Reset
R/W
-
R/W
-
25
24
23
22
PMC6
R/W
-
R/W
-
R/W
-
R/W
-
9
8
7
6
PMC2
R/W
-
R/W
-
R/W
-
R/W
-
21
20
19
18
PMC5
R/W
-
R/W
-
R/W
-
R/W
-
5
4
3
2
PMC1
R/W
-
R/W
-
R/W
-
R/W
-
17
16
R/W
-
R/W
-
1
0
R/W
-
R/W
-
PMC4
PMC0
R/W
-
346
R/W
-
R/W
-
R/W
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
31:28
PMC7
R/W
-
Description
Port Mux Control 7
This field controls the configuration for GPIO pin 7.
27:24
PMC6
R/W
-
Port Mux Control 6
This field controls the configuration for GPIO pin 6.
23:20
PMC5
R/W
-
Port Mux Control 5
This field controls the configuration for GPIO pin 5.
19:16
PMC4
R/W
-
Port Mux Control 4
This field controls the configuration for GPIO pin 4.
15:12
PMC3
R/W
-
Port Mux Control 3
This field controls the configuration for GPIO pin 3.
11:8
PMC2
R/W
-
Port Mux Control 2
This field controls the configuration for GPIO pin 2.
7:4
PMC1
R/W
-
Port Mux Control 1
This field controls the configuration for GPIO pin 1.
3:0
PMC0
R/W
-
Port Mux Control 0
This field controls the configuration for GPIO pin 0.
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 4 (GPIOPeriphID4)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFD0
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID4
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID4
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [7:0]
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Stellaris® LM3S9B95 Microcontroller
Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 5 (GPIOPeriphID5)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFD4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID5
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID5
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [15:8]
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 6 (GPIOPeriphID6)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFD8
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID6
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID6
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [23:16]
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Stellaris® LM3S9B95 Microcontroller
Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC
The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 7 (GPIOPeriphID7)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFDC
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID7
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID7
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [31:24]
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Texas Instruments-Advance Information
General-Purpose Input/Outputs (GPIOs)
Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 0 (GPIOPeriphID0)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFE0
Type RO, reset 0x0000.0061
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID0
RO
0x61
RO
0
RO
0
RO
1
RO
1
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [7:0]
Can be used by software to identify the presence of this peripheral.
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Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 1 (GPIOPeriphID1)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFE4
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID1
RO
0x00
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [15:8]
Can be used by software to identify the presence of this peripheral.
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General-Purpose Input/Outputs (GPIOs)
Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 2 (GPIOPeriphID2)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFE8
Type RO, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID2
RO
0x18
RO
0
RO
0
RO
0
RO
0
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [23:16]
Can be used by software to identify the presence of this peripheral.
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Stellaris® LM3S9B95 Microcontroller
Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC
The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can
conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register,
used by software to identify the peripheral.
GPIO Peripheral Identification 3 (GPIOPeriphID3)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFEC
Type RO, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
PID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
PID3
RO
0x01
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Peripheral ID Register [31:24]
Can be used by software to identify the presence of this peripheral.
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General-Purpose Input/Outputs (GPIOs)
Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 0 (GPIOPCellID0)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFF0
Type RO, reset 0x0000.000D
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
1
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID0
RO
0x0D
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO PrimeCell ID Register [7:0]
Provides software a standard cross-peripheral identification system.
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Stellaris® LM3S9B95 Microcontroller
Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 1 (GPIOPCellID1)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFF4
Type RO, reset 0x0000.00F0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID1
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID1
RO
0xF0
RO
0
RO
1
RO
1
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO PrimeCell ID Register [15:8]
Provides software a standard cross-peripheral identification system.
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General-Purpose Input/Outputs (GPIOs)
Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 2 (GPIOPCellID2)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFF8
Type RO, reset 0x0000.0005
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
1
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID2
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID2
RO
0x05
RO
0
RO
0
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO PrimeCell ID Register [23:16]
Provides software a standard cross-peripheral identification system.
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Stellaris® LM3S9B95 Microcontroller
Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC
The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide
registers, that can conceptually be treated as one 32-bit register. The register is used as a standard
cross-peripheral identification system.
GPIO PrimeCell Identification 3 (GPIOPCellID3)
GPIO Port A (APB) base: 0x4000.4000
GPIO Port A (AHB) base: 0x4005.8000
GPIO Port B (APB) base: 0x4000.5000
GPIO Port B (AHB) base: 0x4005.9000
GPIO Port C (APB) base: 0x4000.6000
GPIO Port C (AHB) base: 0x4005.A000
GPIO Port D (APB) base: 0x4000.7000
GPIO Port D (AHB) base: 0x4005.B000
GPIO Port E (APB) base: 0x4002.4000
GPIO Port E (AHB) base: 0x4005.C000
GPIO Port F (APB) base: 0x4002.5000
GPIO Port F (AHB) base: 0x4005.D000
GPIO Port G (APB) base: 0x4002.6000
GPIO Port G (AHB) base: 0x4005.E000
GPIO Port H (APB) base: 0x4002.7000
GPIO Port H (AHB) base: 0x4005.F000
GPIO Port J (APB) base: 0x4003.D000
GPIO Port J (AHB) base: 0x4006.0000
Offset 0xFFC
Type RO, reset 0x0000.00B1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
3
2
1
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
CID3
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:0
CID3
RO
0xB1
RO
0
RO
1
RO
0
RO
1
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO PrimeCell ID Register [31:24]
Provides software a standard cross-peripheral identification system.
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External Peripheral Interface (EPI)
10
External Peripheral Interface (EPI)
The External Peripheral Interface is a high-speed parallel bus for external peripherals or memory.
It has several modes of operation to interface gluelessly to many types of external devices. The
External Peripheral Interface is similar to a standard microprocessor address/data bus, except that
it must typically be connected to just one type of external device. Enhanced capabilities include
µDMA support, clocking control and support for external FIFO buffers.
The EPI has the following features:
■ 8/16/32-bit dedicated parallel bus for external peripherals and memory
■ Memory interface supports contiguous memory access independent of data bus width, thus
enabling code execution directly from SDRAM, SRAM and Flash memory
■ Blocking and non-blocking reads
■ Separates processor from timing details through use of an internal write FIFO
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for read and write
– Read channel request asserted by programmable levels on the internal non-blocking read
FIFO (NBRFIFO)
– Write channel request asserted by empty on the internal write FIFO (WFIFO)
The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory
(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also
provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same
way as a communication mechanism and is speed-controlled using clocking.
■ Synchronous Dynamic Random Access Memory (SDRAM)
– Supports x16 (single data rate) SDRAM at up to 50 MHz
– Supports low-cost SDRAMs up to 64 MB (512 megabits)
– Includes automatic refresh and access to all banks/rows
– Includes a Sleep/Standby mode to keep contents active with minimal power draw
– Multiplexed address/data interface for reduced pin count
■ Host-bus
– Traditional x8 and x16 MCU bus interface capabilities
– Similar device compatibility options as PIC, ATmega, 8051, and others
– Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
no byte selects)
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– Support of both muxed and de-muxed address and data
– Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
– Speed controlled, with read and write data wait-state counters
– Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn
– Manual chip-enable (or use extra address pins)
■ General Purpose
– Wide parallel interfaces for fast communications with CPLDs and FPGAs
– Data widths up to 32-bits
– Data rates up to 150 MB/second
– Optional “address” sizes from 4 bits to 20 bits
– Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input
■ General parallel GPIO
– 1 to 32 bits, FIFOed with speed control
– Useful for custom peripherals or for digital data acquisition and actuator controls
10.1
EPI Block Diagram
®
Figure 10-1 on page 362 provides a block diagram of a Stellaris EPI module.
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External Peripheral Interface (EPI)
Figure 10-1. EPI Block Diagram
General
Parallel
GPIO
NBRFIFO
8 x 32 bits
WFIFO
SDRAM
4 x 32 bits
AHB
Bus
Interface
With
DMA
AHB
EPI 31:0
Host Bus
Baud
Rate
Control
(Clock)
Wide
Parallel
Interface
10.2
Signal Description
Table 10-1 on page 362 and Table 10-2 on page 363 list the external signals of the EPI controller and
describe the function of each. The EPI controller signals are alternate functions for GPIO signals
and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin Assignment"
lists the GPIO pin placement for the EPI signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 328) should be set to choose the EPI controller function. The
number in parentheses is the encoding that must be programmed into the PMCn field in the GPIO
Port Control (GPIOPCTL) register (page 346) to assign the EPI signals to the specified GPIO port
pins. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 304.
Table 10-1. Signals for External Peripheral Interface (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
Pin Type
a
Buffer Type
Description
EPI0S0
83
PH3 (8)
I/O
TTL
EPI module 0 signal 0.
EPI0S1
84
PH2 (8)
I/O
TTL
EPI module 0 signal 1.
EPI0S2
25
PC4 (8)
I/O
TTL
EPI module 0 signal 2.
EPI0S3
24
PC5 (8)
I/O
TTL
EPI module 0 signal 3.
EPI0S4
23
PC6 (8)
I/O
TTL
EPI module 0 signal 4.
EPI0S5
22
PC7 (8)
I/O
TTL
EPI module 0 signal 5.
EPI0S6
86
PH0 (8)
I/O
TTL
EPI module 0 signal 6.
EPI0S7
85
PH1 (8)
I/O
TTL
EPI module 0 signal 7.
EPI0S8
74
PE0 (8)
I/O
TTL
EPI module 0 signal 8.
EPI0S9
75
PE1 (8)
I/O
TTL
EPI module 0 signal 9.
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Table 10-1. Signals for External Peripheral Interface (100LQFP) (continued)
Pin Name
EPI0S10
Pin Number Pin Mux / Pin
Assignment
76
PH4 (8)
a
Pin Type
Buffer Type
I/O
TTL
Description
EPI module 0 signal 10.
EPI0S11
63
PH5 (8)
I/O
TTL
EPI module 0 signal 11.
EPI0S12
42
PF4 (8)
I/O
TTL
EPI module 0 signal 12.
EPI0S13
19
PG0 (8)
I/O
TTL
EPI module 0 signal 13.
EPI0S14
18
PG1 (8)
I/O
TTL
EPI module 0 signal 14.
EPI0S15
41
PF5 (8)
I/O
TTL
EPI module 0 signal 15.
EPI0S16
14
PJ0 (8)
I/O
TTL
EPI module 0 signal 16.
EPI0S17
87
PJ1 (8)
I/O
TTL
EPI module 0 signal 17.
EPI0S18
39
PJ2 (8)
I/O
TTL
EPI module 0 signal 18.
EPI0S19
50
97
PJ3 (8)
PD4 (10)
I/O
TTL
EPI module 0 signal 19.
EPI0S20
12
PD2 (8)
I/O
TTL
EPI module 0 signal 20.
EPI0S21
13
PD3 (8)
I/O
TTL
EPI module 0 signal 21.
EPI0S22
91
PB5 (8)
I/O
TTL
EPI module 0 signal 22.
EPI0S23
92
PB4 (8)
I/O
TTL
EPI module 0 signal 23.
EPI0S24
95
PE2 (8)
I/O
TTL
EPI module 0 signal 24.
EPI0S25
96
PE3 (8)
I/O
TTL
EPI module 0 signal 25.
EPI0S26
62
PH6 (8)
I/O
TTL
EPI module 0 signal 26.
EPI0S27
15
PH7 (8)
I/O
TTL
EPI module 0 signal 27.
EPI0S28
52
98
PJ4 (8)
PD5 (10)
I/O
TTL
EPI module 0 signal 28.
EPI0S29
53
99
PJ5 (8)
PD6 (10)
I/O
TTL
EPI module 0 signal 29.
EPI0S30
54
100
PJ6 (8)
PD7 (10)
I/O
TTL
EPI module 0 signal 30.
EPI0S31
36
PG7 (9)
I/O
TTL
EPI module 0 signal 31.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 10-2. Signals for External Peripheral Interface (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
Pin Type
a
Buffer Type
Description
EPI0S0
D10
PH3 (8)
I/O
TTL
EPI module 0 signal 0.
EPI0S1
D11
PH2 (8)
I/O
TTL
EPI module 0 signal 1.
EPI0S2
L1
PC4 (8)
I/O
TTL
EPI module 0 signal 2.
EPI0S3
M1
PC5 (8)
I/O
TTL
EPI module 0 signal 3.
EPI0S4
M2
PC6 (8)
I/O
TTL
EPI module 0 signal 4.
EPI0S5
L2
PC7 (8)
I/O
TTL
EPI module 0 signal 5.
EPI0S6
C9
PH0 (8)
I/O
TTL
EPI module 0 signal 6.
EPI0S7
C8
PH1 (8)
I/O
TTL
EPI module 0 signal 7.
EPI0S8
B11
PE0 (8)
I/O
TTL
EPI module 0 signal 8.
EPI0S9
A12
PE1 (8)
I/O
TTL
EPI module 0 signal 9.
EPI0S10
B10
PH4 (8)
I/O
TTL
EPI module 0 signal 10.
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Table 10-2. Signals for External Peripheral Interface (108BGA) (continued)
Pin Name
EPI0S11
Pin Number Pin Mux / Pin
Assignment
F10
PH5 (8)
a
Pin Type
Buffer Type
I/O
TTL
Description
EPI module 0 signal 11.
EPI0S12
K4
PF4 (8)
I/O
TTL
EPI module 0 signal 12.
EPI0S13
K1
PG0 (8)
I/O
TTL
EPI module 0 signal 13.
EPI0S14
K2
PG1 (8)
I/O
TTL
EPI module 0 signal 14.
EPI0S15
K3
PF5 (8)
I/O
TTL
EPI module 0 signal 15.
EPI0S16
F3
PJ0 (8)
I/O
TTL
EPI module 0 signal 16.
EPI0S17
B6
PJ1 (8)
I/O
TTL
EPI module 0 signal 17.
EPI0S18
K6
PJ2 (8)
I/O
TTL
EPI module 0 signal 18.
EPI0S19
M10
B5
PJ3 (8)
PD4 (10)
I/O
TTL
EPI module 0 signal 19.
EPI0S20
H2
PD2 (8)
I/O
TTL
EPI module 0 signal 20.
EPI0S21
H1
PD3 (8)
I/O
TTL
EPI module 0 signal 21.
EPI0S22
B7
PB5 (8)
I/O
TTL
EPI module 0 signal 22.
EPI0S23
A6
PB4 (8)
I/O
TTL
EPI module 0 signal 23.
EPI0S24
A4
PE2 (8)
I/O
TTL
EPI module 0 signal 24.
EPI0S25
B4
PE3 (8)
I/O
TTL
EPI module 0 signal 25.
EPI0S26
G3
PH6 (8)
I/O
TTL
EPI module 0 signal 26.
EPI0S27
H3
PH7 (8)
I/O
TTL
EPI module 0 signal 27.
EPI0S28
K11
C6
PJ4 (8)
PD5 (10)
I/O
TTL
EPI module 0 signal 28.
EPI0S29
K12
A3
PJ5 (8)
PD6 (10)
I/O
TTL
EPI module 0 signal 29.
EPI0S30
L10
A2
PJ6 (8)
PD7 (10)
I/O
TTL
EPI module 0 signal 30.
EPI0S31
C10
PG7 (9)
I/O
TTL
EPI module 0 signal 31.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
10.3
Functional Description
The EPI controller provides a glueless, programmable interface to a variety of common external
peripherals such as SDRAM, Host Bus x8 and x16 devices, RAM, NOR Flash memory, CPLDs and
FPGAs. In addition, the EPI controller provides custom GPIO that can use a FIFO with speed control
by using either the internal write FIFO (WFIFO) or the non-blocking read FIFO (NBRFIFO). The
WFIFO can hold 4 words of data that are written to the external interface at the rate controlled by
the EPI Main Baud Rate (EPIBAUD) register. The NBRFIFO can hold 8 words of data and samples
at the rate controlled by the EPIBAUD register. The EPI controller provides predictable operation
and thus has an advantage over regular GPIO which has more variable timing due to on-chip bus
arbitration and delays across bus bridges. Blocking reads stall the CPU until the transaction
completes. Non-blocking reads are performed in the background and allow the processor to continue
operation. In addition, write data can also be stored in the WFIFO to allow multiple writes with no
stalls.
Main read and write operations can be performed in subsets of the range 0x6000.0000 to
0xDFFF.FFFF. A read from an address mapped location uses the offset and size to control the
address and size of the external operation. When performing a multi-value load, the read is done
as a burst (when available) to maximize performance. A write to an address mapped location uses
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the offset and size to control the address and size of the external operation. When performing a
multi-value store, the write is done as a burst (when available) to maximize performance.
NAND Flash memory (x8) can be read natively. Automatic programming support is not provided;
programming must be done by the user following the manufacturer's protocol. Automatic page ECC
is also not supported, but can be performed in software.
10.3.1
Non-Blocking Reads
The EPI Controller supports a special kind of read called a non-blocking read, also referred to as a
posted read. Where a normal read stalls the processor or μDMA until the data is returned, a
non-blocking read is performed in the background.
A non-blocking read is configured by writing the start address into a EPIRADDRn register, the size
per transaction into a EPIRSIZEn register, and then the count of operations into a EPIRPSTDn
register. After each read is completed, the result is written into the NBRFIFO and the EPIRADDRn
register is incremented by the size (1, 2, or 4).
If the NBRFIFO is filled, then the reads pause until space is made available. The NBRFIFO can be
configured to interrupt the processor or trigger the μDMA based on fullness using the EPIFIFOLVL
register. By using the trigger/interrupt method, the μDMA (or processor) can keep space available
in the NBRFIFO and allow the reads to continue unimpeded.
When performing non-blocking reads, the SDRAM controller issues two additional read transactions
after the burst request is terminated. The data for these additional transfers is discarded. This
situation is transparent to the user other than the additional EPI bus activity and can safely be
ignored.
Two non-blocking read register sets are available to allow sequencing and ping-pong use. When
one completes, the other then activates. So, for example, if 20 words are to be read from 0x100
and 10 words from 0x200, the EPIRPSTD0 register can be set up with the read from 0x100 (with a
count of 20), and the EPIRPSTD1 register can be set up with the read from 0x200 (with a count of
10). When EPIRPSTD0 finishes (count goes to 0), the EPIRPSTD1 register then starts its operation.
The NBRFIFO has then passed 30 values. When used with the μDMA, it may transfer 30 values
(simple sequence), or the primary/alternate model may be used to handle the first 20 in one way
and the second 10 in another. It is also possible to reload the EPIRPSTD0 register when it is finished
(and the EPIRPSTD1 register is active); thereby, keeping the interface constantly busy.
To cancel a non-blocking read, the EPIRPSTDn register is cleared. Care must be taken, however
if the register set was active to drain away any values read into the NBRFIFO and ensure that any
read in progress is allowed to complete.
To ensure that the cancel is complete, the following algorithm is used (using the EPIRPSTD0 register
for example):
EPIRPSTD0 = 0;
while ((EPISTAT & 0x11) == 0x10)
; // we are active and busy
// if here, then other one is active or interface no longer busy
cnt = (EPIRADDR0 – original_address) / EPIRSIZE0; // count of values read
cnt -= values_read_so_far;
// cnt is now number left in FIFO
while (cnt--)
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value = EPIREADFIFO; // drain
The above algorithm can be optimized in code; however, the important point is to wait for the cancel
to complete because the external interface could have been in the process of reading a value when
the cancel came in, and it must be allowed to complete.
10.3.2
DMA Operation
The µDMA can be used to efficiently transfer data from and to the NBRFIFO and the WFIFO. The
µDMA has one channel for write and one for read. The write channel copies values to the WFIFO
when the WFIFO is at the level specified by the EPI FIFO Level Selects (EPIFIFOLVL) register.
The non-blocking read channel copies values from the NBRFIFO when the NBRFIFO is at the level
specified by the EPIFIFOLVL register. For non-blocking reads, the start address, the size per
transaction, and the count of elements must be programmed in the µDMA. Note that both non-blocking
read register sets can be used, and they fill the NBRFIFO such that one runs to completion, then
the next one starts (they do not interleave).
For blocking reads, the µDMA software channel (or another unused channel) is used for
memory-to-memory transfers (or memory to peripheral, where some other peripheral is used). In
this situation, the µDMA stalls until the read is complete and is not able to service another channel
until the read is done. As a result, the arbitration size should normally be programmed to one access
at a time. The µDMA controller can also transfer from and to the NBRFIFO and the WFIFO using
the µDMA software channel in memory mode, however, the µDMA is stalled once the NBRFIFO is
empty or the WFIFO is full. Note that when the µDMA controller is stalled, the core continues
operation. See “Micro Direct Memory Access (μDMA)” on page 246 for more information on configuring
the µDMA.
10.4
Initialization and Configuration
To enable and initialize the EPI controller, the following steps are necessary:
1. Enable the EPI module using the RCGC1 register. See page 181.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register. See page 193. To
find out which GPIO port to enable, refer to Table 10-1 on page 362 or Table 10-2 on page 363.
3. Set the GPIO AFSEL bits for the appropriate pins. See page 328. To determine which GPIOs to
configure, see Table 25-4 on page 1151.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected. See
page 330 and page 338.
5. Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate
pins. See page 346 and Table 25-5 on page 1160.
6. Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the
MODE field in the EPI Configuration (EPICFG) register. Set the mode-specific details (if needed)
using the appropriate mode configuration EPI xxx Configuration (EPIxxxCFG) and EPI xxx
Configuration 2 (EPIxxxCFG2) registers. Set the EPI Main Baud Rate (EPIBAUD) register if
the baud rate must be slower than the system clock rate.
7. Configure the address mapping using the EPI Address Map (EPIADDRMAP) register. The
selected start address and range is dependent on the type of external device and maximum
address (as appropriate). For example, for a 512-megabit SDRAM, program the ERADR field to
0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program the ERSZ field to
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0x3 for 256 MB. If using General-Purpose mode and no address at all, program the EPADR field
to 0x1 for address 0xA000.0000 or 0x2 for address 0xC000.0000; and program the EPSZ field
to 0x0 for 256 bytes.
8. To read or write directly, use the mapped address area (configured with the EPIADDRMAP
register). Up to 4 or 5 writes can be performed at once without blocking. Each read is blocked
until the value is retrieved.
9. To perform a non-blocking read, see “Non-Blocking Reads” on page 365.
The following sub-sections describe the initialization and configuration for each of the modes of
operation. Care must be taken to initialize everything properly to ensure correct operation. Control
of the GPIO states is also important, as changes may cause the external device to interpret pin
states as actions or commands (see “Register Descriptions” on page 317). Normally, a pull-up or
®
pull-down is needed on the board to at least control the chip-select or chip-enable as the Stellaris
GPIOs come out of reset in tri-state.
10.4.1
SDRAM Mode
When activating the SDRAM mode, it is important to consider a few points:
1. Generally, it takes over 100 μs from when the mode is activated to when the first operation is
allowed. The SDRAM controller begins the SDRAM initialization sequence as soon as the mode
is selected and enabled via the EPICFG register. It is important that the GPIOs are properly
configured before the SDRAM mode is enabled, as the EPI controller is relying on the GPIO
block's ability to drive the pins immediately. As part of the initialization sequence, the LOAD
MODE REGISTER command is automatically sent to the SDRAM with a value of 0x27, which
sets a CAS latency of 2 and a full page burst length.
2. The INITSEQ bit in the EPI Status (EPISTAT) register can be checked to determine when the
initialization sequence is complete.
3. When using a frequency range and/or refresh value other than the default value, it is important
to configure the FREQ and RFSH fields in the EPI SDRAM Configuration (EPISDRAMCFG)
register shortly after activating the mode. After the 100-μs startup time, the EPI block must be
configured properly to keep the SDRAM contents stable.
4. The SLEEP bit in the EPISDRAMCFG register may be configured to put the SDRAM into a
low-power self-refreshing state. It is important to note that the SDRAM mode must not be
disabled once enabled, or else the SDRAM is no longer clocked and the contents are lost.
The SIZE field of the EPISDRAMCFG register must be configured correctly based on the amount
of SDRAM in the system.
The FREQ field must be configured according to the value that represents the range being used.
Based on the range selected, the number of external clocks used between certain operations (for
example, PRECHARGE or ACTIVATE) is determined. If a higher frequency is given than is used,
then the only downside is that the peripheral is slower (uses more cycles for these delays). If a lower
frequency is given, incorrect operation occurs.
See “External Peripheral Interface (EPI)” on page 1213 for timing details for the SDRAM mode.
10.4.1.1
External Signal Connections
Table 10-3 on page 368 defines how EPI module signals should be connected to SDRAMs. The
table applies when using a x16 SDRAM up to 512 megabits. Note that the EPI signals must use
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8-mA drive when interfacing to SDRAM, see page 332. Any unused EPI controller signals can be
used as GPIOs or another alternate function.
Table 10-3. EPI SDRAM Signal Connections
a
EPI Signal
SDRAM Signal
EPI0S0
A0
D0
EPI0S1
A1
D1
EPI0S2
A2
D2
EPI0S3
A3
D3
EPI0S4
A4
D4
EPI0S5
A5
D5
EPI0S6
A6
D6
EPI0S7
A7
D7
EPI0S8
A8
D8
EPI0S9
A9
D9
EPI0S10
A10
D10
EPI0S11
A11
D11
EPI0S12
b
A12
D12
EPI0S13
BA0
D13
EPI0S14
BA1
D14
EPI0S15
D15
EPI0S16
DQML
EPI0S17
DQMH
EPI0S18
CASn
EPI0S19
RASn
EPI0S20-EPI0S27
not used
EPI0S28
WEn
EPI0S29
CSn
EPI0S30
CKE
EPI0S31
CLK
a. If 2 signals are listed, connect the EPI signal to both pins.
b. Only for 256/512 megabit SDRAMs
10.4.1.2
Refresh Configuration
The refresh count is based on the external clock speed and the number of rows per bank as well
as the refresh period. The RFSH field represents how many external clock cycles remain before an
AUTO-REFRESH is required. The normal formula is:
RFSH = (tRefresh_us / number_rows) / ext_clock_period
A refresh period is normally 64 ms, or 64000 μs. The number of rows is normally 4096 or 8192. The
ext_clock_period is a value expressed in μsec and is derived by dividing 1000 by the clock speed
expressed in MHz. So, 50 MHz is 1000/50=20 ns, or 0.02 μs. A typical SDRAM is 4096 rows per
bank if the system clock is running at 50 MHz with an EPIBAUD register value of 0:
RFSH = (64000/4096) / 0.02 = 15.625 μs / 0.02 μs = 781.25
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The default value in the RFSH field is 750 decimal or 0x2EE to allow for a margin of safety and
providing 15 μs per refresh. It is important to note that this number should always be smaller or
equal to what is required by the above equation. For example, if running the external clock at 25
MHz (40 ns per clock period), 390 is the highest number that may be used. Note that the external
clock may be 25 MHz when the system clock is 25 MHz or when the system clock is 50 MHz and
configuring the COUNT0 field in the EPIBAUD register to 1 (divide by 2).
If a number larger than allowed is used, the SDRAM is not refreshed often enough, and data is lost.
10.4.1.3
Bus Interface Speed
The EPI Controller SDRAM interface can operate up to 50 MHz. The COUNT0 field in the EPIBAUD
register configures the speed of the EPI clock. For system clock (SysClk) speeds up to 50 MHz, the
COUNT0 field can be 0x0000, and the SDRAM interface can run at the same speed as SysClk.
However, if SysClk is running at higher speeds, the bus interface can run only as fast as half speed,
and the COUNT0 field must be configured to at least 0x0001.
10.4.1.4
Non-Blocking Read Cycle
Figure 10-2 on page 369 shows a non-blocking read cycle of n halfwords; n can be any number
greater than or equal to 1. The cycle begins with the Activate command and the row address on the
EPI0S[15:0] signals. With the programmed CAS latency of 2, the Read command with the column
address on the EPI0S[15:0] signals follows after 2 clock cycles. Following one more NOP cycle,
data is read in on the EPI0S[15:0] signals on every rising clock edge. The Burst Terminate
command is issued during the cycle when the next-to-last halfword is read in. The DQMH and DQML
signals are deasserted after the last halfword of data is received; the CSn signal deasserts on the
following clock cycle, signaling the end of the read cycle. At least one clock period of inactivity
separates any two SDRAM cycles.
Figure 10-2. SDRAM Non-Blocking Read Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
Column
NOP
NOP
Read
Data 0
Data 1
...
Data n
Burst
Term
NOP
AD [15:0] driven in
AD [15:0] driven out
10.4.1.5
AD [15:0] driven out
Normal Read Cycle
Figure 10-3 on page 370 shows a normal read cycle of n halfwords; n can be 1 or 2. The cycle begins
with the Activate command and the row address on the EPI0S[15:0] signals. With the programmed
CAS latency of 2, the Read command with the column address on the EPI0S[15:0] signals follows
after 2 clock cycles. Following one more NOP cycle, data is read in on the EPI0S[15:0] signals
on every rising clock edge. The DQMH, DQML, and CSn signals are deasserted after the last
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halfword of data is received, signaling the end of the cycle. At least one clock period of inactivity
separates any two SDRAM cycles.
Figure 10-3. SDRAM Normal Read Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Column
Activate
NOP
NOP
Read
Data 0
Data 1
NOP
AD [15:0] driven in
AD [15:0] driven out
10.4.1.6
AD [15:0] driven out
Write Cycle
Figure 10-4 on page 371 shows a write cycle of n halfwords; n can be any number greater than or
equal to 1. The cycle begins with the Activate command and the row address on the EPI0S[15:0]
signals. With the programmed CAS latency of 2, the Write command with the column address on
the EPI0S[15:0] signals follows after 2 clock cycles. When writing to SDRAMs, the Write command
is presented with the first halfword of data. Because the address lines and the data lines are
multiplexed, the column address is modified to be (programmed address -1). During the Write
command, the DQMH and DQML signals are high, so no data is written to the SDRAM. On the next
clock, the DQMH and DQML signals are asserted, and the data associated with the programmed
address is written. The Burst Terminate command occurs during the clock cycle following the write
of the last halfword of data. The WEn, DQMH, DQML, and CSn signals are deasserted after the
last halfword of data is received, signaling the end of the access. At least one clock period of inactivity
separates any two SDRAM cycles.
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Figure 10-4. SDRAM Write Cycle
CLK
(EPI0S31)
CKE
(EPI0S30)
CSn
(EPI0S29)
WEn
(EPI0S28)
RASn
(EPI0S19)
CASn
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Row
Activate
Column-1
NOP
NOP
Data 0
Data 1
...
Data n
Burst
Term
Write
AD [15:0] driven out
AD [15:0] driven out
10.4.2
Host Bus Mode
Host Bus supports the traditional 8-bit and 16-bit interfaces popularized by the 8051devices and
SRAM devices. This interface is asynchronous and uses strobe pins to control activity.
10.4.2.1
Control Pins
The main three strobes are ALE (Address latch enable), WRn (write), and RDn (sometimes called
OEn, used for read). Note that the timings are designed for older logic and so are hold-time vs.
setup-time specific. To ensure proper operation on this bus, the EPI block uses two system clocks
per transition to allow significant skewing of control vs. data signals. So, for example, ALE rises one
EPI clock before ADDR/DATA is asserted. Likewise, ALE falls (latch point) one EPI clock before
DATA changes or tri-states. The same approach is used for the WRn and RDn/OEn strobes. The
polarity of the read and write strobes can be active high or active low by clearing or setting the
RDHIGH and WRHIGH bits in the EPI Host-Bus n Configuration 2 (EPIHBnCFG2) register.
The ALE can be changed to an active-low chip select signal, CSn, through the EPIHBnCFG2 register.
The ALE is best used for Host-Bus muxed mode in which EPI address and data pins are shared.
All Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an
external latch to capture the address then hold it until the data phase. CSn is best used for Host-Bus
unmuxed mode in which EPI address and data pins are separate. The CSn indicates when the
address and data phases of a read or write access is occurring. Both the ALE and the CSn modes
can be enhanced to access two external devices using settings in the EPIHBnCFG2 register. Wait
states can be added to the data phase of the access using the WRWS and RDWS bits in the
EPIHBnCFG2 register.
For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and
output to what the XFIFO can handle.
Host-Bus 8 and Host-Bus 16 modes are very configurable. The user has the ability to connect 1 or
2 external devices to the EPI signals as well as control whether byte select signals are provided in
HB16 mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG
register, the CSCFG field in the EPIHBnCFG2 register, and the BSEL bit in the EPIHB16CFG register.
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If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in the EPIHBnCFG2 register),
both chip selects can share the peripheral or the memory space, or one chip select can use the
peripheral space and the other can use the memory space. In the EPIADDRMAP register, if the
EPADR field is not 0x0 and the ERADR field is 0x0, then the address specified by EPADR is used for
both chip selects, with CS0n being asserted when the MSB of the address range is 0 and CS1n
being asserted when the MSB of the address range is 1. If the ERADR field is not 0x0 and the EPADR
field is 0x0, then the address specified by ERADR is used for both chip selects, with the MSB
performing the same delineation. If both the EPADR and the ERADR are not 0x0, then CS0n is asserted
for the address range defined by EPADR and CS1n is asserted for the address range defined by
ERADR. If the CSBAUD bit in the EPIHBnCFG2 register is set, the 2 chip selects can use different
clock frequencies. If the CSBAUD bit is clear, both chip selects use the clock frequency, wait states,
and strobe polarity defined for CS0n.
When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data
can be read and written at any address, however these signals reduce the available address width
by 2 pins. The byte select signals are active low. BSEL0n corresponds to the LSB of the halfword,
and BSEL1n corresponds to the MSB of the halfword.
When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes
at even addresses write invalid values into the odd byte. As a result, accesses should be made as
half-words (16-bits) or words (32-bits). In C/C++, programmers should use only short int and long
int for accesses. Also, because data accesses in HB16 mode with no byte selects are on 2-byte
boundaries, the available address space is doubled. For example, 28 bits of address accesses 512
MB in this mode. Table 10-4 on page 372 shows the capabilities of the HB8 and HB16 modes as
well as the available address bits with the possible combinations of these bits.
Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not
required and should be configured as a GPIO to reduce EMI in the system.
Table 10-4. Capabilities of Host Bus 8 and Host Bus 16 Modes
Host Bus Type
MODE
CSCFG
Max # of
External
Devices
BSEL
Byte Access
Available Address
HB8
0x0
0x0, 0x1
1
N/A
Always
28 bits
HB8
0x0
0x2
2
N/A
Always
27 bits
HB8
0x0
0x3
2
N/A
Always
26 bits
HB8
0x1
0x0, 0x1
1
N/A
Always
20 bits
HB8
0x1
0x2
2
N/A
Always
19 bits
HB8
0x1
0x3
2
N/A
Always
18 bits
HB8
0x3
0x1
1
N/A
Always
none
HB8
0x3
0x3
2
N/A
Always
none
HB16
0x0
0x0, 0x1
1
0
No
28 bits
HB16
0x0
0x0, 0x1
1
1
Yes
26 bits
HB16
0x0
0x2
2
0
No
27 bits
HB16
0x0
0x2
2
1
Yes
25 bits
HB16
0x0
0x3
2
0
No
26 bits
HB16
0x0
0x3
2
1
Yes
24 bits
HB16
0x1
0x0, 0x1
1
0
No
12 bits
HB16
0x1
0x0, 0x1
1
1
Yes
10 bits
HB16
0x1
0x2
2
0
No
11 bits
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Table 10-4. Capabilities of Host Bus 8 and Host Bus 16 Modes (continued)
Host Bus Type
MODE
CSCFG
Max # of
External
Devices
BSEL
Byte Access
Available Address
HB16
0x1
0x2
2
1
Yes
9 bits
HB16
0x1
0x3
2
0
No
10 bits
HB16
0x1
0x3
2
1
Yes
8 bits
HB16
0x3
0x1
1
0
No
none
HB16
0x3
0x1
1
1
Yes
none
HB16
0x3
0x3
2
0
No
none
HB16
0x3
0x3
2
1
Yes
none
a
a. If byte selects are not used, data accesses are on 2-byte boundaries. As a result, the available address space is doubled.
Table 10-5 on page 373 shows how the EPI[31:0] signals function while in Host-Bus 8 mode.
Notice that the signal configuration changes based on the address/data mode selected by the MODE
field in the EPIHB8CFG2 register and on the chip select configuration selected by the CSCFG field
in the same register. Any unused EPI controller signals can be used as GPIOs or another alternate
function.
Table 10-5. EPI Host-Bus 8 Signal Connections
EPI Signal
CSCFG
HB8 Signal (MODE
=ADMUX)
HB8 Signal (MODE
=ADNOMUX (Cont.
Read))
HB8 Signal (MODE
=XFIFO)
EPI0S0
X
a
AD0
D0
D0
EPI0S1
X
AD1
D1
D1
EPI0S2
X
AD2
D2
D2
EPI0S3
X
AD3
D3
D3
EPI0S4
X
AD4
D4
D4
EPI0S5
X
AD5
D5
D5
EPI0S6
X
AD6
D6
D6
EPI0S7
X
AD7
D7
D7
EPI0S8
X
A8
A0
-
EPI0S9
X
A9
A1
-
EPI0S10
X
A10
A2
-
EPI0S11
X
A11
A3
-
EPI0S12
X
A12
A4
-
EPI0S13
X
A13
A5
-
EPI0S14
X
A14
A6
-
EPI0S15
X
A15
A7
-
EPI0S16
X
A16
A8
-
EPI0S17
X
A17
A9
-
EPI0S18
X
A18
A10
-
EPI0S19
X
A19
A11
-
EPI0S20
X
A20
A12
-
EPI0S21
X
A21
A13
-
EPI0S22
X
A22
A14
-
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Table 10-5. EPI Host-Bus 8 Signal Connections (continued)
EPI Signal
CSCFG
HB8 Signal (MODE
=ADMUX)
HB8 Signal (MODE
=ADNOMUX (Cont.
Read))
HB8 Signal (MODE
=XFIFO)
EPI0S23
X
A23
A15
-
EPI0S24
X
A24
A16
-
b
A17
0x0
-
0x1
EPI0S25
A25
0x2
CS1n
0x3
-
0x0
0x1
EPI0S26
A26
A18
CS0n
CS0n
A27
A19
CSn1
CSn1
FEMPTY
0x2
0x3
0x0
0x1
EPI0S27
0x2
FFULL
0x3
EPI0S28
X
RDn/OEn
RDn/OEn
RDn
EPI0S29
X
WRn
WRn
WRn
EPI0S30
EPI0S31
0x0
ALE
ALE
-
0x1
CSn
CSn
CSn
0x2
CS0n
CS0n
CS0n
0x3
ALE
ALE
-
c
X
Clock
c
Clock
c
Clock
a. "X" indicates the state of this field is a don't care.
b. When an entry straddles several row, the signal configuration is the same for all rows.
c. The clock signal is not required for this mode and has unspecified timing relationships to other signals.
Table 10-6 on page 374 shows how the EPI[31:0] signals function while in Host-Bus 16 mode.
Notice that the signal configuration changes based on the address/data mode selected by the MODE
field in the EPIHB16CFG2 register, on the chip select configuration selected by the CSCFG field in
the same register, and on whether byte selects are used as configured by the BSEL bit in the
EPIHB16CFG register. Any unused EPI controller signals can be used as GPIOs or another alternate
function.
Table 10-6. EPI Host-Bus 16 Signal Connections
EPI Signal
CSCFG
BSEL
HB16 Signal (MODE
=ADMUX)
HB16 Signal (MODE
=ADNOMUX (Cont.
Read))
HB16 Signal
(MODE =XFIFO)
EPI0S0
X
a
X
AD0
D0
D0
EPI0S1
X
X
AD1
D1
D1
EPI0S2
X
X
AD2
D2
D2
EPI0S3
X
X
AD3
D3
D3
EPI0S4
X
X
AD4
D4
D4
EPI0S5
X
X
AD5
D5
D5
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Table 10-6. EPI Host-Bus 16 Signal Connections (continued)
EPI Signal
CSCFG
BSEL
HB16 Signal (MODE
=ADMUX)
HB16 Signal (MODE
=ADNOMUX (Cont.
Read))
HB16 Signal
(MODE =XFIFO)
EPI0S6
X
X
AD6
D6
D6
EPI0S7
X
X
AD7
D7
D7
EPI0S8
X
X
AD8
D8
D8
EPI0S9
X
X
AD9
D9
D9
EPI0S10
X
X
AD10
D10
D10
EPI0S11
X
X
AD11
D11
D11
EPI0S12
X
X
AD12
D12
D12
EPI0S13
X
X
AD13
D13
D13
EPI0S14
X
X
AD14
D14
D14
D15
EPI0S15
X
X
AD15
D15
EPI0S16
X
X
A16
A0
b
-
EPI0S17
X
X
A17
A1
-
EPI0S18
X
X
A18
A2
-
EPI0S19
X
X
A19
A3
-
EPI0S20
X
X
A20
A4
-
EPI0S21
X
X
A21
A5
-
EPI0S22
X
X
A22
A6
-
c
0
A23
A7
-
A24
A8
1
BSEL0n
BSEL0n
X
A25
A9
-
0x2
0
A25
A9
CS1n
1
BSEL0n
BSEL0n
0x3
0
A25
A9
EPI0S23
X
0x0
0x1
EPI0S24
1
0
1
0
1
0x2
0
-
1
0x3
0x0
0x1
EPI0S25
0x0
0x1
EPI0S26
0x2
0x3
0
1
BSEL1n
BSEL1n
0
A26
A10
1
BSEL0n
BSEL0n
0
A26
A10
1
BSEL0n
BSEL0n
0
A26
A10
1
BSEL1n
BSEL1n
X
CS0n
CS0n
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Table 10-6. EPI Host-Bus 16 Signal Connections (continued)
EPI Signal
CSCFG
0x0
EPI0S27
EPI0S28
EPI0S29
EPI0S30
EPI0S31
0x1
BSEL
HB16 Signal (MODE
=ADMUX)
HB16 Signal (MODE
=ADNOMUX (Cont.
Read))
0
A27
A11
1
BSEL1n
BSEL1n
HB16 Signal
(MODE =XFIFO)
0
A27
A11
1
BSEL1n
BSEL1n
0x2
X
CS1n
CS1n
0x3
X
X
X
RDn/OEn
RDn/OEn
RDn
FFULL
X
X
WRn
WRn
WRn
0x0
X
ALE
ALE
-
0x1
X
CSn
CSn
CSn
0x2
X
CS0n
CS0n
CS0n
0x3
X
ALE
X
X
Clock
ALE
d
d
Clock
d
Clock
a. "X" indicates the state of this field is a don't care.
b. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address.
c. When an entry straddles several row, the signal configuration is the same for all rows.
d. The clock signal is not required for this mode and has unspecified timing relationships to other signals.
10.4.2.2
Speed of Transactions
The COUNT0 field in the EPIBAUD register must be configured to set the main transaction rate
based on what the slave device can support (including wiring considerations). The main control
transitions are normally ½ the baud rate (COUNT0 = 1) because the EPI block forces data vs. control
to change on alternating clocks. When using dual chip-selects, each chip select can access the bus
using differing baud rates by setting the CSBAUD bit in the EPIHBnCFG2 register. In this case, the
COUNT0 field controls the CS0n transactions, and the COUNT1 field controls the CS1n transactions.
Additionally, the Host-Bus mode provides read and write wait states for the data portion to support
different classes of device. These wait states stretch the data period (hold the rising edge of data
strobe) and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS
bits in the EPI Host-Bus n Configuration (EPIHBnCFG) register.
10.4.2.3
Sub-Modes of Host Bus 8/16
The EPI controller supports four variants of the Host-Bus model using 8 or 16 bits of data in all four
cases. The four sub-modes are selected using the MODE bits in the EPIHBnCFG register, and are:
1. Address and data are muxed. This scheme is used by many 8051 devices, some Microchip PIC
parts, and some ATmega parts. When used for standard SRAMs, a latch must be used between
the microcontroller and the SRAM. This sub-mode is provided for compatibility with existing
devices that support data transfers without a latch (for example, LCD controllers or CPLDs). In
general, the de-muxed sub-mode should normally be used. The ALE configuration should be
used in this mode, as all Host-Bus accesses have an address phase followed by a data phase.
The ALE indicates to an external latch to capture the address then hold until the data phase.
The ALE configuration is controlled by configuring the CSCFG field to be 0x0 in the EPIHBnCFG2
register. The ALE can be enhanced to access two external devices with the addition of two
separate CSn signals. By configuring the CSCFG field in the to be 0x3 in the EPIHBnCFG2
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register, EPI0S30 functions as ALE, EPI0S27 functions as CS1n, and EPI0S26 functions as
CS0n. The CSn is best used for Host-Bus unmuxed mode which EPI address and data pins
are separate. The CSn indicates when the address and data phases of a read or write access
are occurring.
2. Address and data are separate with 8 or 16 bits of data and up to 20 bits of address (1 MB).
This scheme is used by more modern 8051 devices, as well as some PIC and ATmega parts.
This mode is generally used with real SRAMs, many EEPROMs, and many NOR Flash memory
devices. Note that there is no hardware command write support for Flash memory devices; this
mode should only be used for Flash memory devices programmed at manufacturing time. If a
Flash memory device must be written and does not support a direct programming model, the
command mechanism must be performed in software. The CSn configuration should be used
in this mode. The CSn signal indicates when the address and data phases of a read or write
access is occurring. The CSn configuration is controlled by configuring the CSCFG field to be
0x1 in the EPIHBnCFG2 register.
3. Continuous read mode where address and data are separate. This sub-mode is used for real
SRAMs which can be read more quickly by only changing the address (and not using RDn/OEn
strobing). In this sub-mode, reads are performed by keeping the read mode selected (output
enable is asserted) and then changing the address pins. The data pins are changed by the
SRAM after the address pins change. For example, to read data from address 0x100 and then
0x101, the EPI controller asserts the output-enable signal and then configures the address pins
to 0x100; the EPI controller then captures what is on the data pins and increments A0 to 1 (so
the address is now 0x101); the EPI controller then captures what is on the data pins. Note that
this mode consumes higher power because the SRAM must continuously drive the data pins.
This mode is not practical in HB16 mode for normal SRAMs because there are generally not
enough address bits available.
4. FIFO mode uses 8 or 16 bits of data, removes ALE and address pins and optionally adds external
XFIFO FULL/EMPTY flag inputs. This scheme is used by many devices, such as radios,
communication devices (including USB2 devices), and some FPGA configurations (FIFO through
block RAM). This sub-mode provides the data side of the normal Host-Bus interface, but is
paced by the FIFO control signals. It is important to consider that the XFIFO FULL/EMPTY
control signals may stall the interface and could have an impact on blocking read latency from
the processor or μDMA.
The WORD bit in the EPIHBnCFG2 register can be set to use memory more efficiently. By default,
the EPI controller uses data bits [7:0] for Host-Bus 8 accesses or bits [15:0] for Host-Bus 16 accesses.
When the WORD bit is set, the EPI controller can automatically route bytes of data onto the correct
byte lanes such that data can be stored in bits [31:8] (HB8) or [31:16] (HB16). In addition, for the
three modes above (1, 2, 4) that the Host-Bus 16 mode supports, byte select signals can be optionally
implemented by setting the BSEL bit in the EPIHB16CFG register.
See “External Peripheral Interface (EPI)” on page 1213 for timing details for the Host-Bus mode.
10.4.2.4
Bus Operation
Bus operation is the same in Host-Bus 8 and Host-Bus 16 modes and is asynchronous. Timing
diagrams show both ALE and CSn operation, but only one signal or the other is used in all modes
except for ALE with dual chip selects mode (CSCFG field is 0x3 in the EPIHBnCFG2 register).
Address and data on write cycles are held after the CSn signal is deasserted. The optional HB16
byte select signals have the same timing as the address signals. If wait states are required in the
bus access, they can be inserted during the data phase of the access using the WRWS and RDWS
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bits in the EPIHBnCFG2 register. Each wait state adds 2 EPI clock cycles to the duration of the
WRn or RDn strobe.
Figure 10-5 on page 378 shows a basic Host-Bus read cycle. Figure 10-6 on page 378 shows a basic
Host-Bus write cycle. Both of these figures show address and data signals in the non-multiplexed
mode (MODE field ix 0x1 in the EPIHBnCFG register).
Figure 10-5. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1na
Address
Data
a
Data
BSEL0n and BSEL1n are available in Host-Bus 16 mode only.
Figure 10-6. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1na
Address
Data
a
Data
BSEL0n and BSEL1n are available in Host-Bus 16 mode only.
Figure 10-7 on page 379 shows a write cycle with the address and data signals multiplexed (MODE
field is 0x0 in the EPIHBnCFG register). A read cycle would look similar, with the RDn strobe being
asserted along with CSn and data being latched on the rising edge of RDn.
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Figure 10-7. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH = 1, RDHIGH
=1
ALE
(EPI0S30)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn/OEn
(EPI0S28)
BSEL0n/
BSEL1na
Address
(high order, non muxed)
Muxed
Address/Data
a
Address
Data
BSEL0n and BSEL1n are available in Host-Bus 16 mode only.
Figure 10-8 on page 379 shows continuous read mode accesses. In this mode, reads are performed
by keeping the read mode selected (output enable is asserted) and then changing the address pins.
The data pins are changed by the SRAM after the address pins change.
Figure 10-8. Continuous Read Mode Accesses
OEn
Address
Data
Addr1
Data1
Addr2
Data2
Addr3
Data3
FIFO mode accesses are the same as normal read and write accesses, except that the ALE signal
and address pins are not present. Two input signals can be used to indicate when the XFIFO is full
or empty to gate transactions and avoid overruns and underruns. The FFULL and FEMPTY signals
are synchronized and must be recognized as asserted by the microcontroller for 2 system clocks
before they affect transaction status. The MAXWAIT field in the EPIHBnCFG register defines the
maximum number of EPI clocks to wait while the FEMPTY or FFULL signal is holding off a transaction.
Figure 10-9 on page 380 shows how the FEMPTY signal should respond to a write and read from
the XFIFO. Figure 10-10 on page 380 shows how the FEMPTY and FFULL signals should respond
to 2 writes and 1 read from an external FIFO that contains two entries.
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Figure 10-9. Write Followed by Read to External FIFO
FFULL
(EPI0S27)
FEMPTY
(EPI0S26)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn
(EPI0S28)
Data
Data
Data
Figure 10-10. Two-Entry FIFO
FFULL
(EPI0S27)
FEMPTY
(EPI0S26)
CSn
(EPI0S30)
WRn
(EPI0S29)
RDn
(EPI0S28)
Data
10.4.3
Data
Data
Data
General-Purpose Mode
The General-Purpose Mode Configuration (EPIGPCFG) register is used to configure the control,
data, and address pins, if used. Any unused EPI controller signals can be used as GPIOs or another
alternate function. The general-purpose configuration can be used for custom interfaces with FPGAs,
CPLDs, and digital data acquisition and actuator control.
Important: The RD2CYC bit in the EPIGPCFG register must be set at all times in General-Purpose
mode to ensure proper operation.
General-Purpose mode is designed for three general types of use:
■ Extremely high-speed clocked interfaces to FPGAs and CPLDs. Three sizes of data and optional
address are supported. Framing and clock-enable functions permit more optimized interfaces.
■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely
controlled by the EPIBAUD register baud rate (when used with the WFIFO and/or the NBRFIFO)
or by the rate of accesses from software or μDMA. Examples of this type of use include:
– Reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the
COUNT0 field in the EPIBAUD register to some divider, and then using non-blocking reads.
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– Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators, LEDs,
etc.
– Implementing SDIO 4-bit mode where commands are driven or captured on 6 pins with fixed
timing, fed by the µDMA.
■ General custom interfaces of any speed.
The configuration allows for choice of an output clock (free-running or gated), a framing signal (with
frame size), a ready input (to stretch transactions), a read and write strobe, an address (of varying
sizes), and data (of varying sizes). Additionally, provisions are made for separating data and address
phases.
The interface has the following optional features:
■ Use of the EPI clock output is controlled by the CLKPIN bit in the EPIGPCFG register. Unclocked
uses include general-purpose I/O and asynchronous interfaces (optionally using RD and WR
strobes). Clocked interfaces allow for higher speeds and are much easier to connect to FPGAs
and CPLDs (which usually include input clocks).
■ EPI clock, if used, may be free running or gated depending on the CLKGATE bit in the EPIGPCFG
register. A free-running EPI clock requires another method for determining when data is live,
such as the frame pin or RD/WR strobes. A gated clock approach uses a setup-time model in
which the EPI clock controls when transactions are starting and stopping. The gated clock is
held high until a new transaction is started and goes high at the end of the cycle where
RD/WR/FRAME and address (and data if write) are emitted.
■ Use of the ready input (iRDY) from the external device is controlled by the RDYEN bit in the
EPIGPCFG register. The iRDY signal uses EPI0S27 and may only be used with a free-running
clock. iRDY gates transactions, no matter what state they are in. When iRDY is deasserted, the
transaction is held off from completing.
■ Use of the frame output (FRAME) is controlled by the FRMPIN bit in the EPIGPCFG register.
The frame pin may be used whether the clock is output or not, and whether the clock is free
running or not. It may also be used along with the iRDY signal. The frame may be a pulse (one
clock) or may be 50/50 split across the frame size (controlled by the FRM50 bit in the EPIGPCFG
register). The frame count (the size of the frame as specified by the FRMCNT field in the
EPIGPCFG register) may be between 1 and 15 clocks for pulsed and between 2 and 30 clocks
for 50/50. The frame pin counts transactions and not clocks; a transaction is any clock where
the RD or WR strobe is high (if used). So, if the FRMCNT bit is set, then the frame pin pulses
every other transaction; if 2-cycle reads and writes are used, it pulses every other address phase.
FRM50 must be used with this in mind as it may hold state for many clocks waiting for the next
transaction.
■ Use of the RD and WR outputs is controlled by the RW bit in the EPIGPCFG register. For interfaces
where the direction is known (in advance, related to frame size, or other means), these strobes
are not needed. For most other interfaces, RD and WR are used so the external peripheral knows
what transaction is taking place, and if any transaction is taking place.
■ Separation of address/request and data phases may be used on writes using the WR2CYC bit in
the EPIGPCFG register. This configuration allows the external peripheral extra time to act.
Address and data phases must be separated on reads, and the RD2CYC bit in the EPIGPCFG
register must be set. When configured to use an address as specified by the ASIZE field in the
EPIGPCFG register, the address is emitted on the with the RD strobe (first cycle) and data is
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expected to be returned on the next cycle (when RD is not asserted). If no address is used, then
RD is asserted on the first cycle and data is captured on the second cycle (when RD is not
asserted), allowing more setup time for data.
For writes, the output may be in one or two cycles. In the two-cycle case, the address (if any) is
emitted on the first cycle with the WR strobe and the data is emitted on the second cycle (with
WR not asserted). Although split address and write data phases are not normally needed for
logic reasons, it may be useful to make read and write timings match. If 2-cycle reads or writes
are used, the RW bit is automatically set.
■ Address may be emitted (controlled by the ASIZE field in the EPIGPCFG register). The address
may be up to 4 bits (16 possible values), up to 12 bits (4096 possible values), or up to 20 bits
(1 M possible values). Size of address limits size of data, for example, 4 bits of address support
up to 24 bits data. 4-bit address uses EPI0S[27:24]; 12-bit address uses EPI0S[27:16];
20-bit address uses EPI0S[27:8]. The address signals may be used by the external peripheral
as an address, code (command), or for other unrelated uses (such as a chip enable). If the
chosen address/data combination does not use all of the EPI signals, the unused pins can be
used as GPIOs or for other functions. For example, when using a 4-bit address with an 8-bit
data, the pins assigned to EPIS0[23:8] can be assigned to other functions.
■ Data may be 8 bits, 16 bits, 24 bits, or 32 bits (controlled by the DSIZE field in the EPIGPCFG
register). 32-bit data cannot be used with address or EPI clock or any other signal. 24-bit data
can only be used with 4-bit address or no address. 32-bit data requires that either the WR2CYC
bit or the RD2CYC bit in the EPIGPCFG register is set.
■ Memory can be used more efficiently by using the Word Access Mode. By default, the EPI
controller uses data bits [7:0] when the DSIZE field in the EPIGPCFG register is 0x0; data bits
[15:0] when the DSIZE field is 0x1; data bits [23:0] when the DSIZE field is 0x2; and data bits
[31:0] when the DSIZE field is 0x3. When the WORD bit in the EPIGPCFG2 register is set, the
EPI controller automatically routes bytes of data onto the correct byte lanes such that data can
be stored in bits [31:8] for DSIZE=0x0 and bits [31:16] for DSIZE=0x1.
■ When using the EPI controller as a GPIO interface, writes are FIFOed (up to 4 can be held at
any time), and up to 32 pins are changed using the EPIBAUD clock rate specified by COUNT0.
As a result, output pin control can be very precisely controlled as a function of time. By contrast,
when writing to normal GPIOs, writes can only occur 8-bits at a time and take up to two clock
cycles to complete. In addition, the write itself may be further delayed by the bus due to μDMA
or draining of a previous write. With both GPIO and the EPI controller, reads may be performed
directly, in which case the current pin states are read back. With the EPI controller, the
non-blocking interface may also be used to perform reads based on a fixed time rule via the
EPIBAUD clock rate.
Table 10-7 on page 382 shows how the EPI0S[31:0] signals function while in General-Purpose
mode. Notice that the address connections vary depending on the data-width restrictions of the
external peripheral.
Table 10-7. EPI General Purpose Signal Connections
EPI Signal
General-Purpose
Signal (D8, A20)
General- Purpose
Signal (D16, A12)
General- Purpose
Signal (D24, A4)
General- Purpose
Signal (D32)
EPI0S0
D0
D0
D0
D0
EPI0S1
D1
D1
D1
D1
EPI0S2
D2
D2
D2
D2
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Table 10-7. EPI General Purpose Signal Connections (continued)
EPI Signal
General-Purpose
Signal (D8, A20)
General- Purpose
Signal (D16, A12)
General- Purpose
Signal (D24, A4)
General- Purpose
Signal (D32)
EPI0S3
D3
D3
D3
D3
EPI0S4
D4
D4
D4
D4
EPI0S5
D5
D5
D5
D5
EPI0S6
D6
D6
D6
D6
EPI0S7
D7
D7
D7
D7
EPI0S8
A0
D8
D8
D8
EPI0S9
A1
D9
D9
D9
EPI0S10
A2
D10
D10
D10
EPI0S11
A3
D11
D11
D11
EPI0S12
A4
D12
D12
D12
EPI0S13
A5
D13
D13
D13
EPI0S14
A6
D14
D14
D14
EPI0S15
A7
D15
D15
D15
EPI0S16
A8
A0
a
D16
D16
EPI0S17
A9
A1
D17
D17
EPI0S18
A10
A2
D18
D18
EPI0S19
A11
A3
D19
D19
EPI0S20
A12
A4
D20
D20
EPI0S21
A13
A5
D21
D21
EPI0S22
A14
A6
D22
D22
EPI0S23
A15
A7
D23
D23
EPI0S24
A16
A8
A0
b
D24
EPI0S25
A17
A9
A1
D25
EPI0S26
A18
A10
A2
D26
EPI0S27
A19/iRDY
A11/iRDY
A3/iRDY
c
c
c
D27
EPI0S28
WR
WR
WR
D28
EPI0S29
RD
RD
RD
D29
EPI0S30
Frame
Frame
Frame
D30
EPI0S31
Clock
Clock
Clock
D31
a. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address.
b. In this mode, word accesses are used. AO is the LSB of the address and is equivalent to the system A2 address.
c. This signal is iRDY if the RDYEN bit in the EPIGPCFG register is set.
10.4.3.1
Bus Operation
A basic access is 1 EPI clock for write cycles and 2 EPI clocks for read cycles. An additional EPI
clock can be inserted into a write cycle by setting the WR2CYC bit in the EPIGPCFG register. Note
that the RD2CYC bit must always be set in the EPIGPCFG register. If the iRDY signal is deasserted,
further transactions are held off until the iRDY signal is asserted again.
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Figure 10-11. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0
Clock
(EPI0S31)
Frame
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Address
Data
Data
Figure 10-12. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1, WRCYC=1
CLOCK
(EPI0S31)
FRAME
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Address
Data
Data
Read
Data
Write
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Figure 10-13. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1
CLOCK
(EPI0S31)
FRAME
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Addr1
Address
Addr2
Data1
Data
Addr3
Data2
Data3
FRAME Signal Operation
The operation of the FRAME signal is controlled by the FRMCNT and FRM50 bits. When FRM50 is
clear, the FRAME signal is high whenever the WR or RD strobe is high. When FRMCNT is clear, the
FRAME signal is simply the logical OR of the WR and RD strobes so the FRAME signal is high during
every read or write access, see Figure 10-14 on page 385.
Figure 10-14. FRAME Signal Operation, FRM50=0 and FRMCNT=0
Clock
(EPI0S31)
WR
(EPI0S28)
RD
(EPI0S29)
Frame
(EPI0S30)
If the FRMCNT field is 0x1, then the FRAME signal pulses high during every other read or write
access, see Figure 10-15 on page 385.
Figure 10-15. FRAME Signal Operation, FRM50=0 and FRMCNT=1
Clock
(EPI0S31)
WR
(EPI0S28)
RD
(EPI0S29)
Frame
(EPI0S30)
If the FRMCNT field is 0x2 and FRM50 is clear, then the FRAME signal pulses high during every third
access, and so on for every value of FRMCNT, see Figure 10-16 on page 386.
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Figure 10-16. FRAME Signal Operation, FRM50=0 and FRMCNT=2
Clock
(EPI0S31)
WR
(EPI0S28)
RD
(EPI0S29)
Frame
(EPI0S30)
When FRM50 is set, the FRAME signal transitions on the rising edge of either the WR or RD strobes.
When FRMCNT=0, the FRAME signal transitions on the rising edge of WR or RD for every access,
see Figure 10-17 on page 386.
Figure 10-17. FRAME Signal Operation, FRM50=1 and FRMCNT=0
Clock
(EPI0S31)
WR
(EPI0S28)
RD
(EPI0S29)
Frame
(EPI0S30)
When FRMCNT=1, the FRAME signal transitions on the rising edge of the WR or RD strobes for
every other access, see Figure 10-18 on page 386.
Figure 10-18. FRAME Signal Operation, FRM50=1 and FRMCNT=1
Clock
(EPI0S31)
WR
(EPI0S28)
RD
(EPI0S29)
Frame
(EPI0S30)
When FRMCNT=2, the FRAME signal transitions the rising edge of the WR or RD strobes for every
third access, and so on for every value of FRMCNT, see Figure 10-19 on page 386.
Figure 10-19. FRAME Signal Operation, FRM50=1 and FRMCNT=2
CLOCK
(EPI0S31)
WR
(EPI0S28)
RD
(EPI0S29)
FRAME
(EPI0S30)
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iRDY Signal Operation
The ready input (iRDY) from the external device is enabled by the RDYEN bit in the EPIGPCFG
register. iRDY is input on EPI0S27 and may only be used with a free-running clock (CLKGATE is
clear). iRDY is sampled on the falling edge of the EPI clock and gates transactions, no matter what
state they are in. Figure 10-20 on page 387 shows the iRDY signal being recognized as deasserted
on the falling edge of T1. The FRAME, RD, Address, Data signals behave as they would during a
normal transaction in T1. T2 is the frozen state, and signals are held in this state until iRDY is
recognized as asserted again. At the falling edge of T2, when iRDY is asserted again, the cycle
continues and completes in T3.
Figure 10-20. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1
T0
T1
T2
T3
Clock (EPI0S31)
Frame
(EPI0S30)
RD (EPI0S29)
iRDY (EPI0S27)
Address
Data
EPI Clock Operation
If the CLKGATE bit in the EPIGPCFG register is clear, the EPI clock always toggles when
General-purpose mode is enabled. If CLKGATE is set, the clock is output only when a transaction
is occurring, otherwise the clock is held high. If the WR2CYC bit is clear, the EPI clock begins toggling
1 cycle before the WR strobe goes high. If the WR2CYC bit is set, the EPI clock begins toggling when
the WR strobe goes high. The clock stops toggling after the first rising edge after the WR strobe is
deasserted. The RD strobe operates in the same manner as the WR strobe when the WR2CYC bit
is set, as the RD2CYC bit must always be set. See Figure 10-21 on page 387 and Figure
10-22 on page 388.
Figure 10-21. EPI Clock Operation, CLKGATE=1, WR2CYC=0
Clock
(EPI0S31)
WR
(EPI0S28)
Address
Data
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Figure 10-22. EPI Clock Operation, CLKGATE=1, WR2CYC=1
Clock
(EPI0S31)
WR
(EPI0S28)
Address
Data
10.5
Register Map
Table 10-8 on page 388 lists the EPI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the base address of 0x400D.0000. Note that the EPI controller clock
must be enabled before the registers can be programmed (see page 181).
Note:
A back-to-back write followed by a read of the same register reads the value that written
by the first write access, not the value from the second write access. (This situation only
occurs when the processor core attempts this action, the μDMA does not do this.). To read
back what was just written, another instruction must be generated between the write and
read. Read-write does not have this issue, so use of read-write for clear of error interrupt
cause is not affected.
Table 10-8. External Peripheral Interface (EPI) Register Map
Description
See
page
Offset
Name
Type
Reset
0x000
EPICFG
R/W
0x0000.0000
EPI Configuration
390
0x004
EPIBAUD
R/W
0x0000.0000
EPI Main Baud Rate
392
0x010
EPISDRAMCFG
R/W
0x42EE.0000
EPI SDRAM Configuration
394
0x010
EPIHB8CFG
R/W
0x0000.0000
EPI Host-Bus 8 Configuration
396
0x010
EPIHB16CFG
R/W
0x0000.0000
EPI Host-Bus 16 Configuration
400
0x010
EPIGPCFG
R/W
0x0000.0000
EPI General-Purpose Configuration
404
0x014
EPIHB8CFG2
R/W
0x0000.0000
EPI Host-Bus 8 Configuration 2
409
0x014
EPIHB16CFG2
R/W
0x0000.0000
EPI Host-Bus 16 Configuration 2
411
0x014
EPIGPCFG2
R/W
0x0000.0000
EPI General-Purpose Configuration 2
413
0x01C
EPIADDRMAP
R/W
0x0000.0000
EPI Address Map
414
0x020
EPIRSIZE0
R/W
0x0000.0003
EPI Read Size 0
416
0x024
EPIRADDR0
R/W
0x0000.0000
EPI Read Address 0
417
0x028
EPIRPSTD0
R/W
0x0000.0000
EPI Non-Blocking Read Data 0
418
0x030
EPIRSIZE1
R/W
0x0000.0003
EPI Read Size 1
416
0x034
EPIRADDR1
R/W
0x0000.0000
EPI Read Address 1
417
0x038
EPIRPSTD1
R/W
0x0000.0000
EPI Non-Blocking Read Data 1
418
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Table 10-8. External Peripheral Interface (EPI) Register Map (continued)
Offset
Name
Type
Reset
0x060
EPISTAT
RO
0x0000.0000
0x06C
EPIRFIFOCNT
RO
0x070
EPIREADFIFO
0x074
Description
See
page
EPI Status
420
-
EPI Read FIFO Count
422
RO
-
EPI Read FIFO
423
EPIREADFIFO1
RO
-
EPI Read FIFO Alias 1
423
0x078
EPIREADFIFO2
RO
-
EPI Read FIFO Alias 2
423
0x07C
EPIREADFIFO3
RO
-
EPI Read FIFO Alias 3
423
0x080
EPIREADFIFO4
RO
-
EPI Read FIFO Alias 4
423
0x084
EPIREADFIFO5
RO
-
EPI Read FIFO Alias 5
423
0x088
EPIREADFIFO6
RO
-
EPI Read FIFO Alias 6
423
0x08C
EPIREADFIFO7
RO
-
EPI Read FIFO Alias 7
423
0x200
EPIFIFOLVL
R/W
0x0000.0033
EPI FIFO Level Selects
424
0x204
EPIWFIFOCNT
RO
0x0000.0004
EPI Write FIFO Count
426
0x210
EPIIM
R/W
0x0000.0000
EPI Interrupt Mask
427
0x214
EPIRIS
RO
0x0000.0004
EPI Raw Interrupt Status
428
0x218
EPIMIS
RO
0x0000.0000
EPI Masked Interrupt Status
430
0x21C
EPIEISC
R/W1C
0x0000.0000
EPI Error Interrupt Status and Clear
431
10.6
Register Descriptions
This section lists and describes the EPI registers, in numerical order by address offset.
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Register 1: EPI Configuration (EPICFG), offset 0x000
Important: The MODE field determines which configuration register is accessed for offsets 0x010
and 0x014. Any write to the EPICFG register resets the register contents at offsets
0x010 and 0x014.
The configuration register is used to enable the block, select a mode, and select the basic pin use
(based on the mode). Note that attempting to program an undefined MODE field clears the BLKEN
bit and disables the EPI controller.
EPI Configuration (EPICFG)
Base 0x400D.0000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
BLKEN
Bit/Field
Name
Type
Reset
31:5
reserved
RO
0x0000.000
4
BLKEN
R/W
0
R/W
0
MODE
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Block Enable
Value Description
1
The EPI controller is enabled.
0
The EPI controller is disabled.
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Bit/Field
Name
Type
Reset
Description
3:0
MODE
R/W
0x0
Mode Select
Value
Description
0x0
General Purpose
General-Purpose mode. Control, address, and data pins are
configured using the EPIGPCFG and EPIGPCFG2 registers.
0x1
SDRAM
Supports SDR SDRAM. Control, address, and data pins are
configured using the EPISDRAMCFG register.
0x2
8-Bit Host-Bus (HB8)
Host-bus 8-bit interface (also known as the MCU interface).
Control, address, and data pins are configured using the
EPIHB8CFG and EPIHB8CFG2 registers.
0x3
16-Bit Host-Bus (HB16)
Host-bus 16-bit interface (standard SRAM). Control, address,
and data pins are configured using the EPIHB16CFG and
EPIHB16CFG2 registers.
0x3-0xF Reserved
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Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004
The system clock is used internally to the EPI Controller. The baud rate counter can be used to
divide the system clock down to control the speed on the external interface. If the mode selected
emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does
not use an EPI clock, this register controls the speed of changes on the external interface. Care
must be taken to program this register properly so that the speed of the external bus corresponds
to the speed of the external peripheral and puts acceptable current load on the pins. COUNT0 is the
bit field used in all modes except in HB8 and HB16 modes with dual chip selects when different
baud rates are selected, see page 409. If different baud rates are used, COUNT0 is associated with
the address range specified by CS0 and COUNT1 is associated with the address range specified by
CS1.
The COUNTn field is not a straight divider or count. The EPI Clock on EPI0S31 is related to the
COUNTn field and the system clock as follows:
If COUNTn = 0,
EPIClockFreq = SystemClockFreq
otherwise:
EPIClockFreq =
SystemClockFreq
⎛ ⎢COUNTn ⎥
⎞
+ 1⎟ × 2
⎜⎢
⎥
2
⎦
⎝⎣
⎠
where the symbol around COUNTn/2 is the floor operator, meaning the largest integer less than or
equal to COUNTn/2.
So, for example, a COUNTn of 0x0001 results in a clock rate of ½(system clock); a COUNTn of 0x0002
or 0x0003 results in a clock rate of ¼(system clock).
EPI Main Baud Rate (EPIBAUD)
Base 0x400D.0000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
COUNT1
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
COUNT0
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
31:16
COUNT1
RO
0x0000
Description
Baud Rate Counter 1
This bit field is only valid when the CSCFG field is 0x2 or 0x3 and the
CSBAUD bit is set in the EPIHBnCFG2 register.
This bit field contains a counter used to divide the system clock by the
count. The maximum frequency for the external EPI clock is 50 MHz.
A count of 0 means the system clock is used as is.
15:0
COUNT0
R/W
0x0000
Baud Rate Counter 0
This bit field contains a counter used to divide the system clock by the
count. The maximum frequency for the external EPI clock is 50 MHz.
A count of 0 means the system clock is used as is.
June 14, 2010
393
Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 3: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPISDRAMCFG, the MODE field must be 0x1.
The SDRAM Configuration register is used to specify several parameters for the SDRAM controller.
Note that this register is reset when the MODE field in the EPICFG register is changed. If another
mode is selected and the SDRAM mode is selected again, the values must be reinitialized.
The SDRAM interface designed to interface to x16 SDR SDRAMs of 64 MHz or higher, with the
address and data pins overlapped (wire ORed on the board). See Table 10-3 on page 368 for pin
assignments.
EPI SDRAM Configuration (EPISDRAMCFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x42EE.0000
31
30
29
R/W
0
R/W
1
RO
0
15
14
13
RO
0
RO
0
RO
0
FREQ
Type
Reset
28
27
26
25
24
23
22
RO
0
RO
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
1
12
11
10
9
8
7
6
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
RO
0
20
19
18
17
16
R/W
1
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
5
4
3
2
1
0
RO
0
RO
0
RO
0
R/W
0
RFSH
reserved
Type
Reset
21
SLEEP
R/W
0
Bit/Field
Name
Type
Reset
31:30
FREQ
R/W
0x1
reserved
RO
0
SIZE
R/W
0
Description
Frequency Range
This field configures the frequency range of the system clock. This field
must be configured correctly to ensure proper operation. This field does
not affect the refresh counting, which is configured separately using the
RFSH field (and is based on system clock rate and number of rows per
bank). The ranges are:
Value Description
29:27
reserved
RO
0x0
26:16
RFSH
R/W
0x2EE
0x0
0 - 15 MHz
0x1
15 - 30 MHz
0x2
30 - 50 MHz
0x3
50 - 100 MHz
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Refresh Counter
This field contains the refresh counter in system clocks. The reset value
of 0x2EE provides a refresh period of 64 ms when using a 50 MHz clock.
15:10
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
9
SLEEP
R/W
0
Sleep Mode
Value Description
1
The SDRAM is put into low power state, but is self-refreshed.
0
No effect.
8:2
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1:0
SIZE
R/W
0x0
Size of SDRAM
The value of this field affects address pins and behavior.
Value Description
0x0
64 megabits (8MB)
0x1
128 megabits (16MB)
0x2
256 megabits (32MB)
0x3
512 megabits (64MB)
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 4: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIHB8CFG, the MODE field must be 0x2.
The Host Bus 8 Configuration register is activated when the HB8 mode is selected. The HB8 mode
supports muxed address/data (overlay of lower 8 address and all 8 data pins), separated
address/data, and address-less FIFO mode. Note that this register is reset when the MODE field in
the EPICFG register is changed. If another mode is selected and the HB8 mode is selected again,
the values must be reinitialized.
This mode is intended to support SRAMs, Flash memory (read), FIFOs, CPLDs/FPGAs, and devices
with an MCU/HostBus slave or 8-bit FIFO interface support.
Refer to Table 10-5 on page 373 for information on signal configuration controlled by this register
and the EPIHB8CFG2 register.
If less address pins are required, the corresponding AFSEL bit (page 328) should not be enabled so
the EPI controller does not drive those pins, and they are available as standard GPIOs.
There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways:
1. Manually control via GPIOs.
2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses
are not used. For example, if pins EPI0S27 and EPI0S26 are used for Device 1 and 0
respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and
0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the
corresponding GPIOs must be properly configured to ensure that the pins are disabled when
the interface is not in use.
3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after
the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus
providing CEn functionality.
EPI Host-Bus 8 Configuration (EPIHB8CFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
Type
Reset
22
XFEEN
21
20
19
18
WRHIGH RDHIGH
17
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R/W
0
R/W
0
R/W
0
R/W
0
WRWS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RDWS
R/W
0
R/W
0
16
reserved
RO
0
MAXWAIT
Type
Reset
23
XFFEN
reserved
RO
0
RO
0
RO
0
0
MODE
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
23
XFFEN
R/W
0
Description
External FIFO FULL Enable
Value Description
22
XFEEN
R/W
0
1
An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL full signal is high, XFIFO writes
are stalled.
0
No effect.
External FIFO EMPTY Enable
Value Description
21
WRHIGH
R/W
0
1
An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
0
No effect.
WRITE Strobe Polarity
Value Description
1
The WRITE strobe is WRn (active low).
0
The WRITE strobe is WR (active high).
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the programmed write strobe polarity is used for
both CS0n and CS1n accesses.
20
RDHIGH
R/W
0
READ Strobe Polarity
Value Description
1
The READ strobe is RDn (active low).
0
The READ strobe is RD (active high).
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the programmed read strobe polarity is used for
both CS0n and CS1n accesses.
19:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
MAXWAIT
R/W
0x00
Maximum Wait
This field defines the maximum number of external clocks to wait while
an external FIFO ready signal is holding off a transaction (FFULL and
FEMPTY).
When this field is clear, the transaction is held off forever.
Note:
When the MODE field is configured to be 0x2 and the BLKEN
bit is set in the EPICFG register, enabling HB8 mode, this
field defaults to 0xFF.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Bit/Field
Name
Type
Reset
7:6
WRWS
R/W
0x0
Description
Write Wait States
This field adds wait states to the data phase (the address phase is not
affected). The effect is to delay the rising edge of WRn (or the falling
edge of WR). Each wait state adds 2 EPI clock cycles to the access
time.
Value Description
0x0
No wait states.
0x1
1 wait state.
0x2
2 wait states.
0x3
3 wait states.
This field is used in conjunction with the EPIBAUD register.
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the same number of wait states is added to both
CS0n and CS1n accesses.
5:4
RDWS
R/W
0x0
Read Wait States
This field adds wait states to the data phase (the address phase is not
affected). The effect is to delay the rising edge of RDn/Oen (or the falling
edge of RD). Each wait state adds 2 EPI clock cycles to the access
time.
Value Description
0x0
No wait states.
0x1
1 wait state.
0x2
2 wait states.
0x3
3 wait states.
This field is used in conjunction with the EPIBAUD register.
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the same number of wait states is added to both
CS0n and CS1n accesses.
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
1:0
MODE
R/W
0x0
Description
Host Bus Sub-Mode
This field determines which of four Host Bus 8 sub-modes to use.
Sub-mode use is determined by the connected external peripheral. See
Table 10-5 on page 373 for information on how this bit field affects the
operation of the EPI signals.
Value Description
0x0
ADMUX – AD[7:0]
Data and Address are muxed.
0x1
ADNONMUX – D[7:0]
Data and address are separate.
0x2
Continuous Read - D[7:0]
This mode is the same as ADNONMUX, but uses address switch
for multiple reads instead of OEn strobing.
0x3
XFIFO – D[7:0]
This mode adds XFIFO controls with sense of XFIFO full and
XFIFO empty. This mode uses no address or ALE.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 5: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIHB16CFG, the MODE field must be 0x3.
The Host Bus 16 sub-configuration register is activated when the HB16 mode is selected. The HB16
mode supports muxed address/data (overlay of lower 16 address and all 16 data pins), separated
address/data, and address-less FIFO mode. Note that this register is reset when the MODE field in
the EPICFG register is changed. If another mode is selected and the HB16 mode is selected again,
the values must be reinitialized.
This mode is intended to support SRAMs, Flash memory (read), FIFOs, and CPLDs/FPGAs, and
devices with an MCU/HostBus slave or 16-bit FIFO interface support.
Refer to Table 10-6 on page 374 for information on signal configuration controlled by this register
and the EPIHB16CFG2 register.
If less address pins are required, the corresponding AFSEL bit (page 328) should not be enabled so
the EPI controller does not drive those pins, and they are available as standard GPIOs.
There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways:
1. Manually control via GPIOs.
2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses
are not used. For example, if pins EPI0S27 and EPI0S26 are used for Device 1 and 0
respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and
0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the
corresponding GPIOs must be properly configured to ensure that the pins are disabled when
the interface is not in use.
3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after
the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus
providing CEn functionality.
EPI Host-Bus 16 Configuration (EPIHB16CFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
reserved
Type
Reset
22
XFEEN
21
20
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
WRWS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
19
18
WRHIGH RDHIGH
RO
0
MAXWAIT
Type
Reset
23
XFFEN
RDWS
R/W
0
R/W
0
17
16
reserved
RO
0
RO
0
RO
0
1
3
2
reserved
BSEL
RO
0
R/W
0
RO
0
0
MODE
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
Description
31:24
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
23
XFFEN
R/W
0
Description
External FIFO FULL Enable
Value Description
22
XFEEN
R/W
0
1
An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL signal is high, XFIFO writes are
stalled.
0
No effect.
External FIFO EMPTY Enable
Value Description
21
WRHIGH
R/W
0
1
An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
0
No effect.
WRITE Strobe Polarity
Value Description
1
The WRITE strobe is WRn (active low).
0
The WRITE strobe is WR (active high).
If both CS0n and CS1n are enabled (the CSCFG field in the
EPIHB16CFG2 register is 0x2 or 0x3), the programmed write strobe
polarity is used for both CS0n and CS1n accesses.
20
RDHIGH
R/W
0
READ Strobe Polarity
Value Description
1
The READ strobe is RDn (active low).
0
The READ strobe is RD (active high).
If both CS0n and CS1n are enabled (the CSCFG field in the
EPIHB16CFG2 register is 0x2 or 0x3), the programmed read strobe
polarity is used for both CS0n and CS1n accesses.
19:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
MAXWAIT
R/W
0x00
Maximum Wait
This field defines the maximum number of external clocks to wait while
an external FIFO ready signal is holding off a transaction (FFULL and
FEMPTY).
When this field is clear, the transaction is held off forever.
Note:
When the MODE field is configured to be 0x3 and the BLKEN
bit is set in the EPICFG register, enabling HB16 mode, this
field defaults to 0xFF.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Bit/Field
Name
Type
Reset
7:6
WRWS
R/W
0x0
Description
Write Wait States
This field adds wait states to the data phase (the address phase is not
affected). The effect is to delay the rising edge of WRn (or the falling
edge of WR). Each wait state adds 2 EPI clock cycles to the access
time.
Value Description
0x0
No wait states.
0x1
1 wait state.
0x2
2 wait states.
0x3
3 wait states.
This field is used in conjunction with the EPIBAUD register.
If both CS0n and CS1n are enabled (the CSCFG field in the
EPIHB16CFG2 register is 0x2 or 0x3), the same number of wait states
is added to both CS0n and CS1n accesses.
5:4
RDWS
R/W
0x0
Read Wait States
This field adds wait states to the data phase (the address phase is not
affected). The effect is to delay the rising edge of RDn/Oen (or the falling
edge of RD). Each wait state adds 2 EPI clock cycles to the access
time.
Value Description
0x0
No wait states.
0x1
1 wait state.
0x2
2 wait states.
0x3
3 wait states.
This field is used in conjunction with the EPIBAUD register.
If both CS0n and CS1n are enabled (the CSCFG field in the
EPIHB16CFG2 register is 0x2 or 0x3), the same number of wait states
is added to both CS0n and CS1n accesses.
3
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2
BSEL
R/W
0
Byte Select Configuration
This bit enables byte select operation.
Value Description
0
No Byte Selects
Data is read and written as 16 bits.
1
Enable Byte Selects
Two EPI signals function as byte select signals to allow 8-bit
transfers. See Table 10-6 on page 374 for details on which EPI
signals are used.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
1:0
MODE
R/W
0x0
Description
Host Bus Sub-Mode
This field determines which of three Host Bus 16 sub-modes to use.
Sub-mode use is determined by the connected external peripheral. See
Table 10-6 on page 374 for information on how this bit field affects the
operation of the EPI signals.
Value Description
0x0
ADMUX – AD[15:0]
Data and Address are muxed.
0x1
ADNONMUX – D[15:0]
Data and address are separate. This mode is not practical in
HB16 mode for normal peripherals because there are generally
not enough address bits available.
0x2
Continuous Read - D[15:0]
This mode is the same as ADNONMUX, but uses address switch
for multiple reads instead of OEn strobing. This mode is not
practical in HB16 mode for normal SRAMs because there are
generally not enough address bits available.
0x3
XFIFO – D[15:0]
This mode adds XFIFO controls with sense of XFIFO full and
XFIFO empty. This mode uses no address or ALE.
June 14, 2010
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 6: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIGPCFG, the MODE field must be 0x0.
The RD2CYC bit must be set at all times in General-Purpose mode to ensure proper
operation.
The General-Purpose configuration register is used to configure the control, data, and address pins.
This mode can be used for custom interfaces with FPGAs, CPLDs, and for digital data acquisition
and actuator control. Note that this register is reset when the MODE field in the EPICFG register is
changed. If another mode is selected and the General-purpose mode is selected again, the register
the values must be reinitialized.
This mode is designed for 3 general types of use:
■ Extremely high-speed clocked interfaces to FPGAs and CPLDs, with 3 sizes of data and optional
address. Framing and clock-enable permit more optimized interfaces.
■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely
controlled by the baud rate in the EPIBAUD register (when used with the NBRFIFO and/or the
WFIFO) or by rate of accesses from software or μDMA.
■ General custom interfaces of any speed.
The configuration allows for choice of an output clock (free running or gated), a framing signal (with
frame size), a ready input (to stretch transactions), read and write strobes, address of varying sizes,
and data of varying sizes. Additionally, provisions are made for splitting address and data phases
on the external interface.
EPI General-Purpose Configuration (EPIGPCFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
CLKPIN CLKGATE
Type
Reset
29
28
27
26
reserved
25
24
22
FRMCNT
21
20
19
18
17
RDYEN
FRMPIN
FRM50
RW
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
R/W
0
R/W
0
RO
0
RO
0
R/W
0
reserved
R/W
0
Bit/Field
Name
Type
Reset
31
CLKPIN
R/W
0
ASIZE
WR2CYC RD2CYC
16
reserved
MAXWAIT
Type
Reset
23
reserved
reserved
DSIZE
R/W
0
Description
Clock Pin
Value Description
1
EPI0S31 functions as the EPI clock output.
0
No clock output.
The EPI clock is generated from the COUNT0 field in the EPIBAUD
register (as is the system clock which is divided down from it).
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
30
CLKGATE
R/W
0
Clock Gated
Value Description
1
The EPI clock is output only when there is data to write or read
(current transaction); otherwise the EPI clock is held low.
0
The EPI clock is free running.
Note that EPI0S27 is an iRDY signal if RDYEN is set. CLKGATE is ignored
if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register is cleared.
29
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
28
RDYEN
R/W
0
Ready Enable
Value Description
1
The external peripheral drives an iRDY signal into pin EPI0S27.
0
The external peripheral does not drive an iRDY signal and is
assumed to be ready always.
The ready enable signal may only be used with a free-running EPI clock
(CLKGATE=0).
The external iRDY signal is sampled on the falling edge of the EPI clock.
Setup and hold times must be met to ensure registration on the next
falling EPI clock edge.
This bit is ignored if CLKPIN is 0 or CLKGATE is 1.
27
FRMPIN
R/W
0
Framing Pin
Value Description
1
A framing signal is output on EPI0S30.
0
No framing signal is output.
Framing has no impact on data itself, but forms a context for the external
peripheral. When used with a free-running EPI clock, the FRAME signal
forms the valid signal. When used with a gated EPI clock, it is usually
used to form a frame size.
26
FRM50
R/W
0
50/50 Frame
Value Description
1
The FRAME signal is output as 50/50 duty cycle using count
(see FRMCNT).
0
The FRAME signal is output as a single pulse, and then held
low for the count.
This bit is ignored if FRMPIN is 0.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Bit/Field
Name
Type
Reset
25:22
FRMCNT
R/W
0x0
Description
Frame Count
This field specifies the size of the frame in EPI clocks. The frame counter
is used to determine the frame size. The count is FRMCNT+1. So, a
FRMCNT of 0 forms a pure transaction valid signal (held high during
transactions, low otherwise).
A FRMCNT of 0 with FRM50 set inverts the FRAME signal on each
transaction. A FRMCNT of 1 means the FRAME signal is inverted every
other transaction; a value of 15 means every sixteenth transaction.
If FRM50 is set, the frame is held high for FRMCNT+1 transactions, then
held low for that many transactions, and so on.
If FRM50 is clear, the frame is pulsed high for one EPI clock and then
low for FRMCNT EPI clocks.
This field is ignored if FRMPIN is 0.
21
RW
R/W
0
Read and Write
Value Description
1
RD and WR strobes are asserted on EPI0S29 and EPI0S28.
RD is asserted high on the rising edge of the EPI clock when a
read is being performed. WR is asserted high on the rising edge
of the EPI clock when a write is being performed
0
RD and WR strobes are not output.
This bit is forced to 1 when RD2CYC and/or WR2CYC is 1.
20
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
19
WR2CYC
R/W
0
2-Cycle Writes
Value Description
1
Writes are two EPI clock cycles long, with address on one EPI
clock cycle (with the WR strobe asserted) and data written on
the following EPI clock cycle (with WR strobe de-asserted). The
next address (if any) is in the cycle following.
0
Data is output on the same EPI clock cycle as the address.
When this bit is set, then the RW bit is forced to be set.
18
RD2CYC
R/W
0
2-Cycle Reads
Value Description
1
Reads are two EPI clock cycles, with address on one EPI clock
cycle (with the RD strobe asserted) and data captured on the
following EPI clock cycle (with the RD strobe de-asserted). The
next address (if any) is in the cycle following.
0
Data is captured on the EPI clock cycle with READ strobe
asserted.
When this bit is set, then the RW bit is forced to be set.
Caution – This bit must be set at all times in General-Purpose mode to
ensure proper operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
17:16
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
15:8
MAXWAIT
R/W
0x00
Maximum Wait
This field defines the maximum number of EPI clocks to wait while the
iRDY signal (see RDYEN) is holding off a transaction. If this field is 0,
the transaction is held forever. If the maximum wait of 255 clocks
(MAXWAIT=0xFF) is exceeded, an error interrupt occurs and the
transaction is aborted/ignored.
Note:
When the MODE field is configured to be 0x0 and the BLKEN
bit is set in the EPICFG register , enabling General-Purpose
mode, this field defaults to 0xFF.
7:6
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5:4
ASIZE
R/W
0x0
Address Bus Size
This field defines the size of the address bus. The address can be up
to 4-bits wide with a 24-bit data bus, up to 12-bits wide with a 16-bit data
bus, and up to 20-bits wide with an 8-bit data bus. If the full address bus
is not used, use the least significant address bits. Any unused address
bits can be used as GPIOs by clearing the AFSEL bit for the
corresponding GPIOs. Also, if RDYEN is 1, then the address sizes are
1 smaller (3, 11, 19).
The values are:
Value Description
3:2
reserved
RO
0x0
0x0
No address
0x1
Up to 4 bits wide.
0x2
Up to 12 bits wide. This size cannot be used with 24-bit data.
0x3
Up to 20 bits wide. This size cannot be used with data sizes
other than 8.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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External Peripheral Interface (EPI)
Bit/Field
Name
Type
Reset
1:0
DSIZE
R/W
0x0
Description
Size of Data Bus
This field defines the size of the data bus (starting at EPI0S0). Subsets
of these numbers can be created by clearing the AFSEL bit for the
corresponding GPIOs. Note that size 32 may not be used with clock,
frame, address, or other control.
The values are:
Value Description
0x0
8 Bits Wide (EPI0S0 to EPI0S7)
0x1
16 Bits Wide (EPI0S0 to EPI0S15)
0x2
24 Bits Wide (EPI0S0 to EPI0S23)
0x3
32 Bits Wide (EPI0S0 to EPI0S31)
This size may not be used with an EPI clock. This value is
normally used for acquisition input and actuator control as well
as other general-purpose uses that require 32 bits per direction.
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Stellaris® LM3S9B95 Microcontroller
Register 7: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIHB8CFG2, the MODE field must be 0x2.
This register is used to configure operation while in Host-Bus 8 mode. Note that this register is reset
when the MODE field in the EPICFG register is changed. If another mode is selected and the Host-Bus
8 mode is selected again, the values must be reinitialized.
EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2)
Base 0x400D.0000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
WORD
Type
Reset
29
28
27
reserved
26
25
CSBAUD
24
23
22
21
20
CSCFG
19
18
17
16
reserved
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
WORD
R/W
0
RO
0
Description
Word Access Mode
By default, the EPI controller uses data bits [7:0] for Host-Bus 8
accesses. When using Word Access mode, the EPI controller can
automatically route bytes of data onto the correct byte lanes such that
data can be stored in bits [31:8]. When WORD is set, short and long
variables can be used in C programs.
Value Description
30:27
reserved
RO
0x0
26
CSBAUD
R/W
0
0
Word Access mode is disabled.
1
Word Access mode is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Chip Select Baud Rate
Value Description
0
Same Baud Rate
Both CS0n and CS1n use the baud rate for the external bus
that is defined by the COUNT0 field in the EPIBAUD register.
1
Different Baud Rates
CS0n uses the baud rate for the external bus that is defined by
the COUNT0 field in the EPIBAUD register. CSn1 uses the baud
rate defined by the COUNT1 field in the EPIBAUD register.
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External Peripheral Interface (EPI)
Bit/Field
Name
Type
Reset
25:24
CSCFG
R/W
0x0
Description
Chip Select Configuration
Value Description
0x0
ALE Configuration
EPI0S30 is used as an address latch (ALE). When using this
mode, the address and data should be muxed (HB8MODE field
in the EPIHB8CFG register should be configured to 0x0). If
needed, the address can be latched by external logic.
0x1
CSn Configuration
EPI0S30 is used as a Chip Select (CSn). When using this mode,
the address and data should not be muxed (HB8MODE field in
the EPIHB8CFG register should be configured to 0x1). In this
mode, the WR signal (EPI0S29) and the RD signal (EPI0S28)
are used to latch the address when CSn is low.
0x2
Dual CSn Configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n.
Whether CS0n or CS1n is asserted is determined by the most
significant address bit for a respective external address map.
This configuration can be used for a RAM bank split between
2 devices as well as when using both an external RAM and an
external peripheral.
0x3
ALE with Dual CSn Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as
CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n
is asserted is determined by the most significant address bit for
a respective external address map.
23:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 8: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIHB16CFG2, the MODE field must be 0x3.
This register is used to configure operation while in Host-Bus 16 mode. Note that this register is
reset when the MODE field in the EPICFG register is changed. If another mode is selected and the
Host-Bus 16 mode is selected again, the values must be reinitialized.
EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2)
Base 0x400D.0000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
WORD
Type
Reset
29
28
27
reserved
26
25
CSBAUD
24
23
22
21
20
CSCFG
19
18
17
16
reserved
R/W
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
WORD
R/W
0
RO
0
Description
Word Access Mode
By default, the EPI controller uses data bits [15:0] for Host-Bus 16
accesses. When using Word Access mode, the EPI controller can
automatically route bytes of data onto the correct byte lanes such that
data can be stored in bits [31:16]. When WORD is set, long variables can
be used in C programs.
Value Description
30:27
reserved
RO
0x0
26
CSBAUD
R/W
0
0
Word Access mode is disabled.
1
Word Access mode is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Chip Select Baud Rate
Value Description
0
Same Baud Rate
Both CS0n and CS1n use the baud rate for the external bus
that is defined by the COUNT0 field in the EPIBAUD register.
1
Different Baud Rates
CS0n uses the baud rate for the external bus that is defined by
the COUNT0 field in the EPIBAUD register. CSn1 uses the baud
rate defined by the COUNT1 field in the EPIBAUD register.
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External Peripheral Interface (EPI)
Bit/Field
Name
Type
Reset
25:24
CSCFG
R/W
0x0
Description
Chip Select Configuration
This field controls the chip select options, including an ALE format, a
single chip select, two chip selects, and an ALE combined with two chip
selects.
Value Description
0x0
ALE Configuration
EPI0S30 is used as an address latch (ALE). When using this
mode, the address and data should be muxed (HB16MODE field
in the EPIHB16CFG register should be configured to 0x0). If
needed, the address can be latched by external logic.
0x1
CSn Configuration
EPI0S30 is used as a Chip Select (CSn). When using this mode,
the address and data should not be muxed (HB816MODE field
in the EPIHB16CFG register should be configured to 0x1). In
this mode, the WR signal (EPI0S29) and the RD signal
(EPI0S28) are used to latch the address when CSn is low.
0x2
Dual CSn Configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n.
Whether CS0n or CS1n is asserted is determined by the most
significant address bit for a respective external address map.
This configuration can be used for a RAM bank split between
2 devices as well as when using both an external RAM and an
external peripheral.
0x3
ALE with Dual CSn Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as
CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n
is asserted is determined by the most significant address bit for
a respective external address map.
23:0
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Register 9: EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIGPCFG2, the MODE field must be 0x0.
This register is used to configure operation while in General-Purpose mode. Note that this register
is reset when the MODE field in the EPICFG register is changed. If another mode is selected and
the General-Purpose mode is selected again, the values must be reinitialized.
EPI General-Purpose Configuration 2 (EPIGPCFG2)
Base 0x400D.0000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
WORD
Type
Reset
23
22
21
20
19
18
17
16
reserved
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31
WORD
R/W
0x0
RO
0
Description
Word Access Mode
By default, the EPI controller uses data bits [7:0] when the DSIZE field
in the EPIGPCFG register is 0x0; data bits [15:0] when the DSIZE field
is 0x1; data bits [23:0] when the DSIZE field is 0x2; and data bits [31:0]
when the DSIZE field is 0x3.
When using Word Access mode, the EPI controller can automatically
route bytes of data onto the correct byte lanes such that data can be
stored in bits [31:8] for DSIZE=0x0 and bits [31:16] for DSIZE=0x1. For
DSIZE=0x2 or 0x3, this bit must be clear.
Value Description
30:0
reserved
RO
0x000.0000
0
Word Access mode is disabled.
1
Word Access mode is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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External Peripheral Interface (EPI)
Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C
This register enables address mapping. The EPI controller can directly address memory and
peripherals. In addition, the EPI controller supports address mapping to allow indirect accesses in
the External RAM and External Peripheral areas.
If the external device is a peripheral, including a FIFO or a directly addressable device, the EPSZ
and EPADR bit fields should be configured for the address space. If the external device is SDRAM,
SRAM, or NOR Flash memory, the ERADR and ERSZ bit fields should be configured for the address
space.
If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in the EPIHBnCFG2 register),
both chip selects can share the peripheral or the memory space, or one chip select can use the
peripheral space and the other can use the memory space. If the EPADR field is not 0x0 and the
ERADR field is 0x0, then the address specified by EPADR is used for both chip selects, with CS0n
being asserted when the MSB of the address range is 0 and CS1n being asserted when the MSB
of the address range is 1. If the ERADR field is not 0x0 and the EPADR field is 0x0, then the address
specified by ERADR is used for both chip selects, with the MSB performing the same delineation. If
both the EPADR and the ERADR are not 0x0, then CS0n is asserted for the address range defined
by EPADR and CS1n is asserted for the address range defined by ERADR.
EPI Address Map (EPIADDRMAP)
Base 0x400D.0000
Offset 0x01C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
EPSZ
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7:6
EPSZ
R/W
0x0
RO
0
R/W
0
EPADR
R/W
0
R/W
0
R/W
0
ERSZ
R/W
0
ERADR
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Peripheral Size
This field selects the size of the external peripheral. If the size of the
external peripheral is larger, a bus fault occurs. If the size of the external
peripheral is smaller, it wraps (upper address bits unused).
Note:
When not using byte selects in Host-Bus 16, data is accessed
on 2-byte boundaries. As a result, the available address space
is double the amount shown below.
Value Description
0x0
256 bytes; lower address range: 0x00 to 0xFF
0x1
64 KB; lower address range: 0x0000 to 0xFFFF
0x2
16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3
256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
5:4
EPADR
R/W
0x0
Description
External Peripheral Address
This field selects address mapping for the external peripheral area.
Value Description
3:2
ERSZ
R/W
0x0
0x0
Not mapped
0x1
At 0xA000.0000
0x2
At 0xC000.0000
0x3
reserved
External RAM Size
This field selects the size of mapped RAM. If the size of the external
memory is larger, a bus fault occurs. If the size of the external memory
is smaller, it wraps (upper address bits unused):
Value Description
1:0
ERADR
R/W
0x0
0x0
256 bytes; lower address range: 0x00 to 0xFF
0x1
64 KB; lower address range: 0x0000 to 0xFFFF
0x2
16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3
256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF
External RAM Address
Selects address mapping for external RAM area:
Value Description
0x0
Not mapped
0x1
At 0x6000.0000
0x2
At 0x8000.0000
0x3
reserved
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020
Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030
This register selects the size of transactions when performing non-blocking reads with the
EPIRPSTDn registers. This size affects how the external address is incremented.
The SIZE field must match the external data width as configured in the EPIHBnCFG or EPIGPCFG
register.
SDRAM mode uses a 16-bit data interface. If SIZE is 0x1, data is returned on the least significant
bits (D[7:0]), and the remaining bits D[31:8] are all zeros, therefore the data on bits D[15:8] is lost.
If SIZE is 0x2, data is returned on the least significant bits (D[15:0]), and the remaining bits D[31:16]
are all zeros.
Note that changing this register while a read is active has an unpredictable effect.
EPI Read Size 0 (EPIRSIZE0)
Base 0x400D.0000
Offset 0x020
Type R/W, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:2
reserved
RO
0x0000.000
1:0
SIZE
R/W
0x3
0
SIZE
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
1
R/W
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Current Size
Value Description
0x0
reserved
0x1
Byte (8 bits)
0x2
Half-word (16 bits)
0x3
Word (32 bits)
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024
Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034
This register holds the current address value. When performing non-blocking reads via the
EPIRPSTDn registers, this register’s value forms the address (when used by the mode). That is,
when an EPIRPSTDn register is written with a non-0 value, this register is used as the first address.
After each read, it is incremented by the size specified by the corresponding EPIRSIZEn register.
Thus at the end of a read, this register contains the next address for the next read. For example, if
the last read was 0x20, and the size is word, then the register contains 0x24. When a non-blocking
read is cancelled, this register contains the next address that would have been read had it not been
cancelled. For example, if reading by bytes and 0x103 had been read but not 0x104, this register
contains 0x104. In this manner, the system can determine the number of values in the NBRFIFO
to drain.
Note that changing this register while a read is active has an unpredictable effect due to race
condition.
EPI Read Address 0 (EPIRADDR0)
Base 0x400D.0000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
reserved
Type
Reset
22
21
20
19
18
17
16
ADDR
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:29
reserved
RO
0x0
28:0
ADDR
R/W
0x000.0000
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Current Address
Next address to read.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028
Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038
This register sets up a non-blocking read via the external interface. A non-blocking read is started
by writing to this register with the count (other than 0). Clearing this register terminates an active
non-blocking read as well as cancelling any that are pending. This register should always be cleared
before writing a value other than 0; failure to do so can cause improper operation.
The first address is based on the corresponding EPIRADDRn register. The address register is
incremented by the size specified by the EPIRSIZEn register after each read. If the size is less than
a word, only the least significant bits of data are filled into the NBRFIFO; the most significant bits
are cleared.
Note that all three registers may be written using one STM instruction, such as with a structure copy
in C/C++.
The data may be read from the EPIREADFIFO register after the read cycle is completed. The
interrupt mechanism is normally used to trigger the FIFO reads via ISR or μDMA.
If the countdown has not reached 0 and the NBRFIFO is full, the external interface waits until a
NBRFIFO entry becomes available to continue.
Note: if a blocking read or write is performed through the address mapped area (at 0x6000.0000
through 0xDFFF.FFFF), any current non-blocking read is paused (at the next safe boundary), and
the blocking request is inserted. After completion of any blocking reads or writes, the non-blocking
reads continue from where they were paused.
The other way to read data is via the address mapped locations (see the EPIADDRMAP register),
but this method is blocking (core or μDMA waits until result is returned).
To cancel a non-blocking read, clear this register. To make sure that all values read are drained
from the NBRFIFO, the EPISTAT register must be consulted to be certain that bits NBRBUSY and
ACTIVE are cleared. One of these registers should not be cleared until either the other EPIRPSTDn
register becomes active or the external interface is not busy. At that point, the corresponding
EPIRADDRn register indicates how many values were read.
EPI Non-Blocking Read Data 0 (EPIRPSTD0)
Base 0x400D.0000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
RO
0
15
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
14
13
12
11
10
9
8
7
reserved
Type
Reset
RO
0
RO
0
POSTCNT
RO
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:13
reserved
RO
0x0000.0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
Description
12:0
POSTCNT
R/W
0x000
Post Count
A write of a non-zero value starts a read operation for that count. Note
that it is the software's responsibility to handle address wraparound.
Reading this register provides the current count.
A write of 0 cancels a non-blocking read (whether active now or pending).
Prior to writing a non-zero value, this register must first be cleared.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 17: EPI Status (EPISTAT), offset 0x060
This register indicates which non-blocking read register is currently active; it also indicates whether
the external interface is busy performing a write or non-blocking read (it cannot be performing a
blocking read, as the bus would be blocked and as a result, this register could not be accessed).
This register is useful to determining which non-blocking read register is active when both are loaded
with values and when implementing sequencing or sharing.
This register is also useful when canceling non-blocking reads, as it shows how many values were
read by the canceled side.
EPI Status (EPISTAT)
Base 0x400D.0000
Offset 0x060
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
CELOW
XFFULL XFEMPTY INITSEQ
RO
0
Bit/Field
Name
Type
Reset
31:10
reserved
RO
0x0000.00
9
CELOW
RO
0
RO
0
RO
0
RO
0
WBUSY NBRBUSY
RO
0
RO
0
reserved
RO
0
RO
0
ACTIVE
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Enable Low
This bit provides information on the clock status when in general-purpose
mode and the RDYEN bit is set.
Value Description
1
The external device is gating the clock (iRDY is low).
Attempts to read or write in this situation are stalled until the
clock is enabled or the counter times out as specified by the
MAXWAIT field.
0
8
XFFULL
RO
0
The external device is not gating the clock.
External FIFO Full
This bit provides information on the XFIFO when in the FIFO sub-mode
of the Host Bus n mode with the XFFEN bit set in the EPIHBnCFG
register. The EPI0S26 signal reflects the status of this bit.
Value Description
1
The XFIFO is signaling as full (the FIFO full signal is high).
Attempts to write in this case are stalled until the XFIFO full
signal goes low or the counter times out as specified by the
MAXWAIT field.
0
The external device is not gating the clock.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
7
XFEMPTY
RO
0
Description
External FIFO Empty
This bit provides information on the XFIFO when in the FIFO sub-mode
of the Host Bus n mode with the XFEEN bit set in the EPIHBnCFG
register. The EPI0S27 signal reflects the status of this bit.
Value Description
1
The XFIFO is signaling as empty (the FIFO empty signal is
high).
Attempts to read in this case are stalled until the XFIFO empty
signal goes low or the counter times out as specified by the
MAXWAIT field.
0
6
INITSEQ
RO
0
The external device is not gating the clock.
Initialization Sequence
Value Description
1
The SDRAM interface is running through the wakeup period
(greater than 100 μs).
If an attempt is made to read or write the SDRAM during this
period, the access is held off until the wakeup period is
complete.
0
5
WBUSY
RO
0
The SDRAM interface is not in the wakeup period.
Write Busy
Value Description
4
NBRBUSY
RO
0
1
The external interface is performing a write.
0
The external interface is not performing a write.
Non-Blocking Read Busy
Value Description
3:1
reserved
RO
0x0
0
ACTIVE
RO
0
1
The external interface is performing a non-blocking read, or if
the non-blocking read is paused due to a write.
0
The external interface is not performing a non-blocking read.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Register Active
Value Description
1
The EPIRPSTD1 register is active.
0
If NBRBUSY is set, the EPIRPSTD0 register is active.
If the NBRBUSY bit is clear, then neither EPIRPSTDx register is
active.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C
This register returns the number of values in the NBRFIFO (the data in the NBRFIFO can be read
via the EPIREADFIFO register). A race is possible, but that only means that more values may come
in after this register has been read.
EPI Read FIFO Count (EPIRFIFOCNT)
Base 0x400D.0000
Offset 0x06C
Type RO, reset 31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
-
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
COUNT
RO
-
COUNT
RO
-
RO
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FIFO Count
Number of filled entries in the NBRFIFO.
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 19: EPI Read FIFO (EPIREADFIFO), offset 0x070
Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074
Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078
Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C
Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080
Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084
Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088
Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C
Important: Use caution when reading this register. Performing a read may change bit status.
This register returns the contents of the NBRFIFO or 0 if the NBRFIFO is empty. Each read returns
the data that is at the top of the NBRFIFO, and then empties that value from the NBRFIFO. The
alias registers can be used with the LDMIA instruction for more efficient operation (for up to 8
registers). See ARM® Cortex™-M3 Technical Reference Manual for more information on the LDMIA
instruction.
EPI Read FIFO (EPIREADFIFO)
Base 0x400D.0000
Offset 0x070
Type RO, reset 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
RO
-
DATA
Type
Reset
DATA
Type
Reset
Bit/Field
Name
Type
Reset
Description
31:0
DATA
RO
-
Reads Data
This field contains the data that is at the top of the NBRFIFO. After being
read, the NBRFIFO entry is removed.
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200
This register allows selection of the FIFO levels which trigger an interrupt to the interrupt controller
or, more efficiently, a DMA request to the μDMA. The NBRFIFO select triggers on fullness such
that it triggers on match or above (more full). The WFIFO triggers on emptiness such that it triggers
on match or below (less entries).
®
It should be noted that the FIFO triggers are not identical to other such FIFOs in Stellaris peripherals.
In particular, empty and full triggers are provided to avoid wait states when using blocking operations.
The settings in this register are only meaningful if the μDMA is active or the interrupt is enabled.
Additionally, this register allows protection against writes stalling and notification of performing
blocking reads which stall for extra time due to preceding writes. The two functions behave in a
non-orthogonal way because read and write are not orthogonal.
The write error bit configures the system such that an attempted write to an already full WFIFO
abandons the write and signals an error interrupt to prevent accidental latencies due to stalling
writes.
The read error bit configures the system such that after a read has been stalled due to any preceding
writes in the WFIFO, the error interrupt is generated. Note that the excess stall is not prevented,
but an interrupt is generated after the fact to notify that it has happened.
EPI FIFO Level Selects (EPIFIFOLVL)
Base 0x400D.0000
Offset 0x200
Type R/W, reset 0x0000.0033
31
30
29
28
27
26
25
24
23
22
21
20
19
18
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
9
8
7
6
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
5
4
WRFIFO
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
1
RO
0
RO
0
3
2
RO
0
16
RSERR
R/W
0
R/W
0
1
0
RDFIFO
reserved
R/W
1
17
WFERR
R/W
0
R/W
1
R/W
1
Bit/Field
Name
Type
Reset
Description
31:18
reserved
RO
0x000
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
17
WFERR
R/W
0
Write Full Error
Value Description
1
This bit enables the Write Full error interrupt (WTFULL in the
EPIIC register) to be generated when a write is attempted and
the WFIFO is full. The write stalls until a WFIFO entry becomes
available.
0
The Write Full error interrupt is disabled. Writes are stalled when
the WFIFO is full until a space becomes available but an error
is not generated. Note that the Cortex-M3 write buffer may hide
that stall if no other memory transactions are attempted during
that time.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
16
RSERR
R/W
0
Description
Read Stall Error
Value Description
1
This bit enables the Read Stalled error interrupt (RSTALL in the
EPIIC register) to be generated when a read is attempted and
the WFIFO is not empty. The read is still stalled during the time
the WFIFO drains, but this error notifies the application that this
excess delay has occurred.
0
The Read Stalled error interrupt is disabled. Reads behave as
normal and are stalled until any preceding writes have completed
and the read has returned a result.
Note that the configuration of this bit has no effect on non-blocking reads.
15:7
reserved
RO
0x00
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6:4
WRFIFO
R/W
0x3
Write FIFO
This field configures the trigger point for the WFIFO.
Value
Description
0x0
Trigger when there are 1 to 4 spaces available in the WFIFO.
0x1
reserved
0x2
Trigger when there are 1 to 3 spaces available in the WFIFO.
0x3
Trigger when there are 1 to 2 spaces available in the WFIFO.
0x4
Trigger when there is 1 space available in the WFIFO.
0x5-0x7 reserved
3
reserved
RO
0
2:0
RDFIFO
R/W
0x3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Read FIFO
This field configures the trigger point for the NBRFIFO.
Value Description
0x0
reserved
0x1
Trigger when there are 1 or more entries in the NBRFIFO.
0x2
Trigger when there are 2 or more entries in the NBRFIFO.
0x3
Trigger when there are 4 or more entries in the NBRFIFO.
0x4
Trigger when there are 6 or more entries in the NBRFIFO.
0x5
Trigger when there are 7 or more entries in the NBRFIFO.
0x6
Trigger when there are 8 entries in the NBRFIFO.
0x7
reserved
June 14, 2010
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204
This register contains the number of slots currently available in the WFIFO. This register may be
used for polled writes to avoid stalling and for blocking reads to avoid excess stalling (due to
undrained writes). An example use for writes may be:
for (idx = 0; idx < cnt; idx++) {
while (EPIWFIFOCNT == 0) ;
*ext_ram = *mydata++;
}
The above code ensures that writes to the address mapped location do not occur unless the WFIFO
has room. Although polling makes the code wait (spinning in the loop), it does not prevent interrupts
being serviced due to bus stalling.
EPI Write FIFO Count (EPIWFIFOCNT)
Base 0x400D.0000
Offset 0x204
Type RO, reset 0x0000.0004
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
WTAV
RO
0x4
WTAV
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Available Write Transactions
The number of write transactions available in the WFIFO.
When clear, a write is stalled waiting for a slot to become free (from a
preceding write completing).
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Texas Instruments-Advance Information
Stellaris® LM3S9B95 Microcontroller
Register 29: EPI Interrupt Mask (EPIIM), offset 0x210
This register is the interrupt mask set or clear register. For each interrupt source (read, write, and
error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller;
a mask value of 0 prevents the interrupt source from triggering an interrupt.
Note that interrupt masking has no effect on μDMA, which operates off the raw source of the read
and write interrupts.
EPI Interrupt Mask (EPIIM)
Base 0x400D.0000
Offset 0x210
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
WRIM
R/W
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
WRIM
RDIM
ERRIM
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write Interrupt Mask
Value Description
1
RDIM
R/W
0
1
WRRIS in the EPIRIS register is not masked and can trigger an
interrupt to the interrupt controller.
0
WRRIS in the EPIRIS register is masked and does not cause
an interrupt.
Read Interrupt Mask
Value Description
0
ERRIM
R/W
0
1
RDRIS in the EPIRIS register is not masked and can trigger an
interrupt to the interrupt controller.
0
RDRIS in the EPIRIS register is masked and does not cause
an interrupt.
Error Interrupt Mask
Value Description
1
ERRIS in the EPIRIS register is not masked and can trigger an
interrupt to the interrupt controller.
0
ERRIS in the EPIRIS register is masked and does not cause
an interrupt.
June 14, 2010
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Texas Instruments-Advance Information
External Peripheral Interface (EPI)
Register 30: EPI Raw Interrupt Status (EPIRIS), offset 0x214
This register is the raw interrupt status register. On a read, it gives the current state of each interrupt
source. A write has no effect.
Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by
EPIFIFOLVL.
Raw status for error is held until the error is cleared by writing to the EPIIC register.
EPI Raw Interrupt Status (EPIRIS)
Base 0x400D.0000
Offset 0x214
Type RO, reset 0x0000.0004
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
WRRIS
RDRIS
ERRRIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
WRRIS
RO
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write Raw Interrupt Status
Value Description
1
The number of available entries in the WFIFO is within the range
specified by the trigger level (the WRFIFO field in the
EPIFIFOLVL register).
0
The number of available entries in the WFIFO is above the range
specified by the trigger level.
This bit is cleared when the level in the WFIFO is above the trigger point
programmed by the WRFIFO field.
1
RDRIS
RO
0
Read Raw Interrupt Status
Value Description
1
The number of valid entries in the NBRFIFO is within the range
specified by the trigger level (the RDFIFO field in the
EPIFIFOLVL register).
0
The number of valid entries in the NBRFIFO is below the range
specified by the trigger level.
This bit is cleared when the level in the NBRFIFO is below the trigger
point programmed by the RDFIFO field.
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Bit/Field
Name
Type
Reset
0
ERRRIS
RO
0
Description
Error Raw Interrupt Status
The error interrupt occurs in the following situations:
■
WFIFO Full. For a full WFIFO to generate an error interrupt, the
WFERR bit in the EPIFIFOLVL register must be set.
■
Read Stalled. For a stalled read to generate an error interrupt, the
RSERR bit in the EPIFIFOLVL register must be set.
■
Timeout. If the MAXWAIT field in the EPIGPCFG register is
configured to a value other than 0, a timeout error occurs when
iRDY or XFIFO not-ready signals hold a transaction for more than
the count in the MAXWAIT field.
Value Description
1
A WFIFO Full, a Read Stalled, or a Timeout error has occurred.
0
An error has not occurred.
To determine which error occurred, read the status of the EPI Error
Interrupt Status and Clear (EPIEISC) register. This bit is cleared by
writing a 1 to the bit in the EPIEISC register that caused the interrupt.
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External Peripheral Interface (EPI)
Register 31: EPI Masked Interrupt Status (EPIMIS), offset 0x218
This register is the masked interrupt status register. On read, it gives the current state of each
interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no
effect.
The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register,
the interrupt is sent to the interrupt controller.
EPI Masked Interrupt Status (EPIMIS)
Base 0x400D.0000
Offset 0x218
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
WRMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
2
1
0
WRMIS
RDMIS
ERRMIS
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write Masked Interrupt Status
Value Description
1
RDMIS
RO
0
1
The number of available entries in the WFIFO is within the range
specified by the trigger level (the WRFIFO field in the
EPIFIFOLVL register) and the WRIM bit in the EPIIM register is
set, triggering an interrupt to the interrupt controller.
0
The number of available entries in the WFIFO is above the range
specified by the trigger level or the interrupt is masked.
Read Masked Interrupt Status
Value Description
0
ERRMIS
RO
0
1
The number of valid entries in the NBRFIFO is within the range
specified by the trigger level (the RDFIFO field in the
EPIFIFOLVL register) and the RDIM bit in the EPIIM register is
set, triggering an interrupt to the interrupt controller.
0
The number of valid entries in the NBRFIFO is below the range
specified by the trigger level or the interrupt is masked.
Error Masked Interrupt Status
Value Description
1
A WFIFO Full, a Read Stalled, or a Timeout error has occurred
and the ERIM bit in the EPIIM register is set, triggering an
interrupt to the interrupt controller.
0
An error has not occurred or the interrupt is masked.
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Register 32: EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C
This register is used to clear a pending error interrupt. If any of these bits are set, the ERRRIS bit
in the EPIRIS register is set, and an EPI controller error is sent to the interrupt controller if the ERIM
bit in the EPIIM register is set. Clearing any defined bit has no effect; setting a bit clears the error
source and the raw error returns to 0. Note that writing to this register and reading back immediately
(pipelined by the processor) returns the old register contents. One cycle is needed between write
and read.
EPI Error Interrupt Status and Clear (EPIEISC)
Base 0x400D.0000
Offset 0x21C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
8
7
6
5
4
3
2
1
0
WTFULL
RSTALL
TOUT
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W1C
0
R/W1C
0
R/W1C
0
reserved
Type
Reset
reserved
Type
Reset
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2
WTFULL
R/W1C
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write FIFO Full Error
Value Description
1
The WFERR bit is enabled and a write is stalled due to the WFIFO
being full.
0
The WFERR bit is not enabled or no writes are stalled.
Writing a 1 to this bit clears it and the WFERR bit in the EPIFIFOLVL
register.
1
RSTALL
R/W1C
0
Read Stalled Error
Value Description
1
The RSERR bit is enabled and a pending read is stalled due to
writes in the WFIFO.
0
The RSERR bit is not enabled pr no pending reads are stalled.
Writing a 1 to this bit clears it and the RSERR bit in the EPIFIFOLVL
register.
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External Peripheral Interface (EPI)
Bit/Field
Name
Type
Reset
0
TOUT
R/W1C
0
Description
Timeout Error
This bit is the timeout error source. The timeout error occurs when the
iRDY or XFIFO not-ready signals hold a transaction for more than the
count in theMAXWAIT field (when not 0).
Value Description
1
A timeout error has occurred.
0
No timeout error has occurred.
Writing a 1 to bit this clears it.
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Stellaris® LM3S9B95 Microcontroller
11
General-Purpose Timers
Programmable timers can be used to count or time external events that drive the Timer input pins.
®
The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer 0, Timer
1, Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as
Timer A and Timer B) that can be configured to operate independently as timers or event counters,
or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also
be used to trigger μDMA transfers.
In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger
signals from all of the general-purpose timers are ORed together before reaching the ADC module,
so only one timer should be used to trigger ADC events.
®
The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer
resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 80) and the
PWM timer in the PWM module (see “PWM Timer” on page 1032).
The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional
options:
■ Count up or down
■ 16- or 32-bit programmable one-shot timer
■ 16- or 32-bit programmable periodic timer
■ 16-bit general-purpose timer with an 8-bit prescaler
■ 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
■ Eight Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ ADC event trigger
■ User-enabled stalling when the controller asserts CPU Halt flag during debug (excluding RTC
mode)
■ 16-bit input-edge count- or time-capture modes
■ 16-bit PWM mode with software-programmable output inversion of the PWM signal
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine.
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
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General-Purpose Timers
11.1
Block Diagram
Figure 11-1. GPTM Module Block Diagram
0x0000 (Down Counter Modes)
0xFFFF (Up Counter Modes)
Timer A
Free-Running
Value
Timer A Control
GPTMTAPMR
GPTMTAPR
TA Comparator
GPTMTAMATCHR
Clock / Edge
Detect
GPTMTAILR
Interrupt / Config
Timer A
Interrupt
GPTMTAMR
GPTMTAR En
GPTMCTL
GPTMTAV
GPTMIMR
Timer B
Interrupt
32 KHz or
Even CCP Pin
GPTMCFG
RTC Divider
GPTMRIS
GPTMTBV
GPTMMIS
GPTMICR
GPTMTBR En
Clock / Edge
Detect
Timer B Control
GPTMTAMR
GPTMTAILR
Odd CCP Pin
TB Comparator
GPTMTAMATCHR
Timer B
Free-Running
Value
GPTMTAPR
GPTMTAPMR
0x0000 (Down Counter Modes)
0xFFFF (Up Counter Modes)
System
Clock
Note:
In Figure 11-1 on page 434, the specific Capture Compare PWM (CCP) pins available depend
®
on the Stellaris device. See Table 11-1 on page 434 for the available CCP pins and their
timer assignments
Table 11-1. Available CCP Pins
Timer
16-Bit Up/Down Counter
Even CCP Pin
Odd CCP Pin
Timer 0
Timer A
CCP0
-
Timer B
-
CCP1
Timer A
CCP2
-
Timer B
-
CCP3
Timer A
CCP4
-
Timer B
-
CCP5
Timer A
CCP6
-
Timer B
-
CCP7
Timer 1
Timer 2
Timer 3
11.2
Signal Description
Table 11-2 on page 435 and Table 11-3 on page 436 list the external signals of the GP Timer module
and describe the function of each. The GP Timer signals are alternate functions for some GPIO
signals and default to be GPIO signals at reset. The column in the table below titled "Pin Mux/Pin
Assignment" lists the possible GPIO pin placements for these GP Timer signals. The AFSEL bit in
the GPIO Alternate Function Select (GPIOAFSEL) register (page 328) should be set to choose
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the GP Timer function. The number in parentheses is the encoding that must be programmed into
the PMCn field in the GPIO Port Control (GPIOPCTL) register (page 346) to assign the GP Timer
signal to the specified GPIO port pin. For more information on configuring GPIOs, see
“General-Purpose Input/Outputs (GPIOs)” on page 304.
Table 11-2. Signals for General-Purpose Timers (100LQFP)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CCP0
13
22
23
39
42
55
66
72
91
97
PD3 (4)
PC7 (4)
PC6 (6)
PJ2 (9)
PF4 (1)
PJ7 (10)
PB0 (1)
PB2 (5)
PB5 (4)
PD4 (1)
I/O
TTL
Capture/Compare/PWM 0.
CCP1
24
25
34
54
67
90
96
100
PC5 (1)
PC4 (9)
PA6 (2)
PJ6 (10)
PB1 (4)
PB6 (1)
PE3 (1)
PD7 (3)
I/O
TTL
Capture/Compare/PWM 1.
CCP2
6
11
25
41
53
67
75
91
95
98
PE4 (6)
PD1 (10)
PC4 (5)
PF5 (1)
PJ5 (10)
PB1 (1)
PE1 (4)
PB5 (6)
PE2 (5)
PD5 (1)
I/O
TTL
Capture/Compare/PWM 2.
CCP3
6
23
24
35
61
72
74
97
PE4 (1)
PC6 (1)
PC5 (5)
PA7 (7)
PF1 (10)
PB2 (4)
PE0 (3)
PD4 (2)
I/O
TTL
Capture/Compare/PWM 3.
CCP4
22
25
35
52
95
98
PC7 (1)
PC4 (6)
PA7 (2)
PJ4 (10)
PE2 (1)
PD5 (2)
I/O
TTL
Capture/Compare/PWM 4.
CCP5
5
12
25
36
90
91
PE5 (1)
PD2 (4)
PC4 (1)
PG7 (8)
PB6 (6)
PB5 (2)
I/O
TTL
Capture/Compare/PWM 5.
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General-Purpose Timers
Table 11-2. Signals for General-Purpose Timers (100LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CCP6
10
12
50
75
86
91
PD0 (6)
PD2 (2)
PJ3 (10)
PE1 (5)
PH0 (1)
PB5 (3)
I/O
TTL
Capture/Compare/PWM 6.
CCP7
11
13
85
90
96
PD1 (6)
PD3 (2)
PH1 (1)
PB6 (2)
PE3 (5)
I/O
TTL
Capture/Compare/PWM 7.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 11-3. Signals for General-Purpose Timers (108BGA)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CCP0
H1
L2
M2
K6
K4
L12
E12
A11
B7
B5
PD3 (4)
PC7 (4)
PC6 (6)
PJ2 (9)
PF4 (1)
PJ7 (10)
PB0 (1)
PB2 (5)
PB5 (4)
PD4 (1)
I/O
TTL
Capture/Compare/PWM 0.
CCP1
M1
L1
L6
L10
D12
A7
B4
A2
PC5 (1)
PC4 (9)
PA6 (2)
PJ6 (10)
PB1 (4)
PB6 (1)
PE3 (1)
PD7 (3)
I/O
TTL
Capture/Compare/PWM 1.
CCP2
B2
G2
L1
K3
K12
D12
A12
B7
A4
C6
PE4 (6)
PD1 (10)
PC4 (5)
PF5 (1)
PJ5 (10)
PB1 (1)
PE1 (4)
PB5 (6)
PE2 (5)
PD5 (1)
I/O
TTL
Capture/Compare/PWM 2.
CCP3
B2
M2
M1
M6
H12
A11
B11
B5
PE4 (1)
PC6 (1)
PC5 (5)
PA7 (7)
PF1 (10)
PB2 (4)
PE0 (3)
PD4 (2)
I/O
TTL
Capture/Compare/PWM 3.
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Table 11-3. Signals for General-Purpose Timers (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin
Assignment
a
Pin Type
Buffer Type
Description
CCP4
L2
L1
M6
K11
A4
C6
PC7 (1)
PC4 (6)
PA7 (2)
PJ4 (10)
PE2 (1)
PD5 (2)
I/O
TTL
Capture/Compare/PWM 4.
CCP5
B3
H2
L1
C10
A7
B7
PE5 (1)
PD2 (4)
PC4 (1)
PG7 (8)
PB6 (6)
PB5 (2)
I/O
TTL
Capture/Compare/PWM 5.
CCP6
G1
H2
M10
A12
C9
B7
PD0 (6)
PD2 (2)
PJ3 (10)
PE1 (5)
PH0 (1)
PB5 (3)
I/O
TTL
Capture/Compare/PWM 6.
CCP7
G2
H1
C8
A7
B4
PD1 (6)
PD3 (2)
PH1 (1)
PB6 (2)
PE3 (5)
I/O
TTL
Capture/Compare/PWM 7.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
11.3
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as Timer A and Timer B), two 16-bit match registers, two prescaler match registers, two 16-bit
shadow registers, and two 16-bit load/initialization registers and their associated control functions.
The exact functionality of each GPTM is controlled by software and configured through the register
interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 450),
the GPTM Timer A Mode (GPTMTAMR) register (see page 451), and the GPTM Timer B Mode
(GPTMTBMR) register (see page 453). When in one of the 32-bit modes, the timer can only act as
a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers
configured in any combination of the 16-bit modes.
11.3.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters Timer A and Timer B are initialized to
0xFFFF, along with their corresponding load registers: the GPTM Timer A Interval Load
(GPTMTAILR) register (see page 468) and the GPTM Timer B Interval Load (GPTMTBILR) register
(see page 469) and shadow registers: the GPTM Timer A Value (GPTMTAV) register (see page 479)
and the GPTM Timer B Value (GPTMTBV) register (see page 480). The prescale counters are
initialized to 0x00: the GPTM Timer A Prescale (GPTMTAPR) register (see page 472) and the GPTM
Timer B Prescale (GPTMTBPR) register (see page 473).
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11.3.2
32-Bit Timer Operating Modes
This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their
configurations.
The GPTM is placed into 32-bit mode by writing a 0x0 (One-Shot/Periodic 32-bit timer mode) or a
0x1 (RTC mode) to the GPTMCFG bit field in the GPTM Configuration (GPTMCFG) register. In both
configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These
registers include:
■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 468
■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 469
■ GPTM Timer A (GPTMTAR) register [15:0], see page 476
■ GPTM Timer B (GPTMTBR) register [15:0], see page 477
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 479
■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 480
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a 32-bit read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
A 32-bit read access to GPTMTAV returns the value:
GPTMTBV[15:0]:GPTMTAV[15:0]
11.3.2.1
32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the Timer A and Timer
B registers are configured as a 32-bit up or down counter. The selection of one-shot or periodic
mode is determined by the value written to the TAMR field of the GPTM Timer A Mode (GPTMTAMR)
register (see page 451); there is no need to write to the GPTM Timer B Mode (GPTMTBMR) register.
The timer is configured to count up or down using the TACDIR bit in the GPTMTAMR register.
When software sets the TAEN bit in the GPTM Control (GPTMCTL) register (see page 455), the
timer begins counting up from 0x0000.0000 or down from its preloaded value. Alternatively, if the
TAWOT bit is set in the GPTMTAMR register, once the TAEN bit is set, the timer waits for a trigger
to begin counting (see “Wait-for-Trigger Mode” on page 444).
When the timer is counting down and it reaches the time-out event (0x0000.0000), the timer reloads
its start value from the concatenated GPTMTAILR on the next cycle. When the timer is counting
up and it reaches the time-out event (the value in the concatenated GPTMTAILR), the timer starts
counting again from 0x0000.0000 on the next cycle. If configured to be a one-shot timer, the timer
stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer,
it continues counting. In periodic, snap-shot mode (TASNAPS bit in the GPTMTAMR register is set),
the actual free-running value of the timer at the time-out event is loaded into the GPTMTAR register.
In this manner, software can determine the time elapsed from the interrupt assertion to the ISR
entry.
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In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the time-out event. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS)
register (see page 460), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR)
register (see page 466). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR)
register (see page 458), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status
(GPTMMIS) register (see page 463). By setting the TAMIE bit in the GPTMTAMR register, an interrupt
can also be generated when the Timer A value equals the value loaded into the GPTM Timer A
Match (GPTMTAMATCH) register. This interrupt has the same status, masking, and clearing
functions as the time-out interrupt. The ADC trigger is enabled by setting the TAOTE bit in GPTMCTL.
The μDMA trigger is enabled by configuring and enabling the appropriate μDMA channel. See
“Channel Configuration” on page 250.
If software updates the GPTMTAILR register while the counter is counting down, the counter loads
the new value on the next clock cycle and continues counting down from the new value. If software
updates the GPTM Timer A Value (GPTMTAV) register while the counter is counting up or down,
the counter loads the new value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
11.3.2.2
32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time after reset, the
counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the
GPTM Timer A Interval Load (GPTMTAILR) register (see page 468).
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1-Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in
the GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues
counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When
the timer value reaches 0xFFFF.FFFF, the timer rolls over and continues counting up from 0x0. If
the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 250.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
11.3.3
16-Bit Timer Operating Modes
The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration
(GPTMCFG) register (see page 450). This section describes each of the GPTM 16-bit modes of
operation. Timer A and Timer B have identical modes, so a single description is given using an n
to reference both.
11.3.3.1
16-Bit One-Shot/Periodic Timer Mode
In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit up or down-counter
with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits.
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timer n Prescale
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(GPTMTnPR) register. The timer is configured to count up or down using the TnCDIR bit in the
GPTMTnMR register.
When software sets the TnEN bit in the GPTMCTL register, the timer begins counting up from
0x0000.0000 or down from its preloaded value. Alternatively, if the TnWOT bit is set in the GPTMTnMR
register, once the TnEN bit is set, the timer waits for a trigger to begin counting (see “Wait-for-Trigger
Mode” on page 444).
When the timer is counting down and it reaches the time-out event (0x0000), the timer reloads its
start value from the concatenated GPTMTnILR and GPTMTnPR on the next cycle. When the timer
is counting up and it reaches the time-out event (the value in the GPTMTnILR), the timer starts
counting again from 0x0000 on the next cycle. If configured to be a one-shot timer, the timer stops
counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it
continues counting. In periodic, snap-shot mode, (TnSNAPS bit in the GPTMTnMR register is set),
the actual free-running value of the timer at the time-out event is loaded into the GPTMTAR register.
In this manner, software can determine the time elapsed from the interrupt assertion to the ISR
entry.
In addition to reloading the count value, the timer generates interrupts and triggers when it reaches
the time-out event. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it
is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the
GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. By setting the
TnMIE bit in the GPTMTnMR register, an interrupt can also be generated when the timer value
equals the value loaded into the GPTM Timer n Match (GPTMTnMATCH) register. This interrupt
has the same status, masking, and clearing functions as the time-out interrupt. The ADC trigger is
enabled by setting the TnOTE bit in the GPTMCTL register. The μDMA trigger is enabled by
configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 250.
If software updates the GPTMTnILR register while the counter is counting down, the counter loads
the new value on the next clock cycle and continues counting down from the new value. If software
updates the GPTM Timer n Value (GPTMTnV) register while the counter is counting up or down,
the counter loads the new value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
The following example shows a variety of configurations for a 16-bit free-running timer while using
the prescaler. All values assume an 80-MHz clock with Tc=12.5 ns (clock period).
Table 11-4. 16-Bit Timer With Prescaler Configurations
a
Prescale
#Clock (Tc)
Max Time
Units
00000000
1
0.8192
mS
00000001
2
1.6384
mS
00000010
3
2.4576
mS
------------
--
--
--
11111101
254
208.0768
mS
11111110
255
208.896
mS
11111111
256
209.7152
mS
a. Tc is the clock period.
11.3.3.2
Input Edge-Count Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
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for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Count mode, the timer is configured as a 24-bit down-counter with the MSB stored in the
GPTM Timer n Prescale (GPTMTnPR) register and the remaining 16 bits in the GPTMTnILR
register. In this mode, the timer is capable of capturing three types of events: rising edge, falling
edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register
must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of the
GPTMCTL register. During initialization, the GPTM Timer n Match (GPTMTnMATCHR) register is
configured so that the difference between the value in the GPTMTnILR register and the
GPTMTnMATCHR register equals the number of edge events that must be counted.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count
matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the
GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked).
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 250.
The counter is then reloaded using the value in GPTMTnILR, and stopped because the GPTM
automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached,
all further events are ignored until TnEN is re-enabled by software.
Figure 11-2 on page 441 shows how Input Edge-Count mode works. In this case, the timer start
value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so
that four edge events are counted. The counter is configured to detect both edges of the input signal.
Note that the last two edges are not counted since the timer automatically clears the TnEN bit after
the current count matches the value in the GPTMnMR register.
Figure 11-2. 16-Bit Input Edge-Count Mode Example
Count
Timer stops,
flags
asserted
Timer reload
on next cycle
Ignored
Ignored
0x000A
0x0009
0x0008
0x0007
0x0006
Input Signal
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11.3.3.3
16-Bit Input Edge-Time Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
The prescaler is not available in 16-Bit Input Edge-Time mode.
In Edge-Time mode, the timer is configured as a 16-bit free-running down-counter. In this mode,
the timer is initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). In this
mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. The
timer is placed into Edge-Time mode by setting the TnCMR bit in the GPTMTnMR register, and the
type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register.
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture.
When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR
register and is available to be read by the microcontroller. The GPTM then asserts the CnERIS bit
(and the CnEMIS bit, if the interrupt is not masked). The GPTMTnV is the free-running value of the
timer and can be read to determine the time that elapsed between the interrupt assertion and the
entry into the ISR.
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 250.
After an event has been captured, the timer does not stop counting. It continues to count until the
TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the
GPTMnILR register.
Figure 11-3 on page 443 shows how input edge timing mode works. In the diagram, it is assumed
that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture
rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR
register, and is held there until another rising edge is detected (at which point the new count value
is loaded into GPTMTnR).
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Figure 11-3. 16-Bit Input Edge-Time Mode Example
Count
0xFFFF
GPTMTnR=X
GPTMTnR=Y
GPTMTnR=Z
Z
X
Y
Time
Input Signal
11.3.3.4
16-Bit PWM Mode
Note:
The prescaler is not available in 16-Bit PWM mode.
The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a
down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM
frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM
mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down
until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from
GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL
register. No interrupts or status bits are asserted in PWM mode.
The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its
start state), and is deasserted when the counter value equals the value in the GPTM Timer n Match
Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by
setting the TnPWML bit in the GPTMCTL register.
Figure 11-4 on page 444 shows how to generate an output PWM with a 1-ms period and a 66% duty
cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML
=1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is
GPTMnMR=0x411A.
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Figure 11-4. 16-Bit PWM Mode Example
Count
GPTMTnR=GPTMnMR
GPTMTnR=GPTMnMR
0xC350
0x411A
Time
TnEN set
TnPWML = 0
Output
Signal
TnPWML = 1
11.3.3.5
Wait-for-Trigger Mode
The Wait-for-Trigger mode allows daisy chaining of the timer modules such that once configured,
a single timer can initiate mulitple timing events using the Timer triggers. Wait-for-Trigger mode is
enabled by setting the TnWOT bit in the GPTMTnMR register. When the TnWOT bit is set, Timer N+1
does not begin counting until the timer in the previous position in the daisy chain (Timer N) reaches
its time-out event. The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2
follows GPTM1, and so on. If Timer A is in 32-bit mode (controlled by the GPTMCFG bit in the
GPTMCFG register), it triggers Timer A in the next module. If Timer A is in 16-bit mode, it triggers
Timer B in the same module, and Timer B triggers Timer A in the next module. Care must be taken
that the TAWOT bit is never set in GPTM0. Figure 11-5 on page 444 shows how the GPTMCFG bit
affects the daisy chain. This function is valid for both one-shot and periodic modes.
Figure 11-5. Timer Daisy Chain
GP Timer N+1
1
0
GPTMCFG
Timer B ADC Trigger
Timer B
Timer A
Timer A ADC Trigger
GP Timer N
1
0
GPTMCFG
Timer B
Timer A
Timer B ADC Trigger
Timer A ADC Trigger
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11.3.4
DMA Operation
The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA
controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs.
The arbitration size of the μDMA transfer should be set to the amount of data that should be
transferred whenever a timer event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a
periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of
8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items
have been transferred.
No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct
Memory Access (μDMA)” on page 246 for more details about programming the μDMA controller.
11.4
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register (see page 181). If using any CCP pins,
the clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System
Control module (see page 193). To find out which GPIO port to enable, refer to Table 25-4 on page 1151.
Configure the PMCn fields in the GPIOPCTL register to assign the CCP signals to the appropriate
pins (see page 346 and Table 25-5 on page 1160).
This section shows module initialization and configuration examples for each of the supported timer
modes.
11.4.1
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000.
3. Configure the TAMR field in the GPTM Timer A Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Optionally configure the TASNAPS, TAWOT, TAMTE, and TACDIR bits in the GPTMTAMR register
to select whether to capture the value of the free-running timer at time-out, use an external
trigger to start counting, configure an additional trigger or interrupt, and count up or down.
5. Load the start value into the GPTM Timer A Interval Load Register (GPTMTAILR).
6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register
(GPTMIMR).
7. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases,
the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear
Register (GPTMICR).
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If the TAMIE bit in the GPTMTAMR register is set, the RTCRIS bit in the GPTMRIS register is set,
and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out
event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads
the timer and continues counting after the time-out event.
11.4.2
32-Bit Real-Time Clock (RTC) Mode
To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To
enable the RTC feature, follow these steps:
1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0001.
3. Write the match value to the GPTM Timer A Match Register (GPTMTAMATCHR).
4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as needed.
5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR).
6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded
with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared.
11.4.3
16-Bit One-Shot/Periodic Timer Mode
A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0004.
3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register:
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Optionally configure the TnSNAPS, TnWOT, TnMTE and TnCDIR bits in the GPTMTnMR register
to select whether to capture the value of the free-running timer at time-out, use an external
trigger to start counting, configure an additional trigger or interrupt, and count up or down.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR).
7. If interrupts are required, set the appropriate bit in the GPTM Interrupt Mask Register
(GPTMIMR).
8. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start
counting.
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9. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases,
the status flags are cleared by writing a 1 the appropriate bit of the GPTM Interrupt Clear
Register (GPTMICR).
If the TnMIE bit in the GPTMTnMR register is set, the RTCRIS bit in the GPTMRIS register is set,
and the timer continues counting. In One-Shot mode, the timer stops counting after the time-out
event. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode reloads
the timer and continues counting after the time-out event.
11.4.4
Input Edge-Count Mode
A timer is configured to Input Edge-Count mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR
field to 0x3.
4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
7. Load the event count into the GPTM Timer n Match (GPTMTnMATCHR) register.
8. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
9. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events.
10. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM
Interrupt Clear (GPTMICR) register.
In Input Edge-Count Mode, the timer stops after the programmed number of edge events has been
detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 447
through step 9 on page 447.
11.4.5
16-Bit Input Edge Timing Mode
A timer is configured to Input Edge Timing mode by the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR
field to 0x3.
4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM
Control (GPTMCTL) register.
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5. If a prescaler is to be used, write the prescale value to the GPTM Timer n Prescale Register
(GPTMTnPR).
6. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
7. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register.
8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting.
9. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timer n (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
11.4.6
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x0000.0004.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register.
6. Load the GPTM Timer n Match (GPTMTnMATCHR) register with the match value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
11.5
Register Map
Table 11-5 on page 449 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■
■
■
■
Timer0: 0x4003.0000
Timer1: 0x4003.1000
Timer2: 0x4003.2000
Timer3: 0x4003.3000
Note that the GP Timer module clock must be enabled before the registers can be programmed
(see page 181).
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Table 11-5. Timers Register Map
Name
Type
Reset
0x000
GPTMCFG
R/W
0x0000.0000
GPTM Configuration
450
0x004
GPTMTAMR
R/W
0x0000.0000
GPTM Timer A Mode
451
0x008
GPTMTBMR
R/W
0x0000.0000
GPTM Timer B Mode
453
0x00C
GPTMCTL
R/W
0x0000.0000
GPTM Control
455
0x018
GPTMIMR
R/W
0x0000.0000
GPTM Interrupt Mask
458
0x01C
GPTMRIS
RO
0x0000.0000
GPTM Raw Interrupt Status
460
0x020
GPTMMIS
RO
0x0000.0000
GPTM Masked Interrupt Status
463
0x024
GPTMICR
W1C
0x0000.0000
GPTM Interrupt Clear
466
0x028
GPTMTAILR
R/W
0xFFFF.FFFF
GPTM Timer A Interval Load
468
0x02C
GPTMTBILR
R/W
0x0000.FFFF
GPTM Timer B Interval Load
469
0x030
GPTMTAMATCHR
R/W
0xFFFF.FFFF
GPTM Timer A Match
470
0x034
GPTMTBMATCHR
R/W
0x0000.FFFF
GPTM Timer B Match
471
0x038
GPTMTAPR
R/W
0x0000.0000
GPTM Timer A Prescale
472
0x03C
GPTMTBPR
R/W
0x0000.0000
GPTM Timer B Prescale
473
0x040
GPTMTAPMR
R/W
0x0000.0000
GPTM TimerA Prescale Match
474
0x044
GPTMTBPMR
R/W
0x0000.0000
GPTM TimerB Prescale Match
475
0x048
GPTMTAR
RO
0xFFFF.FFFF
GPTM Timer A
476
0x04C
GPTMTBR
RO
0x0000.FFFF
GPTM Timer B
477
0x050
GPTMTAV
RW
0xFFFF.FFFF
GPTM Timer A Value
479
0x054
GPTMTBV
RW
0x0000.FFFF
GPTM Timer B Value
480
11.6
Description
See
page
Offset
Register Descriptions
The remainder of this section lists and describes the GPTM registers, in numerical order by address
offset.
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Register 1: GPTM Configuration (GPTMCFG), offset 0x000
This register configures the global operation of the GPTM module. The value written to this register
determines whether the GPTM is in 32- or 16-bit mode.
GPTM Configuration (GPTMCFG)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x000
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
3
2
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:3
reserved
RO
0x0000.000
2:0
GPTMCFG
R/W
0x0
GPTMCFG
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Configuration
The GPTMCFG values are defined as follows:
Value Description
0x0
32-bit timer configuration.
0x1
32-bit real-time clock (RTC) counter configuration.
0x2
Reserved
0x3
Reserved
0x4
16-bit timer configuration. The function is controlled by bits 1:0
of GPTMTAMR and GPTMTBMR.
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Stellaris® LM3S9B95 Microcontroller
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TAAMS bit , clear the TACMR bit, and configure the TAMR field to
0x2.
In 16-bit timer configuration, TAMR controls the 16-bit timer modes for Timer A. In 32-bit timer
configuration, this register controls the mode, and the contents of GPTMTBMR are ignored.
GPTM Timer A Mode (GPTMTAMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x004
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
1
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
TASNAPS TAWOT
RO
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
TASNAPS
R/W
0
RO
0
R/W
0
R/W
0
5
4
3
2
TAMIE
TACDIR
TAAMS
TACMR
R/W
0
R/W
0
R/W
0
R/W
0
0
TAMR
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer A Snap-Shot Mode
Value Description
6
TAWOT
R/W
0
0
Snap-shot mode is disabled.
1
If Timer A is configured in the periodic mode, the actual
free-running value of Timer A is loaded at the time-out event
into the GPTM Timer A (GPTMTAR) register.
GPTM Timer A Wait-on-Trigger
Value Description
0
Timer A begins counting as soon as it is enabled.
1
If Timer A is enabled (TAEN is set in the GPTMCTL register),
Timer A does not begin counting until it receives a trigger from
the timer in the previous position in the daisy chain, see Figure
11-5 on page 444. This function is valid for both one-shot and
periodic modes.
This bit must be clear for GP Timer Module 0, Timer A.
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General-Purpose Timers
Bit/Field
Name
Type
Reset
5
TAMIE
R/W
0
Description
GPTM Timer A Match Interrupt Enable
Value Description
4
TACDIR
R/W
0
0
The match interrupt is disabled.
1
An interrupt is generated when the match value in the
GPTMTAMATCHR register is reached in the one-shot and
periodic modes.
GPTM Timer A Count Direction
Value Description
0
The timer counts down.
1
When in one-shot or periodic mode, the timer counts up. When
counting up, the timer starts from a value of 0x0000.
When in 16-bit PWM or 32-bit RTC mode, this bit must be clear; if this
bit is set, unpredictable behavior results.
3
TAAMS
R/W
0
GPTM Timer A Alternate Mode Select
The TAAMS values are defined as follows:
Value Description
0
Capture mode is enabled.
1
PWM mode is enabled.
Note:
2
TACMR
R/W
0
To enable PWM mode, you must also clear the TACMR
bit and configure the TAMR field to 0x2.
GPTM Timer A Capture Mode
The TACMR values are defined as follows:
Value Description
1:0
TAMR
R/W
0x0
0
Edge-Count mode
1
Edge-Time mode
GPTM Timer A Mode
The TAMR values are defined as follows:
Value Description
0x0
Reserved
0x1
One-Shot Timer mode
0x2
Periodic Timer mode
0x3
Capture mode
The Timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register (16-or 32-bit).
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Stellaris® LM3S9B95 Microcontroller
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008
This register configures the GPTM based on the configuration selected in the GPTMCFG register.
When in 16-bit PWM mode, set the TBAMS bit, clear the TBCMR bit, and configure the TBMR field to
0x2.
In 16-bit timer configuration, these bits control the 16-bit timer modes for Timer B. In 32-bit timer
configuration, this register’s contents are ignored, and GPTMTAMR is used.
GPTM Timer B Mode (GPTMTBMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x008
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
15
14
13
12
11
10
9
8
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
6
5
4
3
2
1
0
TBMIE
TBCDIR
TBAMS
TBCMR
R/W
0
R/W
0
R/W
0
R/W
0
reserved
Type
Reset
reserved
Type
Reset
TBSNAPS TBWOT
RO
0
Bit/Field
Name
Type
Reset
31:8
reserved
RO
0x0000.00
7
TBSNAPS
R/W
0
R/W
0
R/W
0
TBMR
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Snap-Shot Mode
Value Description
6
TBWOT
R/W
0
0
Snap-shot mode is disabled.
1
If Timer B is configured in the periodic mode, the actual
free-running value of Timer B is loaded at the time-out event
into the GPTM Timer B (GPTMTBR) register.
GPTM Timer B Wait-on-Trigger
Value Description
0
Timer B begins counting as soon as it is enabled.
1
If Timer B is enabled (TBEN is set in the GPTMCTL register),
Timer B does not begin counting until it receives an it receives
a trigger from the timer in the previous position in the daisy
chain. See Figure 11-5 on page 444. This function is valid for
both one-shot and periodic modes.
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General-Purpose Timers
Bit/Field
Name
Type
Reset
5
TBMIE
R/W
0
Description
GPTM Timer B Match Interrupt Enable
Value Description
4
TBCDIR
R/W
0
0
The match interrupt is disabled.
1
An interrupt is generated when the match value in the
GPTMTBMATCHR register is reached in the one-shot and
periodic modes.
GPTM Timer B Count Direction
Value Description
0
The timer counts down.
1
When in one-shot or periodic mode, the timer counts up. When
counting up, the timer starts from a value of 0x0000.
When in 16-bit PWM or 32-bit RTC mode, this bit must be clear; if this
bit is set, unpredictable behavior results.
3
TBAMS
R/W
0
GPTM Timer B Alternate Mode Select
The TBAMS values are defined as follows:
Value Description
0
Capture mode is enabled.
1
PWM mode is enabled.
Note:
2
TBCMR
R/W
0
To enable PWM mode, you must also clear the TBCMR
bit and set the TBMR field to 0x2.
GPTM Timer B Capture Mode
The TBCMR values are defined as follows:
Value Description
1:0
TBMR
R/W
0x0
0
Edge-Count mode
1
Edge-Time mode
GPTM Timer B Mode
The TBMR values are defined as follows:
Value Description
0x0
Reserved
0x1
One-Shot Timer mode
0x2
Periodic Timer mode
0x3
Capture mode
The timer mode is based on the timer configuration defined by bits 2:0
in the GPTMCFG register.
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Stellaris® LM3S9B95 Microcontroller
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
2
reserved
Type
Reset
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
15
14
13
12
reserved
TBPWML
TBOTE
reserved
RO
0
R/W
0
R/W
0
RO
0
TBEVENT
R/W
0
R/W
0
RO
0
RO
0
RO
0
9
8
7
6
5
4
TBSTALL
TBEN
reserved
TAPWML
TAOTE
RTCEN
R/W
0
R/W
0
RO
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:15
reserved
RO
0x0000
14
TBPWML
R/W
0
TAEVENT
R/W
0
R/W
0
1
0
TASTALL
TAEN
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B PWM Output Level
The TBPWML values are defined as follows:
Value Description
13
TBOTE
R/W
0
0
Output is unaffected.
1
Output is inverted.
GPTM Timer B Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0
The output Timer B ADC trigger is disabled.
1
The output Timer B ADC trigger is enabled.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 537).
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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General-Purpose Timers
Bit/Field
Name
Type
Reset
11:10
TBEVENT
R/W
0x0
Description
GPTM Timer B Event Mode
The TBEVENT values are defined as follows:
Value Description
9
TBSTALL
R/W
0
0x0
Positive edge
0x1
Negative edge
0x2
Reserved
0x3
Both edges
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
0
Timer B continues counting while the processor is halted by the
debugger.
1
Timer B freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TBSTALL bit is ignored.
8
TBEN
R/W
0
GPTM Timer B Enable
The TBEN values are defined as follows:
Value Description
0
Timer B is disabled.
1
Timer B is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
7
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
6
TAPWML
R/W
0
GPTM Timer A PWM Output Level
The TAPWML values are defined as follows:
Value Description
5
TAOTE
R/W
0
0
Output is unaffected.
1
Output is inverted.
GPTM Timer A Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0
The output Timer A ADC trigger is disabled.
1
The output Timer A ADC trigger is enabled.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 537).
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
4
RTCEN
R/W
0
Description
GPTM RTC Enable
The RTCEN values are defined as follows:
Value Description
3:2
TAEVENT
R/W
0x0
0
RTC counting is disabled.
1
RTC counting is enabled.
GPTM Timer A Event Mode
The TAEVENT values are defined as follows:
Value Description
1
TASTALL
R/W
0
0x0
Positive edge
0x1
Negative edge
0x2
Reserved
0x3
Both edges
GPTM Timer A Stall Enable
The TASTALL values are defined as follows:
Value Description
0
Timer A continues counting while the processor is halted by the
debugger.
1
Timer A freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TASTALL bit is ignored.
0
TAEN
R/W
0
GPTM Timer A Enable
The TAEN values are defined as follows:
Value Description
0
Timer A is disabled.
1
Timer A is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
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General-Purpose Timers
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
GPTM Interrupt Mask (GPTMIMR)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x018
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
7
11
10
9
8
TBMIM
CBEIM
CBMIM
TBTOIM
R/W
0
R/W
0
R/W
0
R/W
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
TBMIM
R/W
0
reserved
RO
0
RO
0
RO
0
4
3
2
1
0
TAMIM
RTCIM
CAEIM
CAMIM
TATOIM
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Mode Match Interrupt Mask
The TBMIM values are defined as follows:
Value Description
10
CBEIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Capture B Event Interrupt Mask
The CBEIM values are defined as follows:
Value Description
9
CBMIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Capture B Match Interrupt Mask
The CBMIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
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Stellaris® LM3S9B95 Microcontroller
Bit/Field
Name
Type
Reset
8
TBTOIM
R/W
0
Description
GPTM Timer B Time-Out Interrupt Mask
The TBTOIM values are defined as follows:
Value Description
7:5
reserved
RO
0x0
4
TAMIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer A Mode Match Interrupt Mask
The TAMIM values are defined as follows:
Value Description
3
RTCIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM RTC Interrupt Mask
The RTCIM values are defined as follows:
Value Description
2
CAEIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Capture A Event Interrupt Mask
The CAEIM values are defined as follows:
Value Description
1
CAMIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Capture A Match Interrupt Mask
The CAMIM values are defined as follows:
Value Description
0
TATOIM
R/W
0
0
Interrupt is disabled.
1
Interrupt is enabled.
GPTM Timer A Time-Out Interrupt Mask
The TATOIM values are defined as follows:
Value Description
0
Interrupt is disabled.
1
Interrupt is enabled.
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General-Purpose Timers
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
11
10
TBMRIS
CBERIS
R/W
0
RO
0
RO
0
RO
0
RO
0
9
8
7
CBMRIS TBTORIS
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
TBMRIS
R/W
0
RO
0
reserved
RO
0
RO
0
RO
0
4
3
2
TAMRIS
RTCRIS
CAERIS
R/W
0
RO
0
RO
0
CAMRIS TATORIS
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Mode Match Raw Interrupt
Value Description
1
The TBMIE bit is set in the GPTMTBMR register, and the match
value in the GPTMTBMATCHR register has been reached when
in the one-shot and periodic modes.
0
The match value has not been reached.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
10
CBERIS
RO
0
GPTM Capture B Event Raw Interrupt
Value Description
1
The Capture B event has occurred.
0
The Capture B event has not occurred.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
9
CBMRIS
RO
0
GPTM Capture B Match Raw Interrupt
Value Description
1
The Capture B match has occurred.
0
The Capture B match has not occurred.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
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Bit/Field
Name
Type
Reset
8
TBTORIS
RO
0
Description
GPTM Timer B Time-Out Raw Interrupt
Value Description
1
Timer B has timed out.
0
Timer B has not timed out.
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
7:5
reserved
RO
0x0
4
TAMRIS
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer A Mode Match Raw Interrupt
Value Description
1
The TAMIE bit is set in the GPTMTAMR register, and the match
value in the GPTMTAMATCHR register has been reached when
in the one-shot and periodic modes.
0
The match value has not been reached.
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR
register.
3
RTCRIS
RO
0
GPTM RTC Raw Interrupt
Value Description
1
The RTC event has occurred.
0
The RTC event has not occurred.
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR
register.
2
CAERIS
RO
0
GPTM Capture A Event Raw Interrupt
Value Description
1
The Capture A event has occurred.
0
The Capture A event has not occurred.
This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR
register.
1
CAMRIS
RO
0
GPTM Capture A Match Raw Interrupt
Value Description
1
The Capture A match has occurred.
0
The Capture A match has not occurred.
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR
register.
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General-Purpose Timers
Bit/Field
Name
Type
Reset
0
TATORIS
RO
0
Description
GPTM Timer A Time-Out Raw Interrupt
Value Description
1
Timer A has timed out.
0
Timer A has not timed out.
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR
register.
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Stellaris® LM3S9B95 Microcontroller
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
6
5
2
1
0
reserved
Type
Reset
RO
0
RO
0
RO
0
RO
0
15
14
13
12
reserved
Type
Reset
RO
0
RO
0
RO
0
11
TBMMIS
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
10
9
8
7
CBEMIS CBMMIS TBTOMIS
R/W
0
RO
0
RO
0
Bit/Field
Name
Type
Reset
31:12
reserved
RO
0x0000.0
11
TBMMIS
R/W
0
RO
0
reserved
RO
0
RO
0
RO
0
4
3
TAMMIS
RTCMIS
R/W
0
RO
0
CAEMIS CAMMIS TATOMIS
RO
0
RO
0
RO
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B Mode Match Masked Interrupt
Value Description
1
An unmasked Timer B Mode Match interrupt
has occurred.
0
A Timer B Mode Match interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
10
CBEMIS
RO
0
GPTM Capture B Event Masked Interrupt
Value Description
1
An unmasked Capture B event interrupt
has occurred.
0
A Capture B event interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
June 14, 2010
463
Texas Instruments-Advance Information
General-Purpose Timers
Bit/Field
Name
Type
Reset
9
CBMMIS
RO
0
Description
GPTM Capture B Match Masked Interrupt
Value Description
1
An unmasked Capture B Match interrupt
has occurred.
0
A Capture B Mode Match interrupt has not occurred or is
masked.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
8
TBTOMIS
RO
0
GPTM Timer B Time-Out Masked Interrupt
Value Description
1
An unmasked Timer B Time-Out interrupt
has occurred.
0
A Timer B Time-Out interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
7:5
reserved
RO
0x0
4
TAMMIS
R/W
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read