ON NCL30073 Current-mode pwm controller Datasheet

NCL30073
Current-Mode PWM
Controller for LED
Application
The NCL30073 is a highly integrated PWM controller capable of
delivering a rugged and high performance LED converter in a tiny
TSOP−6 package. With a supply range up to 24 V, the controller hosts
a 65 kHz switching circuitry operated in peak current mode control.
When the voltage on FB pin decreases, the controller enters skip cycle
while limiting the peak current.
Over Power Protection (OPP) is a difficult exercise especially when
no−load standby requirements drive the converter specifications. The
ON proprietary integrated OPP lets you harness the maximum
delivered power without affecting your standby performance simply
via two external resistors. An Over Voltage Protection is also
combined on the same pin but also on the VCC line. They offer an
efficient protection in case of adverse open loop operation.
Finally, a timer−based short−circuit protection offers the best
protection scheme, letting you precisely select the protection trip point
without caring of a loose coupling between the auxiliary and the power
windings.
Features
•
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Fixed−frequency 65 kHz Current−mode Control Operation
Internal and Adjustable Over Power Protection (OPP) Circuit
Internal Ramp Compensation
Internally Fixed 4 ms Soft−start
115 ms Timer−based Auto−recovery Short−circuit Protection
Protection − Autorecovery
♦ OVP by VCC
♦ OIP
♦ OTP − Foldback
♦ Short Circuit
Up to 24 V VCC Operation
Extremely Low No−load Standby Power
Isolated and Non−isolated Outputs
Good Regulation – 5%
High Power Factor > 0.9
Single Winding Inductor
Low Parts Count
EPS 2.0 Compliant
Pb−Free Devices
+300 mA/ −500 mA Source/Sink Drive Capability
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1
TSOP−6
CASE 318G−02
MARKING DIAGRAM
73AAYWG
G
1
73A = Specific Device Code
A
=Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
OPP
VCC
FB
DRV
CS
GND
TSOP−6 (Top view)
ORDERING INFORMATION
Device
Package
Shipping†
NCL30073SN065T1G
TSOP−6
(Pb−Free)
3000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Typical Application
• Dimmable Retrofit and Low Power Fixture LED Applications
• Phase Cut Dimmer Compatible – LE or TE Types
• Multiple Topology Support
♦
♦
♦
Buck
Buck Boost
Flyback
© Semiconductor Components Industries, LLC, 2017
May, 2017 − Rev. 1
1
Publication Order Number:
NCL30073/D
NCL30073
TYPICAL APPLICATION SCHEMATIC
Figure 1. Typical Non−isolated (Buck−Boost) Application
Figure 2. Typical Isolated (Flyback) Application Example
Table 1. PIN FUNCTION DESCRIPTION
Pin #
Pin Name
Function
1
OPP
Adjust the Over Power
Protection
2
FB
Feedback pin
3
CS
Current Sense + Slope
Compensation
4
GND
5
DRV
6
VCC
Pin Description
A resistive divider from the auxiliary winding to this pin sets the OPP compensation
level. When brought above 3 V, the part enters auto−recovery mode.
A voltage variation on this pin will allow regulation.
This pin monitors the primary peak current but also offers a means to introduce slope
compensation.
The controller ground.
Driver Output
The driver output to an external MOSFET gate.
Supplies the Controller − This pin is connected to an external auxiliary voltage. When the VCC exceeds
Protects the IC
a certain level, the part enters an auto−recovery hiccup mode.
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NCL30073
INTERNAL CIRCUIT ARCHITECTURE
OVP /OTP
V CC(OVP )
DRV stop
OPP
Auto-recovery
management
VCC (min)
Auto-recovery
mode
V OPP
OCP Fault
Auto-recovery
mode
IC start
+
RST
IC stop
t latch(del )
Up Counter
to 4
_
+
Vl atch
OVP/OTP
Internal
supply
DRV pulse
tlatch(blank )
V CC and logic
management
IC reset
V CC(OVP )
VCC
+
t
_
OVP (del)
+
V
OVP
Clamp
DRV pulse
DRV
pulse
65 kHz
Oscillator
Rramp
D max
S
Q
R
Q
DRV
IC stop
DRV pulse
DRV stop
_
+
+
V skip
VFB(open )
IC in regulation
R eq
K ratio
FB
Up counter
to 8
_
+
RST
peak current
freeze
Error
flag
Soft-start
R
Q
S
Q
+
LEB
VOPP
+
Vlimit + VOPP
RST
Fault timer
OCP
Fault
_
CS
+
Vlimit
GND
Figure 3. Internal Circuit Architecture
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NCL30073
Table 2. MAXIMUM RATINGS TABLE
Symbol
Rating
VCC
Power Supply voltage, VCC pin, continuous voltage
VDRV(tran)
Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1)
VCS, VFB, VOPP
Value
Units
−0.3 to 35
V
−0.3 to VCC + 0.3
V
−0.3 to 5.5
V
Maximum voltage on low power pins CS, FB and OPP (Note 2)
VOPP(tran)
Maximum negative transient voltage on OPP pin (Note 2)
−1
V
Isource,max
Maximum sourced current, pulsed width < 800 ns
0.6
A
Isink,max
Maximum sinked current, pulse width < 800 ns
1.0
A
IOPP
Maximum injected negative current into the OPP pin (pin 1)
−2
mA
RθJ−A
Thermal Resistance Junction−to−Air
360
°C/W
TJ,max
Maximum Junction Temperature
Storage Temperature Range
HBM
Human Body Model ESD Capability per JEDEC JESD22−A114F (All pins)
CDM
Charged−Device Model ESD Capability per JEDEC JESD22−C101E
150
°C
−60 to +150
°C
4
kV
750
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.
2. See the Figure 4 for detailed specification of transient voltage.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
on−time
500 ns
t
0V
Max current during
overshoot can’t
exceed 3 mA
VCS
VFB
VOPP(t)
7.5 V
VOPP
–
Max transient
voltage
cycle−by−cycle
5.5 V
VOPP,max
–
Max DC
voltage
VOPP,max = −0.75 V, Tj = −25°C
VOPP,max = −0.65 V, Tj = 25°C
VOPP,max = −0.3 V, Tj = 125°C − Worst case
−1 V
VOPP
SOA
VOPP must stay between 0 V and −0.3 V for
a linear OPP operation
500 ns
0V
Figure 4. Negative Pulse for OPP Pin during On−time and Positive Pulse for all Low Power Pins
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t
NCL30073
Table 3. ELECTRICAL CHARACTERISTICS
For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted.
Symbol
Rating
Pin
Min
Typ
Max
Units
SUPPLY SECTION
VCC(on)
VCC increasing level at which driving pulses are authorized
6
16
18
20
V
VCC(min)
VCC decreasing level at which driving pulses are stopped
6
8.3
8.9
9.5
V
VCC(hyst)
Hysteresis VCC(on) – VCC(min)
6
7.7
−
−
V
VCC(reset)
Auto−recovery state reset voltage
6
−
8.6
−
V
Defined hysteresis between minimum and reset voltage
VCC(min) – VCC(reset)
6
0.15
0.30
0.45
V
ICC1
Start−up current (VCC(on) – 100 mV)
6
−
6
10
mA
ICC2
Internal IC consumption with VFB = 3.2 V, fSW = 65 kHz and
CL = 0 nF
6
−
1.0
1.4
mA
ICC3
Internal IC consumption with VFB = 3.2 V, fSW = 65 kHz and
CL = 1 nF
6
−
1.8
2.7
mA
ICC(no−load)
Internal consumption in skip mode – non switching, VFB = 0 V
6
−
300
−
mA
ICC(fault)
Internal consumption in fault mode – during going−down VCC
cycle, VFB = 4 V
6
0.6
0.9
1.2
mA
Internal IC consumption in skip mode for 65 kHz version
(VCC = 14 V, driving a typical 7 A / 600 V MOSFET, includes FB
pin current) – (Note 5)
6
−
420
−
mA
tr
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
5
−
25
−
ns
tf
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
5
−
30
−
ns
ROH
Source resistance, VCC = 12 V, IDRV = 100 mA
5
−
28
−
W
ROL
Sink resistance, VCC = 12 V, IDRV = 100 mA
5
−
7
−
W
Peak source current, VGS = 0 V (Note 4)
5
−
300
−
mA
VCC(reset_hyst)
ICC(standby)
DRIVE OUTPUT
Isource
Peak sink current, VGS = 12 V (Note 4)
5
−
500
−
mA
VDRV(low)
Isink
DRV pin level at VCC = VCC(min) + 100 mV with a 33 kW resistor
to GND
5
8
−
−
V
VDRV(high)
DRV pin level at VCC = VOVP – 100 mV (DRV unloaded)
5
10
12
14
V
0.744
0.720
0.810
0.810
0.856
0.880
260
−
mV
CURRENT COMPARATOR
Vlimit
Maximum internal current set point (pin 1 grounded)
TJ = 25°C
TJ = −40°C to 125°C
3
Internal peak current setpoint freeze (≈31% of Vlimit)
3
−
tDEL
Propagation delay from CS pin to DRV output
3
−
35
80
ns
tLEB
Leading Edge Blanking Duration
3
−
270
−
ns
tSS
Internal soft−start duration activated upon startup or
auto−recovery
3
−
4.1
−
ms
VCS(freeze)
V
IOPPs
Set point decrease for pin 1 grounded
1
−
0
−
%
IOPPo
Set point decrease for pin 1 biased to −250 mV (Note 4)
1
−
31.3
−
%
IOOPv
Voltage set point for pin 1 biased to −250 mV
TJ = 25°C
TJ = −40°C to 125°C
1
0.51
0.50
0.55
0.55
0.60
0.62
63.0
61.0
65.5
65.5
67.0
69.0
76
80
84
V
INTERNAL OSCILLATOR
fOSC(nom)
Dmax
Oscillation frequency
TJ = 25°C
TJ = −40°C to 125°C
−
Maximum duty−ratio
−
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5
kHz
%
NCL30073
Table 3. ELECTRICAL CHARACTERISTICS
For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 12 V unless otherwise noted.
Symbol
Rating
Pin
Min
Typ
Max
Units
FEEDBACK SECTION
Req
Internal equivalent feedback resistance
2
−
29
−
kW
Kratio
FB pin to current set point division ratio
−
−
4
−
−
VFB(freeze)
Feedback voltage below which the peak current is frozen
2
−
1
−
V
VFB(limit)
Feedback voltage corresponding with maximum internal current
set point
2
−
3.2
−
V
VFB(open)
Internal pull−up voltage on FB pin
2
−
4
−
V
Skip−cycle level voltage on the feedback pin
−
−
0.8
−
V
Hysteresis on the skip comparator (Note 4)
−
−
50
−
mV
SKIP SECTION
Vskip
Vskip(hyst)
INTERNAL SLOPE COMPENSATION
Vramp
Internal ramp level @ 25°C (Note 6)
3
−
2.5
−
V
Rramp
Internal ramp resistance to CS pin
3
−
20
−
kW
Fault level input on OPP pin
1
2.85
3.0
3.15
V
tlatch (blank)
Blanking time after Drive output turn off
1
−
1
−
ms
tlatch (count)
Number of clock cycles before fault is confirmed
1
−
4
−
PROTECTIONS
V(latch)
tlatch (del)
OVP/OTP delay time constant before fault is confirmed
1
−
600
−
ns
tfault
Internal auto−recovery fault timer duration
−
100
115
130
ms
VOVP
Over voltage protection on the VCC pin
6
24.0
25.5
27.0
V
Delay time constant before OVP on VCC is confirmed
6
−
20
−
ms
tOVP(del)
4. Guaranteed by design.
5. Application parameter for information only.
6. 1 MW resistor is connected from pin 3 to the ground for the measurement.
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NCL30073
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
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NCL30073
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
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NCL30073
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
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NCL30073
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
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NCL30073
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
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NCL30073
Figure 35.
Figure 36.
Figure 37.
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NCL30073
APPLICATION INFORMATION
• Auto−recovery Input:
Introduction
NCL30073 implements a standard current mode
architecture where the switch−off event is dictated by the
peak current set point. This component represents the ideal
candidate for LED applications. The NCL30073 packs all
the necessary components normally needed in today modern
LED converter designs, bringing several enhancements
such as a non−dissipative OPP, OVP/OTP implementation,
short−circuit protection, improved consumption, robustness
and ESD capabilities.
• Current−mode Operation with Internal Slope
Compensation:
Implementing peak current mode control at a 65 kHz
switching frequency, the NCL30073 offers an internal
slope compensation signal that can easily by summed
up to the sensed current. Sub harmonic oscillations can
thus be fought via the inclusion of a simple resistor in
series with the current−sense information.
• Internal OPP:
By routing a portion of the negative voltage present
during the on−time on the auxiliary winding to the
dedicated OPP pin (pin 1), the user has a simple and
non−dissipative means to alter the maximum peak
current set point as the bulk voltage increases. If the pin
is grounded, no OPP compensation occurs. If the pin
receives a negative voltage, then a peak current is
reduced down.
• Low Startup and Standby Current:
Reaching a low no−load standby power always
represents a difficult exercise when the controller draws
a significant amount of current during startup.
• Skip Capability:
A continuous flow of pulses is not desired in all
application. The controller monitors FB pin voltage and
when it reaches a level of Vskip, the controller enters
skip−cycle mode, to reduce number of switching
periods
• Internal Soft−start:
A soft−start precludes the main power switch from
being stressed upon start−up. The soft−start duration is
internally fixed for time tSS and it is activated during
new startup sequence or during recovering after
auto−recovery hiccup mode.
•
•
The controller includes an OPP input (pin 1) that can be
used to sense an over voltage or an over temperature
event on the converter. If this pin is brought higher than
the internal reference voltage Vlatch for four
consecutive cycles, then the circuit enters into
auto−recovery mode.
Auto−recovery OVP on VCC:
An OVP protects the circuit against VCC runaways. If
the fault is present at least for time tOVP(del) then the
OVP is validated and the controller enters hiccup mode.
When the VCC returns to a nominal level, the controller
resumes operation.
Short−circuit Protection:
Short−circuit and especially overload protections are
difficult to implement when a strong leakage
inductance between auxiliary and power windings
affects the transformer (the aux winding level does not
properly collapse in presence of an output short). In this
controller, every time the internal maximum peak
current limit Vlimit is activated (or less when OPP is
used), an error flag is asserted and a time period starts
thanks to an internal timer. When the timer has elapsed
while a fault is still present, the controller enters an
auto−recovery mode.
Start−up Sequence
The NCL30073 start−up voltage is made purposely high
to permit large energy storage in a small VCC capacitor
value. This helps operate with a small start−up current
which, together with a small VCC capacitor, will not hamper
the start−up time. To further reduce the standby power, the
start−up current of the controller is extremely low, below
10 mA. The start−up resistor can therefore be connected to
the bulk capacitor or directly to the mains input voltage to
further reduce the power dissipation.
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NCL30073
Rstart−up
+
Input
Cbulk
mains
VCC
+
+
CVCC
aux.
winding
Figure 38. The Startup Resistor can be Connected to the Input Mains for further Power Dissipation Reduction
The first step starts with the calculation of the needed
VCC capacitor which will supply the controller which it
operates until the auxiliary winding takes it over. Experience
shows that this time t1 can be between 5 and 20 ms. If we
consider we need at least an energy reservoir for a t1 time of
10 ms, the VCC capacitor must be larger than:
C VCC w
I CC @ t 1
w 1.6m @ 10m w 1.7 mF
18*8.9
V CC(on)*V CC(min)
This calculation is purely theoretical, considering a
constant charging current. In reality, the take over time can
be shorter (or longer!) and it can lead to a reduction of the
VCC capacitor. Thus, a decrease in charging current and an
increase of the start−up resistor can be experimentally
tested, for the benefit of standby power. Laboratory
experiments on the prototype are thus mandatory to fine tune
the converter. If we chose the 92 kW resistor as suggested by
Eq.4 , the dissipated power at high line amounts to:
(eq. 1)
Let us select a 2.2 mF capacitor at first and experiments in
the laboratory will let us know if we were too optimistic for
the time t1 . The VCC capacitor being known, we can now
evaluate the charging current we need to bring the VCC
voltage from 0 V to the VCC(on) of the IC. This current has
to be selected to ensure a start−up at the lowest mains
(85 Vrms) to be less than 200 ms (acceptable time):
I charge w
V CC(on) @ C VCC
18 @ 2.2 m
w
w 198 mA
t start*up
0.1
PR
Now that the first VCC capacitor has been selected, we
must ensure that the self−supply does not disappear when in
no−load conditions. In this mode, the skip−cycle can be so
deep that refreshing pulses are likely to be widely spaced,
inducing a large ripple on the VCC capacitor. If this ripple
is too large, chances exist to touch the VCC(min) and reset the
controller into a new start−up sequence. A solution is to
grow this capacitor but it will obviously be detrimental to the
start−up time. The option offered in Figure 38 elegantly
solves this potential issue by adding an extra capacitor on the
auxiliary winding. However, this component is separated
from the VCC pin via a simple diode. You therefore have the
ability to grow this capacitor as you need to ensure the
self−supply of the controller without affecting the start−up
time and standby power.
(eq. 2)
V ac,rmsǸ2
*V CC(on)
p
R start*up
Internal Over Power Protection
(eq. 3)
There are several known ways to implement Over Power
Protection (OPP), all suffering from particular problems.
These problems range from the added consumption burden
on the converter or the skip−cycle disturbance brought by
the current−sense offset. A way to reduce the power
capability at high line is to capitalize on the negative voltage
To make sure this current is always greater than 346 mA,
then, the minimum value for Rstart−up can be extracted:
R start*up v
V ac,rmsǸ2
*V CC(on)
p
I CVCC(min)
v
85Ǹ2
p *18
208 m
2
V ac,peak
(230 @ Ǹ2 ) 2
[
[ 287 mW
4 @ R start*up
4 @ 92k
(eq. 5)
If we account for the 10 mA (maximum) that will flow to
the controller, then the total charging current delivered by
the start−up resistor must be 208 mA. If we connect the
start−up network to the mains (half−wave connection then),
we know that the average current flowing into this start−up
resistor will be the smallest when VCC reaches the VCC(on)
of the controller:
I CVCC,min +
start*up,max
[
v 97 kW
(eq. 4)
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NCL30073
appears in Figure 40 and shows how the final peak current
set point is constructed.
Let’s assume we need to reduce the peak current from
2.5 A at low line, to 2 A at high line. This corresponds to a
20% reduction or a set point voltage of 640 mV. To reach this
level, then the negative voltage developed on the OPP pin
must reach:
swing present on the auxiliary diode anode. During the
turn−on time, this point dips to –N2 Vbulk , where N2 being the
turns ratio between the primary winding and the auxiliary
winding. The negative plateau observed on Figure 39 will
have amplitude depending on the input voltage. The idea
implemented in this chip is to sum a portion of this negative
swing with the internal voltage reference Vlimit = 0.8 V. For
instance, if the voltage swings down to −150 mV during the
on−time, then the internal peak current set point will be fixed
to the value 0.8 V – 0.150 V = 650 mV. The adopted principle
V OPP + 0.8 @ V limit*V limit + 0.64*0.8 + * 160 mV
(eq. 6)
40.0
off−time
Plot1 in Volts
20.0
N1(Vout + Vf)
1
0
−N2Vbulk
−20.0
on−time
−40.0
464u
472u
480u
488u
496u
time in seconds
Figure 39. The Signal Obtained on the Auxiliary Winding Swings Negative During the On−time
ROPPU
This point will be
adjusted to reduce
the „ref“ at hi line to
the desired level
swings to:
N 1V out during t off
−N 2V in during t on
V CC
+
aux.
winding
ref = 0.8V + V OPP
(V OPP is negative )
I OPP
driver reset
K1
K2
+
ROPPL
_
OPP
ref
SUM
+
V limit = 0.8 V ± 7%
CS
Rsense
Figure 40. The OPP Circuitry Affects the Maximum Peak Current Set Point by Summing a Negative Voltage to
the Internal Voltage Reference
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NCL30073
Short−Circuit Protection
The OPP pin is surrounded by Zener diodes stacked to
protect the pin against ESD pulses. These diodes accept
some peak current in the avalanche mode and are designed
to sustain a certain amount of energy. On the other side,
negative injection into these diodes (or forward bias) can
cause substrate injection which can lead to an erratic circuit
behavior. To avoid this problem, the pin is internal clamped
slightly below –300 mV which means that if more current is
injected before reaching the ESD forward drop, then the
maximum peak reduction is kept to 40%. If the voltage
finally forward biases the internal zener diode, then care
must be taken to avoid injecting a current beyond –2 mA.
Finally, please note that another comparator internally
fixes the maximum peak current set point to value Vlimit even
if the OPP pin is adversely biased above 0 V.
Short−circuit case I. → Error flag
raised → UVLO → auto−recovery
VCC(t)
In case of output short−circuit or if the LED converter
experiences a severe overloading situation, an internal error
flag is raised and the fault timer starts countdown. If the
UVLO has come (see Figure 41 – Short−circuit case I.) or the
error flag is asserted throughout the tfault time (see Figure 41
– Short−circuit case II.) – i.e. the fault timer has elapsed, the
driving pulses are stopped and the VCC falls down as the
auxiliary voltage are missing. When the supply voltage VCC
touches the VCC(min) level, the controller consumption is
down to a few mA and the VCC slowly builds up again thanks
to the resistive startup network. When VCC reaches VCC(on) ,
the controller enter into start−up cycle. Please note that
soft−start is activated upon every re−start attempt.
Short−circuit case II. → Error flag raised →
→ Fault timer elapsed → auto−recovery
VCC(on)
VCC(min)
t
VDRV(t)
t
Error flag
Fault timer has
elapsed
Fault timer has
elapsed
t
VCS(t)
SS
Vlimit
t
Figure 41. An Auto−recovery Description
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NCL30073
Slope Compensation
half the switching frequency and occur only during
Continuous Conduction Mode (CCM) with a duty ratio
greater than 50%. To lower the current loop gain, one usually
injects between 50 and 100% of the primary inductance
downslope. Figure 42 depicts how the ramp is generated
internally. Please note that the ramp signal will be
disconnected from the CS pin during the off−time.
The NCL30073 includes an internal slope compensation
signal. This is the buffered oscillator clock delivered during
the on−time only. Its amplitude is around 2.5 V at the
maximum duty ratio. Slope compensation is a known means
used to cure sub harmonic oscillations in CCM−operated
current−mode converters. These oscillations take place at
2 .5 V
0 V
Dmax
TSW
ON time
Driver
reset
Rramp
20 kW
+
tLEB
_
CS
Rcomp
Rsense
From FB
Figure 42. Inserting a Resistor in Series with the Current Sense Information Brings Slope Compensation and
Stabilizes the Converter in CCM Operation
In the NCL30073 controller, the oscillator ramp features
a 2.5 V swing. If the clock operates at a 65 kHz frequency,
then the available oscillator slope corresponds to:
S ramp +
V ramp,peak
2.5
+
+ 208 mVńms
0.8 @ 15m
D max @ T SW
If we select 50% of the downslope as the required amount
of slope compensation, then we shall inject a ramp whose
slope is 17 mV/ms. Our internal compensation being of
208 mV/ms, the divider ratio (divratio) between Rcomp and
the internal Rramp = 20 kW resistor is:
(eq. 7)
divratio +
In a flyback design, let’s assume that our primary
inductance Lp is 770 mH, and the SMPS delivers 19 V with
a Np :Ns ratio of 1:0.25. The off−time primary current slope
Sp is thus given by:
Ns
Sp +
(V out ) V f) @ N
Lp
p
(eq. 10)
The series compensation resistor value is thus:
R comp + R ramp @ divratio + 20k @ 0.082 + 1.64 kW
(eq. 11)
(19 ) 0.7) @ 4
+
+ 102 mAńms
770m
A resistor of the calculated value will then be inserted
from the sense resistor to the current sense pin. We
recommend adding a small capacitor of 100 pF, from the
current sense pin to the controller ground for an improved
immunity to the noise. Please make sure both components
are located very close to the controller.
(eq. 8)
Given a sense resistor of 330 mW, the above current ramp
turns into a voltage ramp of the following amplitude:
S sense + S p @ R sense + 102m @ 0.33 + 34 mVńms
0.5 @ S sense
+ 0.082
S ramp
(eq. 9)
www.onsemi.com
17
NCL30073
Protection Pin
minimum time tlatch−del . Below this value, the event is
ignored. Then, a counter ensures that only 4 successive OVP
events have occurred before actually auto−recovery mode is
triggered. There are several possible implementations,
depending on the needed precision and the parameters you
want to control.
The first and easiest solution is the additional resistive
divider on top of the OPP one. This solution is simple and
inexpensive but requires the insertion of a diode to prevent
disturbing the OPP divider during the on−time.
The OPP pin not only allows a reduction of the peak
current set point in relationship to the line voltage, it also
offers a means to enter the auto−recovery mode.
The auto−recovery detection is made by observing the
OPP pin by a comparator featuring a Vlatch reference
voltage. However, for noise reasons and in particular to
avoid the leakage inductance contribution at turn off, a
blanking delay tlatch−blank is introduced before the output of
the OVP comparator is checked. Then, the OVP comparator
output is validated only if its high−state duration lasts for a
Vlatch(t)
The IC is latched after the fault is confirmed
for 4 consecutive DRV cycles
Vlatch
t
VCC(t)
VCC(on)
VCC(min)
VCC(reset)
t
VDRV(t)
t
Figure 43. Auto−recovery of the Controller and Resuming Operation
ROVP
D1
ROPPU
VCC
+
+
OPP
100 p
_
C1
ROPPL
+
OVP
aux.
winding
OPP
Vlatch
Figure 44. A Simple Resistive Divider Brings the OPP Pin above 3 V in case of a VCC Voltage Runaway
above 18 V
www.onsemi.com
18
NCL30073
First, calculate the OPP network with the above equations.
Then, suppose we want to trigger auto−recovery of our
controller when Vout exceeds 25 V. On the auxiliary winding,
the plateau reflects the output voltage by the turns ratio
between the power and the auxiliary winding. In case of
voltage runaway for 19 V output, the plateau will go up to:
V aux,OVP + V out @
Ns
+ 25 @ 0.18 + 18 V
0.25
N aux
R OVP + V out @
V
R
OVP
+ 18 * 3 + 5 kW
3
1k
OPPL
(eq. 13)
In nominal conditions, the plateau establishes to around
14 V. Given the divide by 6 ratio, the OPP pin will swing to
14/6 = 2.3 V during normal conditions, leaving 700 mV for
the noise immunity. A 100 pF capacitor can be added to
improve it and avoid erratic trips in presence of external
surges. Do not increase this capacitor too much otherwise
the OPP signal will be affected by the integrating time
constant.
A second solution for the OVP detection alone is to use
a Zener diode wired as recommended by Figure 45.
(eq. 12)
Since our OVP comparator trips at level Vlatch = 3 V,
across the 1 kW selected OPP pull−down resistor, it implies
a 3 mA current. From 3 V to go up to 18 V, we need an
additional 15 V. Under 3 mA and neglecting the series diode
forward drop, it requires a series resistor of:
15 V
V aux,OVP * V latch
D1
ROPPU
VCC
+
+
OPP
ROPPL
_
C1
22p
+
OVP
aux.
winding
OPP
Vlatch
Figure 45. A Zener Diode in Series with a Diode Helps to Improve the Noise Immunity of the System
its breakdown voltage during the leakage inductance reset
period (hence the internal blanking delay tlatch−blank at turn
off). This spike despite its very short time is energetic
enough to charge the added capacitor C1 and given the time
constant, could make it discharge slower, potentially
disturbing the blanking circuit. When implementing the
Zener option, it is important to carefully observe the OPP pin
voltage (short probe connections!) and check that enough
margin exists to that respect.
In this case, to still trip at 18 V level, we have selected a
15 V Zener diode. In nominal conditions, the voltage on the
OPP pin is almost 0 V during the off−time as the Zener is
fully blocked. This technique clearly improves the noise
immunity of the system compared to that obtained from a
resistive string as in Figure 44. Please note the reduction of
the capacitor on the OPP pin to 10−22 pF. This is because of
the potential spike going through the Zener parasitic
capacitor and the possible auxiliary level shortly exceeding
www.onsemi.com
19
NCL30073
Over Temperature Protection
how to implement a simple OTP using an external NTC and
a series diode. The principle remains the same: make sure the
OPP network is not bothered by the additional NTC hence
the presence of this diode.
In a lot of designs, the converter must be protected against
thermal runaways, e.g. when the temperature inside the
converter box increases a certain value. Figure 46 shows
NTC
D1
ROPPU
VCC
+
+
OPP
_
ROPPL
+
OVP
aux.
winding
OPP
Vlatch
Figure 46. The Internal Circuitry Hooked to OPP Pin can be used to Implement Over Temperature Protection
(OTP)
When the NTC resistor will diminish as the temperature
increases, the voltage on the OPP pin during the off−time
will slowly increase and, once it passes Vlatch level for 4
consecutive clock cycles, the controller will enter
auto−recovery mode.
We have found that the plateau voltage on the auxiliary
diode was 14 V in nominal conditions. We have selected an
NTC which offers a 470 kW resistance at 25°C and drops to
8.8 kW at 110°C. If our auxiliary winding plateau is 14 V and
we consider a 0.7 V forward drop for the diode, then the
voltage across the NTC in fault mode must be:
R OPPL +
VR
OPPU
+ V aux * V OPP + −67.5 ) 0.2 + −67.3 V
(eq. 17)
The current circulating the pull down resistor ROPPL in
this condition will be:
(eq. 14)
Based on the 8.8 kW NTC resistor at 110°C, the current
inside the device must be:
IR
V NTC
+ 10.3 + 1.2 mA
R NTC(110)
8.8k
(eq. 16)
Now the pull down OPP resistor is known, we can
calculate the upper resistor value ROPPU to adjust the power
limit at the chosen output power level. Suppose we need a
200 mV decrease from the Vlimit setpoint and the on−time
swing on the auxiliary anode is −67.5 V, then we need to drop
over ROPPU a voltage of:
V NTC + V aux * V latch * V F + 14 * 3 * 0.7 + 10.3 V
I NTC +
V latch
+ 2.5 kW
I NTC
OPPL
+
V OPP
+ −0.2 + −80 mA
R OPPL
2.5k
(eq. 18)
The ROPPU value is therefore easily derived:
(eq. 15)
R OPPU +
As such, the bottom resistor ROPPL , can easily be
calculated:
www.onsemi.com
20
VR
IR
OPPU
OPPU
+ −67.3 [ 841 kW
−80m
(eq. 19)
NCL30073
Combining OVP and OTP
On the contrary, in nominal temperature conditions, if the
loop is broken, the voltage runaway will be detected and
acknowledged by the controller.
In case the OPP pin is not used for either OPP or OVP, it
can simply be grounded.
The OTP and Zener−based OVP can be combined
together as illustrated by Figure 47. In nominal VCC/output
conditions, when the Zener is not activated, the NTC can
drive the OPP pin and trigger the protection in case of a fault.
15 V
D1
NTC
ROPPU
VCC
+
aux.
winding
+
OPP
_
+
ROPPL
OVP
OPP
Vlatch
Figure 47. With the NTC Back in Place, the Circuit Nicely Combines OVP, OTP and OPP on the Same Pin
Filtering the Spikes
recommend the installation of a small RC filter before the
detection network as illustrated by Figure 48. The values of
resistance and capacitance must be selected to provide the
adequate filtering function without degrading the stand−by
power by an excessive current circulation.
The auxiliary winding is the seat of spikes that can couple
to the OPP pin via the parasitic capacitances exhibited by the
Zener diode and the series diode. To prevent an adverse
triggering of the Over Voltage Protection circuitry, we
15 V
NTC
D1
Additional filter
ROPPU
R1
C1
+
+
OPP
+
aux.
winding
_
ROPPL
VCC
OVP
OPP
Vlatch
Figure 48. A Small RC Filter Prevents the Fast Rising Spikes from Reaching the Protection Pin OPP in Presence
of Energetic Perturbations Superimposed on the Input Line
www.onsemi.com
21
NCL30073
PACKAGE OUTLINE
TSOP−6
CASE 318G−02
ISSUE V
D
ÉÉ
ÉÉ
6
E1
1
NOTE 5
5
2
H
4
L2
GAUGE
PLANE
E
3
L
M
b
SEATING
PLANE
DIM
A
A1
b
c
D
E
E1
e
L
L2
M
DETAIL Z
e
0.05
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
A
c
A1
DETAIL Z
MIN
0.90
0.01
0.25
0.10
2.90
2.50
1.30
0.85
0.20
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
2.75
3.00
1.50
1.70
0.95
1.05
0.40
0.60
0.25 BSC
−
10°
RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60
6X
3.20
0.95
0.95
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCL30073/D