TI1 LMZ31520 20a simple switcherâ® power module with 3.0v-14.5v input in qfn package Datasheet

LMZ31520
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SLVSBM9B – OCTOBER 2013 – REVISED DECEMBER 2013
20A SIMPLE SWITCHER® Power Module with 3.0V-14.5V Input in QFN Package
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FEATURES
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Complete Integrated Power Solution;
Smaller than a Discrete Design
15 mm × 16 mm × 5.8 mm Package Size
- Pin Compatible with LMZ31530
Ultra-Fast Load Step Response
Efficiencies Up To 96%
Wide-Output Voltage Adjust
0.6 V to 3.6 V, with 1% Reference Accuracy
Optional Split Power Rails Allows
Input Voltage Down to 3.0 V
Selectable Switching Frequency
(300 kHz to 850 kHz)
Selectable Slow-Start
Adjustable Overcurrent Limit
Power Good Output
Output Voltage Sequencing
Over Temperature Protection
Pre-bias Output Start-up
Operating Temperature Range: –40°C to 85°C
Enhanced Thermal Performance: 8.6°C/W
Meets EN55022 Class A Emissions
- Integrated Shielded Inductor
APPLICATIONS
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DESCRIPTION
The LMZ31520 SIMPLE SWITCHER® power module
is an easy-to-use integrated power solution that
combines a 20-A DC/DC converter with power
MOSFETs, a shielded inductor, and passives into a
low profile, QFN package. This total power solution
allows as few as three external components and
eliminates the loop compensation and magnetics part
selection process.
The 15x16x5.8 mm QFN package is easy to solder
onto a printed circuit board and allows a compact
point-of-load design. Achieves greater than 95%
efficiency, has ultra-fast load step response and
excellent power dissipation capability with a thermal
impedance of 8.6°C/W. The LMZ31520 offers the
flexibility and the feature-set of a discrete point-ofload design and is ideal for powering a wide range of
ICs and systems. Advanced packaging technology
affords a robust and reliable power solution
compatible with standard QFN mounting and testing
techniques.
SIMPLIFIED APPLICATION
VIN
CI
Broadband and Communications
Infrastructure
DSP and FPGA Point of Load Applications
High Density Power Systems
100
95
PVIN
VIN
V5V
LMZ31520
SENSE+
VOUT
INH
ILIM
FREQ_SEL VADJ
PWRGD
AGND
SS_SEL
VOUT
CO
RSET
90
PGND
Efficiency (%)
85
80
75
Vout = 1.8 V
Fsw = 500 kHz
70
65
PVIN = 3.3 V, VIN = 5 V
60
PVIN = VIN = 5 V
55
PVIN = VIN = 12 V
50
0
4
8
12
16
Output Current (A)
20
C001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
is a trademark of ~ Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LMZ31520
SLVSBM9B – OCTOBER 2013 – REVISED DECEMBER 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
over operating temperature range (unless otherwise noted)
Input Voltage
VALUE
MIN
MAX
VIN, PVIN
–0.3
20
V
INH, VADJ, PWRGD, PWRGD_PU, ILIM, FREQ_SEL, SS_SEL, V5V
–0.3
7
V
–1
25
V
–2
27
PH
Output Voltage
UNIT
PH 10ns Transient
VOUT
–0.3
VDIFF (GND to exposed thermal
pad)
6
V
±200
mV
Operating Junction Temperature
–40
125 (2)
°C
Storage Temperature
–55
150
°C
G
Mechanical Shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
250
Mechanical Vibration
Mil-STD-883D, Method 2007.2, 20-2000Hz
20
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
See the temperature derating curves in the Typical Characteristics section for thermal information.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
PVIN
Input Switching Voltage
3.0
14.5
V
VIN
Input Bias Voltage
4.5
14.5
V
VOUT
Output Voltage
0.6
3.6
V
fSW
Switching Frequency
300
850
kHz
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
2
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THERMAL INFORMATION
LMZ31520
THERMAL METRIC (1)
RLG
UNIT
72 PINS
θJA
Junction-to-ambient thermal resistance (2)
Natural Convection
8.6
(3)
100 LFM
7.8
θJA(100LFM)
Junction-to-ambient thermal resistance
ψJT
Junction-to-top characterization parameter (4)
1.6
ψJB
Junction-to-board characterization parameter (5)
4.2
(1)
(2)
(3)
(4)
(5)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm, 6-layer PCB with 1 oz.
copper and natural convection cooling. Additional airflow reduces θJA.
The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm, 6-layer PCB with 1 oz.
copper and 100 LFM forced air cooling. Additional airflow reduces θJA.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
PACKAGE SPECIFICATIONS
LMZ31520
Weight
Flammability
MTBF Calculated reliability
UNIT
4.96 grams
Meets UL 94 V-O
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
26.5 MHrs
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ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C, VIN = 12 V, VOUT = 1.8 V, IOUT = 20A
CIN = 2x 22 µF ceramic & 330 µF bulk, COUT = 4x 100 µF ceramic (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOUT
Output current
VIN
Input bias voltage range
PVIN
Input switching voltage range
A
4.5
14.5
V
Over IOUT range
3.0 (1)
14.5
V
4.33
V
3.6
V
VIN Increasing
4.0
Output voltage adjust range
Over IOUT range
Set-point voltage tolerance
IOUT = 20 A, FCCM mode
Temperature variation
-40°C ≤ TA ≤ +85°C
Load regulation
Over IOUT range
Total output voltage variation
Includes set-point, load, and temperature variation
Hysteresis
0.6
94
VOUT = 1.8 V, fSW = 500kHz
92
VOUT = 1.2 V, fSW = 500kHz
88
VOUT = 0.9 V, fSW = 500kHz
86
VOUT = 0.6 V, fSW = 500kHz
82
VOUT = 3.3 V, fSW = 500kHz
96
VOUT = 1.8 V, fSW = 500kHz
94
VOUT = 1.2 V, fSW = 500kHz
91
VOUT = 0.9 V, fSW = 500kHz
88
IIN(stby)
VIN standby current
2.5 A/µs load step from 25 to 75%
IOUT(max)
Recovery time
VOUT over/undershoot
0.6
V
INH pin to AGND
Switching frequency
FREQ_SEL pin OPEN, IOUT = 10 A
fSEL
(4)
(4)
(5)
4
mV
-0.3
fSW
(3)
25
Inhibit Low Voltage
I(PWRGD) = 2 mA
(1)
(2)
µs
Open (3)
PWRGD Low Voltage
CIN
A
25
1.8
VOUT falling
Thermal Shutdown
VOUT
30
Inhibit High Voltage
PWRGD Thresholds
Frequency Select
%
1%
VOUT rising
Power Good
%
85
20 MHz bandwith
Current limit threshold
Inhibit Control
(2)
±0.5%
VOUT = 3.3 V, fSW = 500kHz
VOUT = 0.6 V, fSW = 500kHz
VINH
±1.8%
±0.1%
PVIN = VIN = 5 V
IO = 15 A
Transient response
(2)
+0.3%
PVIN = VIN = 12 V
IO = 15 A
ILIM
±1.0%
±0.25%
Over PVIN range
Output voltage ripple
4.2
0.25
PVIN ±10%
Efficiency
UNIT
Over IOUT range
VOUT(adj)
η
MAX
20
VIN Undervoltage lockout
Line regulation
TYP
0
UVLO
VOUT
MIN
V
VIN = 5 V
0.5
0.7
mA
VIN = 12 V
1.2
1.5
mA
Good
95
Fault
115
Fault
90
Good
110
470
%
0.2
0.3
V
520
570
kHz
66 kΩ resistor between FREQ_SEL pin and PGND
300
kHz
FREQ_SEL pin connected to V5V (pin 61)
850
kHz
145
°C
10
°C
Thermal shutdown
Thermal shutdown hysteresis
Ceramic
External input capacitance
Non-ceramic
44
(5)
94
330
µF
The minimum PVIN voltage is 3.0V or (VOUT+ 1.1V), whichever is greater. See VIN and PVIN Input Voltage for more details.
The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal
adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
This pin has an internal pull-up to approximately 0.4 x VIN. If this pin is left open circuit, the device operates when a valid input voltage is
applied. A small, low-leakage (<300nA) MOSFET is recommended for control.
See the Frequency Select section for more information on selecting the frequency.
A minimum of 44 µF (2x 22 µF) of external ceramic capacitance is required across the input (PVIN/VIN and PGND connected) for
proper operation. Locate the capacitor close to the device. See Table 3 for more details. When operating with split VIN and PVIN rails,
place 4.7 µF of ceramic capacitance directly at the VIN pin to PGND.
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ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, VIN = 12 V, VOUT = 1.8 V, IOUT = 20A
CIN = 2x 22 µF ceramic & 330 µF bulk, COUT = 4x 100 µF ceramic (unless otherwise noted)
PARAMETER
COUT
(6)
TEST CONDITIONS
External output capacitance
MIN
TYP
MAX
UNIT
(6)
400
5000
µF
100
A minimum of 100 µF of ceramic capacitance is required at the output. Locate the capacitance close to the device. Adding additional
capacitance close to the load improves the response of the regulator to load transients and reduces ripple. See Table 3 for more details.
DEVICE INFORMATION
PGND
PGND
PGND
49
PGND
DNC
DNC
PGND
PGND
PGND
PGND
PGND
PVIN
PVIN
PVIN
NC
PGND
PGND
PGND
RLG PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
50
51
65
PVIN
66
PGND
PGND
67
33
PGND
32
NC
31
NC
30
NC
VOUT
52
VOUT
53
29
NC
VOUT
54
28
PH
VOUT
55
27
PH
VOUT
56
VOUT
PVIN
PGND
PH
26
PH
VOUT
57
68
69
70
71
25
PH
VOUT
58
24
PH
VOUT
59
23
PH
VOUT
60
22
PH
V5V
61
21
DNC
20
DNC
PGND
72
PWRGD_PU
6
7
8
9
10 11 12 13 14 15 16
17
PGND
INH
5
VIN
4
SENSE+
3
VADJ
2
DNC
1
PH
PGND
VOUT
18
AGND
64
DNC
PGND
FREQ_SEL
PWRGD
ILIM
19
PGND
63
DNC
PGND
SS_SEL
62
VIN
PGND
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PIN DESCRIPTIONS
TERMINAL
NAME
NO.
AGND
9
DESCRIPTION
This pin is connected internally to the power ground of the device. This pin should only be used as the zero
volt ground reference for connecting the voltage setting resistor (RSET). Do not connect AGND to PGND.
See Layout Recommendations.
4
8
12
DNC
20
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These
pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
21
35
36
FREQ_SEL
7
Frequency Select pin. Leave this pin open (floating) to select 500 kHz (typ) operating frequency. Connect
this pin to V5V pin to select 850 kHz (typ) operating frequency. Connect a 66 kΩ resistor between this pin
and PGND to select 300 kHz (typ) operating frequency. See Table 2 for more info.
ILIM
6
Current limit setting pin. Connecting a resistor between this pin and PGND sets the current limit. When left
open, refer to the Electrical Characterization table for current limit value.
INH
16
Inhibit pin. Use an open drain or open collector logic device to ground this pin to control the INH function.
29
30
NC
31
32
Not Connected. These pins are internally isolated from any signal and all other pins. Each pin must be
soldered to a pad on the PCB. These pins can be left isolated, connected to one another, or connected to
any signal on the PCB.
45
1
5
17
33
34
37
38
39
40
41
46
PGND
47
48
This is the return current path for the power stage of the device. Connect these pins to the load and to the
bypass capacitors associated with VIN and VOUT. Pads 65, 67, 70, and 72 should be connected to PCB
ground planes using multiple vias for good thermal performance. Not all pins are connected together
internally. All pins must be connected together externally with a copper plane or pour directly under the
device.
49
50
51
62
63
64
65
67
70
72
6
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PIN DESCRIPTIONS (continued)
TERMINAL
NAME
DESCRIPTION
NO.
11
22
23
24
PH
25
Phase switch node. Do not place any external component on these pins or tie them to a pin of another
function. Connect these pins using a copper area beneath pad 71.
26
27
28
71
42
43
PVIN
44
Input switching voltage pin. This pin supplies voltage to the power switches of the converter.
66
69
PWRGD
19
Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately
±6% out of regulation.
PWRGD_PU
18
Power Good pull-up pin. This pin is connected to a 100kΩ resistor which is tied to the PWRGD pin internally.
Connect this pin to V5V or to any voltage between 1.3V and 6.5V.
SENSE+
14
Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be
connected to VOUT at the load, or at the module pins.
SS_SEL
3
Slow-start select pin. Connect a resistor between this pin and PWRGD (or PGND) to select the slow-start
time. See the SS_SEL section of the datasheet for slow-start times and corresponding resistor values.
Connect the SS_SEL pin to PGND to select Auto-skip Eco-mode or to the PWRGD pin (pin 19) to select
FCCM.
V5V
61
5V regulator pin. This regulator supplies the internal circuitry.
VADJ
13
Output voltage adjust pin. Connecting a resistor between this pin and AGND sets the output voltage.
VIN
2
15
Input bias voltage pins. Supplies the control circuitry of the power converter.
10
52
53
54
55
VOUT
56
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output
load and connect external bypass capacitors between these pins and PGND.
57
58
59
60
68
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FUNCTIONAL BLOCK DIAGRAM
LMZ31520
VIN
ILIM
OCP
PWRGD_PU
PWRGD
Logic
SENSE+
V5V
VIN
Thermal
Shutdown
VIN
UVLO
1.43kΩ
PVIN
SS/
FCCM/
Skip
+
+
VREF
Power
Stage
and
Control
Logic
PH
VOUT
Frequency
Select
AGND
8
LDO
Ramp
Comp
VADJ
FREQ_SEL
10kΩ
6.65kΩ
PWRGD
SS_SEL
INH
Shutdown
Logic
100kΩ
PGND
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TYPICAL CHARACTERISTICS (PVIN = VIN = 12 V)
100
55
Output Ripple Voltage (mV)
90
Efficiency (%)
80
70
60
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
50
40
30
0
4
8
12
16
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
45
35
25
15
5
0
20
Output Current (A)
12
16
20
C004
Figure 2. Voltage Ripple vs. Output Current
90
80
Ambient Temperature (ƒC)
Power Dissipation (W)
4.0
8
Output Current (A)
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
5.0
4
C001
Figure 1. Efficiency vs. Output Current
6.0
(1) (2)
3.0
2.0
1.0
70
60
50
Airflow = 0 LFM
40
9R”9IVZ N+]
30
Vo = 3.3V, fsw = 500kHz
0.0
20
0
4
8
12
16
20
Output Current (A)
0
4
8
12
16
Output Current (A)
C004
Figure 3. Power Dissipation vs. Output Current
20
C001
Figure 4. Safe Operating Area (0 LFM)
90
Ambient Temperature (ƒC)
80
70
60
50
Airflow = 100 LFM
40
All Output Voltages
30
20
0
4
8
12
16
Output Current (A)
20
C001
Figure 5. Safe Operating Area (100 LFM)
(1)
(2)
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 1, Figure 2, and Figure 3.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm six-layer PCB with 1 oz. copper.
Applies to Figure 4 and Figure 5.
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TYPICAL CHARACTERISTICS (PVIN = VIN = 5 V)
45
100
Output Voltage Ripple (mV)
90
Efficiency (%)
80
70
60
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
50
40
30
0
4
8
12
16
Output Current (A)
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
35
25
15
5
0
20
2.0
0.0
C004
60
50
Airflow = 0 LFM
40
All Output Voltages
20
0
4
8
12
16
Output Current (A)
20
0
C004
Figure 8. Power Dissipation vs. Output Current
10
20
70
30
(2)
16
80
1.0
(1)
12
90
Ambient Temperature (ƒC)
Power Dissipation (W)
3.0
8
Output Current (A)
Figure 7. Voltage Ripple vs. Output Current
Vo = 3.3V, fsw = 500kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 500kHz
Vo = 0.9V, fsw = 500kHz
Vo = 0.6V, fsw = 500kHz
4.0
4
C001
Figure 6. Efficiency vs. Output Current
5.0
(1) (2)
4
8
12
16
Output Current (A)
20
C001
Figure 9. Safe Operating Area (0 LFM)
The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 6, Figure 7, and Figure 8.
The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm six-layer PCB with 1 oz. copper.
Applies to Figure 9.
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APPLICATION INFORMATION
ADJUSTING THE OUTPUT VOLTAGE
The VADJ control sets the output voltage of the LMZ31520. The output voltage adjustment range is from 0.6V to
3.6V. The adjustment method requires the addition of RSET, which sets the output voltage, and the connection of
SENSE+ to VOUT. The RSET resistor must be connected directly between the VADJ (pin 13) and AGND (pin 9).
The SENSE+ pin (pin 14) must be connected to VOUT either at the load for improved regulation or at VOUT of
the device.
The LMZ31520 relies on a precision trimmed 0.6 V reference for the feedback voltage regulation and operates by
regulating the valley of the voltage ripple appearing at the VADJ pin. The voltage ripple is a function of the input
voltage and the output voltage, therefore the RSET resistor will change based on the input voltage. Table 1 gives
the calculated external RSET resistor for a number of common bus voltages for PVIN of 12 V, 5 V, and 3.3 V. The
recommended switching frequency is 500 kHz which can be configured by leaving the FREQ_SEL pin open. To
adjust the frequency, see Table 2.
Table 1. RSET Resistor Values
RSET (Ω)
RSET (Ω)
VOUT (V)
PVIN = 12 V
PVIN = 5 V
PVIN = 3.3 V
VOUT (V)
PVIN = 12 V
PVIN = 5 V
PVIN = 3.3 V
0.60
open
open
open
2.15
566
563
560
0.65
18787
18681
18588
2.20
548
545
542
0.70
9024
8993
8966
2.25
532
528
525
0.75
5939
5923
5908
2.30
516
513
510
0.80
4427
4416
4406
2.35
502
498
495
0.85
3529
3521
3513
2.40
488
484
481
0.90
2934
2927
2921
2.45
475
471
468
0.95
2511
2505
2500
2.50
462
459
456
1.00
2195
2190
2185
2.55
451
447
444
1.05
1950
1945
1941
2.60
439
436
433
1.10
1754
1749
1745
2.65
429
425
422
1.15
1594
1589
1586
2.70
419
415
412
1.20
1460
1456
1453
2.75
409
405
402
1.25
1348
1344
1341
2.80
400
396
393
1.30
1251
1248
1244
2.85
391
387
384
1.35
1168
1164
1161
2.90
382
379
375
1.40
1095
1091
1088
2.95
374
370
367
1.45
1031
1027
1024
3.00
367
363
359
1.50
973
970
968
3.05
359
355
352
1.55
922
919
916
3.10
352
348
345
1.60
876
873
870
3.15
345
341
338
1.65
834
831
828
3.20
339
335
331
1.70
797
793
790
3.25
332
328
325
1.75
762
759
756
3.30
326
322
318
1.80
730
727
724
3.35
320
316
312
1.85
701
698
695
3.40
315
310
307
1.90
674
671
668
3.45
309
305
301
1.95
650
646
643
3.50
304
300
296
2.00
626
623
620
3.55
299
294
291
2.05
605
602
599
3.60
294
289
286
2.10
585
581
578
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Frequency Select
The LMZ31520 switching frequency can be selected from several values as shown in Table 2. To select a
switching frequency, a resistor (RFREQ) must be connected between the FREQ_SEL pin and either PGND or V5V
(pin 61) as shown in Table 2. For all output voltages, the recommended switching frequency is 500 kHz which
can be configured by leaving the FREQ_SEL pin open. Table 2 also shows the output voltage range for each
frequency.
Table 2. Frequency Selection
VOUT RANGE (V)
Frequency Select (kHz)
RFREQ (kΩ)
Connect To
MIN
MAX
300
66
PGND
0.6
3.6
400
498
PGND
0.6
3.6
500
open
-
0.6
3.6
650
745
V5V
0.8
3.6
750
188
V5V
1.0
3.6
850
short
V5V
1.2
3.6
CAPACITOR RECOMMENDATIONS FOR THE LMZ31520 POWER SUPPLY
Capacitor Technologies
Electrolytic, Polymer-Electrolytic Capacitors
Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz.
When using electrolytic capacitors, high-quality, polymer-electrolytic capacitors are recommended. Polymerelectrolytic type capacitors are recommended for applications where the ambient operating temperature is less
than 0°C. The Panasonic OS-CON capacitor series is suggested due to the lower ESR, higher rated surge,
power dissipation, ripple current capability, and small package size.
Ceramic Capacitors
The performance of ceramic capacitors is most effective above 150 kHz. Multilayer ceramic capacitors have a
low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the
reflected ripple current at the input as well as improve the transient response of the output.
Tantalum, Polymer-Tantalum Capacitors
Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is
less than 0°C. The Panasonic POSCAP series and Kemet T530 capacitor series are recommended rather than
many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current
capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not
recommended for power applications.
Input Capacitor
The LMZ31520 requires a minimum input capacitance of 44 μF of ceramic type. The voltage rating of input
capacitors must be greater than the maximum input voltage. The input RMS ripple current is a function of the
output current and the duty cycle for any application. The input capacitor must be rated for the application's RMS
ripple current. Table 3 includes a preferred list of capacitors by vendor.
Output Capacitor
The required output capacitance of the LMZ31520 can be comprised of either all ceramic capacitors, or a
combination of ceramic and bulk capacitors. The required output capacitance must include at least 100 µF of
ceramic type. When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended
in Table 3 are required. The required capacitance above the minimum is determined by actual transient deviation
requirements. See Table 4 for typical transient response values for several output voltage, input voltage and
capacitance combinations. Table 3 includes a preferred list of capacitors by vendor.
12
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Table 3. Recommended Input/Output Capacitors (1)
CAPACITOR CHARACTERISTICS
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE
(V)
CAPACITANCE
(µF)
ESR (2)
(mΩ)
Murata
X5R
GRM32ER61E226K
25
22
2
TDK
X5R
C3216X5R1E476M
25
47
2
TDK
X5R
C3216X5R1C476M
16
47
2
Murata
X5R
GRM32ER61C476M
16
47
2
TDK
X5R
C3225X5R0J107M
6.3
100
2
Murata
X5R
GRM32ER60J107M
6.3
100
2
TDK
X5R
C3225X5R0J476K
6.3
47
2
Murata
X5R
GRM32ER60J476M
6.3
47
2
EEH-ZA1E101XP
25
100
30
Panasonic
EEH-ZA
Kemet
T520V107M010ASE025
10
100
25
Panasonic
POSCAP
T520
6TPE100MI
6.3
100
25
Panasonic
POSCAP
2R5TPE220M7
2.5
220
7
Kemet
T530
T530D227M006ATE006
6.3
220
6
Kemet
T530
T530D337M006ATE010
6.3
330
10
Panasonic
POSCAP
2TPF330M6
2.0
330
6
Panasonic
POSCAP
6TPE330MFL
6.3
330
15
(1)
(2)
Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
Maximum ESR @ 100kHz, 25°C.
Transient Response
The LMZ31520 is designed to have an ultra-fast load step response with minimal output capacitance. Table 4
shows the voltage deviation and recovery time for several different transient conditions. Several transient
waveforms are shown in Transient Waveforms (3).
Table 4. Output Voltage Transient Response
CIN1 = 3 x 47 µF CERAMIC
VOLTAGE DEVIATION (mV)
VOUT (V)
0.6
COUT1 Ceramic
COUT2 BULK
5 A LOAD STEP,
(1 A/µs)
10 A LOAD STEP,
(1 A/µs)
5
500 µF
-
8
15
35
12
500 µF
-
8
15
35
500 µF
-
8
15
40
500 µF
470 µF
6
12
40
500 µF
-
8
20
40
500 µF
470 µF
7
16
40
500 µF
-
10
20
40
500 µF
330 µF
8
15
40
500 µF
-
10
20
40
500 µF
330 µF
8
16
40
500 µF
-
10
20
40
500 µF
330 µF
8
16
40
500 µF
-
10
20
40
5
0.9
12
5
1.2
12
5
1.8
12
3.3
(3)
RECOVERY TIME
(µs)
VIN (V)
500 µF
330 µF
8
16
45
5
500 µF
-
12
25
50
12
500 µF
-
12
25
50
Device configured for FCCM mode of operation, (pin 3 connected to pin 19).
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Transient Waveforms
www.ti.com
(1)
Figure 10. PVIN = 5V, VOUT = 1.8V, 5A Load Step
Figure 11. PVIN = 5V, VOUT = 1.2V, 10A Load Step
Figure 12. PVIN = 12V, VOUT = 1.0V, 10A Load
Step
Figure 13. PVIN = 12V, VOUT = 1.8V, 10A Load
Step
(1)
14
Device configured for FCCM mode of operation, (pin 3 connected to pin 19).
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Application Schematics
LMZ31520
VIN
VIN / PVIN
4.5 V to 14.5 V
VOUT
1.2 V
SENSE+
PVIN
VOUT
+
+
CIN1
CIN2
100 µF 22 µF
COUT1
2x 100 µF
CIN3
22 µF
COUT2
220 µF
INH
FREQ_SEL PWRGD
RSET
1.43 k
VADJ
SS_SEL
AGND
PGND
Figure 14. Typical Schematic
PVIN = VIN = 4.5 V to 14.5 V, VOUT = 1.2 V
VIN
4.5 V to 14.5 V
CIN3
4.7 µF
LMZ31520
VOUT
0.9 V
SENSE+
PVIN
3.3 V
PVIN
VOUT
+
+
CIN1
CIN2
100 µF 22 µF
COUT1
3x 100 µF
CIN3
22 µF
COUT2
330 µF
INH
FREQ_SEL PWRGD
RSET
2.87 k
VADJ
SS_SEL
AGND
PGND
Figure 15. Typical Schematic
PVIN = 3.3 V, VIN = 4.5 V to 14.5 V, VOUT = 0.9 V
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VIN and PVIN Input Voltage
The LMZ31520 allows for a variety of applications by using the VIN and PVIN pins together or separately. The
VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the
power converter system.
If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 14.5 V. If using the
VIN pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from
as low as 3.0 V to 14.5 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for
best performance.
3.3 V PVIN Operation
Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN
from 5 V to 12 V, for best performance. See application note, SNVA692 for help creating 5 V from 3.3 V using a
small, simple charge pump device.
Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 90% and 115% of the
set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is
between 10 kΩ and 100 kΩ to a voltage source that is less than 7 V. An internal 100 kΩ pull-up resistor is
provided internal to the device between the PWRGD pin (pin 19) and PWRGD_PU pin (pin 18). The
PWRGD_PU pin can be connected to a voltage source less than 7 V or connected directly to V5V (pin 61), which
is an internal 5V regulator. The PWRGD pin is in a defined state once VIN is greater than 1.0 V. The PWRGD
pin is pulled low when the voltage on SENSE+ is lower than 90% or greater than 115% of the nominal set
voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted or the INH pin is
pulled low.
Slow Start (SS_SEL)
Connecting the SS_SEL pin to PWRGD or PGND sets the slow start interval of approximately 0.7 ms. The
connection to either PWRGD or PGND determines the mode of the LMZ31520 as decribed in Auto-Skip EcoMode ™ / Forced Continuous Conduction Mode. Adding a resistor between SS_SEL pin and PWRGD or PGND
increases the slow start time. Increasing the slow start time will reduce inrush current.Table 5 shows a resistor
connected between SS_SEL pin and PWRGD to select FCCM and Figure 17 shows a resistor between SS_SEL
pin and PGND to select Auto-skip mode. See Table 5 below for SS resistor values and timing interval.
PWRGD
PWRGD
SS_SEL
SS_SEL
RSS
RSS
PGND
Figure 16. Slow-Start Resistor (RSS) in FCCM
PGND
Figure 17. Slow-Start Resistor (RSS) in Auto-skip
Mode
Table 5. Slow-Start Resistor Values and Slow-Start Time
16
RSS (kΩ)
short
61.9
161
436
SS Time (msec)
0.7
1.4
2.8
5.6
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Auto-Skip Eco-Mode ™ / Forced Continuous Conduction Mode
Auto-skip Eco-mode or Forced Continuous Conduction Mode (FCCM) can be selected using the SS_SEL pin
(pin 3). Connect the SS_SEL pin to PGND to select Auto-skip Eco-mode or to the PWRGD pin to select FCCM.
In Auto-skip Eco-mode, the LMZ31520 automatically reduces the switching frequency at light load conditions to
maintain high efficiency. In FCCM, the controller keeps continuous conduction mode in light load condition and
the switching frequency is kept almost constant over the entire load range. Transient performance is best in
FCCM.
Power-Up Characteristics
When configured as shown in the front page schematic, the LMZ31520 produces a regulated output voltage
following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate
that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input
source. Figure 18 shows the start-up waveforms for a LMZ31520, operating from a 5-V input (PVIN=VIN) and
with the output voltage adjusted to 1.8 V. Figure 19 shows the start-up waveforms for a LMZ31520 starting up
into a pre-biased output voltage. The waveforms were measured with a 15-A constant current load.
Figure 18. Start-Up Waveforms
Figure 19. Start-up into Pre-bias
Pre-Biased Start-Up
The LMZ31520 has been designed to prevent the low-side MOSFET from discharging a pre-biased output.
During pre-biased startup, the low-side MOSFET does not turn on until the high-side MOSFET has started
switching. The high-side MOSFET does not start switching until the slow start voltage exceeds the voltage on the
VADJ pin. Refer to Figure 19.
Remote Sense
The SENSE+ pin must be connected to VOUT at the load, or at the device pins.
Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by
allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by
the high output current flowing through the small amount of pin and trace resistance. This should be limited to a
maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear
or frequency dependent components that may be placed in series with the converter
output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When
these components are enclosed by the SENSE+ connection, they are effectively placed
inside the regulation control loop, which can adversely affect the stability of the regulator.
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Output On/Off Inhibit (INH)
The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold
voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low quiescent current state.
The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to
interface with the pin.
Figure 20 shows the typical application of the inhibit function. The Inhibit control has its own internal pull-up to
VIN potential. An open-collector or open-drain device is recommended to control this input.
Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown
in Figure 21. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 22. A
regulated output voltage is produced within 2 ms. The waveforms were measured with a 5-A constant current
load.
INH
Q1
INH
Control
PGND
Figure 20. Typical Inhibit Control
Figure 21. Inhibit Turn-Off
18
Figure 22. Inhibit Turn-On
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Overcurrent Protection
For protection against load faults, the LMZ31520 incorporates cycle-by-cycle overcurrent limiting control. The
inductor current is monitored during the OFF state and the controller maintains the OFF state during the period in
that the inductor current is larger than the overcurrent trip level. In cycle-by-cycle mode, applying a load that
exceeds the regulator's overcurrent threshold limits the output current and reduces the output voltage as shown
in Figure 23. If the overcurrent condition remains and the output voltage drops below 70% of the set-point, the
LMZ31520 shuts down. Following shutdown, the module periodically attempts to recover by initiating a soft-start
power-up as shown in Figure 23. This is described as a hiccup mode of operation, whereby the module
continues in a cycle of successive shutdown and power up until the load fault is removed. During this period, the
average current flowing into the fault is significantly reduced which reduces power dissipation. Once the fault is
removed, the module automatically recovers and returns to normal operation as shown in Figure 24.
Figure 23. Typical Overcurrent Limiting
Figure 24. Typical Removal of Overcurrent
Current Limit (ILIM) Adjust
The current limit of this device can be adjusted lower by connecting a resistor, RILIM, between the ILIM pin (pin 6)
and PGND. To adjust the typical current limit threshold, as listed in the electrical characteristics table, refer to
Table 6.
Table 6. Current Limit Adjust Resistor
Current Limit Reduction
RILIM (kΩ)
10 %
715
20 %
383
30 %
243
Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
145°C typically. The device reinitiates the power up sequence when the junction temperature drops below 135°C
typically.
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Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 25 thru
Figure 30, shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another. AGND should only be used as the return for RSET.
• Place RSET, RFREQ, and RSS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
Figure 25. Typical Top Layer Layout
20
Figure 26. Typical Layer 2 Layout
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Figure 27. Typical Layer 3 Layout
Figure 28. Typical Layer 4 Layout
Figure 29. Typical Layer 5 Layout
Figure 30. Typical Bottom Layer Layout
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EMI
The LMZ31520 is compliant with EN55022 Class A radiated emissions. Figure 31 and Figure 32 show typical
examples of radiated emissions plots for the LMZ31520 operating from 5V and 12V respectively. Both graphs
include the plots of the antenna in the horizontal and vertical positions.
Figure 31. Radiated Emissions 5-V Input, 1.8-V
Output, 20-A Load (EN55022 Class A)
22
Figure 32. Radiated Emissions 12-V Input, 3.3-V
Output, 20-A Load (EN55022 Class A)
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REVISION HISTORY
Changes from Revision A (December 2013) to Revision B
•
Page
Added additional capacitors to the recommended capacitor table ..................................................................................... 13
Changes from Original (October 2013) to Revision A
•
Page
Changed status from Preview to Production ........................................................................................................................ 1
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Jul-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
LMZ31520RLGT
ACTIVE
Package Type Package Pins Package
Drawing
Qty
BQFN
RLG
72
250
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
(53353DQP ~
LMZ31520)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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17-Jul-2015
Addendum-Page 2
IMPORTANT NOTICE
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