PD -97148A
IRLS3036-7PPbF
HEXFET® Power MOSFET
Applications
l DC Motor Drive
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
G
l Hard Switched and High Frequency Circuits
D
S
Benefits
l Optimized for Logic Level Drive
l Very Low RDS(ON) at 4.5V VGS
l Superior R*Q at 4.5V VGS
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
ID (Package Limited)
60V
1.5m:
1.9m:
300Ac
240A
D
S
G
S
S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
300c
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
210
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
240
IDM
Pulsed Drain Current d
1000
PD @TC = 25°C
Maximum Power Dissipation
380
W
Linear Derating Factor
2.5
VGS
Gate-to-Source Voltage
± 16
W/°C
V
dv/dt
TJ
Peak Diode Recovery f
8.1
V/ns
Operating Junction and
TSTG
Storage Temperature Range
A
-55 to + 175
°C
300
Soldering Temperature, for 10 seconds (1.6mm from case)
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy e
IAR
Avalanche Current d
EAR
Repetitive Avalanche Energy d
300
mJ
See Fig. 14, 15, 22a, 22b
A
mJ
Thermal Resistance
Typ.
Max.
Units
RθJC
Symbol
Junction-to-Case kl
–––
0.40
°C/W
RθJA
Junction-to-Ambient (PCB Mount, steady state) j
–––
40
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Parameter
1
10/28/10
IRLS3036-7PPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
IDSS
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
60
–––
–––
–––
1.0
–––
–––
–––
–––
RG(int)
Internal Gate Resistance
–––
Conditions
––– –––
V VGS = 0V, ID = 250μA
0.059 ––– V/°C Reference to 25°C, ID = 5mAd
1.5
1.9
VGS = 10V, ID = 180A g
mΩ
VGS = 4.5V, ID = 150A g
1.7
2.2
–––
2.5
V VDS = VGS, ID = 250μA
–––
20
VDS = 60V, VGS = 0V
μA
––– 250
VDS = 60V, VGS = 0V, TJ = 125°C
––– 100
VGS = 16V
nA
––– -100
VGS = -16V
1.9
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
390 ––– –––
––– 110 160
–––
33
–––
–––
53
–––
–––
57
–––
Turn-On Delay Time
–––
81
–––
Rise Time
––– 540 –––
Turn-Off Delay Time
–––
89
–––
Fall Time
––– 170 –––
Input Capacitance
––– 11270 –––
Output Capacitance
––– 1025 –––
Reverse Transfer Capacitance
––– 520 –––
Effective Output Capacitance (Energy Related)i––– 1460 –––
––– 1630 –––
Effective Output Capacitance (Time Related) h
Conditions
S
VDS = 10V, ID = 180A
ID = 180A
VDS = 30V
nC
VGS = 4.5V g
ID = 180A, VDS =0V, VGS = 4.5V
VDD = 39V
ID = 180A
ns
RG = 2.1Ω
VGS = 4.5V g
VGS = 0V
VDS = 50V
pF ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 48V i
VGS = 0V, VDS = 0V to 48V h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
ISM
(Body Diode)
Pulsed Source Current
–––
–––
VSD
trr
(Body Diode)e
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Notes:
Calculated continuous current based on maximum allowable junction
temperature Bond wire current limit is 240A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.018mH
RG = 25Ω, IAS = 180A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 180A, di/dt ≤ 1070A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
300
A
1000
Conditions
MOSFET symbol
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 180A, VGS = 0V g
VR = 51V,
TJ = 25°C
IF = 180A
TJ = 125°C
di/dt = 100A/μs g
TJ = 25°C
S
––– –––
1.3
V
–––
57
–––
ns
–––
60
–––
––– 140 –––
nC
TJ = 125°C
––– 160 –––
–––
4.6
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as
Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
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IRLS3036-7PPbF
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
10
1
2.7V
BOTTOM
100
2.7V
≤ 60μs PULSE WIDTH
Tj = 175°C
≤ 60μs PULSE WIDTH
Tj = 25°C
0.1
10
0.1
1
10
100
0.1
VDS , Drain-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
1000
TJ = 175°C
100
(Normalized)
ID, Drain-to-Source Current(Α)
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
TJ = 25°C
10
VDS = 25V
≤ 60μs PULSE WIDTH
1
2.0
3.0
4.0
ID = 180A
VGS = 10V
2.0
1.5
1.0
0.5
5.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
20000
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
Ciss
10000
5000
Coss
Crss
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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VDS = 48V
ID= 180A
VDS = 30V
4
3
2
1
0
0
1
20 40 60 80 100 120 140 160 180
Fig 4. Normalized On-Resistance vs. Temperature
5
VGS = 0V,
f = 100 kHz
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
15000
0
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
0
20
40
60
80
100
120
140
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRLS3036-7PPbF
1000
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
TJ = 175°C
100
TJ = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
100μsec
100
1msec
LIMITED BY PACKAGE
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.1
1.6
LIMITED BY PACKAGE
ID , Drain Current (A)
250
200
150
100
50
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage
300
50
100
80
ID = 5mA
70
60
50
-60 -40 -20
TC , Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
1200
EAS, Single Pulse Avalanche Energy (mJ)
4.0
3.0
Energy (μJ)
10
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
1
VDS , Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
2.0
1.0
0.0
ID
22A
37A
BOTTOM 180A
TOP
1000
800
600
400
200
0
0
10
20
30
40
50
60
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
70
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRLS3036-7PPbF
1
Thermal Response ( Z thJC )
D = 0.50
0.1
0.20
0.10
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
τ2
τ1
τ3
τ2
Ci= τi/Ri
Ci= τi/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.001
Ri (°C/W)
τC
τ3
τ
τι (sec)
0.103731 0.000184
0.196542 0.001587
0.098271 0.006721
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
300
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 180A
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRLS3036-7PPbF
24
ID = 1.0A
ID = 1.0mA
ID = 250μA
2.5
18
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
3.0
2.0
12
1.5
IF = 120A
VR = 51V
6
1.0
TJ = 125°C
TJ = 25°C
0
-75
-50
-25
0
25
50
75
100 125 150 175
100
200
300
TJ , Temperature ( °C )
400
500
600
700
800
900
dif / dt - (A / μs)
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
1000
24
800
QRR - (nC)
IRRM - (A)
18
12
IF = 180A
VR = 51V
6
600
400
200
TJ = 125°C
TJ = 25°C
0
100
200
300
400
500
600
IF = 120A
VR = 51V
TJ = 125°C
TJ = 25°C
0
700
800
100
900
300
400
500
600
700
800
900
dif / dt - (A / μs)
dif / dt - (A / μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
1000
800
QRR - (nC)
200
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 180A
VR = 51V
TJ = 125°C
TJ = 25°C
600
400
200
0
100
200
300
400
500
600
700
800
900
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRLS3036-7PPbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRLS3036-7PPbF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
8
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IRLS3036-7PPbF
D2Pak - 7 Pin Part Marking Information
25
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/10
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