AD AD7118TQ2 Logdac cmos logarithmic d/a converter Datasheet

a
LOGDAC
CMOS Logarithmic D/A Converter
AD7118*
FEATURES
Dynamic Range 85.5 dB
Resolution 1.5 dB
Full 625 V Input Range Multiplying DAC
Full Military Temperature Range –558C to +1258C
Low Distortion
Low Power Consumption
Latch Proof Operation (Schottky Diodes Not Required)
Single 5 V to 15 V Supply
APPLICATIONS
Digitally Controlled AGC Systems
Audio Attenuators
Wide Dynamic Range A/D Converters
Sonar Systems
Function Generators
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
GENERAL DESCRIPTION
The LOGDAC® AD7118 is a CMOS multiplying D/A converter which attenuates an analog input signal over the range
0 to –85.5 dB in 1.5 dB steps. The analog output is determined
by a six-bit attenuation code applied to the digital inputs.
Operating frequency range of the device is from dc to several
hundred kHz.
The device is manufactured using an advanced monolithic
silicon gate thin-film on CMOS process and is packaged in a
14-pin dual-in-line package.
ORDERING INFORMATION
Model
Temperature
Range
Specified
Accuracy
Range
Package
Option1
AD7118KN
AD7118LN
AD7118BQ
AD7118CQ
AD7118TQ2
AD7118UQ2
0°C to +70°C
0°C to +70°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
0 to 42 dB
0 to 48 dB
0 to 42 dB
0 to 48 dB
0 to 42 dB
0 to 48 dB
N-16
N-16
Q-16
Q-16
Q-16
Q-16
NOTES
1
N = Plastic DIP; Q = Cerdip.
2
To order MIL-STD-883, Class B processed parts, add /883B to part number.
*Protected by U.S. Patent No. 4521,764.
LOGDAC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD7118–SPECIFICATIONS
(VDD = +5 V or +15 V, VIN = –10 V dc, IOUT = AGND = DGND = 0 V, output amplifier
AD544 except where noted)
Parameter
TA = +258C
TA = TMIN, TMAX
VDD = +5 V VDD = +15 V VDD = +5 V VDD = +15 V Units
NOMINAL RESOLUTION
1.5
1.5
1.5
1.5
dB
± 0.35
± 0.7
± 1.0
± 0.35
± 0.5
± 0.7
± 0.4
± 0.8
± 1.3
± 0.4
± 0.7
± 1.0
dB max
dB max
dB max
± 0.5
± 0.75
± 0.5
± 0.75
± 0.5
± 1.0
± 0.5
± 0.8
dB max
dB max
ACCURACY RELATIVE TO VIN
AD7118L/C/U
0 dB to –30 dB
–31.5 dB to –42 dB
–43.5 dB to –48 dB
AD7118K/B/T
0 dB to –30 dB
–31.5 dB to –42 dB
MONOTONIC RANGE
Nominal 1.5 dB Steps
L/C/U Grade
K/B/T Grade
All Grades
Monotonic Over Full
0 to –72
Code Range
0 to –66
Monotonic Over Full Code Range
0 to –72
0 to –66
dB
dB
VIN INPUT RESISTANCE
(PIN 12)
All Grades
L/C/U Grade
K/B/T Grade
9
17
21
9
17
21
9
17
21
9
17
21
kΩ min
kΩ max
kΩ max
RFB INPUT RESISTANCE
(PIN 13)
All Grades
L/C/U Grade
K/B/T Grade
9.45
18
22
9.45
18
22
9.45
18
22
9.45
18
22
kΩ min
kΩ max
kΩ max
3.0
0.8
±1
13.5
1.5
±1
3.0
0.8
± 10
13.5
1.5
± 10
V min
V max
µA max
5
–
0.5
–
15
1
5
–
1
–
15
2
V min
V max
mA max
Nominal 3 dB Steps
DIGITAL INPUTS
Input High Voltage Requirements VIH
Input Low Voltage Requirements VIL
Input Leakage Current
POWER SUPPLY
VDD for Specified Accuracy
IDD
Test Conditions/Comments
Accuracy is measured using
circuit of Figure 1 and includes
any effects due to mismatch
between RFB and the R-2R
ladder circuit.
Digital Inputs 000000 to 110000
Digital Inputs 000000 to 101100
Digital Inputs = VDD
Digital Inputs = 0 V or VDD
(See Figure 7)
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
(VDD = +5 V or +15 V, VIN = –10 V except where stated, IOUT = AGND = DGND =
0 V, output amplifier AD544 except where noted)
These characteristics are included for design guidance only and are not subject to test.
Parameter
TA = +258C
TA = TMIN, TMAX
VDD = +5 V VDD = +15 V VDD = +5 V VDD = +15 V Units
DC Supply Rejection, ∆Gain/∆VDD
0.01
0.005
0.01
0.005
dB per % max
Propagation Delay
Digital-to-Analog Glitch Impulse
1.8
225
0.4
1200
2.2
–
0.5
–
µs max
nV secs typ
Output Capacitance (Pin 14)
Input Capacitance Pin 12 and Pin 13
Feedthrough at 1 kHz
L/C/U Grade
K/B/T Grade
Total Harmonic Distortion
Intermodulation Distortion
Output Noise Voltage Density
Digital Input Capacitance
100
7
–86
–80
–85
–79
70
7
100
7
–86
–80
–85
–79
70
7
100
7
–68
–63
–85
–79
70
7
100
7
–68
–63
–85
–79
70
7
pF max
pF max
dB max
dB max
dB typ
dB typ
nV/√Hz max
pF max
∆VDD = ± 10%,
Input code = 100000
Full-Scale Change
Measured with ADLH0032CG
as output amplifier for input
code transition 100000 to 000000.
C1 of Figure 1 is 0 pF.
Feedthrough is also determined by circuit layout
VIN = 6 V rms
per DIN 45403 Blatt 4
Includes AD544 amplifier noise
Specifications subject to change without notice.
Accuracy Specification for K/B/T Grade Devices at T A = +25°C
–2–
Accuracy Specification for L/C/U Grade Devices at T A = +25°C
REV. A
Applications Information–AD7118
ABSOLUTE MAXIMUM RATINGS*
TERMINOLOGY
(TA = +25°C unless otherwise noted)
RESOLUTION: Nominal change in attenuation when moving
between two adjacent binary codes.
VDD (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
VIN (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 35 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
IOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD
Power Dissipation (Any Package)
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates Above +75°C by . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (K, L Versions) . . . . . . . . . . . . . 0°C to +70°C
Industrial (B, C Versions) . . . . . . . . . . . . . –25°C to +85°C
Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
MONOTONICITY: The device is monotonic if the analog output decreases (or remains constant) as the digital code increases.
FEEDTHROUGH ERROR: That portion of the input signal
which reaches the output when all digital inputs are high. See
section on Applications.
OUTPUT LEAKAGE CURRENT: Current which appears on
the IOUT terminal with all digital inputs high.
TOTAL HARMONIC DISTORTION: Is a measure of the
harmonics introduced by the circuit when a pure sinusoid is
applied to the input. It is expressed as the harmonic energy
divided by the fundamental energy at the output.
ACCURACY: Is the difference (measured in dB) between the
ideal transfer function as listed in Table I and the actual transfer
function as measured with the device.
*Stresses above those listed under “Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
OUTPUT CAPACITANCE: Capacitance from IOUT to
ground.
DIGITAL-TO-ANALOG GLITCH IMPULSE: The amount
of charge injected from the digital inputs to the analog output
when the inputs change state. This is normally specified as the
area of the glitch in either pA-secs or nV-secs depending upon
whether the glitch is measured as a current or voltage signal.
Digital charge injection is measured with VIN = AGND.
PROPAGATION DELAY: This is a measure of the internal
delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its
final value.
INTERMODULATION DISTORTION: Is a measure of the
interaction which takes place within the circuit between two
sinusoids applied simultaneously to the input.
The reader is referred to Hewlett Packard Application Note 192
for further information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7118 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
AD7118
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7118 consists of a 17-bit R-2R CMOS multiplying D/A
converter with extensive digital input logic. The logic translates
the 6-bit binary input into a 17-bit word which is used to drive
the D/A converter. Table I gives the nominal output voltages
(and levels relative to 0 dB = 10 V) for all possible input codes.
The transfer function for the circuit of Figure 1 is given by:
1.5N 
V O = −V IN 10exp− 

 20 
V
or O
= −1.5N
V IN dB
The current source ILEAKAGE is composed of surface and junction leakages and as with most semiconductor devices, roughly
doubles every 10°C–see Figure 10. The resistor RO as shown in
Figure 3 is the equivalent output resistance of the device which
varies with input code (excluding all 0’s code) from 0.8R to
2R. R is typically 12 kΩ. COUT is the capacitance due to the
N-channel switches and varies from about 50 pF to 80 pF depending upon the digital input. For further information on
CMOS multiplying D/A converters refer to “Application Guide
to CMOS Multiplying D/A Converters” which is available from
Analog Devices, Publication Number G479–15–8/78.
where N is the binary input for values 0 to 57. For 60 ≤ N ≤ 63
the output is zero. See note 3 at bottom of Table I.
Figure 2. Simplified D/A Circuit of AD7118
Figure 1. Typical Circuit Configuration
EQUIVALENT CIRCUIT ANALYSIS
Figure 2 shows a simplified circuit of the D/A converter section
of the AD7118 and Figure 3 gives an approximate equivalent
circuit.
Figure 3. Equivalent Analog Output Circuit of AD7118
Table I. Ideal Attenuation vs. Input Code
N
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Digital Input
D5
D0
00 00 00
00 00 01
00 00 10
00 00 11
00 01 00
00 01 01
00 01 10
00 01 11
00 10 00
00 10 01
00 10 10
00 10 11
00 11 00
00 11 01
00 11 10
00 11 11
01 00 00
01 00 01
01 00 10
01 00 11
01 01 00
01 01 01
01 01 10
01 01 11
01 10 00
01 10 01
01 10 10
01 10 11
01 11 00
01 11 01
01 11 10
Attenuation
dB
00.0
01.5
03.0
04.5
06.0
07.5
09.0
10.5
12.0
13.5
15.0
16.5
18.0
19.5
21.0
22.5
24.0
25.5
27.0
28.5
30.0
31.5
33.0
34.5
36.0
37.5
39.0
40.5
42.0
43.5
45.0
VOUT1
10.00
8.414
7.079
5.957
5.012
4.217
3.548
2.985
2.512
2.113
1.778
1.496
1.259
1.059
0.891
0.750
0.631
0.531
0.447
0.376
0.316
0.266
0.224
0.188
0.158
0.133
0.112
0.0944
0.0794
0.0668
0.0562
N
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Digital Input
01 11 11
10 00 00
10 00 01
10 00 10
10 00 11
10 01 00
10 01 01
10 01 10
10 01 11
10 10 00
10 10 01
10 10 10
10 10 11
10 11 00
10 11 01
10 11 10
10 11 11
11 00 00
11 00 01
11 00 10
11 00 11
11 01 00
11 01 01
11 01 10
11 01 11
11 10 00
11 10 01
11 10 10
11 10 11
11 11 XX2
Attenuation
46.5
48.0
49.5
51.0
52.5
54.0
55.5
57.0
58.5
60.0
61.5
63.0
64.5
66.0
67.5
69.0
70.5
72.0
73.5
75.0
76.5
78.0
79.5
81.0
82.5
84.0
85.5
87.0
88.5
∞
VOUT1
0.0473
0.0398
0.0335
0.0282
0.0237
0.0200
0.0168
0.0141
0.0119
0.0100
0.00841
0.00708
0.00596
0.00501
0.00422
0.00355
0.00299
0.00251
0.00211
0.00178
0.00150
0.00126
0.00106
0.000891
0.000750
0.000631
0.000531
0.000447
0.000376
NOTES
1
VIN = –10 V dc
2
X = 1 or 0. Output is fully muted for N ≥ 60
3
Monotonic operation is not guaranteed for N = 58, 59
–4–
REV. A
Applications Information–AD7118
coupling across the parasitic capacitance. It should be noted
that the accuracy of the AD7118 improves as VDD is increased
(see Figure 8) but the device maintains monotonic behavior to
at least –66 dB in the range 5 ≤ VDD ≤ 15 volts.
DYNAMIC PERFORMANCE
The dynamic performance of the AD7118 will depend upon the
gain and phase characteristics of the output amplifier, together
with the optimum choice of PC board layout and decoupling
components. Figure 4 shows a printed circuit layout which
minimizes feedthrough from VIN to the output in multiplying
applications. Circuit layout is most important if the optimum
performance of the AD7118 is to be achieved. Most application
problems stem from either poor layout, grounding errors, or inappropriate choice of amplifier.
For operation beyond 250 kHz, capacitor C1 may be reduced in
value. This gives an increase in bandwidth at the expense of a
poorer transient response as shown in Figures 6 and 11. In circuits where C1 is not included the high frequency roll-off point
is primarily determined by the characteristics of the output amplifier and not the AD7118.
Feedthrough and absolute accuracy for attenuation levels beyond 42 dB are sensitive to output leakage current effects. For
this reason it is recommended that the operating temperature of
the AD7118 be kept as close to 25°C as is practically possible,
particularly where the device’s performance at high attenuation
levels is important. A typical plot of leakage current vs. temperature is shown in Figure 10.
Some solder fluxes and cleaning materials can form slightly conductive films which cause leakage effects between analog input
and output. The user is cautioned to ensure that the manufacturing process for circuits using the AD7118 does not allow
such films to form. Otherwise the feedthrough, accuracy and
maximum usable range will be affected.
Figure 4. Suggested Layout for AD7118 and Op Amp
It is recommended that when using the AD7118 with a high
speed amplifier, a capacitor C1 be connected in the feedback
path as shown in Figure 1. This capacitor, which should be
between 30 pF and 50 pF, compensates for the phase lag introduced by the output capacitance of the D/A converter. Figures 5
and 6 show the performance of the AD7118 using the AD517, a
fully compensated high gain superbeta amplifier, and the
AD544, a fast FET input amplifier. The performance without
C1 is shown in the middle trace and the response with C1 in
circuit is shown in the bottom trace.
STATIC ACCURACY PERFORMANCE
The D/A converter section of the AD7118 consists of a 17-bit
R-2R type converter. To obtain optimum static performance at
this level of resolution it is necessary to pay great attention to
amplifier selection, circuit grounding, etc.
Amplifier input bias current results in a dc offset at the output
of the amplifier due to the current flowing through the feedback
resistor RFB. It is recommended that an amplifier with an input
bias current of less than 10 nA be used (e.g., AD517 or AD544)
to minimize this offset.
Another error arises from the output amplifier’s input offset
voltage. The amplifier is operated with a fixed feedback resistance, but the equivalent source impedance (the AD7118 output impedance) varies as a function of attenuation level. This
has the effect of varying the “noise” gain of the amplifier, thus
creating a varying error due to amplifier offset voltage. To
achieve an output offset error less than one half the smallest step
size, it is recommended that an amplifier with less than 50 µV of
input offset be used (such as the AD517 or AD OP07).
Figure 5. Response of AD7118 with AD517L
If dc accuracy is not critical in the application, it should be
noted that amplifiers with offset voltage up to approximately 2
millivolts can be used. Amplifiers with higher offset voltage may
cause audible “thumps” due to dc output changes.
The AD7118 accuracy is specified and tested using only the
internal feedback resistor. It is not recommended that “gain”
trim resistors be used with the AD7118 because the internal
logic of the circuit executes a proprietary algorithm which approximates a logarithmic curve with a binary D/A converter: as a
result no single point on the attenuator transfer function can be
guaranteed to lie exactly on the theoretical curve. Any “gainerror” (i.e., mismatch of RFB to the R-2R ladder) that may exist
in the AD7118 D/A converter circuit results in a constant
attenuation error over the whole range. Since the gain error of
CMOS multiplying D/A converters is normally less than 1%,
the accuracy error contribution due to “gain error” effects is
normally less than 0.09 dB.
Figure 6. Response of AD7118 with AD544S
In conventional CMOS D/A converter design parasitic
capacitance in the N-channel D/A converter switches can give
rise to glitches on the D/A converter output. These glitches result from digital feedthrough. The AD7118 has been designed
to minimize these glitches as much as possible. It is recommended that for minimum glitch energy the AD7118 be operated with VDD = 5 V. This will reduce the available energy for
REV. A
–5–
C628a–10–3/83
AD7118 –Typical Performance Characteristics
Figure 10. Output Leakage Current as Temperature at
VDD = 5, 10 and 15 Volts
Figure 7. Digital Threshold & Power Supply Current vs.
Power Supply
Figure 8. DC Attenuation Error vs. Attenuation & VDD
PRINTED IN U.S.A.
Figure 11. Frequency Response with AD544 and
AD517 Amplifiers
Figure 9. DC Attenuation Error vs. Attenuation &
Temperature
Figure 12. Distortion vs. Frequency Using AD544
Amplifier
–6–
REV. A