IDT MC100ES6056EGR2 2.5v, 3.3v ecl/lvpecl/lvds dual differential 2:1 multiplexer Datasheet

MC100ES6056
2.5V, 3.3V ECL/LVPECL/LVDS DUAL
DIFFERENTIAL 2:1 MULTIPLEXER
The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path
makes the device ideal for multiplexing low skew clock or other skew sensitive signals.
Multiple VBB pins are provided.
The VBB pin, an internally generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is connected to VBB as a
switching reference voltage. VBB may also rebias AC coupled inputs. When used,
decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5
mA. When not used, VBB should be left open.
The device features both individual and common select inputs to address both data
path and random logic applications.
The 100ES Series contains temperature compensation.
DT SUFFIX
20-LEAD TSSOP PACKAGE
CASE 948E-03
EJ SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 948E-03
Features
•
•
•
•
•
•
•
•
•
•
360 ps Typical Propagation Delays
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
ECL Mode Operating Range: VCC = 0 V with VEE = –2.375 V to –3.8 V
Open Input Default State
Separate and Common Select
Q Output Will Default LOW with Inputs Open or at VEE
VBB Outputs
LVDS Input Compatible
20-Lead Pb-Free Package Available
EG SUFFIX
20-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
ORDERING INFORMATION
Device
MC100ES6056DT
MC100ES6056DTR2
VCC
Q0
Q0
20
19
18
1
SEL0 COM_SEL SEL1
17
16
15
0
VCC
Q1
Q1
VEE
14
13
12
11
1
Package
TSSOP-20
TSSOP-20
MC100ES6056EJ
TSSOP-20 (Pb-Free)
MC100ES6056EJR2
TSSOP-20 (Pb-Free)
MC100ES6056EG
MC100ES6056EGR2
SOIC-20 (Pb-Free)
SOIC-20 (Pb-Free)
0
1
2
3
4
5
6
7
8
9
10
D0a
D0a
VBB0
D0b
D0b
D1a
D1a
VBB1
D1b
D1b
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram
IDT™ / ICS™ 2:1 MULTIPLEXER
1
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
Table 1. Pin Description
Pin
ADVANCED CLOCK DRIVERS DEVICES
Table 2. Function Table
Function
D0a* – D1a*
ECL Input Data a
D0a* – D1a*
ECL Input Data a Invert
D0b* – D1b*
ECL Input Data b
D0b* – D1b*
ECL Input Data b Invert
SEL0* – SEL1*
ECL Indiv. Select Input
COM_SEL*
ECL Common Select Input
VBB0, VBB1
Output Reference Voltage
Q0 – Q1
ECL True Outputs
Q0 – Q1
ECL Inverted Outputs
VCC
Positive Supply
VEE
Negative Supply
SEL0
SEL1
COM_SEL
Q0, Q0
Q1, Q1
X
L
L
H
H
X
L
H
H
L
H
L
L
L
L
a
b
b
a
a
a
b
a
a
b
* Input function will default LOW when left open.
Table 3. General Specifications
Characteristics
Value
Internal Input Pulldown Resistor
75 kΩ
Internal Input Pullup Resistor
75 kΩ
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 400 V
> 2 kV
Thermal Resistance
(Junction-to-Ambient)
0 LFPM, 20 TSSOP
500 LFPM, 20 TSSOP
140°C/W
100°C/W
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
IDT™ / ICS™ 2:1 MULTIPLEXER
2
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
ADVANCED CLOCK DRIVERS DEVICES
Table 4. DC Characteristics (VCC = 0 V, VEE = –2.5 V ± 5% or 3.8 V to –3.135 V; VCC = 2.5 V ± 5% or 3.135 V to 3.8 V, VEE = 0 V)
Symbol
IEE
VOH
–40°C
Characteristics
Min
0°C to 85°C
Typ
Max
30
60
VCC–960
VCC–880
Power Supply Current
Min
Unit
Typ
Max
30
60
mA
VCC–930
(1)
VCC–1085
VCC–860
mV
(1)
VCC–1950 VCC–1695 VCC–1500 VCC–1950 VCC–1705 VCC–1500
mV
Output HIGH Voltage
VCC–1025
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VCC–1165
VCC–880
VCC–1165
VCC–880
mV
VIL
Input LOW Voltage
VCC–1810
VCC–1475 VCC–1810
VCC–1475
mV
VBB
Output Reference Voltage
VCC–1380 VCC–1290 VCC–1220 VCC–1380 VCC–1290 VCC–1200
mV
VPP
VCMR
Differential Input Voltage
(2)
Differential Cross Point Voltage
IIH
Input HIGH Current
IIL
Input LOW Current
(3)
0.15
1.3
0.15
1.3
VCC –2.3
VCC–0.8
VCC –2.3
VCC–0.8
V
150
µA
150
0.5
V
µA
0.5
1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase.
2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
Table 5. Absolute Maximum Ratings(1)
Symbol
VSUPPLY
Characteristic
Power Supply Voltage
VIN
Input Voltage
IOUT
Output Current
Conditions
Rating
Units
Difference between VCC & VEE
3.9
V
VCC – VEE ≤ 3.6 V
VCC + 0.3
VEE – 0.3
V
Continuous
Surge
50
100
mA
mA
±0.5
°C
IBB
VBB Sink/Source Current
TA
Operating Temperature Range
–40 to +85
°C
Storage Temperature Range
–65 to +150
°C
TSTG
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
IDT™ / ICS™ 2:1 MULTIPLEXER
3
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
ADVANCED CLOCK DRIVERS DEVICES
Table 6. AC Characteristics (VCC = 0 V; VEE = –2.5 V ± 5% or –3.8 V to –3.135 V; VCC = 2.5 V ± 5% or 3.135 V to 3.8 V;
VEE = 0 V)(1)
–40°C to 85°C
Symbol
fmax
tPLH, tPHL
Characteristics
Max
300
300
300
400
430
490
500
600
650
ps
ps
ps
10
50
200
ps
ps
1
ps
>3
D to Q, Q
SEL to Q, Q
COM_SEL to Q, Q
tSKEW
Skew
Output-to-Output(2)
Part-to-Part
tJITTER
Cycle-to-Cycle Jitter
VPP
Minimum Input Swing
tr / tf
Typ
Maximum Frequency
Propagation Delay to Output Differential
VCMR
Min
RMS (1σ)
200
Differential Cross Point Voltage
800
VCC–2.1
Output Rise/Fall Time (20%–80%)
70
120
Unit
GHz
1200
mV
VCC–1.1
V
230
ps
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50Ω to VCC–2.0 V.
2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are
measured from the cross point of the inputs to the cross point of the outputs.
Q
D
Driver
Device
Receiver
Device
Q
D
50 Ω
50 Ω
VTT
Figure
1
VTT = VCC – 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
IDT™ / ICS™ 2:1 MULTIPLEXER
4
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
ADVANCED CLOCK DRIVERS DEVICES
PACKAGE DIMENSIONS
CASE 948E-03
ISSUE B
20-LEAD TSSOP PACKAGE
IDT™ / ICS™ 2:1 MULTIPLEXER
5
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
ADVANCED CLOCK DRIVERS DEVICES
PACKAGE DIMENSIONS
CASE 948E-03
ISSUE B
20-LEAD TSSOP PACKAGE
IDT™ / ICS™ 2:1 MULTIPLEXER
6
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
ADVANCED CLOCK DRIVERS DEVICES
PACKAGE DIMENSIONS
CASE 751D-07
ISSUE J
20-LEAD SOIC PACKAGE
IDT™ / ICS™ 2:1 MULTIPLEXER
7
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER
ADVANCED CLOCK DRIVERS DEVICES
PACKAGE DIMENSIONS
CASE 751D-07
ISSUE J
20-LEAD SOIC PACKAGE
IDT™ / ICS™ 2:1 MULTIPLEXER
8
MC100ES6056 REV. 5 JULY 16, 2007
MC100ES6056
3.3V, 2.5VECL/LVPECL/LVDS DUAL DIFFERENTIAL 2:1 MULTIPLEXER ADVANCED CLOCK DRIVERS DEVICESADVANCED
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