Ver1.0 1 A1 PROs Ai5412 A1 PROs Timing Controller for CCD Monochrome Camera Description Pin Configuration CKI OSCOUT OSCIN HCOMP MODE5 VDD2 MODE4 MODE3 ESYNC VR/SYNC HPLL EXT The Ai5412 is a timing and sync one chip controller IC with auto IRIS function for B/W CCD camera systems, which is fabricated in the Hynix 0.8§ -CMOS process. HVDD H1 H2 HVSS RG VSS1 XV2 XV1 XSG1 XV3 XSG2 XV4 Feature Ai5412 XSUB ENB IRENB MODE2 IRIN/ED1 Vss2 VDD1 Vreg CVDD SPDNV/ED2 SPUPV/ED0 CVSS • EIA / CCIR standards • Auto IRIS function • Supports field / frame accumulation mode • Supports external sync mode • Supports non-interlacing mode • Oscillator frequency : 1212fh (EIA : 19.0699MHz, CCIR : 18.9375MHz) • 48 pin TQFP • Kit with Ai1001S, Ai4402 • Built-in sync signal generation function BLKO SYNC HD VD FLD VSS3 CLP1 CLP2 FL/FR MODE1 SHD SHP Application 48 PIN TQFP (Top View) CCD monochrome camera systems. Absolute Maximum Ratings (Ta = 25¡ É , Vss=0V) Symbol Parameter Rating Unit VDD Supply Voltage Vss-0.5 to +7.5 V VI Input Voltage Vss-0.5 to VDD+0.5 V Vo Output Voltage Vss-0.5 to VDD+0.5 V TOPR Operating Temperature -20 ~ +75 ¡ É TSTG Storage Temperature -55 ~ +150 ¡ É Operating Conditions Symbol Parameter Rating Unit VDD Supply Voltage 5.0 ¡ ¾0.25 V TOPR Operating Temperature -20 ~ +75 ¡ É 1 2 1 5 HVDD RG 8 7 10 XV1 XV2 XV3 XV4 12 26 SHD SHP 25 3 H2 2 H1 48 4 CKI HVSS 1212fH 9 11 XSG1 XSG2 1/2 37 35 VR1 1/606 39 36 32 30 29 41 16 24 1/525 RESET GEN 42 22 33 HD MODE4 MODE3 VD 34 Timing Logic SYNC SEP 38 CVSS SYNC BLKO FLD CLP1CLP2 MODE2 40 EXT ESYNC HPLLVR/SYNC HD1 45 Delay HCOMP OSCOUT 47 46 OSCIN LPF Block Diagram Field/ Frame 28 SPDNV /ED2 17 IRIN /ED1 UP/DOWN O/E 27 MODE1 FL/FR 21 LPF Vreg 20 CVDD ED0 SELECTOR SPUPV / ED0 23 6 VSS1 18 VSS2 31 ED1 IRIS SIGNAL ED2 GATE 44 VSS3 MODE5 DECODE IRIS/SHUTTER CK GEN. 43 VDD2 IRIS COUNTER 19 VDD1 15 IRENB 14 ENB 13 XSUB Ai5412 Ai5412 Pin Description NO. Symbol I/O Description 1 HVDD - Power supply (for H1, H2) 2 H1 O H1 clock output for CCD horizontal register drive 3 H2 O H2 clock output for CCD horizontal register drive 4 HVSS - GND(for H1, H2) 5 RG - Reset gate pulse output 6 VSS 1 - GND 7 XV2 O XV2 clock output for CCD vertical register drive 8 XV1 O XV1 clock output for CCD vertical register drive 9 XSG1 O CCD sensor charge readout pulse output 10 XV3 O XV3 clock output for CCD vertical register drive 11 XSG2 O CCD sensor charge readout pulse output 12 XV4 O XV4 clock output for CCD vertical register drive 13 XSUB O CCD discharge pulse output 14 ENB I 15 IRENB I 16 MODE2 I 17 IRIN/ED1 18 Vss2 - GND 19 VDD 1 - Power supply 20 Vreg - Bias current supply for comparator 21 CVDD - Power supply (for comparator) 22 23 SPDNV /ED2 SPUPV /ED0 I*1 I*1 I*1 XSUB pulse output ON/OFF control (with pull-up resistance) Low : XSUB pulse output stop ; High : XSUB pulse output Low : Electronic shutter mode ; High : Auto iris mode (with pull-up resistance) Electronic shutter speed input switchover (with pull-up resistance) Low : serial input ; High : parallel input Iris signal input/shutter speed setting ; clock input in serial mode Shutter speed down reference voltage/ Shutter speed setting ; data input in serial mode Shutter speed up reference voltage / Shutter speed setting ; strobe input in serial mode 24 CVSS - GND(for comparator) 25 SHP O Pre charge level sample-and-hold pulse 26 SHD O Data sample-and-hold pulse 27 MODE1 I Low : EIA ; High : CCIR (with pull-down resistance) 3 Ai5412 NO. Symbol I/O Description 28 FL/FR I Field accumulation/frame accumulation, odd field/even field switchover (with pull-down resistance) 29 CLP2 O Pulse output for clamp 30 CLP1 O Pulse output for clamp 31 VSS3 - GND 32 FLD O Field identification signal output (High : odd field ; Low : even field) 33 VD O Vertical drive output 34 HD O Horizontal drive output 35 SYNC O Composite sync output 36 BLKO O Composite blanking output 37 EXT O External sync/internal sync identification signal High : external sync ; Low : internal sync 38 HPLL I Horizontal drive signal input (with pull-up resistance) 39 VR/SYNC I Vertical drive signal input/composite sync input (with pull-up resistance) 40 ESYNC I Low : SYNC sync or internal sync ; High : VD/HD sync (with pull-down resistance) 41 MODE3 I Low : interlace mode ; High : non-interlace mode (with pull-down resistance) 42 MODE4 I Line number selection pin (with pull-down resistance) Low : EIA 262H/CCIR 312H ; High : EIA 263H/CCIR 313H 43 VDD2 - Power supply 44 MODE5 I*2 Low : Normal mode ; High : Test mode (with pull-down resistance) 45 HCOMP O Comparator output (H phase comparator) 46 OSCIN I*3 Oscillation (crystal oscillator) inverter input 47 OSCOUT O Oscillation (crystal oscillator) inverter output 48 CKI I*4 Clock input I*1 Comparator Input I*2 Fixed to low level I*3 OSCILLATOR Cell Input cell with feedback resistance I*4 4 Ai5412 Electrical Characteristics (VDD = 5V¡ ¾ 0.25V, Topr = -20 to 75 ¡ É) 1) DC Characteristics Item Min Typ Max Unit VDD 4.75 5.0 5.25 V VIH 0.7VDD Symbol Supply voltage Input voltage Conditions V 0.3VDD VIL VOH1 Output voltage 1 (All output pins except those below)VOL1 IOH = -2mA V IOL = 4mA Output voltage 2 (Pins 25, 26) VOH2 IOH = -4mA VOL2 IOL = 8mA Output voltage 3 (Pin 5, 45) VOH3 IOH = -8mA VOL3 IOL = 8mA Output voltage 4 (Pins 2, 3) VOH4 IOH = -12mA VOL4 IOL = 12mA Output voltage 5 (Pin 47) VOH5 IOH = -1mA VOL5 IOL = 1mA Feedback resistance RFB VIN = VSS or VDD Pull-up current IPU VIL = 0V Pull-down current IPD VIH = VDD Current consumption IDD VDD = 5V normal operating state V VDD - 0.8 0.4 V 0.4 V VDD - 0.8 V VDD - 0.8 V 0.4 V VDD - 8 0.4 VDD / 2 V 0.4 V 2.5M ¥Ø -80 -30 § Ë 40 110 § Ë 250K 1M § Ì 28 2) AC Characteristics SPDNV(ED2) ts2 th2 IRIN(ED1) ts1 ts0 SPUPV(ED0) tw0 Symbol Item Min. Max. ts2 SPDNV (ED2) setup time for IRIN (ED1) rise 20ns - th2 SPDNV (ED2) hold time for IRIN (ED1) rise 20ns - ts1 IRIN (ED1) setup time for SPUPV (ED0) rise 20ns - tw0 SPUPV (ED0) pulse width 20ns 50§ Á ts0 SPUPV (ED0) setup time for IRIN (ED1) rise 20ns - 5 Ai5412 Electronic Shutter/Auto IRIS By setting the ENB pin (Pin 14) high, the XSUB pulse is output for a specific period to activate the electronic shutter and auto iris. 1) Auto Iris (IRENB=high, MODE2=any level) Symbol NO. Function IRIN/ED1 17 Iris signal input SPDNV/ED2 22 Shutter speed down reference voltage SPUPV/ED0 23 Shutter speed up reference voltage 2) Parallel input electronic shutter (IRENB=low, MODE2=high) Symbol NO. SPDNV/ED2 22 H H H H L L L L IRIN/ED1 17 H H L L H H L L SPUPV/ED0 23 H L H L H L: H L EIA: 1/100 CCIR: 1/120 1/250 1/500 1/1000 1/2000 1/5000 Shutter speed Function 1/10000 1/100000 3) Serial input electronic shutter (IRENB=low, MODE2=high) Serial input data format SPDNV/ED2 D7 D6 D5 D4 D3 D2 D1 D0 IRIN/ED1 SPUPV/ED0 The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise. Typical shutter speed EIA CCIR Load value Shutter speed Load value Shutter speed 00h 1/100000 00h 1/80000 4Eh 1/10000 4Ah 1/10000 6Ah 1/5000 65h 1/5000 87h 1/2000 82h 1/2000 9Ch 1/1000 97h 1/1000 ACh 1/500 A7h 1/500 CAh 1/250 C5h 1/250 EDh 1/100 E1h 1/120 6 Ai5412 External Synchronization 1) External/internal sync selection External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations. VR/SYNC pin : SYNC signal VR/SYNC pin : VD signal HPLL pin : Open HPLL pin : HD signal ESYNC pin : Open ESYNC pin : VDD Input pattern EXT pin output Sync state VR/SYNC pin : Open HPLL pin : Open ESYNC pin : Open High High Low External sync External sync Internal sync Note ) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal. The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for improving the oscillation accuracy for internal synchronization. 2) Modes for external synchronization Mode Interlace SYNC synchronization Field accumulation Frame accumulation O O X X (Cannot be accomplished since interlace operation is the prior condition) (Cannot be accomplished since interlace operation is the prior condition) Interlace O O Non-interlace O (Not practically applicable since the sensitivity is halved) Non-interlace VD/HD synchronization X 3) Reset operation SYNC synchronization The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA,V reset is performed so that the VD pulse falls at the count of 259H (262.5-3.5H) from the fall of the VR1 pulse. For CCIR, it is reset in such a way that the VD pulse falls at the count of 309H(312.5-3.5H).For these reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard. VD/HD synchronization V reset is performed so that the VD pulse 1H later after detecting the fall of the VD(VDR) pulse supplied externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference between the VDRpulse and HD pulse which is locked horizontally at PLL circuit identifies whether the field is odd or even. (VDR must have a pulse width of 2H or more.) 7 Ai5412 Mode Control Symbol NO. I/O Low High ENB 14 I XSUB stop XSUB output IRENB 15 I Electronic shutter Auto iris Valid only when ENB is high. MODE2 16 I Serial input Parallel input Valid only when ENB is high and IRENB is low IRIN/ED1 17 I SPDNV/ED2 22 I SPUPV/ED0 23 I MODE1 27 I FL/FR 28 Auto iris control signal input pin (IRENB = high) Shutter speed setting pin (IRENB = low) Remarks Valid only when ENB is high. EIA CCIR Odd field Even field Valid only when MODE3 is high and EXT is low. Field accumulation Frame accumulation Valid in all other modes. I Internal sync : HPLL (open) VR/SYNC (open) SYNC sync : HPLL (open) VR/SYNC (SYNC input) VD/HD sync : HPLL (HD input) VR/SYNC (VD input) HPLL 38 I VR/SYNC 39 I ESYNC 40 I SYNC sync Internal sync VD/HD sync MODE3 41 I Interlace Non-interlace Valid only when EXT is low. MODE4 42 I EIA : 262H CCIR : 312H EIA : 263H CCIR : 313H Valid only when EXT is low and MODE 3 is high. External sync Switchover between internal and external sync is automatically identified by input state at Pins 38, 39 and 40. EXT 37 O Internal sync 8 Ai5412 Mode Tables 1) Internal sync mode HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : Open ESYNC pin (Pin 40) : Open Interlace Non-interlace Odd field *2 Even field *2 Field Frame Field Frame readout readout readout readout O X O X XSUB pulse OFF*1 Field readout O Frame readout O Electronic shutter ON O O O X O X Auto iris ON O O O X O X *1 EIA for 1/60 s accumulation ; CCIR for 1/50 s accumulation *2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. O : Can be used. X : Cannot be used. 2) SYNC sync (external sync) mode HPLL pin (Pin 38) : Open VR/SYNC pin (Pin 39) : SYNC input ESYNC pin (Pin 40) : Open Interlace Non-interlace Odd field *2 Even field *2 Field Frame Field Frame readout readout readout readout X X X X XSUB pulse OFF*1 Field readout O Frame readout O Electronic shutter ON O O X X X X Auto iris ON O O X X X X *1 EIA for 1/60 s accumulation ; CCIR for 1/50 s accumulation *2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. O : Can be used. X : Cannot be used. 3) VD/HD sync (external sync ) mode HPLL pin (Pin 38) : HD input VR/SYNC pin (Pin 39) : VD input ESYNC pin (Pin 40) : VDD (power supply) XSUB pulse OFF*1 Serial input electronic shutter ON Parallel input electronic shutter ON Auto iris ON VD input with normal cycle VD input with longer cycle than Non-interlace Interlace normal Interlace 2 2 Odd field * Even field * Field Frame Field Frame Field Frame Field Frame readout readout readout readout readout readout readout readout O O O X O X O X O O O X O X X X O O ¡ â X ¡ â X X X O O O X O X X X *1 EIA for 1/60 s accumulation ; CCIR for 1/50 s accumulation *2 Line number is 262H or 263H for EIA and 312H or 313H for CCIR. O : Can be used. ¡ â: The shutter speed may change from its value in the interlace mode. X : Cannot be used. Note ) Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with longer cycle than normal are input to the VR/SYNC pin. 9 Ai5412 ( Timing Chart 1 ) High-Speed phase EIA/CCIR 52.4ns(EIA) 52.8ns(CCIR) CK H1 26.2ns(EIA) 26.4ns(CCIR) RG CCD OUT SHP SHD 10 11 FLD VD VSYNC EQ HSYNC BLKO HD CCIR FLD VD VSYNC EQ HSYNC BLKO HD EIA 2.3 s (22CK) 4.75 s (45CK) 12.04 s (114CK) 6.23 s (59CK) 1.478 s(14CK) 2.3 s (22CK) 4.72 s (45CK) 10.9 s (104CK) 6.187 s (59CK) 1.468 s(14CK) 4.75 s (45CK) 4.72 s (45CK) (Timing Chart 2) Horizontal effective period 1/2H 1/2H 1.478 s(14CK) 1.468 s(14CK) 1CK=105.6ns 1CK=104.87ns Ai5412 EVEN ODD 12 XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 XSG2 XSG1 HD A. Field accumulation (366CK) E:38.38 S C:38.65 S ( Timing Chart 3 ) Charge Readout Timing (3CK) E:0.315 S C:0.317 S (12CK) E:1.26 S C:1.27 S (24CK) E:2.51 S C:2.53 S (19CK) E:1.99 S C:2.0 S (15CK) E:1.57 S C:1.58 S E:EIA 1CK=104.87ns C:CCIR 1CK=105.6ns Ai5412 EVEN ODD 13 XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 XSG2 XSG1 HD B. Frame accumulation (378CK) E:39.64 S C:39.92 S (3CK) E:0.315 S C:0.317 S (24CK) E:2.51 S E:2.53 S E:EIA 1CK=104.87ns C:CCIR 1CK=105.6ns Ai5412 14 14 VSYNC VD 14 14 EQ FLD 14 49 7 10 HSYNC XSUB XV4 XV3 XV2 XV1 CLP2 CLP1 SHD SHP RG H2 H1 MCK HD A. H direction, EIA ( Timing Chart 4 ) 20 26 23 32 30 36 38 40 44 50 50 55 59 56 59 62 60 73 68 70 80 80 90 94 100 103 104 ( MCK=CKI/2 ) Ai5412 15 14 VSYNC VD 14 14 EQ FLD 14 7 10 HSYNC XSUB XV4 XV3 XV2 XV1 CLP2 CLP1 SHD SHP RG H2 H1 MCK HD B. H direction, CCIR 23 20 31 30 36 37 43 40 49 50 55 60 59 60 59 61 67 73 70 77 80 84 90 98 100 107 114 ( MCK=CKI/2 ) Ai5412 16 XV1 XV2 XV3 XV4 CCD OUT CLP1 CLP2 HD VD SYNC BLKO FLD XSG1 XSG2 CLP1 CLP2 FLD XSG1 XSG2 XV1 XV2 XV3 XV4 CCD OUT HD VD SYNC BLKO A. V direction, EIA 3 4 1 2 493 9H 492 FIELD. O 3 1 492 20H 20H 2 FIELD. E 9H FIELD. O 491 493 FIELD. E ( Timing Chart 5) Low - Speed Phase Ai5412 17 HD VD SYNC BLKO FLD XSG1 XSG2 XV1 XV2 XV3 XV4 CCD OUT CLP1 CLP2 HD VD SYNC BLKO FLD XSG1 XSG2 XV1 XV2 XV3 XV4 CCD OUT CLP1 CLP2 B. V direction, CCIR 583 583 582 FIELD. O 582 581 FIELD. E 7.5H FIELD. E 14.5H 7.5H FIELD. O 14H 25H 25H 1 3 2 Ai5412 18 VDR VR1 HD1 SYNC VD HD VDR VR1 HD1 SYNC VD HD VDR VR1 HD1 SYNC VD HD VDR VR1 HD1 SYNC VD HD FIELD. O FIELD. E FIELD. O FIELD. E 7.5H FIELD. E 7.5H FIELD. O 9H FIELD. E 9H FIELD. O External Synchronization reset Operation ( Timing Chart 6 ) CCIR EIA Ai5412 19 22p 19.0699MHz(EIA) or 18.9375MHz(CCIR) 22p SYNC IN 33 2.2K 47p 220p 2.2K 2.2K 271p 100 100 1 2 3 4 6.8¥ì/6.3V RG ADJ 0.1¥ì VSUB ADJ 7 8 9 10 11 12 Vertical Driver 14 47 6 15 46 5 16 45 13 17 44 48 18 43 19 20 41 Ai5412 21 42 22 39 23 38 40 24 37 36 35 34 33 32 31 30 29 28 27 26 25 2.2K CCD(250/290K pixels 33 0.1¥ì 6.8¥ì /6.3V 0.1¥ì 47p 0.1¥ì 10K 0.1¥ì 36K 6.8¥ì /6.3V 6.8¥ì/6.3V 50K 0.15¥ì 270K IMX1 CCD OUT 150K 50K 3.9K 27 20 21 25 30 4 29 IRIS VIDEO OUT Signal Processor 24 Ai5412 Application Circuit Ai5412 Package Outline -C- 48pin TQFP(PLASTIC) 0.10 0.05 0.10 C UNIT : mm D 8-12±1 "A" 1.50MAX -D- v 0.20 C A-B D 0.5BSC # 0.22±0.05 *7.0BSC 9.00BSC (3.5) -B- -A- DATUM PLANE (3.5) D D *7.0BSC 9.00BSC 0.20 H A-B D 0.20 C A-B D 0.2MIN 0.09-0.2 0 0.25 20 -0. 08 . 0.6±0.15 GAUGE PLANE 1.40±0.05 . RO 0-7 0.10±0.05 (0.6375) (0.6375) 0.MIN -H- 1.00REF DETAILS of " A " Note ) 1. DIMENSION * MARK DOES NOT INCLUDE MOLD FLASH 2. DIMENSION # MARK DOES NOT INCLUDE DAMBAR PROTRUSION 3.UNSPECIFIED IS ACCORDING TO JEDEC MO-136, VARIATION "BE" 20