MC14532B 8−Bit Priority Encoder The MC14532B is constructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active input with the highest priority. Eight data inputs (D0 thru D7) and an enable input (Ein) are provided. Five outputs are available, three are address outputs (Q0 thru Q2), one group select (GS) and one enable output (Eout). http://onsemi.com Features MARKING DIAGRAMS • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low−Power TTL Loads or One Low−Power Schottky TTL Load over the Rated Temperature Range MC14532BCP AWLYYWWG • Pb−Free Packages are Available* 1 MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Value Unit DC Supply Voltage Range Rating VDD −0.5 to +18.0 V Input or Output Voltage Range (DC or Transient) Vin, Vout −0.5 to VDD + 0.5 V Iin, Iout ± 10 mA Power Dissipation, per Package (Note 1) PD 500 mW Ambient Temperature Range TA −55 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Lead Temperature (8 Sec Soldering) TL 260 °C Input or Output Current (DC or Transient) per Pin Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. TRUTH TABLE Input Output 1 PDIP−16 P SUFFIX CASE 648 1 SOIC−16 D SUFFIX CASE 751B A WL YY, Y WW G 14532BG AWLYWW 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN ASSIGNMENT D4 1 16 VDD D5 2 15 Eout D6 3 14 GS Ein D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0 Eout D7 4 13 D3 0 1 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 0 0 0 0 0 0 0 0 0 1 Ein 5 12 D2 1 1 1 1 1 0 0 0 X 1 0 0 X X 1 0 X X X 1 X X X X X X X X X X X X X X X X 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 Q2 6 11 D1 Q1 7 10 D0 VSS 8 9 Q0 1 0 0 0 0 1 X X X 1 0 1 1 0 1 0 0 0 0 0 1 X X 1 0 1 0 0 ORDERING INFORMATION 1 0 0 0 0 0 0 1 X 1 0 0 1 0 See detailed ordering and shipping information in the package 1 0 0 0 0 0 0 0 1 1 0 0 0 0 dimensions section on page 2 of this data sheet. X = Don’t Care *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 6 1 Publication Order Number: MC14532B/D MC14532B ORDERING INFORMATION Device Shipping † Package MC14532BCP PDIP−16 MC14532BCPG PDIP−16 (Pb−Free) MC14532BD SOIC−16 MC14532BDG SOIC−16 (Pb−Free) MC14532BDR2 SOIC−16 MC14532BDR2G SOIC−16 (Pb−Free) 25 Units / Rail 48 Units / Rail 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) − 55_C 25_C VDD 125_C Symbol Vdc Min Max Min Typ (Note 2) Max Min Max Unit “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 – 0.64 –1.6 – 4.2 − − − − –2.4 – 0.51 –1.3 –3.4 –4.2 – 0.88 – 2.25 – 8.8 − − − − –1.7 – 0.36 –0.9 –2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Characteristic Output Voltage Vin = VDD or 0 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.74 mA/kHz) f + IDD IT = (3.65 mA/kHz) f + IDD IT = (5.73 mA/kHz) f + IDD 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005. http://onsemi.com 2 mAdc MC14532B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) (Note 5) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time — Ein to Eout tPLH, tPHL = (1.7 ns/pF) CL + 120 ns tPLH, tPHL = (0.66 ns/pF) CL + 77 ns tPLH, tPHL = (0.5 ns/pF) CL + 55 ns tPLH, tPHL Propagation Delay Time — Ein to GS tPLH, tPHL = (1.7 ns/pF) CL + 90 ns tPLH, tPHL = (0.66 ns/pF) CL 57 ns tPLH, tPHL = (0.5 ns/pF) CL + 40 ns tPLH, tPHL Propagation Delay Time — Ein to Qn tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH, tPHL = (0.66 ns/pF) CL + 107 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPHL, tPLH Propagation Delay Time — Dn to Qn tPLH, tPHL = (1.7 ns/pF) CL + 265 ns tPLH, tPHL = (0.66 ns/pF) CL + 137 ns tPLH, tPHL = (0.5 ns/pF) CL + 85 ns tPLH, tPHL Propagation Delay Time — Dn to GS tPLH, tPHL = (1.7 ns/pF) CL + 195 ns tPLH, tPHL = (0.66 ns/pF) CL + 107 ns tPLH, tPHL = (0.5 ns/pF) CL + 75 ns tPLH, tPHL VDD Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 5.0 10 15 − − − 205 110 80 410 220 160 5.0 10 15 − − − 175 90 65 350 180 130 5.0 10 15 − − − 280 140 100 560 280 200 5.0 10 15 − − − 300 170 110 600 340 220 5.0 10 15 − − − 280 140 100 560 280 200 Unit ns ns ns ns ns ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. Vout Ein SWITCH MATRIX D0 D1 Eout D2 D3 Q0 Q1 D4 D5 Q2 VDD ID GS D6 500 mF D7 EXTERNAL POWER SUPPLY VGS = VDD VDS = Vout Sink Current VGS = – VDD VDS = Vout – VDD Source Current Output Under Test D0 thru D7 Ein D0 thru D6 D7 Ein Eout Q0 Q1 Q2 GS X X X X X 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 PULSE GENERATOR (fo) Figure 1. Typical Sink and Source Current Characteristics ID 0.01 mF Ein Eout D0 D1 Q0 D2 D3 Q1 D4 D5 Q2 CL CL CL CL D6 GS D7 VSS CL Figure 2. Typical Power Dissipation Test Circuit http://onsemi.com 3 MC14532B VDD PROGRAMMABLE PULSE GENERATOR Ein Eout D0 D1 Q0 D2 D3 Q1 D4 D5 Q2 CL CL CL D6 CL GS D7 VSS CL NOTE: Input rise and fall times are 20 ns PIN NO. D0 10 D1 11 D2 12 D3 13 D4 1 D5 2 D6 3 D7 4 Ein 5 Eout 15 50% 50% 50% 50% 50% 50% 50% 50% 50% tPLH tPHL 90% 50% 10% tTHL tPLH tTLH GS Q0 Q1 14 9 tTLH tPLH tPHL tPLH tPLH tPLH tPHL tPHL tPLH tPHL tPLH 7 tPLH Q2 6 tTLH Figure 3. AC Test Circuit and Waveforms http://onsemi.com 4 tTLH tPHL tTLH 90% 50% 10% tTHL tPHL 90% 50% 10% tTHL tPHL 90% 50% 10% tTHL tPHL 90% 50% 10% tTHL MC14532B LOGIC EQUATIONS Eout = Ein D0 D1 D2 D3 D4 D5 D6 D7 Q0 = Ein (D1 D2 D4 D6 + D3 D4 D6 + D5 D6 + D7) D0 D1 D2 D3 D4 D5 D6 D7 Ein Q1 = Ein (D2 D4 D5 + D3 D4 D5 + D6 + D7) 10 Q2 = Ein (D4 + D5 + D6 + D7) GS = Ein (D0 + D1 + D2 + D3 + D4 + 05 + D6 + D7) 11 9 Q0 12 13 1 7 Q1 2 3 4 6 5 14 15 Figure 4. Logic Diagram (Positive Logic) http://onsemi.com 5 Q2 GS Eout MC14532B D15 D14 D13 D12 D11 D10 D7 VDD D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Eout Ein Ein GS Q2 Q1 Eout = 1" WITH Din = 0" Eout Q0 Q2 Q1 Q0 3/4 MC14071B Q3 Q2 Q1 Q0 Figure 5. Two MC14532B’s Cascaded for 4−Bit Output VDD VSS CLOCK INPUT C E R C E 1/2 MC14520B DIGITAL TO ANALOG CONVERSION Q1 The digital eight−bit word to be converted is applied to the inputs of the MC14512 with the most significant bit at X7 and the least significant bit at X0. A clock input of up to 2.5 MHz (at VDD = 10 V) is applied to the MC14520B. A compromise between Ibias for the MC1710 and DR between N and P−channel outputs gives a value of R of 33 kW. In order to filter out the switching frequencies, RC should be about 1.0 ms (if R = 33 kW, C [ 0.03 mF). The analog 3.0 dB bandwidth would then be dc to 1.0 kHz. Q3 Q4 Q1 An analog signal is applied to the analog input of the MC1710. A digital eight−bit word known to represent a digitized level less than the analog input is applied to the MC14512 as in the D to A conversion. The word is incremented at rates sufficient to allow steady state to be reached between incrementations (i.e. 3.0 ms). The output of the MC1710 will change when the digital input represents the first digitized level above the analog input. This word is the digital representation of the analog word. Q2 Q4 8−BIT WORD TO BE CONVERTED Ein Q2 Q1 Q0 A B C X7 X6 X5 X4 X3 X2 X1 X0 MC1710 STOP WORD INCREMENTATION Figure 6. Digital to Analog and Analog to Digital Converter http://onsemi.com 6 Q3 DIGITAL INPUT/OUTPUT D0 D1 D2 D3 D4 D5 D6 D7 VDD ANALOG TO DIGITAL CONVERSION Q2 R 1/2 MC14520B MC14512 Z R C ANALOG INPUT ANALOG OUTPUT MC14532B PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L DIM A B C D F G H J K L M S S −T− SEATING PLANE K H D M J G 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC−16 CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 S ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 7 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC14532B/D