Cypress CY7C1011CV33 2-mbit (128 k ã 16) static ram Datasheet

CY7C1011CV33
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
❐ Automotive-E: –40 °C to 125 °C
The CY7C1011CV33 is a high performance complementary
metal oxide semiconductor (CMOS) static RAM organized as
131,072 words by 16 bits. This device has an automatic power
down feature that significantly reduces power consumption when
deselected.
■
Pin and function compatible with CY7C1011BV33
■
High speed
❐ tAA = 10 ns (Industrial and Automotive-A)
❐ tAA = 12 ns (Automotive-E)
■
Low active power
❐ 360 mW (max) (Industrial and Automotive-A)
■
2.0 V data retention
■
Automatic power down when deselected
■
Independent control of upper and lower bits
■
Easy memory expansion with Chip Enable (CE) and Output
Enable (OE) features
■
Available in Pb-free 44-pin thin small outline package
(TSOP) II, 44-pin thin quad flat package (TQFP), and non
Pb-free 48-ball very fine-pitch ball grid array (VFBGA)
packages
To write to the device, take CE and Write Enable (WE) inputs
LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins
(I/O0 through I/O7), is written into the location specified on the
address pins (A0 through A16). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A16).
To read from the device, take CE and OE LOW while forcing the
Write Enable (WE) HIGH. If BLE is LOW, then data from the
memory location specified by the address pins appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. For more information, see the Truth
Table on page 10 for a complete description of Read and Write
modes.
The input and output pins (I/O0 through I/O15) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
Logic Block Diagram
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
128 K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
•
BHE
WE
CE
OE
BLE
A16
A14
A15
A12
A13
A9
Cypress Semiconductor Corporation
Document Number: 38-05232 Rev. *N
A10
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 8, 2013
CY7C1011CV33
Contents
Pin Configuration ............................................................. 3
Selection Guide ................................................................ 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
Electrical Characteristics ................................................. 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Document Number: 38-05232 Rev. *N
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
Page 2 of 16
CY7C1011CV33
Pin Configuration
Figure 1. 44-pin TSOP II [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
A11
A10
A9
OE
BHE
BLE
39
38
37
36
35
34
A12
40
A13
A14
A15
A16
Figure 2. 44-pin TQFP
42
41
43
44
1
1
33
I/O15
I/O0
2
32
I/O14
I/O1
3
31
I/O13
I/O2
4
30
I/O12
I/O3
5
29
VSS
VCC
6
28
VCC
I/O11
CE
20
21
22
A6
A7
A8
NC
19
23
A5
11
18
I/O7
17
I/O8
A4
10
NC
I/O6
16
I/O9
A3
25
24
14
9
15
I/O5
A1
I/O10
A2
26
13
8
12
7
I/O4
WE
A0
VSS
27
Note
1. NC pins are not connected on the die.
Document Number: 38-05232 Rev. *N
Page 3 of 16
CY7C1011CV33
Selection Guide
Description
-10
Maximum access time
Maximum operating current
Maximum CMOS standby current
Document Number: 38-05232 Rev. *N
-12
Unit
10
12
ns
Industrial
100
95
mA
Automotive-A
100
–
mA
Automotive-E
–
120
mA
Industrial
10
10
mA
Automotive-A
10
–
mA
Automotive-E
–
15
mA
Page 4 of 16
CY7C1011CV33
Maximum Ratings
Current into outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature with
power applied .......................................... –55 C to +125 C
Static discharge voltage .......................................... > 2001 V
(MIL-STD-883, method 3015)
Latch up current ..................................................... > 200 mA
Operating Range
Range
Supply voltage on VCC relative to GND[2] .....–0.5 V to +4.6 V
Ambient
Temperature (TA)
VCC
–40 C to +85 C
3.3 V  10%
DC voltage applied to outputs
in High Z state[2] .................................. –0.5 V to VCC+ 0.5 V
Industrial
DC input voltage[2] ............................... –0.5 V to VCC+ 0.5 V
Automotive-A
–40 C to +85 C
Automotive -E
–40 C to +125 C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
-10
Min
-12
Max
Unit
Max
Min
2.4
–
2.4
–
V
–
0.4
–
0.4
V
VOH
Output HIGH voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW voltage
VCC = Min, IOL = 8.0 mA
VIH
Input HIGH voltage
2.0
VCC + 0.3
2.0
VCC + 0.3
V
VIL
Input LOW voltage[2]
–0.3
0.8
–0.3
0.8
V
IIX
Input leakage current
Industrial
–1
+1
–1
+1
A
Automotive-A
–1
+1
–
–
IOZ
ICC
ISB1
ISB2
GND < VI < VCC
Output leakage current GND < VI < VCC,
Output disabled
Automotive-E
–
–
–20
+20
Industrial
–1
+1
–1
+1
Automotive-A
–1
+1
–
–
Automotive-E
–
–
–20
+20
VCC operating supply
current
VCC = Max, IOUT = 0 mA,
f = fMAX = 1/tRC
Automotive-E
–
Automatic CE power
down current —TTL
Inputs
Max VCC, CE > VIH,
Industrial
VIN > VIH or VIN < VIL, f = fMAX Automotive-A
–
–
40
–
–
Automotive-E
–
–
–
45
Industrial
–
10
–
10
Automotive-A
–
10
–
–
Automotive-E
–
–
–
15
Automatic CE power
Max VCC, CE > VCC – 0.3 V,
down current — CMOS VIN > VCC – 0.3 V, or
inputs
VIN < 0.3 V, f = 0
Industrial
–
100
–
95
Automotive-A
–
100
–
–
–
–
120
40
–
40
A
mA
mA
mA
Note
2. VIL (min) = –2.0 V for pulse durations of less than 20 ns.
Document Number: 38-05232 Rev. *N
Page 5 of 16
CY7C1011CV33
Capacitance
Parameter [3]
Description
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
CIN
Input capacitance
COUT
Output capacitance
Max
Unit
8
pF
8
pF
Thermal Resistance
Parameter [3]
Description
Test Conditions
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
44-pin TSOP II
44-pin TQFP
Unit
44.56
42.66
C/W
10.75
14.64
C/W
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [4]
10-ns devices:
12-ns devices:
Z = 50 
50 
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317
3.3 V
OUTPUT
30 pF*
OUTPUT
R2
351
30 pF*
1.5 V
(b)
(a)
High-Z characteristics:
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
Rise Time: 1 V/ns
10%
(c)
R 317
3.3 V
Fall Time: 1 V/ns
OUTPUT
R2
351
5 pF
(d)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) for 10-ns parts are tested using the load conditions shown in Figure 3 (a). All other speeds are tested using the Thevenin load shown
in Figure 3 (b). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (d).
Document Number: 38-05232 Rev. *N
Page 6 of 16
CY7C1011CV33
Switching Characteristics
Over the Operating Range
Parameter [5]
-10
Description
-12
Min
Max
Min
Max
Unit
Read Cycle
tpower[6]
VCC (typical) to the first access
1
–
1
–
s
tRC
Read cycle time
10
–
12
–
ns
tAA
Address to data valid
–
10
–
12
ns
tOHA
Data hold from address change
3
–
3
–
ns
tACE
CE LOW to data valid
–
10
–
12
ns
tDOE
OE LOW to data valid
Industrial/Automotive-A
–
5
–
6
ns
Automotive-E
–
–
–
8
0
–
0
–
ns
–
5
–
6
ns
3
–
3
–
ns
–
5
–
6
ns
Z[7]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[7, 8]
tLZCE
CE LOW to Low
Z[7]
Z[7, 8]
tHZCE
CE HIGH to High
tPU
CE LOW to power up
0
–
0
–
ns
tPD
CE HIGH to power down
–
10
–
12
ns
tDBE
Byte enable to data valid
Industrial/Automotive-A
–
5
–
6
ns
Automotive-E
–
–
–
8
tLZBE
Byte enable to Low Z
0
–
0
–
ns
tHZBE
Byte disable to High Z
–
5
–
6
ns
10
–
12
–
ns
Write Cycle [9, 10]
tWC
Write cycle time
tSCE
CE LOW to write end
7
–
8
–
ns
tAW
Address setup to write end
7
–
8
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
7
–
8
–
ns
tSD
Data setup to write end
5
–
6
–
ns
tHD
Data hold from write end
0
–
0
–
ns
WE HIGH to Low
Z[7]
3
–
3
–
ns
tHZWE
WE LOW to High
Z[7, 8]
–
5
–
6
ns
tBW
Byte enable to end of write
7
–
8
–
ns
tLZWE
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of Figure 3 on page 6. Transition is measured 500 mV from steady state voltage
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05232 Rev. *N
Page 7 of 16
CY7C1011CV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [11, 12]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [12, 13]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tLZOE
BHE, BLE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05232 Rev. *N
Page 8 of 16
CY7C1011CV33
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [14, 15]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
t BW
BHE, BLE
tSD
tHD
DATA IO
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes
14. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05232 Rev. *N
Page 9 of 16
CY7C1011CV33
Switching Waveforms (continued)
Figure 8. Write Cycle No. 3 (WE Controlled, LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High Z
L
L
H
L
L
Data Out
Data Out
Read – all bits
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read – lower bits only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read – upper bits only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write – all bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write – lower bits only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write – upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, outputs disabled
Active (ICC)
Document Number: 38-05232 Rev. *N
I/O0–I/O7
I/O8–I/O15
High Z
Mode
Power down
Power
Standby (ISB)
Page 10 of 16
CY7C1011CV33
Ordering Information
Speed
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
10
CY7C1011CV33-10ZSXA
51-85087 44-pin TSOP II (Pb-free)
Automotive-A
12
CY7C1011CV33-12ZSXE
51-85087 44-pin TSOP II (Pb-free)
Automotive-E
Ordering Code Definitions
CY 7
C 1
01 1
C
V33 - XX XX X
X
Temperature range: X = A or I or E
A = Automotive-A; I = Industrial; E = Automotive-E
Pb-free
Package Type: XX = ZS or A or BV
ZS = 44-pin TSOP II
A = 44-pin TQFP
Speed grade: XX = 10 ns or 12 ns
V33 = 3.3 V
Process Technology: 150 nm
Bus Width: × 16 bits
Density: 2-Mbit
Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05232 Rev. *N
Page 11 of 16
CY7C1011CV33
Package Diagrams
Figure 9. 44-pin TSOP Z44-II, 51-85087
51-85087 *E
Document Number: 38-05232 Rev. *N
Page 12 of 16
CY7C1011CV33
Package Diagrams (continued)
Figure 10. 44-pin TQFP (10 × 10 × 1.4 mm) A44S, 51-85064
51-85064 *E
Document Number: 38-05232 Rev. *N
Page 13 of 16
CY7C1011CV33
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degree Celsius
CMOS
complementary metal oxide semiconductor
MHz
megahertz
CE
chip enable
µA
microampere
I/O
input/output
µs
microsecond
OE
output enable
mA
milliampere
SRAM
static random access memory
mm
millimeter
TQFP
thin quad flat pack
ms
millisecond
TSOP
thin small outline package
mV
millivolt
TTL
transistor-transistor logic
mW
milliwatt
VFBGA
very fine-pitch ball gird array
ns
nanosecond
WE
write enable
%
percent
Document Number: 38-05232 Rev. *N
Symbol
Unit of Measure
pF
pico farad
V
volt
W
watt
Page 14 of 16
CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128 K × 16) Static RAM
Document Number: 38-05232
Orig. of
Submission
Revision
ECN
Description of Change
Change
Date
**
117132
HGK
07/31/02
New Data Sheet
*A
118057
HGK
08/19/02
Pin configuration for 48-ball FBGA correction
*B
119702
DFP
10/11/02
Updated FBGA to VFBGA; updated package code on page 8 to BV48A. Updated
address pinouts on page 1 to A0 to A16. Updated CMOS standby current on page
1 from 8 to 10 mA
*C
386106
PCI
See ECN Added lead-free parts in Ordering Information Table
*D
498501
NXR
See ECN Corrected typo in the Logic Block Diagram on page# 1
Included the Maximum Ratings for Static Discharge Voltage and Latch up Current
on page# 3
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Updated the Ordering Information Table
*E
522620
VKN
See ECN Added Thermal Resistance Table
*F
1891366 VKN/AESA
See ECN Added -10ZSXA part
Updated Ordering Information table
*G
2428606 VKN/PYRS
See ECN Corrected typo in the 44-Pin TSOP and 48-Ball FBGA pinout
Removed Commercial parts
Removed 15 ns speed bin
Removed inactive parts from the Ordering Information table
*H
2664421 VKN/AESA
02/25/09
Added Automotive-E specs for 12 ns speed
Updated Ordering Information table
*I
2898399 KAO/AJU
03/24/2010 Updated Package Diagrams
*J
2950666
VKN
06/11/2010 Included “CY7C1011CV33-12BVXE” in Ordering Information
Added Contents and Acronyms
Updated Sales, Solutions, and Legal Information
Added Ordering Code Definitions.
*K
3089939
PRAS
11/13/2010 Removed inactive part from Ordering Information.
*L
3276463
KAO
06/07/2011 Updated Functional Description (Removed “For best practice recommendations,
refer to the Cypress application note AN1064, SRAM System Guidelines.”).
Added Units of Measure.
Updated Package Diagrams.
Updated in new template.
*M
3591978
TAVA
04/19/2012 Removed all information related to 48-ball VFBGA throughout the document.
Updated package diagram revisions.
*N
3861271
KAO
01/08/2013 Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85087 – Changed revision from *D to *E.
Document Number: 38-05232 Rev. *N
Page 15 of 16
CY7C1011CV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2002-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05232 Rev. *N
Revised January 8, 2013
All products and company names mentioned in this document may be the trademarks of their respective holders.
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