Micross AS5LC512K8 Ultra high speed asynchronous operation Datasheet

SRAM
AS5LC512K8
512K x 8 SRAM
PIN ASSIGNMENT
(Top View)
3.3 VOLT HIGH SPEED SRAM with
CENTER POWER PINOUT
36-Pin PSOJ (DJ)
36-Pin CLCC (EC)
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883 for Ceramic
•Extended Temperature Plastic (COTS)
FEATURES
• Ultra High Speed Asynchronous Operation
• Fully Static, No Clocks
• Multiple center power and ground pins for improved
noise immunity
• Easy memory expansion with CE\ and OE\
options
• All inputs and outputs are TTL-compatible
• Single +3.3V Power Supply +/- 0.3V
• Data Retention Functionality Testing
• Cost Efficient Plastic Packaging
• Extended Testing Over -55ºC to +125ºC for plastics
• RoHS Compliant Options Available
OPTIONS
36-Pin Flat Pack (F)
MARKING
• Timing
10ns access
12ns access
15ns access
20ns access
25ns access
-10
-12
-15
-20
-25
• Operating Temperature Ranges
883C (-55oC to +125oC)
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
/883C
/XT
/IT
• Package(s)
Ceramic Flatpack
Ceramic LCC
Plastic SOJ (400 mils wide)
F
EC
DJ
• 2V data retention/low power*
L
No. 307
No. 210
For more products and information
please visit our web site at
www.micross.com
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
1
SRAM
AS5LC512K8
GENERAL DESCRIPTION
As a option, the device can be supplied offering a reduced power
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5LC512K8DJ offers the convenience and reliability of
the AS5LC512K8 SRAM and has the cost advantage of a plastic encapsulation. TSOPII with copper lead frames offers superior thermal
performance.
The AS5LC512K8 is a 3.3V high speed SRAM. It offers flexibility in high-speed memory applications, with chip enable (CE\) and
output enable (OE\) capabilities. These features can place the outputs
in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
FUNCTIONAL BLOCK DIAGRAM
GND
DQ8
I/O
CONTROLS
4,194,304-BIT
MEMORY ARRAY
ROW DECODER
A0-A18
INPUT BUFFER
VCC
1024 ROWS X
4096 COLUMNS
DQ1
CE\
OE\
COLUMN DECODER
WE\
*POWER
DOWN
*On the low voltage Data Retention option.
PIN FUNCTIONS
TRUTH TABLE
MODE
OE\ CE\ WE\
STANDBY
X
H
X
READ
L
L
H
NOT SELECTED H
L
H
WRITE
X
L
L
I/O
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
X = Don’t Care
AS5LC512K8
Rev. 2.4 10/13
A0 - A18
Address Inputs
WE\
Write Enable
CE\
Chip Enable
OE\
Output Enable
I/O0 - I/O7
Data Inputs/Outputs
VCC
Power
VSS
Ground
NC
No Connection
Micross Components reserves the right to change products or specifications without notice.
2
SRAM
AS5LC512K8
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc .........................................................................-.5V to 4.0V
Storage Temperature .....................................-65C to +150C
Short Circuit Output Current (per I/O)…........................20mA
Voltage on any Pin Relative to Vss........................-.5V to 4.6V
Maximum Junction Temperature**..............................+150C
Power Dissipation ................................................................1W
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
** Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 3.3V +0.3%)
CONDITIONS
DESCRIPTION
SYM
-10
-12
MAX
-15
-20
-25
ICCSP
90
80
70
60
55
ICCLP
-
60
50
40
35
mA
ISBTSP
30
20
20
20
20
mA
ISBTLP
-
15
15
15
15
mA
ISBCSP
20
15
15
15
15
mA
ISBCLP
-
9
9
9
9
mA
UNITS NOTES
CE\ < VIL; Vcc = MAX
f = MAX = 1/t RC
Outputs Open
Power Supply
Current: Operating
"L" Version Only
CE\ > VIH, All other inputs < VIL,
Vcc = MAX, f = 0,
Outputs Open
Power Supply
Current: Standby
"L" Version Only
CE\ > Vcc -0.2V; Vcc = MAX
VIN<Vss +0.2V or
mA
3, 2
VIN>Vcc -0.2V; f = 0
"L" Version Only
µ
µ
CAPACITANCE
PARAMETER
Input Capacitance
Output Capactiance
AS5LC512K8
Rev. 2.4 10/13
CONDITIONS
SYMBOL
MAX
UNITS
NOTES
TA = 25oC, f = 1MHz
VIN = 0
CI
8
pF
4
Co
6
pF
4
Micross Components reserves the right to change products or specifications without notice.
3
SRAM
AS5LC512K8
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3%)
DESCRIPTION
SYM
-10
MIN
-12
MAX
MIN
-15
MAX
MIN
-20
MAX
MIN
-25
MAX
MIN
MAX
UNITS NOTES
READ CYCLE
Read Cycle Time
tRC
Address Access Time
tAA
10
12
15
20
25
ns
Chip Enable Access Time
tACE
10
12
15
20
25
ns
Output Hold From Address Change
tOH
2
2
2
2
2
Chip Enable to Output in Low-Z
tLZCE
2
2
2
2
2
ns
4, 6, 7
Chip Disable to Output in High-Z
tHZCE
4
6
7
8
9
ns
4, 6, 7
Output Enable Acess Time
tAOE
4.5
6
7
8
9
ns
Output Enable to Output in Low-Z
tLZOE
Output Disable to Output in High-Z
WRITE CYCLE
WRITE Cycle Time
tHZOE
10
12
0
15
0
20
0
4
6
25
0
7
ns
ns
0
8
9
ns
4, 6, 7
ns
4, 6, 7
tWC
10
12
15
20
25
ns
Chip Enable to End of Write
tCW
8
8
10
12
13
ns
Address Valid to End of Write
tAW
8
8
10
12
13
ns
Address Setup Time
tAS
0
0
0
0
0
ns
Address Hold From End of Write
tAH
0
0
0
0
0
ns
WRITE Pulse Width
tWP
8
10
12
15
15
ns
Data Setup Time
tDS
6
6
7
8
8
ns
Data Hold Time
tDH
1
1
1
1
1
ns
Write Disable to Output in Low-Z
tLZWE
2
2
2
2
2
Write Enable to Output in High-Z
tHZWE
AS5LC512K8
Rev. 2.4 10/13
5
5
6
7
7
ns
4, 6, 7
ns
4, 6, 7
Micross Components reserves the right to change products or specifications without notice.
4
SRAM
AS5LC512K8
AC TEST CONDITIONS
Input pulse levels ................................................ Vss to 3.0V
Input rise and fall times .................................................. 3ns
Input timing reference levels ......................................... 1.5V
Output reference levels .................................................. 1.5V
Output load ............................................ See Figures 1 and 2
3.3V
RL = 50
Q
ZO=50
319
VL = 1.5V
Q
30 pF
5 pF
353
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. All voltages referenced to VSS (GND).
2. ICC limit shown is for absolute worst case switching of
ADDR, ADDR\, ADDR, etc.
3. ICC is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7. At any given temperature and voltage condition,
t
HZCE is less than tLZCE, and tHZWE is less than
t
LZWE.
8. WE\ is HIGH for READ cycle.
9.
10.
11.
12.
13.
14.
15.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
Chip enable and write enable can initiate and
terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
Output enable (OE\) is active (LOW).
ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
Vcc for Retention Data
Data Retention Current
CONDITIONS
CE\ > VCC -0.2V
VIN > VCC -0.2 or 0.2V
Vcc = 2.0V
Chip Deselect to Data
Operation Recovery Time
AS5LC512K8
Rev. 2.4 10/13
SYM
MIN
VDR
2
MAX
NOTES
V
6.5
ICCDR
UNITS
mA
tCDR
0
ns
4
tR
20
ms
4, 11
Micross Components reserves the right to change products or specifications without notice.
5
SRAM
AS5LC512K8
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
3.0V
3.0V
VDR > 2V
tR
tCDR
VIH-
VDR
CE\
VIL-
READ CYCLE NO. 11, 2
(Address Controlled, CE\ = OE\ = VIL, WE\ = VIH)
tRC
ADDRESS
VALID
tAA
tOH
I/O, DATA IN
& OUT
Previous Data Valid
Data Valid
READ CYCLE NO. 2
(WE\ = VIH)
tRC
ADDRESS
tAOE
tLZOE
tHZOE
CE\
tLZCE
tACE
I/O, DATA IN
& OUT
tHZCE
Data Valid
High-Z
tPU
tPD
Icc
NOTES:
Don’t Care
1. WE\ is HIGH for READ cycle.
2. Device is continuously selected. Chip enables and output enables are held in their
active state.
Undefined
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
6
SRAM
AS5LC512K8
WRITE CYCLE NO. 11
(CE Controlled)
tWC
ADDRESS
tAW
tAS
tAH
tCW
CE\
tWP1
WE\
tDH
tDS
Data Valid
I/O, DATA IN
I/O, DATA OUT
High-Z
High-Z
WRITE CYCLE NO. 21, 2
(Write Enabled Controlled)
tWC
ADDRESS
tAW
tCW
tAH
CE\
tAS
tWP1
WE\
tDH
Data Valid
I/O, DATA IN
I/O, DATA OUT
High-Z
High-Z
NOTES:
1.
2.
Chip enable and write enable can initiate and terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
7
SRAM
AS5LC512K8
WRITE CYCLE NO. 31, 2, 3
(WE Controlled)
tWC
ADDRESS
tAW
tAH
tCW
CE\
tAS
tWP2
WE\
tDH
tDS
Data Valid
DATA IN
tHZWE
DATA OUT
tLZWE
High-Z
Data Undefined
NOTES:
1. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE.
2. Chip enable and write enable can initiate and terminate a WRITE cycle.
3. Output enable (OE\) is active (LOW).
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
8
SRAM
AS5LC512K8
MECHANICAL DEFINITIONS*
Micross Case #307 (Package Designator F)
E
L
Pin 1 identifier area
36
1
e
D
b
D1
Bottom View
S
Top View
A
c
Q
E2
SYMBOL
A
b
c
D
D1
E
E2
e
L
Q
MICROSS SPECIFICATIONS
MIN
MAX
0.096
0.125
0.015
0.022
0.003
0.009
0.910
0.930
0.840
0.860
0.505
0.515
0.385
0.397
0.050 BSC
0.250
0.370
0.020
0.045
*All measurements are in inches.
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
9
SRAM
AS5LC512K8
MECHANICAL DEFINITIONS*
Package Designator DJ
SYMBOL
A
A1
A2
B
b
C
D
E
E1
E2
e
MICROSS SPECIFICATIONS
MIN
MAX
0.128
0.148
0.025
--0.082
--0.015
0.020
0.026
0.032
0.007
0.013
0.920
0.930
0.435
0.445
0.395
0.405
0.370 BSC
0.050 BSC
*All measurements are in inches.
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
10
SRAM
AS5LC512K8
MECHANICAL DEFINITIONS*
Micross Case #210 (Package Designator EC)
P
A
Pin 1 identifier area
R
L2
1
D
36
L
e
B
D1
E
A1
SYMBOL
A
A1
B
D
D1
E
e
L
L2
P
R
MICROSS SPECIFICATIONS
MIN
MAX
0.080
0.100
0.054
0.066
0.022
0.028
0.910
0.930
0.840
0.860
0.445
0.460
0.050 BSC
0.100 TYP
0.115
0.135
--0.006
0.009 TYP
*All measurements are in inches.
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
11
SRAM
AS5LC512K8
ORDERING INFORMATION
36-Pin Ceramic Flat Pack
EXAMPLE: AS5LC512K8F-12L/XT
Package
Speed
Device Number
Type
ns
AS5LC512K8
F
-10
AS5LC512K8
F
-12
AS5LC512K8
F
-15
AS5LC512K8
F
-25
36-Pin Plastic PSOJ
EXAMPLE: AS5LC512K8DJ-20L/IT
Package
Speed
Device Number
Type
ns
AS5LC512K8
DJ
-12
AS5LC512K8
DJ
-15
AS5LC512K8
DJ
-20
AS5LC512K8
DJ
-25
36-Pin Ceramic CLCC
EXAMPLE: AS5LC512K8EC-15L/IT
Speed
Package
Device Number
Type
ns
AS5LC512K8
EC
-12
AS5LC512K8
EC
-15
AS5LC512K8
EC
-20
AS5LC512K8
EC
-25
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing1
Options**
Process
L
L
L
L
/*
/*
/*
/*
Options**
Process
L
L
L
L
/*
/*
/*
/*
Options**
Process
L
L
L
L
/*
/*
/*
/*
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
**OPTIONS DEFINITIONS
L = 2V Data Retention / Low Power
NOTES: 1. 883C process available with ceramic packaging only.
AS5LC512K8
Rev. 2.4 10/13
Micross Components reserves the right to change products or specifications without notice.
12
SRAM
AS5LC512K8
DOCUMENT TITLE
512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT
Rev #
2.1
History
Pg 1: Changed 0.3% to 0.3V
Release Date
August 2009
Status
Release
2.2
Updated Micross Information
January 2010
Release
2.3
Expanded package offering to include March 2011
Copper Lead Frames and RoHS
Compliancy, added -10 speed option,
Reduced CL from 9pF to 8pF, corrected
tHZWE from min’s to max’s on page 4,
corrected 4.5V reference points on data
retention waveform to 3.0V, pg. 6
Release
2.4
Removed Cu-lead frame option
Release
AS5LC512K8
Rev. 2.4 10/13
October 2013
Micross Components reserves the right to change products or specifications without notice.
13