E2C0022-27-Y3
¡ Semiconductor
MSC1215-xx
¡ Semiconductor
This version:MSC1215-xx
Nov. 1997
Previous version: Jul. 1996
17 ¥ 2 Duplex Driver with Dimming, Keyscan and A/D Converter Function
GENERAL DESCRIPTION
The MSC1215-xx is a 1/2-duty vacuum fluorescent display tube driver implemented in BiCMOS technology. This LSI consists of a 37-bit shift register, 34 latches, an analog dimming
circuit, (a PWM conversion circuit), a 3¥4 keyscan circuit, a 6ch-6-bit A/D converter and 17
segment drivers, and 2-grid pre-drivers.
The MSC1215-xx has capabilities of displaying audio system frequencies and various informations on a VFD tube for the automobile application and also interfacing with keyboard inputs and
on an analog volume input.
For automobile audio systems, the front panel functions (such as a frequency display, keyboard
input and analog voltage input from a volume) can be accomplished by this IC.
The analog dimming/PWM conversion modes can be selected automatically for the brightness
control, so this IC is applicable to any type of automobile without any change of the specifications.
The interface with a MCU can be done only with 3 wires (CS, DATA I/O and CLOCK signals).
Also, DATA I/O and CLOCK signal lines can be shared with other peripherals because of chip
select function by CS signal.
FEATURES
• Power supply voltage
: VDD=8 to 18 V
• Operating temperature range
: Ta=–40 to +85°C)
• 17-segment driver outputs (IOH=–5mA at VOH=VDD–0.8 V)
• Built-in analog dimming circuit (6-bit resolution, user-programmable)
• Built-in PWM conversion circuit (Lamp PWM signal to vacuum fluorescent display PWM
signal)
• Built-in automatic-selection circuit for analog dimming/PWM conversion function
• Built-in 6ch 6-bit A/D converter
• Built-in 3 ¥ 4 Keyscan circuit
• Built-in oscillation circuit (external R and C, fOSC=3.3 MHz)
• Built-in Power-On-Reset circuit
• Package:
42-pin plastic DIP (DIP 42-P-600-2.54) (Product name: MSM1215-xxRS)
xx indicates the code number.
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¡ Semiconductor
MSC1215-xx
BLOCK DIAGRAM
SEG1
VDD
SEG17
17 Segment VF Tube Driver
P. O. R
Regulator
GND
5V
34Æ17 Segment Control
PWMOUT
bit 34-18
(Grid2)
CS
L
Timing
bit 17-1
(Grid1)
Mode
Select
DATA I/O
bit1
D bit34
34-bit Shift Register
R
CLOCK
SW1 (VF Data)
SW2 (Keyscan)
SW3 (A/D)
3-bit
Latch
34-bit Latch
Test1-8
Test
3-bit
S/R
SW1
OSC0
OSC
OSC1
VK
VD
+
-
MUX
Latch
GRID1
GRID2
Grid
Pre-driver
Timing Generator
to PWM OUT
PWM
Select
D/A
Logarithm Counter
Decoder
De-glitch
SI
SW2
PWM detector
12-bit Presetable S/R
Set
S
S
4
4-bit
L Latch
4
4
L
Look up table
out
PE
4
L
4
4
6-bit dig. comp.
"H" at SW3 ON
Read Eable
SW3
CH1
CH2
CH3
CH4
CH5
CH6
Timing
Generator
Channel
Select
VREF
+
-
VREF
Read Enable
"H"at SW2 ON
Timing
Generator
Detector
Row 3 2 1
Col 4 3 2 1
With 100kW pull-up resistor
6ch 6-bit
A/D
& Logic
O
PE
36-bit
S/R
2/22
¡ Semiconductor
MSC1215-xx
INPUT AND OUTPUT CONFIGURATION
• Schematic Diagrams of Logic Portion Input Circuit 1
VDD
(5V Reg.)
INPUT
GND
GND
• Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input/
Circuit 2
Output Circuit
VDD
(5V Reg.)
VDD
(5V Reg.)
(5V Reg.)
DATAI/O
COLn
GND
GND
GND
GND
GND
GND
• Schematic Diagrams of Logic Portion Output • Schematic Diagrams of Driver Output Circuit
Circuit
(5V Reg.)
(5V Reg.)
VDD
OUTPUT
OUTPUT
GND
GND
VDD
GND
GND
3/22
¡ Semiconductor
MSC1215-xx
PIN CONFIGURATION (TOP VIEW)
COL4 1
42 COL3
GRID1 2
41 COL2
GRID2 3
40 COL1
SEG 1 4
39 VD
SEG 2 5
38 VREF
SEG 3 6
37 CH6
SEG 4 7
36 CH5
SEG 5 8
35 CH4
SEG 9 9
34 CH3
SEG10 10
33 CH2
SEG11 11
32 CH1
VDD 12
31 GND
SEG12 13
30 OSC0
SEG13 14
29 OSC1
SEG14 15
28 VK
SEG15 16
27 DATA I/O
SEG16 17
26 CS
SEG17 18
25 CLOCK
SEG 6 19
24 ROW 1
SEG 7 20
23 ROW 2
SEG 8 21
22 ROW 3
42-Pin Plastic DIP
4/22
¡ Semiconductor
MSC1215-xx
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage
VDD
—
–0.3 to +20
V
Input Voltage (1)
VIN1
All inputs except VK
–0.3 to +6
V
Input Voltage (2)
VIN2
VK
–0.3 to +VDD
V
Power Dissipation
PD
Ta=85°C
400
mW
TSTG
—
–55 to +150
°C
Storage Temperature
RECOMMENDED OPERATING CONDITION
Parameter
Supply Voltage
Symbol
Condition
Min.
Typ.
Max.
Unit
VDD
—
8
—
18
V
Operating Temperature
TOP
—
–40
—
85
°C
High Level Input Voltage (1)
VIH1
All inputs except VK
3.8
—
5.5
V
High Level Input Voltage (2)
VIH2
VK
3.8
—
VDD
V
Low Level Input Voltage
VIL
All inputs
0
—
0.8
V
Clock Frequency
fc
—
—
—
250
kHz
OSC Frequency
fosc
R=4.7 kW, C=10 pF
—
3.33
—
MHz
Frame Frequency
fFR
—
—
200
—
Hz
5/22
¡ Semiconductor
MSC1215-xx
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Ta=–40 to +85°C, VDD=8 to 18V)
Parameter
"H" Input Voltage
Symbol
Condition
Min.
Max.
Unit
VIH
All inputs except VD
3.8
—
V
"L" Input Voltage
VIL
All inputs except VD
—
0.8
V
"H" Input Current (1)
IIH1
All inputs except COL1-4
VIN=4.4 V
–5
5
mA
"H" Input Current (2)
IIH2
COL1-4, VIN=3.8 V
–70
–5
mA
"L" Input Current (1)
IIL1
All inputs except COL1-4
VIN=0 V
–5
5
mA
IIL2
COL1-4, VIN=0 V
–160
–10
mA
"H" Output Voltage (1)
VOH1
SEG, GRID
IOH1=–5 mA, VDD=9.5 V
VDD-0.8
—
V
"H" Output Voltage (2)
VOH2
DATA I/O, VDD=9.5 V
IOH2=–200 mA
Output open
4
4.5
—
—
V
V
SEG,GRID, VDD=9.5 V
IOL1=500 mA
IOL1=200 mA
IOL1=2 mA
—
—
—
2
1
0.3
V
V
V
"L" Input Current (2)
"L" Output Voltage (1)
VOL1
"L" Output Voltage (2)
VOL2
DATA I/O, ROW1-3
VDD=9.5 V, IOL2=200 mA
—
0.8
V
Current Consumption
IDD
fosc=3.3 MHz, no load
—
20
mA
6/22
¡ Semiconductor
MSC1215-xx
Switching Characteristics
(Ta=–40 to +85°C, VDD=8 to 18 V)
Symbol
fosc
Condition
—
Clock Frequency
fc
Clock Pulse Width
tcw
Parameter
Oscillation Frequency
Min.
2
Max.
4.5
Unit
MHz
—
—
250
kHz
—
1.3
—
ms
Data Set-up Time
tDS
—
1
—
ms
Data Hold Time
tDH
—
200
—
ns
CS Pulse Width
tCSW
Except reset mode
8
—
ms
CS Off Time
tCSL
Except reset mode
32
—
ms
CS Pulse Width
tRCSW
Reset mode
4
—
ms
CS Off Time
tRCSL
Reset mode
4
—
ms
CS Set-up Time
CS-clock Time
tCSS
—
2
—
ms
CS Hold Time
Clock-CS Time
tCSH
—
2
—
ms
DATA Output Delay
CLCOK-DATA Out Time
tPD
—
—
1
ms
SEG & GRID Outputs Delay
Time from CS
tODS
CL=100 pF
—
8
ms
tR
CL=100 pF
t=20% to 80% or
80% to 20% of VDD
—
5
ms
tPCS
—
300
—
ms
Slew Rate (All Drivers)
Power on Timing
7/22
¡ Semiconductor
MSC1215-xx
Analog Dimming Characteristics
(Ta=–40 to +85°C, VDD=8 to 18V)
Condition
Min.
Typ.
Max.
Unit
D/A Ouput Voltage Error
Parameter
—
—
—
±3
%
Reference Voltage Accuracy *1
—
—
—
±6
%
*1 Reference voltage is 6.6 V typical.
A/D Converter Characteristics
(Ta=–40 to +85°C, VDD=8 to 18 V)
Parameter
Condition
Min.
Typ.
Max.
Unit
—
—
—
±1
LSB
Reference Voltage (VREF)
*2
4.5
5
5.5
V
Output Current
—
—
—
4
mA
—
GND
—
VREF
V
fOSC=3.3MHz
384
543
896
ms
A/D Conversion Accuracy
Input Voltage Range
Conversion Time/Channel
*2 When six loads of 10 kW are connected in parallel.
Keyscan Characteristics
(Ta=–40 to +85°C, VDD=8 to 18 V)
Condition
Min.
Typ.
Max.
Unit
Keyscan Cycle Time
Parameter
fOSC=3.3MHz
220
312
512
ms
Keyscan Pulse Width
fOSC=3.3MHz
55
78
128
ms
PWM Conversion Characteristics
(Ta=–40 to +85°C, VDD=8 to 18 V)
Parameter
Condition
Min.
Typ.
Max.
Unit
—
112
122
132
Hz
tr=10%Æ90%, tf=90%Æ10%
100
300
800
ms
t=50%Æ50%
125
—
—
ms
Input Duty Cycle
VD pin
1.65
—
98.3
%
"H" Input Threshold voltage
VD pin
0.26VDD
0.28VDD
0.30VDD
V
"L" Input Threshold voltage
VD pin
0.20VDD
0.22VDD
0.24VDD
V
Hysteresis Width
VD pin
0.02VDD
0.06VDD
0.10VDD
V
PWM Input Frequency
Rise/Fall Time
PWM Pulse Width
8/22
¡ Semiconductor
MSC1215-xx
TIMING DIAGRAM
tCSW
CS
3.8 V
tCSL
0.8 V
tCSS
fc
tcw
CLOCK
tCSH
tcw
3.8 V
0.8 V
tDS
tDS
tDH
DATA I/O
(INPUT)
3.8 V
0.8 V
VALID
tDH
VALID
Figure 1. DATA Input Timing
CS
3.8 V
0.8 V
tCSS
CLOCK
tCSH
3.8 V
0.8 V
tPD
DATA I/O
(OUTPUT)
tPD
3.8 V
0.8 V
Figure 2. DATA Outpout Timing
9/22
¡ Semiconductor
MSC1215-xx
8V
VDD
tPCS
CS
tRCSW
tRCSL
3.8 V
0.8 V
Figure 3. Power-on-Reset Timing
tCSW
CS
3.8 V
0.8 V
tODS
tODS
tR
SEG1-17
GRID1, 2
tR
80%
20%
Figure 4. SEG and GRID Output Timing
1 Frame Cycle fFR
4096-bit times
GRID1
16-bit times min
GRID2
2032-bit times
6-bit times
SEG1-17
2038-bit times
10-bit times
Figure 5. SEG-GRID output Timing (Daylight Mode)
Note: 1. Timing shown for analog dimming with a duty cycle of 2032/2048 at VK="L".
2. 1-bit time=TOSC (=4/fOSC)=1.2 µs typical.
10/22
¡ Semiconductor
MSC1215-xx
1 Frame Cycle fFR
4096-bit times
GRID1
2048-bit times
GRID2
208-bit times max.
SEG1-17
Figure 6. SEG-GRID output Timing (Dark Mode)
Note: 1. Timing shown for analog dimming with a duty cycle of 208/2048 at VK="H".
2. 1-bit time=TOSC (=4/fOSC)=1.2 µs typical.
90%
VD
(PWM Input)
50%
10%
tr
tf
tPW
T
Figure 7. PWM Waveform
Keyscan Cycle Time
ROW1
Keyscan Pulse Width
ROW2
ROW3
Figure 8. Keyscan Timing
Note: 1. Key scanning from ROW1 to ROW3 is started when any key is pushed down or
released. Scanning will stop when CS turns to "L" from "H", after 2 times of CS pulses
and the transfer of display data.
11/22
¡ Semiconductor
MSC1215-xx
Push
Keyscan
Keyscan Stop
CS
Display Data Output
Figure 9. Keyscan Stop Timing
FUNCTIONAL DESCRIPTION
Pin Functional Description
• VDD
Power supply input pin
Connected to a 12V power supply
• GND
Ground Pin
This pin is 0V level.
• CLOCK
Serial clock input pin
• CS
Chip select input pin
When "H" is input to this pin, interfacing with a MCU is available through the CLOCK and the
DATA pins.
Therefore, 2 signal lines of the CLOCK and the DATA can be shared with other peripherals.
• DATA I/O (Input-output)
Serial data input-output pin
This pin inputs display data and outputs keyscan and A/D conversion data.
• VK
Daylight/dark mode selection input pin
When "H" is input, the dark mode is selected and an output duty cycle is determined by analog
or PWM data input into the VD pin.
When "L" is input, the daylight mode is selected and the output duty cycle becomes about
100%.
• VD
Analog/PWM dimming data input pin
Analog/PWM dimming mode selection will be done by an internal detection circuit automatically.
• VREF
Reference voltage output pin for the A/D converter
12/22
¡ Semiconductor
MSC1215-xx
• CH1-6
Analog voltage input pin for the A/D converter
• COL1-4
Key matrix input pins
These pins are active "Low" and pulled up to "H" through built-in resistors except when "L" is
input by a pushed down key.
• ROW1-3
Key matrix scanning output
Normally ROW1-3 output "L", by detecting the key switch to be pushed down or released, a
key scan starts, sending CS pulses two times and VF data, after above turning the CS pin to "L"
from "H". After scan stops, all the ROW outputs turn to "L".
• OSC0, 1
RC oscillation input pins
A resistor and a capacitor are connected to these pins. (See figure below)
OSC1
R
OSC0
C
• SEG1-17
Segment output pins
• GRID1, 2
Grid output pins
Output an inverted signal of a grid signal.
These pins are connected to inputs of external drivers (such as a PNP transistor).
13/22
¡ Semiconductor
MSC1215-xx
Functional Flowchart
POWER-ON
(Power-on Reset)
*1
Display Data
Input Mode
*2
2CS Pulses
CS="H"
Dispaly Data Input (34 bits)
Test Data Input
(3 bits)
Input Total
(37 bits)
CS="L"
Keyscan Data
Output Mode
CS="H"
Keyscan Data Output
(12 bits)
CS="L"
A/D Data Output Mode
CS="H"
A/D Data Output
(36 Bit)
CS="L"
Note: 1. When power supply turns on, the internal circuits are initialized as follows by the
built-in power-on reset circuit.
• Display data input mode is selected
• All segment outputs are in OFF state ("L")
• All internal registers and latches are set to "0" level
2. The status of the internal circuit after serial 2 CS pulses were applied, are as follows.
• Display data input mode is selected
• The other status are the same as before the serial 2CS pulses were applied.
14/22
¡ Semiconductor
MSC1215-xx
Display Data Input
Data input is available only when "H" is applied to the "CS" pin. Input data is shifted into shift
registers through the "DATA I/O" pin at the rising edge of the clock. The data is automatically
loaded to latches at the falling edge of "CS" signal.
[Data Format]
Bit
37
36
35
6
5
4
3
2
1
Data
34
33
32
3
2
1
T3
T2
T1
Display Data
First in
Test Data
*1
Note: Three bits (T1 to T3) for the test data are used for shipping inspection.
For the normal operation mode, all these bits should be set to "0" level.
Keyscan Data Output
Data output is available only when "H" is applied to the "CS" pin. When keyscan data output
mode is selected, "DATA I/O" pin is changed to an output mode. Then, 12 bits of keyscan data
come out from "DATA I/O" pin synchronizing with the rising edge of the clock. This output
mode is changed to A/D data output mode at the falling edge of the CS input signal. To select
directly the display input mode from this output mode, serial 2CS pulses should be input to the
CS pin.
[Data Format]
Bit
12
Data
S34 S33 S32 S31 S24 S23 S22 S21 S14 S13 S12 S11
11
10
9
8
7
6
5
4
3
2
1
First out
*2
Note: Symbols of the keyscan data are as follows.
SRC
COL Number (COL1-4)
ROW Number (ROW1-3)
A/D Data Output
A/D data output is available only when "H" is input to the CS pin.
When the A/D data output mode is selected, DATA I/O pin is changed to an output mode.
Then 36 bits of A/D data come out from DATA I/O pin synchronizing with the rising edge of
the shift clock.
This output mode is changed to the display input mode at the falling edge of the CS input signal.
[Data Format]
Bit
Data
36-31
30-25
24-19
18-13
12-7
6-1
MSB-LSB
CH6
MSB-LSB
CH5
MSB-LSB
CH4
MSB-LSB
CH3
MSB-LSB
CH2
MSB-LSB
CH1
First out
15/22
¡ Semiconductor
MSC1215-xx
Keyscan
To keep a scanning noise to a minimum, a scanning of the key switch starts only when a key is
pushed down or released. The scanning stops when CS input turns to "L" from "H" after sending
CS pulses two times and display data.
[Key Matrix of COL Input and ROW Output]
ROW1
ROW2
ROW3
S11
S21
S31
S12
S22
S32
S13
S23
S33
S14
S24
S34
COL1
COL2
COL3
COL4
=
A/D Conversion
The IC has a built-in 6-ch ¥ 6-bit A/D converter.
As shown in the circuit below, the VREF output pin is connected to a variable resistor forming a
voltage divider and the divided analog voltage is used to input into the CH1 to CH6 pins.
[Circuit Example]
VREF
Variable
Resistor
CH1
PWM Dimming
Lamp PWM signal is input to the VD pin and converted to VF display PWM signal by the PWM
conversion circuit.
The conversion table is mark-programmable.
Note: The duty cycle of the lamp PWM signal is measured with a reference point of the
threshold voltage of the VD input pin. The threshold voltage changes due to process
parameter deviation. Therefore, the PWM conversion error increases as the rise/fall time
of the lamp PWM increases.
16/22
¡ Semiconductor
MSC1215-xx
Analog Dimming
The PWM duty cycle is controlled by analog voltage which is the output of the brightness control
volume on a dashboard. The dimming curve is mask-programmable with the following
limitations;
1. Maximum duty cycle is 12.5%.
12.5%
DUTY CYCLE STEP
Max 12.5%
100% (DUTY)
512kHz
2. Number of pulse stops is max. 52.
3. Input Voltage to "VD"
The input voltage to "VD" needs to use a voltage divider as shown below.
2R
VD-IN
VD
R
Note: The maximum voltage to the VD is 5V.
4. Maximum Threshold Voltage
The maximum threshold voltage is 5.0V.
5. Minimum & Maximum VDIM Input Voltage
The minimum threshold voltage step is 20mV.
Only for the first step, the threshold voltage can be any value between 20mV and 3V.
min 20mV
max 3V
0
1
2
3
17/22
¡ Semiconductor
MSC1215-xx
PWM Conversion Table
LAMP PWM VFD PWM
LAMP PWM VFD PWM
STEP No. DUTY CYCLE
DUTY CYCLE STEP No. DUTY CYCLE DUTY CYCLE
100.00%
12.50%
58.75%
0
33
1
98.75%
34
57.50%
2
97.50%
35
56.25%
3
96.25%
36
55.00%
4
95.00%
37
53.75%
5
93.75%
38
52.50%
6
92.50%
39
51.25%
7
91.25%
40
50.00%
8
90.00%
41
48.75%
9
88.75%
42
47.50%
10
87.50%
43
46.25%
11
86.25%
44
12
45
45.00%
43.75%
13
85.00%
83.75%
46
42.50%
14
82.50%
47
41.25%
15
81.25%
48
40.00%
16
80.00%
49
38.75%
17
78.75%
50
37.50%
18
77.50%
51
36.25%
19
76.25%
52
35.00%
20
75.00%
53
33.75%
21
73.75%
54
32.50%
22
72.50%
55
31.25%
23
71.25%
56
30.00%
24
70.00%
57
28.75%
25
68.75%
58
27.50%
26
67.50%
59
26.25%
27
66.25%
60
25.00%
28
65.00%
61
23.75%
29
63.75%
62
22.50%
30
62.50%
63
21.25%
31
61.25%
64
20.00%
32
60.00%
18/22
¡ Semiconductor
MSC1215-xx
Dimming Voltage-Pulse width Correspondence Table
VDI Threshold dimming voltage vs. PWM duty cycle (Typical Value)
12.5% PWM maximum table
PWM Duty Cycle
Pulse Step
Number
Pulse Count
52
256/2048
%
12.5
51
240/2048
50
224/2048
49
48
Threshold Pulse Step
PWM Duty Cycle
Voltage
Number
Pulse Count
%
26
56/2048
2.73
11.7
25
52/2048
2.54
10.9
24
48/2048
2.34
208/2048
10.2
23
46/2048
2.25
192/2048
9.38
22
44/2048
2.15
47
184/2048
8.98
21
42/2048
2.05
46
176/2048
8.59
20
40/2048
1.95
45
168/2048
8.20
19
38/2048
1.86
44
160/2048
7.81
18
36/2048
1.76
43
152/2048
7.42
17
34/2048
1.66
42
144/2048
7.03
16
32/2048
1.56
41
136/2048
6.64
15
30/2048
1.46
40
128/2048
120/2048
6.25
14
28/2048
1.37
39
5.86
13
26/2048
1.27
38
112/2048
5.47
12
24/2048
1.17
37
104/2048
5.08
11
23/2048
1.12
36
96/2048
4.69
10
22/2048
1.07
35
92/2048
4.49
9
21/2048
1.03
34
88/2048
4.30
8
20/2048
0.98
33
84/2048
4.10
7
19/2048
0.93
32
80/2048
3.91
6
18/2048
0.88
31
76/2048
3.71
5
17/2048
0.83
30
72/2048
3.52
4
16/2048
0.78
29
68/2048
3.32
3
15/2048
0.73
28
64/2048
3.13
2
14/2048
0.68
27
60/2048
2.93
1
13/2048
0.63
(@VDD=2.8 V)
Threshold
Voltage
0.000
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¡ Semiconductor
MSC1215-xx
APPLICATION CIRCUITS
Dimming Mode
1
12 V
2
3
1
ROW
2
3
4
12 V
COL
Microcontroller
VDD
GRID1
GND
DATAI/O
CLOCK
CS
VREF
CH1
12 V
MSC1215-xx
GRID2
12 V
CH6
Small Lamp Switch
VK
Dashboard
Lamp
Lamp PWM
Signal
OSC1
OSC0
SEG17
VD
SEG1
1/2 Duty VF Display Tube
20/22
¡ Semiconductor
MSC1215-xx
Analog Dimming Mode
1
12 V
2
3
1
ROW
3
2
4
12 V
COL
Microcontroller
VDD
GRID1
GND
DATAI/O
CLOCK
CS
VREF
CH1
12 V
MSC1215-xx
GRID2
12 V
CH6
Small Lamp
Switch
VK
OSC1
Brightness
Control
Resistor
Dashboard Lamp
OSC0
SEG17
VD
SEG1
1/2 Duty VF Display Tube
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¡ Semiconductor
MSC1215-xx
PACKAGE DIMENSIONS
(Unit : mm)
DIP42-P-600-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
6.20 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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