DLP3000 DLPS022 – JANUARY 2012 www.ti.com ® DLP 0.3 WVGA Series 220 DMD Check for Samples: DLP3000 FEATURES 1 • 2 • • • • • • • • • 0.3-Inch (7.62 mm) Diagonal Micromirror Array – 608 × 684 Array of Aluminum, Micrometer-Sized Mirrors – 7.6-µm Micromirror Pitch – ±12° Micromirror Tilt Angle (Relative to Flat State) – Side Illumination for Optimized Efficiency – 3-µs Micromirror Cross Over Time Highly Efficient in Visible Light (420 nm–720 nm): – Window Transmission 97% (Single Pass, Through Two Window Surfaces) – Micromirror Reflectivity 88% – Array Diffraction Efficiency 86% – Array Fill Factor 92% – Polarization Independent Up to WVGA Resolution (854x480) Wide Aspect Ratio Display Low Power Consumption, only 200 mW (Typical) 15-Bit, Double Data Rate (DDR) Input Data Bus 60-MHz to 80-MHz Input Data Clock Rate Integrated Micromirror Driver Circuitry Supports –10 °C to 70 °C 16.6-mm by 7-mm by 5-mm Package Footprint Dedicated DLPC300 Controller for Reliable Operation • Package Mates to PANASONIC AXT550224 Socket APPLICATIONS • • • • • • • • • • • • • • • Machine Vision Industrial Inspection 3D Scanning 3D Optical Metrology Automated Fingerprint Identification Face Recognition Augmented Reality Embedded Display Interactive Display Information Overlay Spectroscopy Chemical Analyzers Medical Instruments Photo-Stimulation Virtual Gauges DESCRIPTION The DLP3000 digital micromirror device (DMD) is a digitally controlled MOEMS (micro-opto-electromechanical system) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP3000 can be used to modulate the amplitude, direction, and/or phase of incoming light. The DLP3000 creates light patterns with speed, precision, and efficiency. Architecturally, the DLP3000 is a latchable, electrical-in/optical-out semiconductor device. This architecture makes the DLP3000 well suited for use in applications such as 3D scanning or metrology with structured light, augmented reality, microscopy, medical instruments, and spectroscopy. The compact physical size of the DLP3000 is well-suited for portable equipment where small form factor and lower cost are important. The compact package compliments the small size of LEDs to enable highly efficient, robust light engines. The DLP3000 is one of two devices in the DLP 0.3 WVGA chipset (see Figure 1). Proper function and reliable operation of the DLP3000 requires that it be used in conjunction with the DLPC300 controller. See the DLP 0.3 WVGA Chip-set data sheet (TI literature number DLPZ005) for further details. Figure 2 shows a typical system application using the DLP 0.3-inch WVGA chipset. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a registered trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated DLP3000 DLPS022 – JANUARY 2012 www.ti.com DLPC300 DATA(14:0) LOADB TRC SCTRL SAC_BUS CONTROL SAC_CLK DRC_BUS SDRAM INTERFACE Serial FLASH FLASH INTERFACE VCC VSS VOFFSET VBIAS VRESET VDD10 VCC18 VCC_INTF GND VDD_PLL RTN_PLL SPICLK SPICSZ0 SPIDOUT SPIDIN VCC_FLSH DRC_OE DRC_STROBE LED DRIVER Memory Interface CAMERA TRIGGER CMOS MEMORY ARRAY MICROMIRROR ARRAY MICROMIRROR ARRAY RESET CONTROL SCL SDA PARK RESET GPIO4_INTF PLL_REFCLK DATA & CONTROL RECEIVER PARALLEL RGB Data Interface DLP3000 VCC VSS Illumination Interface Camera Trigger Figure 1. DLP 0.3 WVGA Chip Set 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Data Control Address Mobile DDR RAM HSYNC,VSYNC Red PWN, Green PWM, Blue PWM 24-Bit RGB Data LED Strobes PCLK LED Drivers LEDs Illumination Optics I22 C I22 C DLPC300 DMD Control DLP3000 DMD Data SPICS SPIDIN, SPIDOUT SPICLK CTL OSC VBIAS Control Processor (MSP430) VRST Control LED Sensor VOFF Digital Video DVI Receiver (TVP5151) DMD™ Voltage Supplies SPI FLASH Figure 2. Typical Application Electrically, the DLP3000 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 608 memory cell columns by 684 memory cell rows. The CMOS memory array is addressed on column-by-column basis, over a 15-bit double data rate (DDR) bus. Addressing is handled via a serial control bus. The specific CMOS memory access protocol is handled by the DLPC300 digital controller. Optically, the DLP3000 consists of 415,872 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors) organized in a two-dimensional array. The micromirror array consists of 608 micromirror columns by 684 micromirror rows in diamond pixel configuration (Figure 3). Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns of the even row. Each aluminum micromirror is approximately 7.6 microns in size (see Micromirror Pitch in Figure 3), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are measured relative to a 0° flat reference when the mirrors are parked in their inactive state, parallel to the array plane (see Figure 4). The tilt direction is perpendicular to the hinge-axis. The on-state landed position is directed toward the left side of the package (see DLP3000 Active Mirror Array, Micromirror Pitch, and Micromirror Hinge-Axis Orientation in Figure 3). Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a –12° position. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 3 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the CMOS memory. Second, application of a mirror reset to all or a portion of the micromirror array (depending upon the configuration of the system). Mirror reset pulses are generated internally by the DLP3000 DMD, with application of the pulses being coordinated by the DLPC300 controller. See SWITCHING CHARACTERISTICS timing specifications. Around the perimeter of the 608 × 684 array of micromirrors is a uniform band of border micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 608 by 684 active array. 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Incident Illumination Package Pin-1 Corner Col 0 Col 2 Row Row Row Row 0 1 2 3 680 681 682 683 Row Row Row Row 680 681 682 683 7. 63 7m 10.8 µm Micromirror Pitch 7m 63 7. 10.8 µm Col 3 Col 1 0 1 2 3 Col 607 Row Row Row Row (Border micromirrors omitted for clarity) Col 605 Row Row Row Row Col 604 Col 606 DLP3000 Active Mirror Array Micromirror Hinge-Axis Orientation “Off-State” Tilt Direction “On-State” Tilt Direction Figure 3. Micromirror Array, Pitch, and Hinge-Axis Orientation Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 5 DLP3000 DLPS022 – JANUARY 2012 www.ti.com –a ± b a±b Figure 4. Micromirror Landed Positions and Light Paths 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Related Documents The following documents contain additional information related to the use of the DLP3000 device: Table 1. Related Documents DOCUMENT TI LITERATURE NUMBER DLP 0.3 WVGA Chipset data sheet DLPZ005 DLPC300 Digital Controller data sheet DLPS023 DLPC300 Software Programmer's Guide DLPU004 Device Part Number Nomenclature Figure 5 provides a legend for reading the complete device name for any DLP device. DLP3000FQB Package Type Device Descriptor Figure 5. Device Nomenclature Device Marking The device marking consists of the fields shown in Figure 6. Lot Trace Code GHJJJJKHVVVV Encoded Device Part Number Figure 6. Device Marking Device Terminals This section describes the input/output characteristics of signals that interface to the DLP3000, organized by functional groups. Table 2 includes I/O, Type, Internal Termination, Clock Domain, and Data Rate characteristics which are further described in subsequent sections. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 7 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Figure 7. Package Connector Signal Names (Device Bottom View) 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Table 2. Connector Pins TERMINAL NAME CONNECTOR PINS I/O/P TYPE INTERNAL TERMINATION CLOCKED BY DATA RATE DATA(0) D2 Input LVCMOS None DCLK DDR DATA(1) D4 Input LVCMOS None DCLK DDR DATA(2) D5 Input LVCMOS None DCLK DDR DATA(3) D6 Input LVCMOS None DCLK DDR DATA(4) D8 Input LVCMOS None DCLK DDR DATA(5) D10 Input LVCMOS None DCLK DDR DATA(6) D12 Input LVCMOS None DCLK DDR DATA(7) D14 Input LVCMOS None DCLK DDR DATA(8) E16 Input LVCMOS None DCLK DDR DATA(9) E14 Input LVCMOS None DCLK DDR DATA(10) E12 Input LVCMOS None DCLK DDR DATA(11) E10 Input LVCMOS None DCLK DDR DATA(12) E5 Input LVCMOS None DCLK DDR DATA(13) E6 Input LVCMOS None DCLK DDR DATA(14) E8 Input LVCMOS None DCLK DDR DCLK E18 Input LVCMOS None – – LOADB E20 Input LVCMOS None DCLK DDR Parallel data load enable TRC E4 Input LVCMOS None DCLK DDR Input data toggle rate control SCTRL E2 Input LVCMOS None DCLK DDR Serial control bus SAC_BUS E24 Input LVCMOS None SAC_CLK DDR Stepped address control serial bus data SAC_CLK D24 Input LVCMOS None – – Stepped address control serial bus clock DESCRIPTION Data Inputs Input data bus Input data bus clock Data Control Inputs Mirror Reset Control Inputs DRC_BUS D22 Input LVCMOS None SAC_CLK DRC_OE D20 Input LVCMOS None – DRC_STROBE E22 Input LVCMOS None SAC_CLK DMD reset-control serial bus – Active-low output enable signal for internal DMD Reset driver circuitry Strobe signal for DMD Reset Control inputs Power VBIAS D16 Power Analog None – – Mirror reset bias voltage VOFFSET D21 Power Analog None – – Mirror reset offset voltage VRESET D18 Power Analog None – – Mirror reset voltage VREF E21 Power Analog None – – Power supply for double-data-rate low-voltage CMOS logic terminals VCC D1, D13, D25, E1, E13, E25 Power Analog None – – Power supply for single-data-rate LVCMOS logic terminals VSS D3, D7, D9, D11, D15, D17, D19, D23, E3, E7, E9, E11, E15, E17, E19, E23 Power Analog None – – Common return for all power inputs Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 9 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Table 2. Connector Pins (continued) 10 TERMINAL NAME CONNECTOR PINS I/O/P TYPE INTERNAL TERMINATION CLOCKED BY DATA RATE DESCRIPTION No connect A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29 A31, B2, B4, B6, B8, B10, B12, B14, B16, B18, B20, B22, B24, B26, B28, B30, C1, C3, C31, F1, F3, F31, G2, G4, G6, G8, G10, G12, G14, G16, G18, G20, G22, G24, G26, G28, G30, H1, H3, H5, H7, H9, H11, H13, H15, H17, H19, H21, H23, H25, H27, H29, H31 – – – – – No connection (Any connection to these terminals may result in undesirable effects) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional performance of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PARAMETER CONDITIONS MIN MAX UNIT Electrical VCC Voltage applied to VCC (1) (2) –0.5 4 V VREF Voltage applied to VREF (1) (2) –0.5 4 V (1) (2) (3) VOFFSET Voltage applied to VOFFSET –0.5 8.75 V VBIAS Voltage applied to VBIAS (1) (2) (3) –0.5 17 V VRESET Voltage applied to VRESET (1) (2) –11 0.5 V 8.75 V –0.5 VREF + 0.3 Supply voltage delta |VBIAS – VOFFSET| (3) Voltage applied to all other input terminals (1) V Current required from a high-level output VOH = 2.4 V –20 mA Current required from a low-level output VOL = 0.4 V 15 mA Environmental Storage temperature range (4) (5) Storage humidity (4) (5) -40 80 °C 0 95 % RH Non-condensing < 420 nm Illumination power density (4) (6) 420 nm to 700 nm > 700 nm Electrostatic discharge immunity (1) (2) (3) (4) (5) (6) (7) (8) (8) All pins 2 See (7) mW/cm2 10 2000 V All voltages referenced to VSS (ground). Voltages VCC, VREF, VOFFSET, VBIAS, and VRESET are required for proper DMD operation. Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw. Optimal, long-term performance of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, ambient humidity (both storage and operating), and power on/off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle. Contact your local Texas Instruments representative for additional information related to optimizing the DMD performance. Simultaneous exposure to high storage temperature and high storage humidity may affect device reliability. Total integrated illumination power density, above or below the indicated wavelength threshold. Limited only by the resulting array temperature. Refer to the Thermal Characteristics for information related to calculating the micromirror array temperature. Tested in accordance with JESD22-A114-B electrostatic discharge (ESD) sensitivity testing, human-body model (HBM). Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 11 DLP3000 DLPS022 – JANUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. PARAMETER CONDITIONS MIN NOM MAX UNIT 1.65 1.8 1.95 V 2.375 2.5 2.625 V 8.25 8.5 8.75 V 15.5 16 16.5 V – 9.5 –10 –10.5 V 8.75 V Electrical LVCMOS interface supply voltage (1) (2) VREF VCC LVCMOS logic supply voltage VOFFSET VBIAS VRESET (1) (2) Mirror electrode and HVCMOS supply voltage (1) (2) (3) Mirror electrode voltage (1) (2) (3) Mirror electrode voltage (1) (2) Delta supply voltage |VBIAS – VOFFSET| (3) VT+ Positive-going threshold voltage 0.4 × VREF 0.7 × VREF V VT– Negative-going threshold voltage 0.3 × VREF 0.6 × VREF V Vhys Hysteresis voltage (VT+ – VT–) 0.1 × VREF 0.4 × VREF fDCLK DCLK clock frequency 60 80 MHz 45 N 100 N V Mechanical Static load applied to the package electrical connector area (4) (5) Static load applied to the DMD mounting area (6) (5) Environmental Operating Case Temperature (7) (8) Operating Humidity (7) non-condensing 25 °C 50 % RH Operating Device Temperature Gradient (9) Operating Landed Duty-Cycle (7) (10) 10 25 °C % (1) (2) (3) All voltages referenced to VSS (ground) Voltages VCC, VREF, VOFFSET, VBIAS, VRESET are required for proper DMD operation. Exceeding the recommended voltage difference between VBIAS and VOFFSET may result in excessive current draw. See the Absolute Maximum Ratings for further details. (4) Load should be uniformly distributed across the entire connector area. (5) See Figure 8. (6) Load should be uniformly distributed across the three datum-A surfaces. (7) Optimal, long-term performance of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case temperature, ambient humidity (both storage and operating), and power on/off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle. Contact your local Texas Instruments representative for additional information related to optimizing the DMD performance. (8) Refer to the Thermal Characteristics for the calculation of the micromirror array temperature from the thermal test point TC3 shown in Figure 15. (9) As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror array cavity. Refer to the Thermal Characteristics for information related to calculating the micromirror array temperature. (10) "Landed Duty-Cycle" refers to the percentage of time an individual micromirror spends landed in one state (+12 or -12 degrees) versus the other state (-12 or +12 degrees). 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Datum ‘A’ Area (3 Places) DMD Mounting Area (3 Places Opposite Datum ‘A’) 100 N Maximum Uniformly Distributed Over 3 Areas (See Mechanical ICD for Dimensions of Datum ‘A’) Connector Area 45 N Maximum Figure 8. System Interface Loads Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 13 DLP3000 DLPS022 – JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted) PARAMETER CONDITIONS MIN VOH High-level output voltage (1) VCC = 2.5 V, IOH = –21 mA VOL Low-level output voltage (1) VCC = 2.5 V, IOH = 15 mA IOH High-level output current IOL MAX 1.7 UNIT V 0.4 V VOH = 1.7 V –15 mA Low-level output current VOL = 0.4 V 14 mA IIL Low-level input current VREF = 1.95 V, VI = 0 V IIH High-level input current VREF = 1.95 V, VI = VREF 1.9 nA IREF Current into VREF terminal VREF = 1.95 V, fDCLK = 77 MHz 0.7 mA ICC Current into VCC terminal VCC = 2.625 V, fDCLK = 77 MHz 55 mA IOFFSET Current into VOFFSET terminal (2) VOFFSET = 8.75 V 1 mA IBIAS Current into VBIAS terminal 1.6 mA (2) –1.6 VBIAS = 17 V (2) VRESET = –11 V nA IRESET Current into VRESET terminal 1.5 mA PREF Power into VREF terminal (3) VREF = 1.95 V, fDCLK = 77 MHz 1.5 mW PCC Power into VCC terminal (3) VCC = 2.625 V, fDCLK = 77 MHz 144 mW POFFSET Power into VOFFSET terminal (3) 9 mW (3) PBIAS Power into VBIAS terminal PRESET Power into VRESET terminal CI CO (1) (2) (3) VOFFSET = 8.75 V VBIAS = 17 V 27.2 mW VRESET = –11 V 18 mW Input capacitance f = 1 MHz 10 pF Output capacitance f = 1 MHz 10 pF (3) Applies to LVCMOS pins only Exceeding the maximum allowable absolute voltage difference between VBIAS and VOFFSET may result in excesses current draw. (See Absolute Maximum Ratings for details.) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See the Thermal Characteristics for further details. Measurement Conditions The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 9 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of ac timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. RL From Output Under Test Tester Channel CL = 50 pF CL = 5 pF for Disable Time Figure 9. Test Load Circuit for AC Timing Measurements 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT Setup time: DATA before rising or falling edge of DCLK 1 Setup time: TRC before rising or falling edge of DCLK 1 Setup time: SCTRL before rising or falling edge of DCLK 1 ts2 Setup time: LOADB low before rising edge of DCLK 1 ns ts3 Setup time: SAC_BUS low before rising edge of SAC_CLK 1 ns ts4 Setup time: DRC_BUS high before rising edge of SAC_CLK 1 ns ts5 Setup time: DRC_STROBE high before rising edge of SAC_CLK 1 ns Hold time: DATA after rising or falling edge of DCLK 1 Hold time: TRC after rising or falling edge of DCLK 1 Hold time: SCTRL after rising or falling edge of DCLK 1 th2 Hold time: LOADB low after falling edge of DCLK 1 ns th3 Hold time: SAC_BUS low after rising edge of SAC_CLK 1 ns th4 Hold time: DRC_BUS after rising edge of SAC_CLK 1 ns th5 Hold time: DRC_STROBE after rising edge of SAC_CLK 1 ns tc1 Clock cycle: DCLK 12.5 16.67 ns tc3 Clock cycle: SAC_CLK 12.5 16.67 ns tw1 Pulse width high or low: DCLK 5 ns tw2 Pulse width low: LOADB 7 ns tw3 Pulse width high or low: SAC_CLK 5 ns tw5 Pulse width high: DRC_STROBE 7 ns ts1 th1 tr tf ns ns Rise time: DCLK / SAC_CLK 2.5 Rise time: DATA / TRC / SCTRL / LOADB 2.5 Fall time: DCLK / SAC_CLK 2.5 Fall time: DATA / TRC / SCTRL / LOADB 2.5 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 ns ns 15 DLP3000 DLPS022 – JANUARY 2012 www.ti.com tc1 tf tr DCLK tw1 tw1 ts2 th2 LOADB tw2 th1 ts1 th1 ts1 SCTRL DATQA_(0:14) TRC tc3 tf tr SAC_CLK tw3 SAC_BUS th3 DRC_BUS DRC_STROBE tw3 tw5 ts3 ts4 th4 ts5 th5 Figure 10. Switching Characteristics 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com POWER SUPPLY SEQUENCING REQUIREMENTS DLP3000 includes four voltage-level supplies (VCC, VREF, VOFFSET, VBIAS, and VRESET). For reliable operation of DLP3000, the following power supply sequencing requirements must be followed. CAUTION Reliable performance of the DMD requires that the following conditions be met: 1. That the VCC, VREF, VOFFSET, VBIAS, and VRESET power supply inputs all be present during operation. 2. That the VCC, VREF, VOFFSET, VBIAS, and VRESET power supplies be sequenced on and off in the manner prescribed below. Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability DMD Power Supply Power-Up Procedure Step 1: Power up VCC and VREF in any order Step 2: Wait for VCC and VREF to each reach a stable level within their respective recommended operating ranges. Step 3: Power up VBIAS, VOFFSET, and VRESET in any order, provided that the maximum delta-voltage between VBIAS and VOFFSET is not exceeded (see Absolute Maximum Ratings for details). Note 1: During the power-up procedure, the DMD LVCMOS inputs should not be driven high until after Step 2 has been completed. Note 2: Power supply slew rates during power up are unrestricted, provided that all other conditions are met. DMD Power Supply Power-Down Procedure Step 1: Command the chipset controller to execute a mirror-parking sequence. See the controller data sheet (listed in Related Documents) for details. Step 2: Power down VBIAS, VOFFSET, and VRESET in any order, provided that the maximum delta voltage between VBIAS and VOFFSET is not exceeded (see Absolute Maximum Ratings for details). Step 3: Wait for VBIAS, VOFFSET, and VRESET to each discharge to a stable level within 4 V of the reference ground. Step 4: Power down VCC and VREF in any order. Note 1: During the power-down procedure, the DMD LVCMOS inputs should be held at a level less than VREF + 0.3 volts. Note 2: Power-supply slew rates during power down are unrestricted, provided that all other conditions are met. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 17 DLP3000 DLPS022 – JANUARY 2012 www.ti.com VBIAS , VOFFSET , and VRESET Disabled by Software Control Power Off VCC/ VREF Mirror Park Sequence RESET VSS RESET AND PARK VCC/ VREF VCC/ VREF VSS VSS VBIAS VBIAS ...… ... ...… ... ...… ... … … D V < 8.75 V Note1 DV < 8.75 Note1 VBIAS< 4 V VSS VOFFSET VSS ... … ... ...… ... ...… ...… … VOFFSET VOFFSET< 4 V VSS VRESET< 0.5 V VSS VSS VSS VRESET> - 4 V VRESET VRESET ... … ... ...… ... ...… ...… … VCC/ VCCI LVCMOS Inputs VSS VSS NOTE 1: Delta supply voltage |VBIAS – VOFFSET| < 8.75 V Figure 11. Power-Up / Power-Down Timing 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Micromirror Array Physical Characteristics Physical characteristics of the micromirror array are provided in Table 3. Table 3. Micromirror Array Physical Characteristics PARAMETER VALUE Number of active micromirror rows (1) Number of active micromirror columns (1) Micromirror pitch, diagonaL (2) Micromirror active array height Micromirror active array width Micromirror array border (1) (2) (3) (4) micromirrors 608 micromirrors 7.637 Micromirror pitch, vertical and horizontal (2) (3) µm 684 micromirrors 604 6.5718 (4) µm 10.8 3.699 (3) UNITS 684 10 mm micromirrors mm mirrors/side See Figure 14 See Figure 12 SeeFigure 13 The mirrors that form the array border are hard-wired to tilt in the –12° (“Off”) direction once power is applied to the DMD (see Figure 3 and Figure 4). 10.8 mm 6 7. 37 10.8 mm 7. 63 7 mm mm Figure 12. DLP3000 Pixel Pitch Dimensions Pin 1 6571.8 mm (0,0) 3699 mm Illumination On Off (607,683) Figure 13. DLP3000 Micromirror Active Area Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 19 DLP3000 DLPS022 – JANUARY 2012 Col 1 Col 0 Col 4 Col 3 Pin 1 Col 604 Col 606 Col 605 Col 607 www.ti.com Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Incoming Light Row 607 Row 677 Row 678 Row 679 Row 680 Row 681 Row 682 Row 683 Figure 14. DLP3000 Pixel Arrangement 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Micromirror Array Optical Characteristics TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. See the related application reports (listed in Related Documents) for guidelines. Table 4. Optical Parameters PARAMETER DMD parked state see Figure 4 α Micromirror tilt angle β Micromirror tilt angle variation Micromirror crossover time CONDITIONS MIN , See Figure 4 12 Micromirror switching time (9) Orientation of the micromirror axis-of-rotation Micromirror array optical efficiency (12) (13) degrees –1 1 (9) 5 µs 16 µs Non-adjacent micromirrors Non-operating micromirrors (10) 10 Adjacent micromirrors (11) 0 89 420 nm to 700 nm, with all micromirrors in the ON state Mirror metal specular reflectivity (420 nm – 700 nm) UNIT 0 DMD “landed” state (1) (4) (5), see Figure 4 (1) (4) (6) (7) (8) NOM MAX (1) (2) (3) 90 91 micromirrors degrees 68 % 89.4 % (1) (2) Measured relative to the plane formed by the overall micromirror array Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by the overall micromirror array). (3) When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled. (4) Additional variation exists between the micromirror array and the package datums. (5) When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in an nominal angular position of +12 degrees. A binary value of 0 results in a micromirror landing in an nominal angular position of –12 degrees. (6) Represents the landed tilt angle variation relative to the nominal landed tilt angle (7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices. (8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle varation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations and/or system contrast varations. (9) Performance as measured at the start of life. (10) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12 degree position to +12 degrees or vice versa. (11) Measured relative to the package datums B and C, shown in the Package Mechanical Data section at the end of this document. (12) The minimum or maximum DMD optical efficiency observed in a specific application depends on numerous application-specific design variables, such as: (a) Illumination wavelength, bandwidth/line-width, degree of coherence (b) Illumination angle, plus angle tolerance (c) Illumination and projection aperture size, and location in the system optical path (d) IIllumination overfill of the DMD micromirror array (e) Aberrations present in the illumination source and/or path (f) Aberrations present in the projection path (g) Etc. The specified nominal DMD optical efficiency is based on the following use conditions: (a) Visible illumination (420 nm–700 nm) (b) Input illumination optical axis oriented at 24° relative to the window normal (c) Projection optical axis oriented at 0° relative to the window normal (d) f/3 illumination aperture (e) f/2.4 projection aperture Based on these use conditions, the nominal DMD optical efficiency results from the following four components: (a) Micromirror array fill factor: nominally 92.5% (b) Micromirror array diffraction efficiency: nominally 86% (c) Micromirror surface reflectivity: nominally 88% (d) Window transmission: nominally 97% (single pass, through two surface transitions) (13) Does not account for the effect of micromirror switching duty cycle, which is application dependant. Micromirror switching duty cycle represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 21 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Table 4. Optical Parameters (continued) PARAMETER CONDITIONS Illumination overfill (14) NOM MAX 10 Window material Window refractive index MIN UNIT % Corning Eagle XG At 546.1 nm 1.5119 See Window aperture (15) (14) The active area of the DLP3000 is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can create artifacts from the mechanical features that surround the active array and other surface anomalies that may be visible on the projected image. The illumination optical system should be designed to limit light flux incident anywhere outside the active array less than 10% of the average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause visible artifacts. (15) See the Package Mechanical Characteristics for details regarding the size and location of the window aperture. 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 DLP3000 DLPS022 – JANUARY 2012 www.ti.com Thermal Characteristics Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the maximum temperature of any individual micromirror in the active array, the maximum temperature of the window aperture, and the temperature gradient between any two points on or within the package. See the Absolute Maximum Ratings and Recommended Operation Conditions for applicable temperature limits. Package Thermal Resistance The DMD is designed to conduct the absorbed and dissipated heat back to the Series 220 package where it can be removed by an appropriate system thermal management. The system thermal management must be capable of maintaining the package within the specified operational temperatures at the Thermal Test Point location, see Figure 15. The total heat load on the DMD is typically driven by the incident light absorbed by the active area; although other contributions can include light energy absorbed by the window aperture, electrical power dissipation of the array, and/or parasitic heating. Table 5. Package Thermal Resistance Min Nom Thermal resistance from active micromirror array to TC3 Max Units 5 °C/W Case Temperature The temperature of the DMD case can be measured directly. For consistency, a thermal test point location is defined, as shown in Figure 15. Figure 15. Thermal Test Point Location Micromirror Array Temperature Calculation Micromirror array temperature cannot be measured directly. Therefore, it must be computed analytically from: Thermal test point location (See Figure 15) Package thermal resistance Electrical power dissipation Illumination heat load The relationship between the micromirror array and the case temperature is provided by the following equations: TArray = TCeramic + (QArray × RArray-To-Ceramic) QArray = QElec + QIllum Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 23 DLP3000 DLPS022 – JANUARY 2012 www.ti.com QIllum = CL2W × SL where the following elements are defined as: TArray = computed micromirror array temperature (°C) TCeramic = ceramic case temperature (°C) (TC3 location) QArray = Total DMD array power (electrical + absorbed) (W) RArray-to-Ceramic = thermal resistance of DMD package from array to TC3 (°C/W) QElec = nominal electrical power (W) QIllum = absorbed illumination heat (W) CL2W = Lumens-to-watts constant, estimated at 0.00274 watt/lumen, based on array charasteristics. It assumes a spectral efficiency of 300 lumens/watt for the projected light, illumination distribution of 83.7% on the active array, and 16.3% on the array border and window aperture. SL = Screen lumens These equations are based on traditional 1-chip DLP system with a total projection efficiency from the DMD to the screen of 87%. An example calculation is provided below. DMD electrical power dissipation varies and is dependent on the voltage, data rates, and operating frequencies. The nominal electrical power dissipation used in this calculation is 0.15 watts. Screen lumens is nominally 20 lumens. The ceramic case temperature at TC3 is 55 °C. Using these values in the above equations, the following values are computed: QArray = QElec + CL2W × SL = 0.144 W + (0.00274 W/Lumen × 20 Lumen) = 0.1988 W TArray = TCeramic + (QArray * RArray-To-Ceramic) = 55 °C + (0.1988 W × 5 °C/W) = 55.99 °C 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): DLP3000 PACKAGE OPTION ADDENDUM www.ti.com 19-Jan-2012 PACKAGING INFORMATION Orderable Device DLP3000FQB Status (1) ACTIVE Package Type Package Drawing LCCC FQB Pins Package Qty 50 10 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Level-1-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 8 5 6 7 3 4 C NOTES UNLESS OTHERWISE SPECIFIED: 1 DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY. DWG NO. COPYRIGHT 2009 TEXAS INSTRUMENTS UN-PUBLISHED, ALL RIGHTS RESERVED. REV A 2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES. B 2510388 1 1 SH REVISIONS DESCRIPTION ECO 2097098 INITIAL RELEASE DATE 03/02/09 BY J. HOLM ECO 2098984 TIGHTEN DIE ROTATION, NOTE 2; ADD 'DD1' SUFFIX TO CONNECTOR PART#; CHG DWG TO INVENTOR 08/27/09 BMH 3 BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY. D 4 DMD MARKING TO APPEAR ON BOTTOM OF CONNECTOR. D 5 NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC, AS SHOWN IN SECTION A-A. 6 ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN IN VIEWS C AND G (SHEET 2). 5 2X 0.8 `0.1 4X R0.2 `0.05 5 C (ILLUMINATION DIRECTION) R0.6 `0.1 5 +0.3 70.1 5 90° `1° 3 `0.075 +0.2 5 2X 2 0.1 A 5 +0.2 1 - 0.1 5 B 0 MIN (3) 5 A +0.2 3.5 0.1 (1.4) C 2X R0.4 `0.1 (1) 14.6 `0.08 +0.3 16.6 0.1 WINDOW APERTURE 5 1.359 `0.079 D 0.65 `0.05 2X ENCAPSULANT 6 B 0.4 MIN (2.139) 1 SECTION A-A NOTCH OFFSETS f 0.038 A 0.02 D ACTIVE ARRAY A 3 SURFACES INDICATED IN VIEW B (SHEET 2) 0.78 `0.063 1.4 `0.1 (1.05) c 0.05 E (SHEET 3) E (SHEET 3) (PANASONIC AXT650224DD1, 50-CONTACT, 0.4 mm PITCH BOARD-TO-BOARD HEADER) INTERFACE TO PANASONIC AXT550224DD1 SOCKET A UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS TOLERANCES: THIRD ANGLE PROJECTION NONE 0314DA NEXT ASSY USED ON DRAWN 2/25/2009 ENGINEER 2/25/2009 ANGLES `1~ B. HASKETT 2 PLACE DECIMALS `0.25 QA/CE 1 PLACE DECIMALS `0.50 DIMENSIONAL LIMITS APPLY BEFORE PROCESSES INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME Y14.5M-1994 REMOVE ALL BURRS AND SHARP EDGES PARENTHETICAL INFORMATION FOR REFERENCE ONLY DATE J. HOLM P. KONRAD 8 7 6 5 4 TITLE CM J. GRIMMETT 3/9/2009 3 2 ICD, MECHANICAL, DMD, .3 WVGA DDR SERIES 220 0.4 mm PITCH CONNECTOR REV DWG NO SIZE D SCALE APPLICATION INV11-2006a Dallas Texas 3/9/2009 APPROVED A TEXAS INSTRUMENTS B 2510388 15:1 SHEET 1 1 OF 3 8 D 0.812 5 6 7 3 4 DWG NO. 2510388 SH 1 2 3X (1) 2X 14.6 A3 D A2 C 3X 1.7 (3) n1.5 B 3X (1.8) VIEW B DATUMS A, B, AND C C 6 A1 6 0.812 14.6 C (FROM SHEET 1) (n1.5) 6 B 7.3 3.7 6 VIEW C ENCAPSULANT MAXIMUM X/Y DIMENSIONS B B (FROM SHEET 1) 6 A 2X 40° A VIEW G ENCAPSULANT HEIGHT LIMITS TEXAS INSTRUMENTS Dallas Texas INV11-2006a 8 7 6 5 4 3 DRAWN J. HOLM DATE 2/25/2009 SIZE D SCALE 2 DWG NO REV 2510388 SHEET 1 2 OF B 3 8 5 6 7 3 4 2510388 DWG NO. SH 1 3 D D (6.5718) ACTIVE ARRAY 5.188 `0.075 2 4X (0.108) 3 1.624 `0.075 0.377 `0.0885 1.602 `0.05 (6.516) WINDOW 4.914 `0.05 C 3.946 `0.0885 (3.699) ACTIVE ARRAY (n1.5) (4.323) APERTURE (3) F B C C 0.64 `0.0885 6.963 `0.0885 CL (7.603) APERTURE 2.2 `0.05 CL 8.039 `0.05 67X TEST PADS (10.239) WINDOW j 0.314 VIEW D WINDOW AND ACTIVE ARRAY n0.1 A 15 X 1.04 = 15.6 (0.52) 4 (0.47) (n0.52) TYP. (FROM SHEET 1) B n0.2 A B C H CL G F (3) 4.22 (n1.5) 25 20 15 10 5 1 B D (42°) TYP. (0.15) TYP. 2X 0.93 E 2.11 (42°) TYP. B C C B 2X (1.86) j 0.4 A B C A 2 X 0.47 = 0.94 (0.068) TYP. 30 31 26 27 24 25 22 23 20 21 18 19 16 17 14 15 12 13 10 11 8 9 6 7 4 5 2 3 1 BACK INDEX MARK (11.8) 2.212 CL j 0.4 A B C DETAIL F APERTURE SHORT EDGES A 28 29 VIEW E-E TEST PADS AND LE A C S : CONNECTOR 5 1 SCALE 50 : 1 A (FROM SHEET 1) TEXAS INSTRUMENTS Dallas Texas INV11-2006a 8 7 6 5 4 3 DRAWN J. HOLM DATE 2/25/2009 SIZE D SCALE 2 DWG NO REV 2510388 SHEET 1 3 OF B 3 PACKAGE OPTION ADDENDUM www.ti.com 19-Jan-2012 PACKAGING INFORMATION Orderable Device DLP3000FQB Status (1) ACTIVE Package Type Package Drawing LCCC FQB Pins Package Qty 50 10 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Level-1-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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