MCNIX MX23L12822MC-12 128m-bit (8m x 16 / 4m x 32) mask rom with page mode Datasheet

MX23L12822
128M-BIT (8M x 16 / 4M x 32) MASK ROM WITH PAGE MODE
FEATURES
• Current
- Operating: 75mA (max.)
- Standby: 15uA (max.)
• Supply voltage
- 3.3V±10%
• Package
- 70 pin SSOP (500 mil)
- 86 pin TSOP(2)
• Bit organization
- 8M x 16 (byte mode)
- 4M x 32 (double word mode)
• Fast access time
- Random access: 120ns (max.)
- Page access: 30ns (max.)
• Page Size
- 8 double words per page
PIN CONFIGURATION
70 SSOP
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
NC
A0
A1
A2
A3
A4
A5
NC
NC
VCC
D0
D16
D1
D17
VSS
VCC
D2
D18
D3
D19
NC
NC
D4
D20
D5
D21
VSS
VCC
D6
D22
D7
D23
VSS
A6
A7
A8
A9
A10
A11
A12
A13
NC
NC
NC
A21
A20
WORD
OE
CE
VSS
D31/A-1
D15
D30
D14
VSS
VCC
D29
D13
D28
D12
D27
D11
D26
D10
VSS
VCC
D25
D9
D24
D8
VCC
A19
A18
A17
A16
A15
A14
A13
P/N:PM0561
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
MX23L12822
A0
A1
A2
A3
A4
A5
VCC
D0
D16
D1
D17
VSS
VCC
D2
D18
D3
D19
D4
D20
D5
D21
VSS
VCC
D6
D22
D7
D23
VSS
A6
A7
A8
A9
A10
A11
A12
MX23L12822
86 TSOP
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
NC
NC
A21
A20
WORD
OE
CE
NC
VSS
NC
D31/A-1
D15
D30
D14
VSS
VCC
D29
D13
D28
D12
NC
D27
D11
D26
D10
VSS
VCC
D25
D9
D24
D8
VCC
A19
A18
A17
A16
A15
A14
NC
NC
NC
NC
REV. 1.5, DEC. 26, 2000
1
MX23L12822
ORDER INFORMATION
Part No.
MX23L12822MC-12
MX23L12822YC-12
Access Time
120ns
120ns
Page Access Time
30ns
30ns
Package
70 pin SSOP
86 pin TSOP
PIN DESCRIPTION
Symbol
A0~A21
D0~D30
Pin Function
Address Inputs
Data Outputs
D31/A-1
CE
OE
Word
VCC
VSS
NC
D31 (Double Word Mode)/ LSB Address (Word Mode)
Chip Enable Input
Output Enable Input
Double Word/ Word Mode Selection
Power Supply Pin
Ground Pin
No Connection
MODE SELECTION
CE
H
L
L
L
OE
X
H
L
L
Word
X
X
H
L
D31/A-1
X
X
Output
Input
D0~D15
High Z
High Z
D0~D15
D0~D15
P/N:PM0561
D16~D31
High Z
High Z
D16~D31
High Z
Mode
Double Word
Word
Power
Stand-by
Active
Active
Active
REV. 1.5, DEC. 26, 2000
2
MX23L12822
BLOCK DIAGRAM
A0/(A-1)
A2
A3
Address
Memory
Page
Page
Buffer
Array
Buffer
Decoder
Double
Word/
Word
A21
Output
Buffer
D0
D31/(D15)
CE
WORD
OE
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any Pin Relative to VSS
Ambient Operating Temperature
Storage Temperature
Symbol
VIN
Topr
Tstg
Ratings
-1.3V to 2.0V
0°C to 70°C
-65°C to 125°C
Note: Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -1.3V for periods of up to 20ns. Maximum DC voltage
on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns.
DC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
VOH
VOL
VIH
VIL
ILI
ILO
ICC1
MIN.
2.4V
2.2V
-0.3V
-
MAX.
0.4V
VCC+0.3V
0.8V
5uA
5uA
75mA
Standby Current (TTL)
Standby Current (CMOS)
Input Capacitance
Output Capacitance
ISTB1
ISTB2
CIN
COUT
-
1mA
15uA
10pF
10pF
P/N:PM0561
Conditions
IOH = -0.4mA
IOL = 1.6mA
0V, VCC
0V, VCC
tRC = 120ns, all output open,
with normal sequential access
testing pattern
CE = VIH
CE>VCC-0.2V
Ta = 25°C, f = 1MHZ
Ta = 25°C, f = 1MHZ
REV. 1.5, DEC. 26, 2000
3
MX23L12822
AC CHARACTERISTICS (Ta = 0°C ~ 70°C, VCC = 3.3V±10%)
Item
Symbol
23L12822-12
MIN.
MAX.
Read Cycle Time
tRC
120ns
-
Address Access Time
tAA
-
120ns
Chip Enable Access Time
tACE
-
120ns
Page Mode Access Time
tPA
-
30ns
Output Enable Time
tOE
-
30ns
Output Hold After Address
tOH
0ns
-
Output High Z Delay
tHZ
-
20ns
Note:Output high-impedance delay (tHZ) is measured
from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Level
Output Timing Level
Output Load
0.4V~ 2.4V
10ns
1.4V
1.4V
See Figure
IOH (load)=-0.4mA
DOUT
IOL (load)=1.6mA
C<100pF
Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
P/N:PM0561
REV. 1.5, DEC. 26, 2000
4
MX23L12822
TIMING DIAGRAM
RANDOM READ
ADD
ADD
ADD
ADD
tRC
tACE
CE
OE
tOE
tOH
tAA
DATA
VALID
VALID
tHZ
VALID
PAGE READ
VALID ADD
A3-A21
(A-1),A0,A1,A2
2'nd ADD
1'st ADD
tAA
DATA
3'rd ADD
tPA
VALID
VALID
VALID
Note: CE, OE are enable.
Page size is 8 double words in 32-bit mode, 16 words in 16-bit mode.
P/N:PM0561
REV. 1.5, DEC. 26, 2000
5
MX23L12822
Revision History
Revision #
1.3
1.4
1.5
Description
DC Characteristics ISTB2(CMOS Standby Current) 5uA-->15uA
Operating Current (ICC1) 60mA-->75mA
Modify Pin Configuration--86 TSOP D31-->D31/A-1
P/N:PM0561
Page
P3
P1,3
P1
Date
DEC/15/1999
JAN/14/2000
DEC/26/2000
REV. 1.5, DEC. 26, 2000
6
MX23L12822
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-6688
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
7
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