Microchip MCP2021P Lin transceiver with voltage regulator Datasheet

MCP2021/2/1P/2P
LIN Transceiver with Voltage Regulator
Features
Description
• The MCP2021/2/1P/2P are compliant with LIN
Bus Specifications 1.3, 2.0, and 2.1 and are
compliant to SAE J2602
• Support Baud Rates up to 20 Kbaud with
LIN-compatible output driver
• 43V Load dump protected
• Very low EMI meets stringent OEM requirements
• Wide supply voltage, 6.0V - 18.0V continuous:
- Maximum input voltage of 30V
• Extended Temperature Range: -40 to +125°C
• Interface to PIC EUSART and standard USARTs
• Local Interconnect Network (LIN) bus pin:
- Internal pull-up resistor and diode
- Protected against ground shorts
- Protected against loss of ground
- High current drive
• Automatic thermal shutdown
• On-Chip Voltage Regulator:
- Output voltage of 5.0V with tolerances of
±3% overtemperature range
- Available with alternate output voltage of
3.3V with tolerances of ±3% overtemperature
range
- Maximum continuous input voltage of 30V
- Internal thermal overload protection
- Internal short circuit current limit
- External components limited to filter capacitor
only and load capacitor
• Two low-power modes:
- Receiver on, Transmitter off, voltage
regulator on (≅ 85 µA)
- Receiver monitoring bus, Transmitter off,
voltage regulator off (≅ 16 µA)
The MCP2021/2/1P/2P provides a bidirectional, halfduplex communication physical interface to automotive
and industrial LIN systems that meets the LIN bus
specification Revision 2.0. The devices incorporate a
voltage regulator with 5V at 50 mA or 3.3V at 50 mA
regulated power-supply outputs.
© 2005-2012 Microchip Technology Inc.
The regulator is short-circuit protected, and is protected
by an internal thermal shutdown circuit. The device has
been specifically designed to operate in the automotive
operating environment and will survive all specified
transient conditions while meeting all of the stringent
quiescent current requirements.
The MCP2021/2/1P/2P family of devices includes the
following packages.
8-pin PDIP, DFN and SOIC packages:
• MCP2021-330, LIN-compatible driver, 8-pin, 3.3V
regulator, wake up on dominant level of LBUS
• MCP2021-500, LIN-compatible driver, 8-pin, 5.0V
regulator, wake up on dominant level of LBUS
• MCP2021P-330, LIN-compatible driver, 8-pin,
3.3V regulator, wake up at falling edge of LBUS
voltage
• MCP2021P-500, LIN-compatible driver, 8-pin,
5.0V regulator, wake up at falling edge of LBUS
voltage
14-pin PDIP, TSSOP and SOIC packages with RESET
output:
• MCP2022-330, LIN-compatible driver, 14-pin,
3.3V regulator, RESET output, wake up on dominant level of LBUS
• MCP2022-500, LIN-compatible driver, 14-pin,
5.0V regulator, RESET output, wake up on dominant level of LBUS
• MCP2022P-330, LIN-compatible driver, 14-pin,
3.3V regulator, RESET output, wake up at falling
edge of LBUS voltage
• MCP2022P-500, LIN-compatible driver, 14-pin,
5.0V regulator, RESET output, wake up at falling
edge of LBUS voltage
DS22018F-page 1
MCP2021/2/1P/2P
Package Types
DFN-8, PDIP-8, SOIC-8
1
2
3
4
MCP2021
MCP2021P
RXD
CS/LWAKE
VREG
TXD
8
7
6
5
FAULT/TXE
VBB
LBUS
VSS
PDIP-14, SOIC-14, TSSOP-14
1
14
2
13
VREG
TXD
3
RESET
NC
NC
4
5
6
7
MCP2022
MCP2022P
RXD
CS/LWAKE
12
11
10
9
8
FAULT/TXE
VBB
LBUS
VSS
NC
NC
NC
MCP2021/2 Block Diagram
Short Circuit
Protection
Thermal
Protection
RESET
(MCP2022 ONLY)
Voltage
Regulator
VREG
Internal Circuits
VBB
Ratiometric
Reference
Wake-Up
Logic and
Power Control
–
RXD
+
~30 kΩ
CS/LWAKE
TXD
LBUS
OC
FAULT/TXE
VSS
Thermal
Protection
DS22018F-page 2
Short Circuit
Protection
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
MCP2021P/2P Block Diagram
Thermal
Protection
RESET
Voltage
Regulator
VBB
(MCP2022P ONLY)
Short-Circuit
Protection
VREG
Internal Circuits
Ratiometric
Reference
Wake-Up
Logic and
Power Control
–
RXD
+
CS/LWAKE
TXD
~30
kΩ
OC
LBUS
FAULT/TXE
VSS
Thermal
and
Short-Circuit
Protection
© 2005-2012 Microchip Technology Inc.
Short-Circuit
Protection
DS22018F-page 3
MCP2021/2/1P/2P
NOTES:
DS22018F-page 4
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
1.0
DEVICE OVERVIEW
EQUATION 1-1:
The MCP2021/2/1P/2P provides a physical interface
between a microcontroller and a LIN half-duplex bus. It
is intended for automotive and industrial applications
with serial bus speeds up to 20 Kbaud.
The MCP2021/2/1P/2P provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. This device will
translate the CMOS/TTL logic levels to LIN-level logic,
and vice versa.
The LIN specification 2.0 requires that the transceiver(s) of all nodes in the system be connected via
the LIN pin, referenced to ground, and with a maximum
external termination resistance load of 510Ω from LIN
bus to battery supply. The 510Ω corresponds to 1 Master and 16 Slave nodes.
The MCP2021/2/1P/2P-500 provides a +5V, 50 mA,
regulated power output. The regulator uses an LDO
design, is short-circuit protected, and will turn the
regulator output off if it falls below 3.5V.
The MCP2021/2/1P/2P
shutdown protection.
also
includes
thermal-
The regulator is specifically designed to operate in the
automotive environment and will survive +43V load
dump transients, double-battery jumps, and reverse
battery connections when a reverse blocking diode is
used. The other members of the MCP2021/2/1P/2P330 family output +3.3V at 50 mA with a turn-off voltage
of 2.5V. (See Section 1.6 “Internal Voltage
Regulator”).
MCP2021/2 wakes from Power-Down mode on a
dominant level on LBUS. MCP2021P/2P wakes at a
transition from recessive level to dominant level on
LBUS.
1.1
1.1.1
RTP <= (VBBmin - 5.5) / 250 mA.
5.5V = VUVLO + 1.0V,
250 mA is the peak current at Power-On when
VBB = 5.5V
1.2
1.2.1
Internal Protection
ESD PROTECTION
For component-level ESD ratings, please refer to the
Section 2.1 “Absolute Maximum Ratings†”.
1.2.2
GROUND LOSS PROTECTION
The LIN Bus specification states that the LIN pin must
transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces
the LIN line to a hi-impedance level.
1.2.3
THERMAL PROTECTION
The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and
voltage regulator if it detects a thermal overload.
There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions:
• Voltage regulator overload
• LIN bus output overload
• Increase in die temperature due to increase in
environmental temperature
Driving the TXD and checking the RXD pin makes it
possible to determine whether there is a bus contention
(i.e., Rx = low, Tx = high) or a thermal overload condition (i.e., Rx = high, Tx = low).
Optional External Protection
REVERSE BATTERY PROTECTION
An external reverse-battery-blocking diode should be
used to provide polarity protection (see Figure 1-6).
1.1.2
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
An external 43V transient suppressor (TVS) diode,
between VBB and ground, with a 50Ω transient protection resistor (RTP) in series with the battery supply and
the VBB pin protect the device from power transients
(see Figure 1-6) and ESD events. While this protection
is optional, it is considered good engineering practice.
The resistor value is chosen according to Equation 1-1.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 5
MCP2021/2/1P/2P
LIN Bus
Overload
to VBB
Output
Overload
Voltage
Regulator
Shutdown
Operation
Mode
Temperature <SHUTDOWNTEMP
FIGURE 1-1:
1.3
Modes of Operation
POWER-ON RESET MODE
Upon application of VBB, the device enters Power-on
Reset mode (POR). During this mode, the part maintains the digital section in a Reset mode and waits until
the voltage on pin VBB rises above the “ON” threshold
(Typ. 5.75V) to enter to the Ready mode. If during the
operation, the voltage on pin VBB falls below the “OFF”
threshold (Typ. 4.25V), the part comes back to the POR
mode.
1.3.2
POWER-DOWN MODE
In the Power-Down mode, the transmitter and the
voltage regulator are off. Only the receiver wake-up
from LIN bus section, and the CS/LWAKE pin wake-up
circuits are in operation. This is the lowest power mode.
If pin CS/LWAKE goes to a high level during PowerDown mode, the device immediately enters Ready
mode and enables the voltage regulator; and after the
output has stabilized (approximately 0.3 ms to 1.2 ms),
the device goes to Operation mode or Transmitter-Off
mode (see Figure 1-2 for MCP2021/2 and Figure 1-3
for MCP2021P/2P).
Note:
Temperature <SHUTDOWNTEMP
Thermal Shutdown State Diagrams.
For an overview of all operational modes, please refer
to Table 1-1.
1.3.1
Transmitter
Shutdown
The above time interval <1.2 ms assumes
12V VBB input and no thermal shutdown
event.
LIN bus activity will also change the device from
Power-Down mode to Ready mode. MCP2021/2
wakes up on dominant level of LIN bus, and
MCP2021P/2P on a falling edge that follows a dominant level lasting 20 µs of time.
The Power-Down mode can be reached through either
Operation mode or Transmitter-Off mode.
1.3.3
READY MODE
Upon entering Ready mode, the voltage regulator and
receiver-threshold-detect circuit are powered up. The
transmitter remains in off state. The device is ready to
receive data as soon as the regulator is stabilized, but
not to transmit. If a microcontroller is being driven by
the voltage regulator output, it will go through a POR
and initialization sequence. The LIN pin is in the recessive state for MCP2021/2 and in floating state for
MCP2021P/2P.
The device will stay in Ready mode until the output of
the voltage regulator has stabilized and the CS/LWAKE
pin is true (‘1’). After VREG is stable and CS/LWAKE is
high, MCP2021/2 will enter Operation mode; and
MCP2021P/2P will enter either Operation mode or
Transmitter-Off mode, depending on the level of the
FAULT/TXE pin (refer to Figure 1-3).
1.3.4
OPERATION MODE
In this mode, all internal modules are operational.
The device will go into the Power-Down mode on the
falling edge of CS/LWAKE.
For the MCP2021P/2P devices, the pull-up resistor is
switched on only in this mode.
DS22018F-page 6
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
1.3.5
TRANSMITTER-OFF MODE
Whenever the FAULT/TXE signal is low, or permanent
dominant on TXD/LBUS is detected, the LBUS
transmitter is off.
The transmitter may be re-enabled whenever the
FAULT/TXE signal returns high, either by removing the
internal fault condition or when the CPU returning the
FAULT/TXE high. The transmitter will not be enabled if
the FAULT/TXE pin is brought high when the internal
fault is still present.
If TX-OFF mode is caused by TXD/LBUS permanent
dominant level, the transmitter can recover when the
permanent dominant status disappears.
The transmitter is also turned off whenever the voltage
regulator is unstable or recovering from a fault. This
prevents unwanted disruption of the bus during times of
uncertain operation.
1.3.6
WAKE-UP
The Wake-Up sub-module observes the LBUS in order
to detect bus activity. Bus activity is detected when the
voltage on the LBUS stays below a threshold of approximately 0.4VBB for at least a typical duration of 20 µs.
The MCP2021/2 device is level sensitive to LBUS. Dominant level longer than 20 µs will cause the device to
leave the Power-Down mode. The MCP2021P/2P
device is falling-edge sensitive to LBUS. Only the LBUS
transition from recessive to dominant followed by at
least 20 µs dominant level can wake up the device.
Putting CS/LWAKE to high level also wakes up the
device. Refer to Figure 1-2 and Figure 1-3.
1.3.7
DIFFERENCE DETAILS BETWEEN
MCP2021/2 AND MCP2021P/2P
The MCP202xP is a minor variation of the MCP202x
device that adds improved state machine control as
well as the ability to disconnect the internal 30kΩ pullup between LIN and VBB in all modes except normal
operation. These changes allow the system designer
to better handle fault conditions and reduce the overall
system current consumption. The differences between
the two device versions are as follows:
1.
Because of this, if the LIN bus becomes permanently shorted, it becomes impossible to place
the MCP202x in a low power state.
3.
State Machine Options:
The MCP202xP device is able to enter Transmitter Off Mode from Ready Mode without transitioning through Operation Mode. The
MCP202x device must enter Operation Mode
from Ready Mode. (See State Machine Diagrams, Figure 1-2 and Figure 1-3 for details).
This capability allows the system designer to
monitor the bus in Ready Mode to determine if
the system should transition to normal operation
and connect the internal pull-up or if Ready
Mode was reached due to an invalid condition.
In the case of an invalid condition, the
MCP202xP device can be placed into Power
Down mode without connecting the internal pullup and waking other nodes on the LIN Bus network.
Note:
To enter Transmitter Off, the system must
set TXE ‘low’ before pulling CS high (see
Figure 1-5). Otherwise, if CS is pulled high
first, the MCP202xP will enter Operation
Mode due to the internal pull-up on TXE.
To properly take advantage of the device differences
will require the system designer to implement some
microcontroller code to the power-up routine. This code
will monitor the status of the LIN bus to determine how
the dominant signal should be responded to. It will also
determine if the local LIN node needs to respond or can
‘Listen Only’. If the local LIN node does not need to
respond, it can enter Transmitter Off Mode, disconnecting the 30kΩ pull-up, reducing module current while still
maintaining the ability to properly receive all valid LIN
messages.
Switchable LIN-VBB Pull-Up Resistor:
On the MCP202xP device, the internal 30kΩ
pull-up resistor is disconnected in all modes
except Operation Mode. On the MCP202x
device, this pull-up resistor is always connected.
(See the MCP2021/2 Block Diagram and the
MCP2021P/2P Block Diagram for details.)
2.
Power Down Wake-up on LIN Traffic:
The MCP202xP device requires a LIN falling
edge to generate a valid Wake condition due to
bus traffic. The MCP202x device will generate a
Wake anytime LIN is at a valid dominant level.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 7
MCP2021/2/1P/2P
Power-Down
TX: OFF
RX: OFF
VREG: OFF
CS/LWAKE=0
CS/LWAKE=0
Operation
TX: ON
RX: ON
VREG: ON
FAULT/TXE=0
Or Faults*
CS/LWAKE=1
or dominant level on LBUS
CS/LWAKE=1&
VREG_OK=1
FAULT/TXE=1
&No Faults*
Ready
POR
TX: OFF
RX: ON
VREG: ON
Transmitter Off
TX: OFF
RX: ON
VREG: ON
VBAT>5.75V
TX: OFF
RX: OFF
VREG: OFF
Start
*Fault: thermal shutdown and TXD/LBUS permanent dominant
FIGURE 1-2:
Note:
MCP2021/2 Operational Modes State Diagrams.
While the device is in shutdown, TXD should not be actively driven high or it may power internal logic
through the ESD diodes and may damage the device.
Power-Down
TX: OFF
RX: OFF
VREG: OFF
CS/LWAKE=0
CS/LWAKE=0
Operation
TX: ON
RX: ON
VREG: ON
FAULT/TXE=0
Or Faults*
FAULT/TXE=1
&No Faults*
CS/LWAKE=1
or Falling edge on LBUS
CS/LWAKE=1&
VREG_OK=1&
FAULT/TXE=1
Ready
TX: OFF
RX: ON
VREG: ON
Transmitter Off
TX: OFF
RX: ON
VREG: ON
CS=1&VREG_OK=1
&FAULT/TXE=0
POR
VBAT>5.75V
TX: OFF
RX: OFF
VREG: OFF
Start
*Fault: thermal shutdown and TXD/LBUS permanent dominant
FIGURE 1-3:
DS22018F-page 8
MCP2021P/2P Operational Modes State Diagrams.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
CS_LWAKE
0
VREG
nFAULT_TXE
LBUS
0
Sleep
State
FIGURE 1-4:
Ready
MCP2021P/2P Wake-Up Due to Bus Disconnecting.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 9
MCP2021/2/1P/2P
tCSactive> = 2S
CS/LWAKE
VREG
FAULT/TXE = 1
Forced internally
FAULT/TXE = 0
Forced externally
FAULT/TXE
LBUS disconnected;
e.g., Master pull-up &
internal resistor off;
LBUS floating.
LBUS
STATE
Operation Mode
Transmitter-Off
Mode
Power-Down
Mode
Forced Power-Down Mode after BUS-OFF
instruction or a longer LIN-Bus inactivity
( > = 4 sec according to LIN specification)
FIGURE 1-5:
DS22018F-page 10
Forced Power-Down Mode Sequence for MCP2021P/2P.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
TABLE 1-1:
OVERVIEW OF OPERATIONAL MODES
Transmitter
Receiver
Voltage
Regulator
POR
OFF
OFF
OFF
Read VBB; if VBB>5.75V, enter Ready
mode
Ready
OFF
ON
ON
MCP2021/2:
Bus Off state
If CS/LWAKE is high level, then Operation
mode.
MCP2021P/2P:
If CS/LWAKE is high level and FAULT/TXE
is high level, then Operation mode.
If CS/LWAKE is high level and FAULT/TXE
is low level, then TXOFF mode.
Operation
ON
ON
ON
If CS/LWAKE is low level, then PowerDown mode.
If FAULT/TXE is low level or TXD/LBUS
permanent dominant is detected, then
Transmitter-Off mode.
Normal
Operation
mode
Power-Down
OFF
Activity
Detect
OFF
On LIN bus falling, go to Ready mode. On
CS/LWAKE high level, go through Ready
mode; then, to either operation or
Transmitter-Off mode (refer to Figure 1-2
and Figure 1-3).
Low Power
mode
Transmitter-Off
OFF
ON
ON
If CS/LWAKE is low level, then PowerDown mode.
If FAULT/TXE is high, then Operation
mode.
State
© 2005-2012 Microchip Technology Inc.
Operation
Comments
DS22018F-page 11
MCP2021/2/1P/2P
1.4
Pin Descriptions
TABLE 1-1:
PINOUT DESCRIPTIONS
Devices
Function
Pin
Name
8-Pin
DFN,
PDIP,
SOIC
14-Pin
PDIP,
SOIC,
TSSOP
Pin
Type
VREG
3
3
O
Power Output
VSS
5
11
P
Ground
VBB
7
13
P
Battery Supply
TXD
4
4
I
Transmit Data Input (TTL)
RXD
1
1
O
Receive Data Output (CMOS)
LBUS
6
12
I/O
LIN bus (bidirectional)
CS/LWAKE
2
2
TTL
Chip Select (TTL)
FAULT/TXE
8
14
OD
Fault Detect Output, Transmitter Enable (OD)
RESET
—
5
OD
RESET signal Output (OD)
Normal Operation
Legend: O = Output, P = Power, I = Input, TTL = TTL input buffer, OD = Open-Drain output
Ground pin.
The internal LIN receiver observes the activities on the
LIN bus, and generates output signal RXD that follows
the state of the LBUS. A 1st degree with 1 µS time constant (160KhZ), low-pass input filter is placed to
maintain EMI immunity.
1.4.3
1.4.7
1.4.1
POWER OUTPUT (VREG)
Positive Supply Voltage Regulator Output pin.
1.4.2
GROUND (VSS)
BATTERY (VBB)
Battery Positive Supply Voltage pin. This pin is also the
input for the internal voltage regulator.
1.4.4
TRANSMIT DATA INPUT (TXD)
The Transmit Data Input pin has an internal pull-up to
VREG. The LIN pin is low (dominant) when TXD is low,
and high (recessive) when TXD is high.
For extra bus security, TXD is internally forced to ‘1’
when VREG is less than 1.8V (typ.).
If the thermal protection detects an over-temperature
condition while the signal TXD is low, the transmitter is
shut down. The recovery from the thermal shutdown is
equal to adequate cooling time.
1.4.5
RECEIVE DATA OUTPUT (RXD)
The Receive Data Output pin is a standard CMOS
output and follows the state of the LIN pin.
1.4.6
LIN BUS
The bidirectional LIN bus Interface pin is the driver unit
for the LIN pin and is controlled by the signal TXD. LIN
has an open collector output with a current limitation.
To reduce EMI, the edges during the signal changes
are slope-controlled. To further reduce radiated emissions, the LBUS pin has corner-rounding control for both
falling and rising edges.
DS22018F-page 12
CS/LWAKE
Chip Select Input pin. A internal pull-down resistor will
keep the CS/LWAKE pin low. This is done to ensure
that no disruptive data will be present on the bus while
the microcontroller is executing a POR and I/O initialization sequence. The pin must see a high level to
activate the transmitter.
If CS/LWAKE= ‘0’ when the VBB supply is turned on,
the device stays in Ready mode (Low-Power mode). In
Ready mode, both the receiver and the voltage
regulator are on and the LIN transmitter driver is off.
If CS/LWAKE = ‘1’ when the VBB supply is turned on,
the device will proceed to either Operation or Transmitter-Off mode (refer to Figure 1-2 and Figure 1-3) after
the VREG output has stabilized.
This pin may also be used as a local wake-up input
(see Figure 1-6). In this implementation, the microcontroller will set the I/O pin that controls the CS/LWAKE
as an high-impedance input. The internal pull-down
resistor will keep the input low. An external switch, or
other source, can then wake up the transceiver and the
microcontroller.
Note:
CS/LWAKE should not be tied directly to
VREG as this could force the MCP202x into
Operation
mode
before
the
microcontroller is initialized.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
1.4.8
FAULT/TXE
Fault Detect Output and Transmitter Enable Input
bidirectional pin.
This pin has an internal
approximately 750 kΩ.
TABLE 1-2:
resistor
of
Note 1: The FAULT/TXE pin is true (0) whenever
the internal circuits have detected a short
or thermal excursion and have disabled
the LBUS output driver.
This pin is an open-drain output. Its state is defined as
shown in Table 1-2. The transmitter driver is disabled
whenever this pin is low (‘0’), either from an internal
fault condition or by external drive. This allows the
transmitter to be placed in an off state and still allow the
voltage regulator to operate. Refer to Table 1-1.
The FAULT/TXE also signals a mismatch between the
TXD input and the LBUS level. This can be used to
detect a bus contention. Since the bus exhibits a
propagation delay, the sampling of the internal
compare is debounced to eliminate false faults.
pull-up
2: FAULT/TXE is true (0) when VREG not OK
and has disabled the LBUS output driver.
The FAULT/TXE pin sampled at a rate faster than every
10 µs.
FAULT/TXE TRUTH TABLE
FAULT/TXE
TXD
In
RXD
Out
LINBUS
I/O
Thermal
Override
L
H
VBB
H
H
L
Definition
External
Input
Driven
Output
OFF
H
L
FAULT, TXD driven low, LINBUS shorted to
VBB (Note 1)
VBB
OFF
H
H
OK
L
GND
OFF
H
H
OK
H
L
GND
OFF
H
H
OK, data is being received from the LINBUS
x
x
VBB
ON
H
L
FAULT, transceiver in thermal shutdown
x
x
VBB
x
L
x
NO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
Legend: x = don’t care
Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.
1.4.9
RESET
RESET is an open-drain output pin. This pin reflects an
internal signal that tracks the internal system voltage
has reached a valid, stable level.
As long as the internal voltage is valid, this pin will keep
high impedance. When the system voltage drops below
the minimum required, the voltage regulator will shut
down and immediately convert the RESET output to
short to GND. A pull-up resistor is needed to change
the output to high/low voltage. When connected to a
micro-controller input, this can provide a warning that
the voltage regulator is shutting down (see Figure 1-2).
Alternately, it can act as an external brown-out by connecting the RESET output to MCLR (see Figure 1-2). In
addition to monitoring the internal voltage, RESET is
asserted immediately upon entering the Power-Down
mode.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 13
MCP2021/2/1P/2P
1.5
Typical Applications
+12
+12
RTP(5)
WAKE-UP
43V(5)
CF
CG
220 kΩ
VDD
VREG
TXD
TXD
Master Node Only
+12
VBB
1 kΩ
RXD
RXD
I/O
LIN Bus
LBUS
27V
CS/LWAKE
(3)
(4)
FAULT/TXE
I/O
100 pF
VSS
Note 1: See Figure 2-3 for correct capacity and ESR for stable operation..
2: CF is the filter capacitor for the external voltage supply.
3: This diode is only needed if CS/LWAKE is connected to a 12V supply.
4: Transient suppressor diode. Vclamp L = 43V.
5: These components are required for additional load dump protection above 43V.
FIGURE 1-6:
DS22018F-page 14
Typical MCP2021/MCP2021P Application.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
+12
+12
RTP(5)
WAKE-UP
43V(5)
CF
CG
220 kΩ
VDD
VREG
TXD
TXD
Master Node Only
+12
VBB
1 kΩ
RXD
I/O
27V (4)
CS/LWAKE
(3)
LIN Bus
LBUS
RXD
FAULT/TXE
I/O
INT or MCLR
RESET
VSS
100 pF
VDD (6)
Note 1: See Figure 2-3 for correct capacity and ESR for stable operation.
2: CF is the filter capacitor for the external voltage supply.
3: This diode is only needed if CS/LWAKE is connected to a 12V supply.
4: Transient suppressor diode. Vclamp L = 43V.
5: These components are required for additional load dump protection above 43V.
6: Required if CPU does not have internal pull-up.
FIGURE 1-7:
Typical MCP2022/MCP2022P Application.
40m
+ Return
LIN bus
1 kΩ
VBB
LIN bus
MCP202X
LIN bus
MCP202X
Slave 1
µC
LIN bus
MCP202X
LIN bus
MCP202X
Slave 2
µC
Slave n <16
µC
Master
µC
FIGURE 1-8:
Typical LIN Network Configuration.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 15
MCP2021/2/1P/2P
1.6
1.6.1
Internal Voltage Regulator
5.0V REGULATOR
The MCP2021 has a low-drop-out voltage, positive regulator capable of supplying 5.00 VDC ±3% at up to
50 mA of load current over the entire operating temperature range of -40°C to +125°C. With a load current of
50 mA, the minimum input to output voltage differential
required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 100 µA
with a full 50 mA load current when the input to output
voltage differential is greater than +3.00V.
When the input voltage (VBB) drops below the differential needed to provide stable regulation, the output
VREG) will track the input down to approximately
+4.25V. The regulator will turn off the output at this
point. This will allow PIC® microcontrollers with internal
POR circuits to generate a clean arming of the POR trip
point. The regulator output will stay off until VBB is
above +5.75 VDC.
In the start phase, the device must detect at least 5.75V
to initiate operation during power up. In the PowerDown mode, the VBB monitor will be turned off.
Note:
The regulator requires an external output bypass
capacitor for stability. See Figure 2-3 for correct
capacity and ESR for stable operation.
Designed for automotive applications, the regulator will
protect itself from double-battery jumps and up to +43V
load dump transients. The voltage regulator has both
short-circuit and thermal-shut-down protection built in.
Regarding the correlation between VBB, VREG and IDD,
please refer to Figure 1-10 throughFigure 1-12. When
the input voltage (VBB) drops below the differential
needed to provide stable regulation, the output VREG
will track the input down to approximately 3.5V, at
which point the regulator will turn off. This will allow
microcontrollers with internal POR circuits to generate
a clean arming of the POR trip point. The MCP2021 will
then monitor VBB and turn on the regulator when VBB
rises above 5.75, again.
The regulator has a thermal shutdown. If the thermal
protection circuit detects an overtemperature condition,
and the signals TXD and RXD are LOW, or TXD is HIGH,
the regulator will shut down. The recovery from the
thermal shutdown is equal to adequate cooling time.
Pass
Element
VREG
The regulator has an overload current
limiting of approximately 100 mA. During a
short circuit, the VREG is monitored. If
VREG is lower than 3.5V, the VREG will turn
off. After a recovery time of about three
milliseconds, the VREG will be checked
again. If there is no short circuit (VREG
>3.5V), the VREG will be switched back on.
VBB
Sampling
Network
Fast
Transient
Loop
Buffer
VSS
VREF
FIGURE 1-9:
DS22018F-page 16
Voltage Regulator Block Diagram.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
1.6.2
3.3V REGULATOR
A metal option provides for a alternate 3.30 VDC ±3%
at up to 50 mA of load current over the entire operating
temperature range of -40°C to +125°C. All
specifications given above for the 5.0V operation apply
except for any difference noted here.
The same input tracking of 4.25V applies the 3.3V
regulator.
Note:
The regulator has an overload current
limiting of approximately 100 mA. If VREG
is lower than 2.5V, the VREG will turn off.
VBB
V
8
6
4
2
0
t
VREG
V
5.0
3.5
3
0
t
(1)
Note 1:
2:
3:
4:
FIGURE 1-10:
(2)
(3)
Start-up, VBB < 5.75V, regulator off.
VBB > 5.75V, regulator on.
VBB ≤ 5.5V, regulator tracks VBB.
VBB < 4.25V, regulator will turn off.
Voltage Regulator Output on POR.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 17
MCP2021/2/1P/2P
VBB
V
12
8
6
4
3.5
2
0
t
VREG
V
5
4
3.5
3
0
t
(1)
Note 1:
2:
3:
4:
FIGURE 1-11:
DS22018F-page 18
(2) (3) (4)
Voltage regulator on.
VBB ≤ 5.5V, regulator tracks VBB until VBB < 4.25V.
VREG < 3.5V, regulator is off.
VBB > 5.75V, regulator on.
Voltage Regulator Output on Power Dip.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
IREG
mA
50
0
6
t
VREG
V
5.0
3.5
3
0
t
(1)
Note 1:
2:
FIGURE 1-12:
1.7
(2)
IREG less than 50 mA, regulator on.
After IREG exceeds IREGmax, voltage regulator output will be reduced until VREG off is reached.
Voltage Regulator Output on Overcurrent Situation.
ICSP™ Considerations
The following should be considered when the
MCP2021/2/1P/2P is connected to pins supporting
in-circuit programming:
• Power used for programming the microcontroller
can be supplied from the programmer or from the
MCP2021/2/1P/2P.
• The voltage on VREG should not exceed the
maximum output voltage of VREG.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 19
MCP2021/2/1P/2P
NOTES:
DS22018F-page 20
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
2.0
ELECTRICAL CHARACTERISTICS
2.1
Absolute Maximum Ratings†
VIN DC Voltage on RXD and TXD ........................................................................................................ -0.3 to VREG+0.3V
VIN DC Voltage on FAULT and RESET.........................................................................................................-0.3 to +5.5V
VIN DC Voltage on CS/LWAKE.......................................................................................................................-0.3 to +43V
VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43V
VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V
VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V
VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V
VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V
VBB Battery Voltage, continuous ....................................................................................................................-0.3 to +30V
VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V
VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +43V
ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA
ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150 pF) (Note 3) .............................................. minimum ±9 kV
ESD protection on LIN, VBB (Charge Device Model) (Note 2)..............................................................................±1500V
ESD protection on LIN, VBB (Human Body Model, 1 kOhm, 100 pF) (Note 4) ....................................................... ±8 kV
ESD protection on LIN, VBB (Machine Model) (Note 2) ..........................................................................................±800V
ESD protection on all other pins (Human Body Model) (Note 2) ............................................................................ > 4 kV
Maximum Junction Temperature ............................................................................................................................. 150°C
Storage Temperature .................................................................................................................................. -55 to +150°C
Note 1: ISO 7637/1 load dump compliant (t < 500 ms).
2: According to JESD22-A114-B.
3:
According to IBEE, without bus filter.
4: Limited by Test Equipment.
† NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 21
MCP2021/2/1P/2P
2.2
DC Specifications
DC Specifications
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
CLOADREG = 10 µF
Parameter
Sym
VBB Quiescent Operating
Current
IBBQ
Transmitter-off
Current
IBBTO
Min.
Typ.
Max.
Units
Conditions
115
210
µA
IOUT = 0 mA,
LBUS recessive
—
120
215
µA
VOUT = 3.3V
—
90
190
µA
With VREG on, transmitter
off, receiver on, FAULT/TXE
= VIL, CS = VIH
—
95
210
µA
VOUT = 3.3V
IBBPD
—
16
26
µA
With VREG powered-off,
receiver on and transmitter
off, FAULT/TXE = VIH,
TXD = VIH, CS = VIL)
IBBNOGND
-1
—
1
mA
VBB = 12V, GND to VBB,
VLIN = 0-18V
High Level Input Voltage
(TXD, FAULT/TXE)
VIH
2.0 or
(0.25VREG
+0.8)
—
VREG
+0.3
V
Low Level Input Voltage
(TXD, FAULT/TXE)
VIL
-0.3
—
0.15 VREG
V
High Level Input Current
(TXD, FAULT/TXE)
IIH
-2.5
—
—
µA
Input voltage = 0.8*VREG
Low Level Input Current
(TXD, FAULT/TXE)
IIL
-10
—
—
µA
Input voltage = 0.2*VREG
Pull-up Current on Input
(TXD)
IPUTXD
-3.0
—
—
µA
~800 kΩ internal pull-up to
VREG @ VIH = 0.7*VREG
High Level Input Voltage
(CS/LWAKE)
VIH
0.7VREG
—
VBB
V
Through a current-limiting
resistor
Low Level Input Voltage
(CS/LWAKE)
VIL
-0.3
—
0.3VREG
V
High Level Input Current
(CS/LWAKE)
IIH
—
—
7.0
µA
Input voltage = 0.8*VREG
Low Level Input Current
(CS/LWAKE)
IIL
—
—
3.0
µA
Input voltage = 0.2*VREG
IPDCS
—
—
6.0
µA
~1.3MΩ internal pull-down
to VSS @ VIH = 3.5V
Power
VBB
VBB Power-Down Current
VBB Current with VSS
Floating
Microcontroller Interface
Pull-down Current on
Input (CS/LWAKE)
Note 1:
2:
3:
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).
For design guidance only, not tested.
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
DS22018F-page 22
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
2.2
DC Specifications (Continued)
DC Specifications
Parameter
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
CLOADREG = 10 µF
Sym
Min.
Typ.
Max.
Units
Conditions
High Level Input Voltage
VIH(LBUS)
0.6 VBB
—
18
V
Recessive state
Low Level Input Voltage
VIL(LBUS)
-8
—
0.4 VBB
V
Dominant state
Bus Interface
VHYS
—
—
0.175 VBB
V
Low Level Output Current
IOL(LBUS)
40
—
200
mA
Output voltage = 0.1 VBB,
VBB = 12V
Pull-up Current on Input
IPU(LBUS)
5
—
180
µA
~30 kΩ internal pull-up
@ VIH (LBUS) = 0.7 VBB
ISC
50
—
200
mA
(Note 1)
VOH(LBUS)
0.8 VBB
—
VBB
V
Low Level Output Voltage
VOLLO
(LBUS)
—
—
0.2 VBB
V
Input Leakage Current (at
the receiver during
dominant bus level)
IBUS_PAS_DOM
-1
—
—
mA
Driver off,
VBUS = 0V,
VBAT = 12V
Leakage Current
(disconnected from
ground)
IBUS_NO_GND
-1
—
+1
mA
GNDDEVICE = VBAT,
0V < VBUS < 18V,
VBAT = 12V
IBUS
—
—
10
µA
VBAT = GND,
0 < VBUS < 18V,
TA = -40°C to +85°C
(Note 3)
50
µA
TA = +85°C to +125°C
VBUS_CNT = (VIL (LBUS) +
VIH (LBUS))/2
Input Hysteresis
Short Circuit Current
Limit
High Level Output
Voltage
Leakage Current
(disconnected from VBAT)
Receiver Center Voltage
Slave Termination
Note 1:
2:
3:
VBUS_CNT
0.475 VBB
0.5
VBB
0.525 VBB
V
Rslave
20
30
47
kΩ
VIH(LBUS) - VIL(LBUS)
VOH(LBUS) must be at least
0.8 VBB
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).
For design guidance only, not tested.
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 23
MCP2021/2/1P/2P
2.2
DC Specification (Continued)
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
CLOADREG = 10 µF
DC Specifications
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
VOUT
4.85
5.00
5.15
V
0 mA < IOUT < 50 mA,
ΔVOUT2
—
10
50
mV
5 mA < IOUT < 50 mA
refer to Section 1.6
“Internal Voltage
Regulator”
IVRQ
—
—
25
µA
IOUT = 0 mA, (Note 2)
Power Supply Ripple
Reject
PSRR
—
—
50
dB
1 VPP @10-20 kHz
CLOAD = 10 µf,
ILOAD = 50 mA
Output Noise Voltage
eN
—
—
100
Voltage Regulator - 5.0V
Output Voltage
Load Regulation
Quiescent Current
µVRMS 10 Hz – 40 MHz
CFILTER = 10 µf,
CBP = 0.1 µf, CLOAD 10 µf,
ILOAD = 50 mA
Shutdown Voltage
VSD
3.5
—
4.0
V
Input Voltage to Maintain
Regulation
VBB
6.0
—
18.0
V
Input Voltage to Turn Off
Output
VOFF
4.0
—
4.5
V
Input Voltage to Turn On
Output
VON
5.5
—
6.0
V
Note 1:
2:
3:
See Figure 1-8
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).
For design guidance only, not tested.
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
60
Voltage Regulator Load (mA)
12V DFN
50
12V SOIC
18V DFN
40
18V SOIC
30
20
10
-40
-34
-28
-22
-16
-10
-4
2
8
14
20
26
32
38
44
50
56
62
68
74
80
86
92
98
104
110
116
122
0
Temperature (°C)
FIGURE 2-1:
DS22018F-page 24
MCP2021-500 Safe Operating Range.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
2.2
DC Specification (Continued)
Electrical Characteristics:
Unless otherwise indicated, all limits are specified for:
VBB = 6.0V to 18.0V
TA = -40°C to +125°C
CLOADREG = 10 µF
DC Specifications
Parameter
Sym
Min.
Typ.
Max.
Units
Conditions
Output Voltage
VOUT
3.20
3.30
3.40
V
Line Regulation
ΔVOUT1
—
10
50
mV
IOUT = 1 mA,
6.0V < VBB < 18V
Load Regulation
ΔVOUT2
—
10
50
mV
5 mA < IOUT < 50 mA
Refer to Section 1.6
“Internal Voltage
Regulator”
Voltage Regulator - 3.3V
0 mA < IOUT < 50 mA
IVRQ
—
—
25
µA
IOUT = 0 mA, (Note 2)
Power Supply Ripple
Reject
PSRR
—
—
50
dB
1 VPP @10-20 kHz
CLOAD = 10 µf,
ILOAD = 50 mA
Output Noise Voltage
eN
—
—
100
Shutdown Voltage
VSD
2.5
—
2.7
V
Input Voltage to Maintain
Regulation
VBB
6.0
—
18.0
V
Input Voltage to Turn Off
Output
VOFF
4.0
—
4.5
V
Input Voltage to Turn On
Output
VON
5.5
—
6.0
V
Quiescent Current
Note 1:
2:
3:
µVRMS 10 Hz – 40 MHz
/√Hz CFILTER = 10 µf, CBP =
0.1 µf CLOAD = 10 µf,
ILOAD = 50 mA
See Figure 1-8
Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB).
For design guidance only, not tested.
Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
Voltage Regulator Load (mA)
60
12V DFN
50
12V SOIC
18V DFN
40
18V SOIC
30
20
10
-40
-34
-28
-22
-16
-10
-4
2
8
14
20
26
32
38
44
50
56
62
68
74
80
86
92
98
104
110
116
122
0
Temperature (°C)
FIGURE 2-2:
MCP2021-330 Safe Operating Range.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 25
MCP2021/2/1P/2P
ESR Curves
10
Instable
Stable only
ESR [ohm]
1
with Tantalum or
Electrolytic cap.
Stable with
Tantalum,
Electrolytic and
Ceramic cap.
Instable
0.1
0.01
Instable
0.001
0.1
1
10
100
1000
Load Capacitor [uF]
FIGURE 2-3:
DS22018F-page 26
ESR Curves for Load Capacitor Selection.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
2.3
AC Specification
AC CHARACTERISTICS
Parameter
VBB = 6.0V to 18.0V; TA = -40°C to +125°C
Sym
Min.
Typ.
Max.
Units
Test Conditions
Bus Interface - Constant Slope Time Parameters
tSLOPE
3.5
—
22.5
µs
7.3V <= VBB <= 18V
Propagation Delay of
Transmitter
tTRANSPD
—
—
4.0
µs
tTRANSPD = max (tTRANSPDR or
tTRANSPDF)
Propagation Delay of
Receiver
tRECPD
—
—
6.0
µs
tRECPD = max (tRECPDR or
tRECPDF)
Symmetry of Propagation
Delay of Receiver rising
edge w.r.t. falling edge
tRECSYM
-2.0
—
2.0
µs
tRECSYM = max (tRECPDF tRECPDR)
Symmetry of Propagation
Delay of Transmitter rising
edge w.r.t. falling edge
tTRANSSYM
-2.0
—
2.0
µs
tTRANSSYM = max (tTRANSPDF tTRANSPDR)
tFAULT
—
—
32.5
µs
tFAULT = max (tTRANSPD +
tSLOPE + tRECPD)
Duty Cycle 1 @20.0 kbit/sec
39.6
—
—
%tBIT
CBUS;RBUS conditions:
1 nF; 1 kΩ | 6.8 nF; 660Ω |
10 nF; 500Ω
THREC(MAX) = 0.744 x VBB,
THDOM(MAX) = 0.581 x VBB,
VBB =7.0V - 18V; tBIT = 50 µs.
D1 = tBUS_REC(MIN) / 2 x tBIT)
Duty Cycle 2 @20.0 kbit/sec
—
—
58.1
%tBIT
CBUS;RBUS conditions:
1 nF; 1 kΩ | 6.8 nF; 660Ω |
10 nF; 500Ω
THREC(MAX) = 0.284 x VBB,
THDOM(MAX) = 0.422 x VBB,
VBB =7.6V - 18V; tBIT = 50 µs.
D2 = tBUS_REC(MAX) / 2 x tBIT)
Duty Cycle 3 @10.4 kbit/sec
41.7
—
—
%tBIT
CBUS;RBUS conditions:
1 nF; 1 kΩ | 6.8 nF; 660Ω |
10 nF; 500Ω
THREC(MAX) = 0.778 x VBB,
THDOM(MAX) = 0.616 x VBB,
VBB =7.0V - 18V; tBIT = 96 µs.
D3 = tBUS_REC(MIN) / 2 x tBIT)
Duty Cycle 4 @10.4 kbit/sec
—
—
59.0
%tBIT
CBUS;RBUS conditions:
1 nF; 1 kΩ | 6.8 nF; 660Ω |
10 nF; 500Ω
THREC(MAX) = 0.251 x VBB,
THDOM(MAX) = 0.389 x VBB,
VBB =7.6V - 18V; tBIT = 96 µs.
D4 = tBUS_REC(MAX) / 2 x tBIT)
Slope rising and falling
edges
Time to sample of FAULT/
TXE for bus conflict reporting
© 2005-2012 Microchip Technology Inc.
DS22018F-page 27
MCP2021/2/1P/2P
2.3
AC Specification (Continued)
AC CHARACTERISTICS
VBB = 6.0V to 18.0V; TA = -40°C to +125°C
Parameter
Sym
Min.
Typ.
Max.
Units
Test Conditions
Voltage Regulator
Bus Activity Debounce Time
tBDB
5
10
20
µs
Bus debounce time
tBACTVE
100
250
500
µs
After bus debounce time
Voltage Regulator Enabled
to Ready
tVEVR
—
—
1200
µs
(Note 1)
Chip Select to Operation
Ready
tCSOR
—
—
500
µs
(Note 1)
Bus Activity to Voltage
Regulator Enabled
Chip Select to Power-Down
tCSPD
—
—
80
µs
Short-Circuit to Shut-Down
tSHUTDOWN
20
—
100
µs
VREG OK Detect to RESET
Inactive
tRPU
—
—
10.0
µs
VREG OK Detect to RESET
Active
tRPD
—
—
10.0
µs
RESET Timing
Note 1:
2.4
Time depends on external capacitance and load.
Thermal Specifications
THERMAL CHARACTERISTICS
Parameter
Symbol
Typ
Max
Units
Recovery Temperature
θRECOVERY
+140
—
°C
Shutdown Temperature
θSHUTDOWN
+150
—
°C
tTHERM
1.5
5.0
ms
Short Circuit Recovery Time
Test Conditions
Thermal Package Resistances
Thermal Resistance, 8L-DFN
θJA
35.7
—
°C/W
Thermal Resistance, 8L-PDIP
θJA
89.3
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
149.5
—
°C/W
Thermal Resistance, 14L-PDIP
θJA
70
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
100
—
°C/W
Note 1:
The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. The maximum
allowable power dissipation at an ambient temperature is PD = (TJMAX - TA) ΘJA. If this dissipation is
exceeded, the die temperature will rise above 150°C and the MCP2021 will go into thermal shutdown.
DS22018F-page 28
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
2.5
Timing Diagrams and Specifications
TXD
50%
50%
LBUS
.95VLBUS
.50VBB
.0.4VBB
TTRANSPDR
TTRANSPDF
TRECPDF
0.0V
TRECPDR
RXD
50%
Internal TXD/RXD
Compare
Match
50%
Match
Match
Match
Match
FAULT Sampling
TFAULT
TFAULT
FAULT/TXE Output
FIGURE 2-4:
Stable
Hold
Value
Stable
Hold
Value
Stable
Bus Timing Diagram.
CS/LWAKE
TCSOR
VREG
VOUT
TCSPD
FIGURE 2-5:
Regulator CS/LWAKE Timing Diagram.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 29
MCP2021/2/1P/2P
TVEVR
LBUS
0.4VBB
TBDB + TBACTVE
VREG
VOUT
FIGURE 2-6:
Regulator BUS WAKE Timing Diagram.
6.0V
5.0V
VBB
5.0V
4.0V
3.5V
VREG
TRPD
TRPD
RESET
TRPU
FIGURE 2-7:
DS22018F-page 30
TRPU
RESET Timing Diagram.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
CS/LWAKE
TCSOR
VREG
VOUT
TRPU
TCSPD
RESET
FIGURE 2-8:
CS/LWAKE to RESET Timing Diagram.
0.2
Ibbq mA
0.15
0.1
Vbb = 6V
Vbb = 7.3V
0.05
Vbb = 12V
Vbb = 14.4V
Vbb = 18V
0
-40C
25C
85C
125C
Temperature (°C)
FIGURE 2-9:
Typical IBBQ vs. Temperature.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 31
mA
MCP2021/2/1P/2P
0.18
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
-40C
Vbb = 6V
Vbb = 7.3V
Vbb = 12V
Vbb = 14.4V
Vbb = 18V
25C
85C
125C
Temperature (°C)
FIGURE 2-10:
Typical IBBTO vs Temperature.
0.025
Ipd (mA)
0.02
0.015
0.01
Vbb = 6V
Vbb = 7.3V
Vbb = 12V
0.005
Vbb = 14.4V
Vbb = 18V
0
-40C
25C
85C
125C
Temperature (°C)
FIGURE 2-11:
DS22018F-page 32
Typical IBBPD vs. Temperature.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
3.0
PACKAGING INFORMATION
3.1
Package Marking Information
8-Lead DFN (4x4x0.9 mm)
XXXXXX
XXXXXX
YYWW
NNN
Example
MCP2021
MCP2021P
2021500
2021P50
PIN 1
202150
E/MD 3
1033
256
PIN 1
8-Lead DFN-S (6x5x0.9 mm)
Example
MCP2021
202150
NNN
PIN 1
2021500
E/MF 3
1033
256
PIN 1
8-Lead PDIP (300 mil)
Example
XXXXXXXX
XXXXXNNN
2021500
E/P 3 256
1033
YYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
MCP2021
MCP2021P
2021500
2021P500
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 33
MCP2021/2/1P/2P
3.1
Package Marking Information (Continued)
8-Lead SOIC (3.90 mm)
NNN
Example
MCP2021
MCP2021P
2021500E
2021P50E
14-Lead PDIP (300 mil)
MCP2022P
MCP2022-500 MCP2022P-500
14-Lead SOIC (3.90 mm)
e3
*
Note:
DS22018F-page 34
256
Example
MCP2022
Legend: XX...X
Y
YY
WW
NNN
2021500E
SN 3 1033
MCP2022-500
E/P 3
1033256
Example
MCP2022
MCP2022P
MCP2022-500
2022P-500
MCP2022-500
E/SL 3
1033256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
3.1
Package Marking Information (Continued)
14-Lead TSSOP (4.4 mm)
Example
XXXXXXXX
YYWW
NNN
2022500E
1033
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
MCP2022
MCP2022P
2022500E
2022P50E
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 35
MCP2021/2/1P/2P
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
b
N
N
L
E
E2
K
EXPOSED
PAD
2
2
1
NOTE 1
1
NOTE 1
D2
TOP VIEW
BOTTOM VIEW
A3
A
A1
NOTE 2
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
0.80
0.80 BSC
0.90
1.00
Standoff
A1
0.00
0.02
0.05
Contact Thickness
A3
0.20 REF
Overall Length
D
Exposed Pad Width
E2
Overall Width
E
Exposed Pad Length
D2
0.00
3.00
3.60
b
0.25
0.30
0.35
Contact Length
L
0.30
0.55
0.65
Contact-to-Exposed Pad
K
0.20
–
–
Contact Width
4.00 BSC
0.00
2.20
2.80
4.00 BSC
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-131C
DS22018F-page 36
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
%
D
!"#$
! "# $% &"' "" ($ ) %
*++&&&! !+ $
© 2005-2012 Microchip Technology Inc.
DS22018F-page 37
MCP2021/2/1P/2P
8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
e
D
L
b
N
N
K
E
E2
EXPOSED PAD
NOTE 1
1
2
2
NOTE 1
1
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
0.80
1.27 BSC
0.85
1.00
Standoff
A1
0.00
0.01
0.05
Contact Thickness
A3
0.20 REF
Overall Length
D
5.00 BSC
Overall Width
E
Exposed Pad Length
D2
3.90
4.00
4.10
Exposed Pad Width
E2
2.20
2.30
2.40
6.00 BSC
Contact Width
b
0.35
0.40
0.48
Contact Length
L
0.50
0.60
0.75
Contact-to-Exposed Pad
K
0.20
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
–
Microchip Technology Drawing C04-122B
DS22018F-page 38
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
%
! "# $% &"' "" ($ ) %
*++&&&! !+ $
© 2005-2012 Microchip Technology Inc.
DS22018F-page 39
MCP2021/2/1P/2P
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
e
eB
b1
b
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
8
Pitch
e
Top to Seating Plane
A
–
–
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
D
.348
.365
.400
Tip to Seating Plane
L
.115
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.060
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-018B
DS22018F-page 40
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
A2
A
c
φ
L
A1
L1
Units
Dimension Limits
Number of Pins
β
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
1.25
–
–
Standoff §
A1
0.10
–
0.25
Overall Width
E
Molded Package Width
E1
3.90 BSC
Overall Length
D
4.90 BSC
1.75
6.00 BSC
Chamfer (optional)
h
0.25
–
0.50
Foot Length
L
0.40
–
1.27
Footprint
L1
1.04 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.17
–
0.25
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-057B
© 2005-2012 Microchip Technology Inc.
DS22018F-page 41
MCP2021/2/1P/2P
%
& ' (&))*+
!"#&',-$
! "# $% &"' "" ($ ) %
*++&&&! !+ $
DS22018F-page 42
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
3
2
D
E
A2
A
L
A1
c
b1
b
e
eB
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
14
Pitch
e
Top to Seating Plane
A
–
–
.210
Molded Package Thickness
A2
.115
.130
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.325
Molded Package Width
E1
.240
.250
.280
Overall Length
D
.735
.750
.775
Tip to Seating Plane
L
.115
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.045
.060
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-005B
© 2005-2012 Microchip Technology Inc.
DS22018F-page 43
MCP2021/2/1P/2P
14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
h
b
A
A2
c
φ
L
A1
β
L1
Units
Dimension Limits
Number of Pins
α
h
MILLIMETERS
MIN
N
NOM
MAX
14
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
1.25
–
–
Standoff §
A1
0.10
–
0.25
1.75
Overall Width
E
Molded Package Width
E1
6.00 BSC
3.90 BSC
Overall Length
D
8.65 BSC
Chamfer (optional)
h
0.25
–
0.50
Foot Length
L
0.40
–
1.27
Footprint
L1
1.04 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.17
–
0.25
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-065B
DS22018F-page 44
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
%
! "# $% &"' "" ($ ) %
*++&&&! !+ $
© 2005-2012 Microchip Technology Inc.
DS22018F-page 45
MCP2021/2/1P/2P
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1 2
e
b
A2
A
c
A1
φ
Units
Dimension Limits
Number of Pins
L
L1
MILLIMETERS
MIN
N
NOM
MAX
14
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.80
1.00
1.05
Standoff
A1
0.05
–
0.15
1.20
Overall Width
E
Molded Package Width
E1
4.30
6.40 BSC
4.40
Molded Package Length
D
4.90
5.00
5.10
Foot Length
L
0.45
0.60
0.75
Footprint
L1
4.50
1.00 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.19
–
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087B
DS22018F-page 46
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
APPENDIX A:
REVISION HISTORY
Revision F (January 2012)
The following modifications were made to this data
sheet:
Added the MCP2021P and MCP2022P options
and related information throughout the
document.
Revision E (February 2009)
The following is the list of modifications.
1.
2.
3.
4.
5.
6.
7.
Added Example 1-7 and Example 1-8.
Updated Section 1.4.9 “RESET”.
Updated Section 1.7 “ICSP™ Considerations”.
Updated Section 2.1 “Absolute Maximum
Ratings†”.
Updated Section 2.2 “DC Specifications” and
Section 2.3 “AC Specification”.
Added FIGURE 2-3: “ESR Curves for Load
Capacitor Selection.”.
Updated the Product Identification System
section.
Revision B (August 2007)
The following is the list of modifications:
1.
2.
3.
4.
5.
6.
Modified Block Diagram on page 2.
Section 1.3.5
“Transmitter-OFF
Mode”:
Deleted text in 1st paragraph.
Example 1-6: Removed +5V notation.
Section 1.4 “Pin Descriptions”: Removed 10pin DFN, MSOP column from table.
Section 1.4.8 “Fault/TXE”: Deleted text from
2nd paragraph.
Section 3.0 “Packaging Information”: Added
8-lead 4x4 and 6x5 DFN and 14-lead TSSOP
packages. Updated package outline drawings
and added drawings for 8-lead DFN and 14-lead
TSSOP drawings.
Revision A (November 2005)
Original Release of this Document.
Revision D (July 2008)
The following is the list of modifications.
1.
2.
3.
Updated ESD specs under ‘Absolute DC’.
Updated notes in Example 1-1.
Updated Package Outline Drawings.
Revision C (April 2008)
The following is the list of modifications.
1.
2.
3.
4.
5.
Added LIN2.1 and J2602 compliance statement
to Features section.
Added recommended RC network for CS/
LWAKE in Example 1-1.
Updated 2.1 Absolute Maximum Ratings to
reflect current test results.
Updated 2.2 DC Specifications and 2.3 AC
Specifications to reflect current production
device.
Added 8-Lead SOIC Landing Pattern Outline
drawing.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 47
MCP2021/2/1P/2P
NOTES:
DS22018F-page 48
© 2005-2012 Microchip Technology Inc.
MCP2021/2/1P/2P
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
–X
Temperature
Range
/XX
Package
MCP2021:
LIN Transceiver with Voltage Regulator; wakes up on
dominant level of LIN bus.
MCP2021T: LIN Transceiver with Voltage Regulator; wakes up on
dominant level of LIN bus.
(Tape and Reel) (SOIC only)
MCP2022: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up on dominant level of LIN bus.
MCP2022T: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up on dominant level of LIN bus.
(Tape and Reel) (SOIC only)
MCP2021P: LIN Transceiver with Voltage Regulator; wakes up at a
falling edge of LIN bus level.
MCP2021PT: LIN Transceiver with Voltage Regulator; wakes up at a
falling edge of LIN bus level
(Tape and Reel) (SOIC only)
MCP2022P: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up at a falling edge of LIN bus level.
MCP2022PT: LIN Transceiver with Voltage Regulator, and RESET
pin; wakes up at a falling edge of LIN bus level.
(Tape and Reel) (SOIC only)
Temperature
Range:
E
= -40°C to +125°C
Package:
MD
MF
P
SN
SL
ST
=
=
=
=
=
=
Examples:
a)
b)
c)
d)
e)
f)
g)
h)
i)
a)
b)
c)
d)
e)
f)
g)
MCP2021-330E/SN:
MCP2021-330E/P:
MCP2021-500E/MF:
MCP2021-500E/SN:
MCP2021-500E/MD:
MCP2021-330E/P:
MCP2021T-330E/SN:
3.3V, 8L-SOIC pkg.
3.3V, 8L-PDIP pkg.
5.0V, 8L-DFN-S pkg.
5.0V, 8L-SOIC pkg.
5.0V, 8L-DFN pkg.
5.0V, 8L-PDIP pkg.
Tape and Reel,
3.3V, 8L-SOIC pkg.
MCP2021T-500E/MD: Tape and Reel,
5.0V, 8L-DFN pkg.
MCP2021T-500E/SN: Tape and Reel,
5.0V, 8L-SOIC pkg.
MCP2022-330E/SL:
MCP2022-330E/P:
MCP2022-500E/SL:
MCP2022-500E/P:
MCP2022T-330E/SL:
3.3V, 14L-SOIC pkg.
3.3V, 14L-PDIP pkg.
5.0V, 14L-SOIC pkg.
5.0V, 14L-PDIP pkg.
Tape and Reel,
3.3V, 14L-SOIC pkg.
MCP2022T-500E/SL: Tape and Reel,
5.0V, 14L-SOIC pkg.
MCP2022T-500E/ST: Tape and Reel,
5.0V, 14L-TSSOP pkg.
Plastic Micro Small Outline (4x4), 8-lead
Plastic Micro Small Outline (6x5), 8-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC, (150 mil Body), 8-lead
Plastic SOIC, (150 mil Body), 14-lead
Plastic Thin Shrink Small Outline, 14-lead
© 2005-2012 Microchip Technology Inc.
DS22018F-page 49
MCP2021/2/1P/2P
NOTES:
DS22018F-page 50
© 2005-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-884-0
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2005-2012 Microchip Technology Inc.
DS22018F-page 51
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
Fax: 852-2401-3431
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Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
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Tel: 678-957-9614
Fax: 678-957-1455
Boston
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Tel: 774-760-0087
Fax: 774-760-0088
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Tel: 630-285-0071
Fax: 630-285-0075
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Tel: 216-447-0464
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Tel: 972-818-7423
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Tel: 248-538-2250
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Tel: 317-773-8323
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Tel: 949-462-9523
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Tel: 408-961-6444
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Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
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Korea - Daegu
Tel: 82-53-744-4301
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Spain - Madrid
Tel: 34-91-708-08-90
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China - Hangzhou
Tel: 86-571-2819-3187
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Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
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Tel: 86-25-8473-2460
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Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
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Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS22018F-page 52
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
11/29/11
© 2005-2012 Microchip Technology Inc.