OKI MSM6688 Adpcm solid-state recorder ic Datasheet

FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Issue Date: Mar 12. 2002
ADPCM Solid-State Recorder IC
GENERAL DESCRIPTION
The MSM6688/6688L is a “solid-state recorder” IC developed using the ADPCM method. By externally
connecting a microphone, a speaker, a speaker drive amplifier, and a dedicated register to store ADPCM data, it
can record and play back voice data in a manner similar to a tape recorder.
The MSM6688 supports 5 V operation and has a stand-alone mode and a microcontroller interface mode.
The MSM6688L supports 3 V operation and controls recording/playback in microcontroller interface mode.
In the stand-alone mode, recording/playback conditions can be selected by pins and the MSM6688/6688L can be
controlled by a simple drive timing. In the microcontroller interface mode, recording/playback can be controlled
by commands from the microcontroller. In the microcontroller interface mode, the MSM6688/6688L is much
more flexible than in the stand-alone mode.
In addition, the MSM6688/6688L can form easily a recording and playback circuit with fixed messages by
connecting serial registers and serial voice ROMs as external memories.
Note: This data sheet explains a stand-alone mode and a microcontroller interface mode, separately.
Differences between MSM6688 and MSM6688L
Parameter
MSM6688
MSM6688L
3.5 to 5.5 V
2.7 to 3.6 V
Standalone mode,
Microcontroller interface mode
Microcontroller interface mode only
0 to VDD
1/4 to 3/4 VDD
Operating voltage
Control mode
Full scale of A/D and D/A
converters
Voice detection level for voice
triggered starting
External-only register
±
VDD
64
,±
VDD
32
,±
VDD
16
32M bits (max.)
4M bits (MSM6684B)
8M bits (MSM6685A)
±
VDD
128
,±
VDD
64
, ±
VDD
32
4M bits (max.)
4M bits (MSM66V84B)
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
CONTENTS
GENERAL DESCRIPTION ................................................................................................................................... 1
Differences between MSM6688 and MSM6688L............................................................................................. 1
(1) STAND-ALONE MODE (FOR MSM6688 (5 V VERSION))...................................................................... 4
FEATURES............................................................................................................................................................. 4
BLOCK DIAGRAM ............................................................................................................................................... 5
PIN CONFIGURATION (TOP VIEW) .................................................................................................................. 6
PIN DESCRIPTIONS ............................................................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version))................................................................. 11
RECOMMENDED OPERATING CONDITIONS (for MSM6688 (5 V Version)).............................................. 11
ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version))................................................................ 12
TIMING DIAGRAMS .......................................................................................................................................... 16
FUNCTIONAL DESCRIPTION........................................................................................................................... 29
Recording Time and Memory Capacity........................................................................................................... 29
Connection of an Oscillator ............................................................................................................................. 29
Power Supply Wiring....................................................................................................................................... 31
Configuring SGC and SG pins......................................................................................................................... 31
Analog Input Amplifier Circuit ....................................................................................................................... 32
Connection of LPF Circuit Peripherals............................................................................................................ 34
LPF Characteristics.......................................................................................................................................... 35
Reset Function ................................................................................................................................................. 36
Power Down by the PDWN pin...................................................................................................................... 37
Record/Playback Control Mode....................................................................................................................... 38
Deleting phrases............................................................................................................................................... 40
Recording Method ........................................................................................................................................... 41
Playback Method ............................................................................................................................................. 42
ROM Playback Method ................................................................................................................................... 43
Voice Triggered Starting ................................................................................................................................. 44
Method of Temporarily Stopping Record/Playback by Pause Function.......................................................... 46
APPLICATION CIRCUIT.................................................................................................................................... 47
(2) MICROCONTROLLER INTERFACE MODE (FOR MSM6688 (5 V VERSION)
AND MSM6688L (3 V VERSION)) ............................................................................................................. 48
FEATURES........................................................................................................................................................... 48
BLOCK DIAGRAM ............................................................................................................................................. 49
PIN CONFIGURATION (TOP VIEW) ................................................................................................................ 50
PIN DESCRIPTIONS ........................................................................................................................................... 51
ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version))................................................................. 54
RECOMMENDED OPERATING CONDITIONS (for MSM6688 (5 V Version)).............................................. 54
ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version))................................................................ 54
ABSOLUTE MAXIMUM RATINGS (for MSM6688L (3 V Version)) .............................................................. 59
RECOMMENDED OPERATING CONDITIONS (for MSM6688L (3 V Version)) ........................................... 59
ELECTRICAL CHARACTERISTICS (for MSM6688L (3 V Version)) ............................................................. 59
TIMING DIAGRAMS .......................................................................................................................................... 64
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MSM6688/6688L
FUNCTIONAL DESCRIPTION........................................................................................................................... 83
Recording Time and Memory Capacity........................................................................................................... 83
Connection of an Oscillator ............................................................................................................................. 83
Power Supply Wiring....................................................................................................................................... 86
Configuring SGC and SG pins......................................................................................................................... 86
Analog Input Amplifier Circuit ....................................................................................................................... 87
Connection of LPF Circuit Peripherals............................................................................................................ 89
LPF Characteristics.......................................................................................................................................... 89
Full Scale of A/D and D/A Converters ............................................................................................................ 90
Reset Function ................................................................................................................................................. 91
Power Down by the PDWN pin...................................................................................................................... 92
Record/Playback Control Modes ..................................................................................................................... 93
Data Configuration of External Serial Registers.............................................................................................. 95
Data Configuration of External Serial Voice ROMs ..................................................................................... 104
Command Description ................................................................................................................................... 106
Status Register ............................................................................................................................................... 115
Inputting the Commands................................................................................................................................ 118
Changes of Record/Playback Conditions....................................................................................................... 122
Setting and Confirming the Record/Playback Conditions ............................................................................. 123
Flex Record/Playback Method....................................................................................................................... 134
Direct Record/Playback Method.................................................................................................................... 141
ROM Playback by Inputting Address Code................................................................................................... 144
Direct ROM Playback Method ...................................................................................................................... 148
Stopping Record/Playback Temporarily (by the PAUSE Command) ........................................................... 150
Transferring Data to/from External Memories .............................................................................................. 151
Record/Playback by Inputting/Outputting Voice Data via Data Bus............................................................. 157
Suppression of Pop Noise at AOUT Output (by the LEV Command) .......................................................... 161
APPLICATION CIRCUIT.................................................................................................................................. 163
PACKAGE DIMENSIONS................................................................................................................................. 164
REVISION HISTORY ........................................................................................................................................ 166
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MSM6688/6688L
(1) STAND-ALONE MODE (FOR MSM6688 (5 V VERSION))
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3-bit or 4-bit ADPCM
Built-in 12-bit AD converter
Built-in12-bit DA converter
Built-in microphone amplifier
Built-in low-pass filter
Attenuation characteristics –40 dB/oct
External memories
Serial registers, 32M bits maximum (for variable messages)
8M bit serial register (MSM6685A) can be driven directly
Serial voice ROMs, 4M bits maximum (for fixed messages)
1M bit serial voice ROM (MSM6595A) can be driven directly
2M bit serial voice ROM (MSM6596A) can be driven directly
3M bit serial voice ROM (MSM6597A) can be driven directly
Sampling frequency
4.0 kHz, 5.3 kHz, 6.4 kHz or 8.0 kHz (master clock frequency = 4.096 MHz)
8.0 kHz, 10.6 kHz, 12.8 kHz, or 16.0 kHz (master clock frequency = 8.192 MHz)
Number of phrases
63 phrases for variable messages
63 phrases for fixed messages
Maximum recording time (when external 32M bit RAM is connected)
34 minutes (for 16 kbps ADPCM)
23 minutes (for 24 kbps ADPCM)
17 minutes (for 32 kbps ADPCM)
Voice triggered starting function
Pause function
Master clock frequency: 4.096 to 8.192 MHz
Power supply voltage: Single 5 V power supply
Package:
56-pin plastic QFP (QFP56-P-910-0.65-2K) (MSM6688GS-2K)
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LIN
MOUT
MIN
4B/3B
REC/PLA
XT
XT
MON
NAR
VDS
ROM
SAM1
SAM2
RESET
PDWN
PDMD
MCUM
+
–
+
–
LOUT
Latch
OSC
Controller
Timing
AMON FIN
DEL ST SP PAUSE
LPF
AOUT FOUT
ADIN
12-bit
ADC
ADPCM
Analyzer/Synthesizer
Address Controller
12-bit
DAC
Controller
SG SGC
SG
Circuit
Test Circuit
Phrase Register
Data
I/O
TEST TEST
CA0 CA1 CA2 CA3 CA4 CA5
OKI Semiconductor
AGND
DGND
DVDD’
AVDD
DVDD
CS3
CS4
CS1
CS2
RWCK
WE
SADY
TAS
SADX
RSEL2
RSEL1
DROM
DI/O
FEDL6688-6688L-04
MSM6688/6688L
BLOCK DIAGRAM
Register
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
56
55
54
53
52
51
50
49
48
47
46
45
44
43
REC/PLAY
ST
SP
RESET
NAR
MON
RWCK
DVDD
XT
XT
WE
DROM
DI/0
CS4
PIN CONFIGURATION (TOP VIEW)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CS3
CS2
CS1
SADX
SADY
TAS
SAS
PDWN
TEST
TEST
RSEL2
RSEL1
DGND
AGND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ROM
ADIN
FOUT
AOUT
FIN
AMON
DVDD’
AVDD
SG
SGC
LOUT
LIN
MOUT
MIN
CA0
CA1
CA2
CA3
CA4
CA5
DEL
PAUSE
PDMD
MCUM
SAM1
SAM2
4B/3B
VDS
56-Pin Plastic QFP
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MSM6688/6688L
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
49
DVDD
—
Digital power supply pin. Insert a bypass capacitor of 0.1 µF or more between
this pin and the DGND pin.
21
DVDD’
—
Digital power supply pin
22
AVDD
—
Analog power supply pin. Insert a bypass capacitor of 0.1 µF or more
between this pin and the AGND pin.
30
DGND
—
Digital ground pin
29
AGND
—
Analog ground pin
23
24
SG
SGC
O
Output pin for analog circuit reference voltage (signal ground)
28
26
MIN
LIN
I
Inverting input pin of the built-in OP amplifier. Non-inverting input pin is
internally connected to SG (signal ground).
27
25
MOUT
LOUT
O
MOUT and LOUT are output pins of the built-in OP amplifier for MIN and LIN,
respectively.
20
AMON
O
This pin is connected to the LOUT pin in the recording mode and to the DA
converter output in the playback mode. Used to connect the built-in LPF input
(FIN pin).
19
FIN
I
Input pin of built-in LPF
17
FOUT
O
Output pin of built-in LPF. Used to connect the AD converter input (ADIN pin).
16
ADIN
I
Input pin of the built-in 12-bit AD converter
18
AOUT
O
Output pin of the built-in LPF. This pin outputs playback waveforms and used
to connect an external speaker drive amplifier.
39
38
SADX
SADY
O
(Serial Address Data). SADX is used to connect the SAD pin of each external
serial register and the SADX pin of each external serial voice ROM. SADY is
used to connect the SADY pin of each external serial voice ROM. Outputs of
starting address of read/write.
36
SAS
O
(Serial Address Strobe). Used to connect the SAS pin of external serial
register and the SASX and SASY pins of external serial voice ROM. Clock pin
to write the serial address.
O
(Transfer Address Strobe). Used to connect the TAS pin of each external
serial register and serial voice ROM.
This pin outputs address strobe outputs to set the serial address data from
the SADX and SADY pins into the internal address counter of each serial
register and serial voice ROM.
37
TAS
50
RWCK
O
(Read/Write Clock). Used to connect the RWCK pin of each external serial
register and the RDCK pin of each external serial voice ROM.
This pin outputs a clock to read data from or write it into each external serial
register.
46
WE
O
(Write Enable). Used to connect the WE pin of each external serial register.
This pin outputs WE signal to select either read or write mode.
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FEDL6688-6688L-04
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MSM6688/6688L
Pin
Symbol
Type
Description
44
DI/O
I/O
(Data I/O) Used to connect the DIN and DOUT pins of DRAM and serial
register. This pin outputs the data to be written into the serial register or
inputs the data read from the serial registers.
45
DROM
I
(Data ROM) Used to connect the DOUT pin of each external serial voice
ROM.
40
41
42
43
CS1
CS2
CS3
CS4
O
(Chip Select) Used to connect the CS pin of serial register and the CS (CS1,
CS2, CS3) pins of each serial voice ROM.
(Register Select) These are used to select the number of external serial
registers.
31
32
RSEL1
RSEL2
I
RSEL2
L
L
H
H
RSEL1
L
H
L
H
Number of serial registers
1
2
3
4
10
MCUM
I
This pin is used to select either the stand-alone mode or the microcontroller
interface mode.
Low level:
Stand-alone mode
High level:
Microcontroller interface mode
53
RESET
I
A high input level at this pin causes the MSM6688 to be initialized and to go
into the power down state.
35
PDWN
I
(Power Down) When a low level is input to this pin, the MSM6688 goes to the
power down state. Unlike the RESET pin, this pin does not force to reset the
MSM6688. When an low level is applied to this PDWN pin during recording
operation, the MSM6688 is halted, and will be maintained in the power down
state while PDWN is low. After this pin is restored to a high level,
postprocessing for recording will be performed.
47
XT
I
Used to connect an oscillator. When an external clock is used, input the clock
through this pin. At the power down state, this pin must be set to the ground
level.
48
XT
O
Used to connect an oscillator. When an external clock is used, this pin must
be left open.
34
33
TEST
TEST
I
Used to test the MSM6688. Input a low level to the TEST pin and a high level
to the TEST pin.
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OKI Semiconductor
MSM6688/6688L
Pin
Symbol
Type
15
ROM
I
When low, selects the record/playback operation. When high, selects the
ROM playback operation.
56
REC/PLAY
I
Used to select the recording mode or the playback mode. This pin is invalid
during the ROM playback operation. When low, selects the playback mode.
When high, selects the recording mode.
55
ST
I
When a low-level pulse is applied to this pin, the record/playback or ROM
playback is started.
54
SP
I
When a low-level pulse is applied to this pin, the record/playback or ROM
playback is started.
8
PAUSE
I
When a low-level pulse is applied to this pin, the record/playback or ROM
operation is stopped temporarily.
I
When a low level pulse is applied to this pin, all phrase deletion or specified
phrase deletion can be performed according to the setting of pins CA0
through CA5,
ch00:
All phrase deletion
ch01 to ch3F:
Specified phrase deletion
After powering up, be sure to input RESET signal and then to delete all
phrases.
After completing this procedure, start the record/playback operation.
7
DEL
Description
Input pins used to specify desired phrases.
A total of 63 phrases can be specified independently for record/playback
operation and the ROM playback operation.
CA5
1-6
CA1
CA0
Phrase
No.
Remarks
L
L
ch00
All phrase deletion
L
L
H
ch01
L
L
L
L
H
L
ch02
A total of 63
phrases can be
used both for
record/playback
and ROM playback
operation.
…
L
L
…
L
L
…
L
L
…
L
…
I
CA2
…
4B/3B
I
CA3
…
13
CA0-CA5
CA4
H
H
H
H
H
L
ch3E
H
H
H
H
H
H
ch3F
Input pin used to select one of two types of ADPCM bit length.
When low, selects the 3-bit ADPCM.
When high, selects the 4-bit ADPCM.
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Pin
Symbol
MSM6688/6688L
Type
Description
Used to select one of the following four types of sampling frequency. The
relationship between the master clock frequency (fOSC) and the sampling
frequency (fSAMP) is shown below. Values in parentheses denote the sampling
frequencies for fOSC = 4.096 MHz.
11
12
SAM1
SAM2
I
SAM2
SAM1
fSAMP
L
L
H
H
L
H
L
H
fOSC
fOSC
fOSC
fOSC
1024
768
640
512
(4.0 kHz)
(5.3 kHz)
(6.4 kHz)
(8.0 kHz)
9
PDMD
I
This input pin is used to select the condition for transition to the power-down
state.
Low level: The MSM6688 automatically goes to the power-down state,
excepting the time the record/playback operation is being
performed.
High level: The MSM6688 automatically goes to the standby state, instead of
the power-down state, excepting the time the record/playback
operation is being performed. In this case, the MSM6688 can be
placed in the power-down state by setting the REST pin to a high
level. If it is desired to use the built-in LPF for an external circuit,
this standby mode must be selected by applying a high level to the
PDMD pin.
14
VDS
I
Used to select the voice triggered starting that starts recording when the
voice input exceeds the preset amplitude. A high input level on this pin
enables the voice triggered starting circuit.
51
MON
O
Outputs a high level while the record/playback operation is being performed.
52
NAR
O
Output pin to indicate the enable or disable state of the operation for
specifying a phrase. When continuous ROM playback is performed, the next
phrase can be specified after verifying that the NAR pin becomes high.
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MSM6688/6688L
ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version))
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
VDD
Ta = 25°C
–0.3 to +7.0
V
Input voltage
VIN
Ta = 25°C
–0.3 to VDD+0.3
V
TSTG
—
–55 to +150
°C
Storage temperature
RECOMMENDED OPERATING CONDITIONS (for MSM6688 (5 V Version))
Parameter
Symbol
Condition
Range
Unit
VDD
DGND = AGND = 0 V
3.5 to 5.5 (Note 1)
V
Operating temperature
TOP
—
–40 to +85
°C
Master clock frequency
fOSC
—
4.0 to 8.192
MHz
Power supply voltage
Note: 1. Recording and playback should be performed at a power supply voltage of 4.5 to 5.5 V.
For other operations such as backup for a serial register, the IC operates at 3.5 to 5.5 V.
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MSM6688/6688L
ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version))
DC Characteristics
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V (Note 5)
DGND = AGND = 0 V, Ta = –40 to +85°C
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
High input voltage
VIH
—
0.8 × VDD
—
—
V
Low input voltage
VIL
—
—
—
0.2 × VDD
V
High output voltage
VOH
IOH = –40 µA
VDD – 0.3
—
—
V
Low output voltage
VOL
IOL = 2 mA
—
—
0.45
V
High input current (Note 1)
IIH1
VIH = VDD
—
—
10
µA
High input current (Note 2)
IIH2
VIH = VDD
—
—
20
µA
Low input current (Note 3)
IIL1
VIL = GND
–10
—
—
µA
Low input current (Note 2)
IIL2
VIL = GND
–20
—
—
µA
Low input current (Note 4)
IIL3
VIL = GND
–400
—
–20
µA
Operating current
consumption
IDD
fOSC = 8 MHz, no load
—
15
30
mA
During power down,
no load
—
—
10
µA
—
—
50
µA
Standby current
Consumption
IDDS
Ta = –40 to +70°C
During power down,
no load
Ta = –40 to +85°C
Notes: 1.
2.
3.
4.
Applies to all input pins excluding the XT pin.
Applies to the XT pin.
Applies to the all input pins without pull-up resistors, excluding the XT pin.
Applies to the input pins (ST, SP, PAUSE, DEL) with pull-up resistors, excluding the XT pin.
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MSM6688/6688L
Analog Characteristics
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V
DGND = AGND = 0 V, Ta = –40 to +85°C
Parameter
DA output relative error
Symbol
Condition
Min.
Typ.
Max.
Unit
|VDAE|
No load
—
—
—
mV
FIN admissible input
voltage range
VFIN
—
1
—
VDD –1
V
FIN input impedance
RFIN
—
1
—
—
MΩ
ADIN admissible input
voltage range
VADIN
—
0
—
VDD
V
ADIN input impedance
RADIN
—
1
—
—
MΩ
Op-amp open loop gain
GOP
fIN = 0 to 4 kHz
40
—
—
dB
Op-amp input impedance
RINA
—
1
—
—
MΩ
Op-amp load resistance
ROUTA
—
200
—
—
kΩ
AOUT load resistance
RAOUT
—
50
—
—
kΩ
FOUT load resistance
RFOUT
—
50
—
—
kΩ
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MSM6688/6688L
AC Characteristics
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Symbol
RESET pulse width
RESET execution time
(Note 1)*
PDWN low level time
PDWN high level time
Typ.
Max.
Unit
tRST
1
—
—
µs
tREX
—
1
—
ms
*
tPDL
500
—
—
µs
(Note 1)*
tPDH
500
—
—
µs
*
tPX
125
—
500
µs
Oscillating time after input of PDWN
BUSY time after release of PDWN
Min.
(Note 1)*
tBPD
0.25
—
—
ms
ST pulse width
(Note 2)**
tST
40
—
—
µs
ST pulse width
**
tSP
40
—
—
µs
**
tPSE
40
—
—
µs
(Note 2)*
tDEL
40
—
—
µs
PAUSE pulse width
DEL pulse width
Time required to delete all phrases
*
tWBLA
550
—
—
ms
Time required to delete a specified phrase
*
tWBL1
70
—
—
ms
(Note 2) *
tDCS
—
—
270
µs
Hold time of CA0 to CA5, REC/PLAY after MON rise
tCAH
1
—
—
ms
Address control time at the start of record/playback *
tAD1
—
1
—
ms
Time from input of ST pulse to NAR fall
tSTN
—
—
40
µs
tMID
0.75
—
1
ms
ms
Time from input of DEL pulse to CSI fall
(Note 2)*
Unvoiced time between phrases during repeated
playback
Time from input of ST
pulse to MON rise
POMD
=H
Time from input of SP
pulse to MON fall
*
Record
*
tTMH1
—
—
50
Playback
*
tTMH2
—
—
20
ms
ROM playback *
tTMH3
—
—
1
ms
Record
*
tPMH1
—
—
80
ms
Playback
*
tPMH2
—
—
2
ms
ROM playback *
tPMH3
—
—
2
ms
Time from input of ST pulse to standby for
voice
*
tSTVH
—
—
50
ms
Time from input of SP pulse during
standby for voice to release of standby for
voice
*
tSPVH
—
—
80
ms
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
Note: 1. The oscillation start stabilization time is added to tREX and tBPD.
The oscillation start stabilization time is several tens of milliseconds for crystals and several
hundreds of microseconds for ceramic oscillators.
Note: 2. The oscillation start stabilization time is added if PDMD pin = “L”.
The oscillation start stabilization time is several tens of milliseconds for crystals and several
hundreds of microseconds for ceramic oscillators.
14/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Time from input of ST
pulse to MON rise
Time from input of SP
pulse to MON fall
Symbol
Min.
Typ.
Max.
Unit
Record
*
tTML1
—
—
120
ms
Playback
*
tTML2
—
—
150
ms
ROM playback *
tTML3
—
—
150
ms
Record
*
tPML1
—
—
80
ms
Playback
*
tPML2
—
—
260
ms
ROM playback *
tPML3
—
—
260
ms
Time from input of ST pulse to standby for
voice
*
tSTVL
—
—
120
ms
Time from input of SP pulse during
standby for voice to release of standby for
voice
*
tSPVL
—
—
80
ms
Standby transition time at start of
playback
*
tAOR
—
64
—
ms
Standby transition time at end of
playback
*
tAOF
—
256
—
ms
**
tPP
—
—
1
ms
Time from input of ST pulse during pause to restart
of record/playback
**
tPST
—
—
1
ms
POMD
=L
Time from input of PAUSE pulse to pause
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
15/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
TIMING DIAGRAMS
Reset Function
VDD
tRST
RESET (I)
tREX
Undefined
Power down
Standby for record/playback
Reset operation in progress
Power Down by PDWN Pin
tPDL
tPDH
PDWN (I)
tPX Note 1
XT (I)
XT (O)
Oscillation in progress
Oscillation in progress
tBPD
Power down
Postprocessing
Standby
Note: 1. When an external clock is used, continue to apply the clock input to the XT terminal during
tPX after the PDWN pin is set to a low level.
16/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Timing for Deletion of All Phrases
CA0-CA5 (I)
tDEL
DEL (I)
tWBLA
tDCS
CSI (O)
Deletion of all phrases
Standby
Standby
Timing for Deletion of a Specified Phrase
CA0-CA5 (I)
tDEL
DEL (I)
tWBL1
tDCS
CSI (O)
Standby
Standby
Deletion of a specified phrase
17/167
(I)
ROM
(I)
(I)
(I)
(O)
ST
SP
XT
XT
NAR
tSTN
Power down
(O)
(O)
(I)
REC/PLAY
MON
(I)
CA0-CA5
SAM1, SAM2 (I)
(I)
4B/3B
(I)
RESET
tTMH1
Standby
tST
Recording in progress
Oscillation in progress
Address control
tAD1
tCAH
Bit rate designation
Phase designation
Recording Timing (PDMD Pin = High)
tPMH1
tSP
Standby
Power down
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
18/167
(I)
(I)
ROM
VDS
(I)
(I)
(I)
(I)
(O)
(O)
(O)
REC/PLAY
ST
SP
XT
XT
MON
NAR
tSTN
Power down
(I)
CA0-CA5
SAM1, SAM2 (I)
(I)
4B/3B
(I)
RESET
Standby
tSTVH
tST
tSP
Recording
tPMH1
tSP
Standby
When STOP pulse is input during standby for voice,
the MSM6688 goes to the recording standby state.
Address control
tAD1
Oscillation in progress
tCAH
Power down
OKI Semiconductor
Voice detected
Standby for voice
tSPVH
Phrase designation
Bit rate designation
Timing for Voice Triggered Recording (PDMD Pin = High)
FEDL6688-6688L-04
MSM6688/6688L
19/167
(I)
ROM
(I)
(I)
(I)
(I)
(I)
(O)
(O)
(O)
(O)
CA0-CA5
REC/PLAY
ST
SP
XT
XT
MON
NAR
AOUT
SAM1, SAM2 (I)
4B/3B
(I)
(I)
RESET
Standby
1/2 VDD level
Address control
tAD1
tCAH
Playback
Oscillation in progress
tPMH2
tSP
Standby
1/2 VDD level
Power down
GND level
OKI Semiconductor
Power down
GND level
tSTN
tTMH2
tST
Phrase designation
Bit rate designation
Playback Timing (PDMD Pin = High)
FEDL6688-6688L-04
MSM6688/6688L
20/167
(I)
ROM
(I)
(O)
(O)
(O)
(O) GND level
XT
XT
MON
NAR
AOUT
Power down
(I)
SP
tSTN
(I)
ST
CA0-CA5 (I)
(I)
RESET
tTMH3
Standby
1/2 VDD level
tST
tAD1
tCAH
Address control
Phrase designation
ROM Playback Timing (PDMD Pin = High)
Playback
Oscillation in progress
tPMH3
tSP
Standby
1/2 VDD level
Power down
GND level
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
21/167
(I)
ROM
(I)
(I)
(I)
(O)
(O)
(O)
(O)
ST
SP
XT
XT
MON
NAR
AOUT
CA0-CA5 (I)
(I)
RESET
Power down
GND level
tSTN
tAD1
1st phrase playback
Oscillation in progress
Unvoiced
tMID
2nd phrase playback
tPMH3
tSP
2nd phrase designation
Standby
1/2 VDD level
Power down
GND level
OKI Semiconductor
Address control
Standby
1/2 VDD level
tTMH3
1st phrase designation
Continuous ROM Playback Timing (PDMD Pin = High)
FEDL6688-6688L-04
MSM6688/6688L
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Analog stable time
tAD1
tCAH
Address control
(O)
MON
Power down
(I)
(O)
XT
XT
(O)
(I)
SP
NAR
(I)
ST
tSTN
(I)
REC/PLAY
tTML1
Phrase specifying operation
(I)
CA0-CA5
tST
Bit rate specifying operation
(I)
ROM
SAM1, SAM2 (I)
(I)
4B/3B
(I)
RESET
Recording Timing (PDMD Pin = Low)
Recording in progress
Oscillation in progress
tPML1
tSP
Power down
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
23/167
(I)
(I)
ROM
VDS
(I)
(I)
(I)
(I)
(I)
(O)
(O)
(O)
CA0-CA5
REC/PLAY
ST
SP
XT
XT
MON
NAR
SAM1, SAM2 (I)
(I)
4B/3B
(I)
RESET
Power down
tSTN
Analog stable time
tSTVL
tST
tSPVL
tSP
Recording
tPML1
tSP
the MSM6688 goes to the recording standby state.
When STOP pulse is input during standby for voice,
Address
tAD1
Oscillation in progress
tCAH
Power down
OKI Semiconductor
Voice detected
Standby for voice
Phrase designation
Bit rate designation
Timing for Voice Triggered Recording (PDMD Pin = Low)
FEDL6688-6688L-04
MSM6688/6688L
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(I)
(O)
(O)
(O)
(O)
SP
XT
XT
MON
NAR
AOUT
Standby transition
Address control
tAD1
1/2 VDD level
tCAH
Playback
Oscillation in progress
tSP
tAOF
Standby transition
tPML2
Power down
GND level
OKI Semiconductor
Analog stable time
Power down
tAOR
(I)
ST
GND level
(I)
tSTN
(I)
REC/PLAY
tTML2
Phrase designation
(I)
CA0-CA5
tST
Bit rate designation
(I)
ROM
SAM1, SAM2 (I)
(I)
4B/3B
(I)
RESET
Playback Timing (PDMD Pin = Low)
FEDL6688-6688L-04
MSM6688/6688L
25/167
(I)
ROM
(I)
(I)
(O)
(O)
(O)
(O)
SP
XT
XT
MON
NAR
AOUT
GND level
tSTN
tST
tAOR
tCAH
Address control
tAD1
1/2 VDD level
Standby transition
tTML3
Phrase designation
Playback
Oscillation in progress
tSP
tAOF
GND
l
l
Power down
Standby transition
tPML3
OKI Semiconductor
Analog stable time
Power down
(I)
ST
CA0-CA5 (I)
(I)
RESET
ROM Playback Timing (PDMD Pin = Low)
FEDL6688-6688L-04
MSM6688/6688L
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(I)
ROM
(I)
(I)
(I)
(O)
(O)
(O)
(O)
ST
SP
XT
XT
MON
NAR
AOUT
CA0-CA5 (I)
(I)
RESET
tAOR
tAD1
1/2 VDD level
tTML3
Analog stable time Standby transition
Power down
GND level
tSTN
1st phrase designation
Continuous ROM Playback Timing (PDMD Pin = Low)
Address
t l
1st phrase playback
Oscillation in progress
Unvoiced
tMID
tPML3
tAOF
Standby transition
2nd phrase playback
tSP
2nd phrase designation
Power down
GND level
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
27/167
(I)
(I)
(I)
(O)
ST
SP
PAUSE
MON
Record/Playback
Start pulse
tST
tPP
tPSE
Pause
Record/Playback
tPST
Restart pulse
tST
tPML2 and tPML3.
the record/playback mode and is one of tPMH1, tPMH2, tPMH3, tPML1,
Note 1: This time interval varies depending on the state of PDMD pin and
Standby
Record/Playback Pause Timing
tPP
tPSE
Pause
Note 1
tSP
Standby
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
FUNCTIONAL DESCRIPTION
Recording Time and Memory Capacity
The recording time depends on the memory capacity of the external serial registers, sampling frequency, and
ADPCM bit length, and is given by
Recording time =
1.024 × memory capacity (K bits)
sampling frequency (kHz) × bit length (bits)
(seconds)
4096
For example, if the sampling frequency is
kHz (= 5.333 kHz), ADPCM bit length is 3 bits, and four 8M
768
bit serial registers are used, the recording time can be obtained as follows.
Recording time =
=
1.024 × (8192 × 4 – 64)
5.333 × 3
34 minutes 53 seconds
= 2093 seconds
In the above equation, the memory capacity is obtained by subtracting the memory capacity (64K bits) for the
channel index area from the total memory capacity.
Connection of an Oscillator
Connect a ceramic oscillator or a crystal oscillator to XT and XT pins as shown below. The optimal load
capacities when connecting ceramic oscillators from MURATA MFG. and KYOCERA CORPORATION are
shown below for reference.
MSM6688
XT
XT
C1
C2
Ceramic oscillator
MURATA MFG.
Type
CSTLS4M00G53-B0
(with capacitor)
CSTCR4M00G53-R0
(with capacitor)
CSTLS6M00G53-B0
(with capacitor)
CSTCR6M00G53-R0
(with capacitor)
CSTLS8M00G53-B0
(with capacitor)
CSTCC8M00G53-R0
(with capacitor)
Freq. (MHz)
Optimal load
capacity
C1 (pF)
C2 (pF)
Power supply
voltage (V)
Operating
temperature (°C)
3.5 to 5.5
–40 to +85
4.0
6.0
—
—
8.0
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Ceramic oscillator
KYOCERA CORP.
Type
KBR-4.0MSA
KBR-4.0MKS
(with capacitor)
Freq. (MHz)
Optimal load
capacity
C1 (pF)
C2 (pF)
Power supply
voltage (V)
Operating
temperature (°C)
3.5 to 5.5
–40 to +85
4.0
PBRC4.00A
PBRC4.00B
KBR-6.0MSA
KBR-6.0MKS
(with capacitor)
6.0
33
33
PBRC6.00A
PBRC6.00B
KBR-8.0M
PBRC8.00A
PBRC8.00B
8.0
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Power Supply Wiring
As shown in the following diagram, supply the power to this MSM6688 from the same power source, but
separate the power supply wiring to the analog portion from that to the logic position.
+5 V
DVDD’ DVDD
AVDD
MSM6688
DGND AGND
The following connections are not permitted.
Analog power supply
Digital power supply
+5 V
DVDD DVDD’ AVDD
DVDD DVDD’
AVDD
Configuring SGC and SG pins
The internal equivalent circuit around the SGC and SG pins is shown below.
AVDD
MSM6688
MSM6688L
50 kΩ
(TYP)
+
–
SGC
50 kΩ
(TYP)
AGND
To OP amplifier,
LPF
SG
20 kΩ (TYP)
AGND
Power-down signal
Switch is open
at power-down
AGND
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
The SG signal is a reference voltage (signal ground) for internal OP amplifiers and LPF.
Install a capacitor between the SGC pin and AGND and between the SG pin and AGND respectively in order to
make the SG signal noiseless. It is recommended to use an approx. 0.1 µF capacitor, which should be determined
after evaluating the tone quality.
It takes several ten msec until the DC levels such as the SG level of the analog circuit is stabilized after the
power-down mode is cancelled. The larger capacitance of a capacitor connected to SGC or SG requires the
longer time for stabilizing.
After the power-down mode is cancelled, enter voices after the DC levels for the analog circuit has been
stabilized.
When the device is in power-down mode, the output voltage of the SG pin becomes unstable. Therefore, SG
must not be supplied to external circuits.
Otherwise, power supply current may be leaked via the internal SG circuit.
Same is true for the SGC pin.
Analog Input Amplifier Circuit
This MSM6688 has two built-in operational amplifiers for amplifying the microphone output. Each OP amplifier
is provided with the inverting input pin and output pin. The analog circuit reference voltage SG (signal ground)
is connected internally to the non-inverting input of each OP amplifier.
For amplification, form an inverting amplifier circuit and adjust the amplification factor by using external
resistors as shown below.
– +
VLO
VMO
VIN
R2
R1
MIN
R3
MOUT
–
+ OP amp 1
SG
VLO=
R4
R3
VMO=
R2 • R4
R1 • R3
VLO
R4
LIN
LOUT
–
+ OP amp 2
VDD
VDD–1
1/2VDD
1
GND
VIN(V)
During the time the recording operation is performed, the output VLO of OP amp 2 is connected to the input FIN
of the built-in LPF. The allowable FIN input voltage (VFIN) ranges from 1 V to (VDD – 1) V. Therefore, the
amplification factor must be adjusted so that the VLO amplitude can be within the allowable FIN input voltage
range.
For example, if VDD = 5 V, VLO becomes 3 Vp-p max. If VLO exceeds the allowable FIN input voltage range, the
output of the LPF will be a clipped waveform.
The load resistance ROUTA of the OP amplifier is 200 kΩ minimum, so that the feedback resistors R2 and R4 of
the inverting amplifier circuit must be 200 kΩ or more.
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
When OP amplifier 1 is not used and OP amplifier 2 is used, the MIN pin must be connected to AGND or AVDD,
and the MOUT pin must be open.
Even if amplification is unnecessary, OP amplifier 2 must be always used.
Below is an example of an analog input amplifier circuit when the amplification factor is 1.
Input signal
AGND
(or AVDD)
MIN
SG
(200 kΩ)
R3
MOUT
–
+ OP amplifier 1
LIN
(200 kΩ)
R4
LOUT
–
+ OP amplifier 2
MSM6688
MSM6688L
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Connection of LPF Circuit Peripherals
The AMON pin is connected internally to the output of the amplifier circuit (LOUT pin) in the recording mode
and to the output of the built-in DA converter in the playback mode. Therefore, connect the AMON pin directly
to the input (FIN pin) of the built-in LPF.
Both the FOUT and AOUT pins are the output pins of the built-in LPF. Connect the FOUT pin to the input
(ADIN pin) of the built-in AD converter and connect the AOUT pin to an external speaker through an external
speaker drive amplifier.
In the MSM6688, the connection of each of the FOUT and AOUT pins is changed to one of the output of the
LPF, GND (ground) level, and SG (signal ground) level, depending on the operation status as shown below.
When PDMD pin = high level:
Analog pin
At power down
(RESET pin = H)
During operation (RESET pin = L)
Recording mode
Playback mode
LPF output
LPF output
(playback waveform)
FOUT pin
GND level
LPF output
(recording waveform)
AOUT pin
GND level
SG level
When PDMD pin = L:
Analog pin
At power down
During operation
Recording mode
Playback mode
LPF output
LPF output
(playback waveform)
FOUT pin
GND level
LPF output
(recording waveform)
AOUT pin
GND level
GND level
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
When PDMD pin = H:
LIN
LOUT
Speaker drive amplifier
AMON
FIN
AOUT
FOUT ADIN
Record
mode
–
+
Playback
mode
Playback
mode
SG
LPF
DAC
SG
–
+
ADC
Record mode
Power
down
GND
–
+
Power down
GND
Note: This diagram shows the state of each switch during the recording operation.
When PDMD = L:
Speaker drive amplifier
LIN
LOUT
–
+
SG
AMON
FIN
AOUT
FOUT ADIN
Record
mode
Playback
mode
LPF
–
+
Playback
ADC
DAC
–
+
Power down
GND
Note: This diagram shows the state of each switch during the recording operation.
LPF Characteristics
[dB] 20
10
This IC contains a fourth-order switched-capacitor LPF.
0
The attenuation characteristic of this LPF is –40 dB/oct.
–10
The cut-off frequency and frequency characteristics of
–20
this LPF vary in proportion to the sampling frequency
–30
(fSAMP). The cut-off frequency is preset to 0.4 times
–40
the sampling frequency. The following graph depicts the
–50
frequency characteristics of the LPF at fSAMP = 8 kHz.
–60
–70
–80
100
1K
10K
[Hz]
LPF Frequency Characteristics (fSAMP = 8.0 kHz)
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MSM6688/6688L
Reset Function
By applying a high level to the RESET pin, the MSM6688 stops frequency oscillation to minimize current
consumption and goes to the power-down state. At the same time, the control circuit is reset and initialized.
If a high level is applied to the RESET pin during record/playback operation, the MSM6688 is set to the
power-down state and initialized state, so that voice data becomes undefined.
The following shows the power-down state of the MSM6688.
(1) Frequency oscillation is stopped and all operations of the internal circuit are halted.
(2) The current consumption is minimized. When an external clock is used, apply a ground (GND) level to the
XT pin at power down so that no current can flow into the oscillation circuit.
(3) CS1-CS4 pins are set to a high level to minimize the current consumption of external serial registers and
serial voice ROMs.
(4) Pull-up resistors are removed from the input control ST, SP, PAUSE, and DEL pins.
(5) The state of the output pins are as follows.
Power down mode
with RESET = “H”
Power down mode
with PDWN = “L”
SAS, TAS, CS1-CS4, RWCK
“H” level
“H” level
SADX, WE, NAR
“H” level
“H” level or “L” level
SADY
“L” level
“H” level or “L” level
Pin name
“L” level
AOUT, FOUT
“L” level
“L” level
GND level
GND level
After powering up the MSM6688, be sure to initialize it by applying a high level to the RESET pin.
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MSM6688/6688L
Power Down by the PDWN pin
By applying a low level to the PDWN pin, the MSM6688 may be set to the power-down state, in which the
oscillation and all operations of internal circuits are halted. Unlike the reset operation by the RESET input, the
control circuit will not be initialized by this power-down operation.
The power-down operation will not affect the data in the internal control circuit and external serial registers.
Therefore, this power-down operation is useful when the battery backup takes place in case of power failure.
When PDWN becomes low during one of the following operations, their respective operations will be
performed after the power-down state is released (PDWN = H).
(1) When the MSM6688 is powered down (PDWN = L) during the record/plaback operation: The
record/playback operation is stopped. After the release of the power-down state, the postprocessing will be
performed.
(2) When the MSM6688 is powered down (PDWN = L) during the phrase deleting operation: The phrase
deleting operation is temporarily stopped and will be restarted after the release of the power-down state.
(3) When the MSM6688 is powered down (PDWN = L) during the time the transition of the AOUT output to
a DC level is in progress: This transition operation is temporalily stopped and will be continued after the
release of the power-down state.
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OKI Semiconductor
MSM6688/6688L
Record/Playback Control Mode
Either record/playback mode or ROM playback mode can be selected through the ROM pin as described below.
ROM pin
Record/playback control mode
L
Record/playback
H
ROM playback
1. Record/playback
The recorded voice data is stored in serial registers. The recording area is indirectly allocated to each phrase by
setting the phase specifying pins CA0 to CA5 (63 phrases). The recording area for each phrase is managed by
the MSM6688 as described below.
The total memory capacity of the connected external serial registers is equally divided into 256 memory blocks.
When recording is performed, voice data is written into the memory blocks unused by other phrases. When a
specified phase is deleted, the blocks used by this phrase become unused blocks.
When re-recording is performed, voice data is written in the memory area consisting of the memory blocks used
by this phrase and the unused memory blocks.
The memory capacity of one memory block and the number of initially available memory blocks (recording
time) vary according to the total memory capacity of the connected serial registers.
RSEL2
L
L
H
H
RSEL1
L
H
L
H
Total memory capacity
8M bits
16M bits
24M bits
32M bits
Memory capacity of one block
32K bits
64K bits
128K bits
128K bits
16 kbps
2.0 seconds
4.1 seconds
8.2 seconds
8.2 seconds
24 kbps
1.4 seconds
2.7 seconds
5.5 seconds
5.5 seconds
32 kbps
1.0 seconds
2.0 seconds
4.1 seconds
4.1 seconds
254
255
191
255
Recording time of one
block
Number of initially available blocks
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OKI Semiconductor
MSM6688/6688L
2. ROM playback
For playback of the voice data stored in the connected serial voice ROM, the playback area is allocated
indirectly to each fixed message phrase by setting phrase specifying pins CA0 to CA5 (63 phrases).
The start address, stop address, sampling frequency, and ADPCM bit length which specify the playback area for
each phrase are written in the index area of the serial voice ROM. When the playback operation is started, the
MSM6688 fetches these data from the index area.
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OKI Semiconductor
MSM6688/6688L
Deleting phrases
1. Deleting all phrases
All 63 phrases ch01 through ch3F can be deleted by specifying ch00 and applying a low pulse to the DEL pin.
When all phrases are deleted, all phrases ch01-ch3F (63 phrases) go to the unrecorded status and, at the same
time, the initial data for address control is written in the serial registers. Therefore, whenever the MSM6688 is
powered up, delete all phrases after applying a high level to the RESET pin.
2. Deleting a specified phrase
By specifying one of ch01-ch3F phrases and applying a low level to the DEL pin, the specified phrase can be
deleted and put to the unrecorded state. The blocks for the deleted phrases are added to available unused blocks
(available recording time).
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Recording Method
Whenever the MSM6688 is powered up, be sure to delete all phrases after applying a high level to the RESET
pin. Then, start the recording operation.
(1) Set recording conditions at the relevant pins.
ROM pin:
REC/PLAY pin:
VOS pin:
SAM1 and SAM2 pins:
4B /3B pin:
CA0- CA5 pins:
Low level
High level
Selection of voice triggered starting (high level enables voice activation and low
level disables voice activation.)
Select the sampling frequency.
Select the ADPCM bit length.
Specify one of 63 phrases ch01-ch3F.
(2) To start recording, apply a low pulse to the ST pin.
To stop recording in progress, apply a low pulse to the SP pin. When recording continues to the end of the
memory capacity, recording is automatically stopped. In case of re-recording, voice data will be written in
the memory block used by the specified phrase and unused memory blocks. Therefore, the voice data is
overwritten on the previously recorded contents. The MON pin outputs a high level during recording.
Start pulse Invalid
ST
(I)
(I)
SP
MON (O)
Stop pulse
Recording in progress
(stopped in the middle)
Available memory capacity
Start pulse
(I)
ST
MON (O)
Recording in progress
Available memory capacity
Recording is stopped automatically.
41/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Playback Method
(1) Set playback conditions at the relevant pins.
ROM pin:
REC/PLAY pin:
SAM1 and SAM2 pins:
4B/3B pin:
CA0-CA5 pins:
Low level
Low level
Select the sampling frequency.
Specify the ADPCM bit length selected for recording.
Specify one of 63 phases ch01-ch3F.
(2) To start playback, apply a low pulse to the ST pin.
When playback for the duration of the recorded data is finished, the playback is stopped automatically.
To stop playback in progress, apply a low pulse to the SP pin.
The MON pin outputs a high level during playback.
Start pulse
ST
(I)
MON (O)
Playback in progress
(same as the recorded time)
Playback is stopped automatically
Start pulse
ST
(I)
SP
(I)
MON (O)
Stop pulse
Playback in progress
(stopped in the middle)
Recorded time
By maintaining the ST pin at a low level, repeated playback is possible.
ST
(I)
SP
(I)
(Stop pulse)
MON (O)
1st playback
2nd playback
3rd playback
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
ROM Playback Method
(1) Apply a high level to the ROM pin.
(2) Specify one of 63 phrases ch01-ch3F by setting the CA0-CA5 pins.
(3) To start playback, apply a low pulse to the ST pin. To stop playback in progress, apply a low pulse to the SP
pin.
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Voice Triggered Starting
This MSM6688 has the voice triggered starting function that starts recording when the level of voice input
exceeds a preset amplitude. Using the voice activated function, the unvoiced part prior to voice detection will not
be recorded, so that the memory capacity can be utilized efficiently.
The unvoiced parts in the middle of recording are not eliminated. In the voice triggered starting mode, recording
is started when a voice input exceeds the preset thresholds. Therefore, a consonant part with a low level may not
be recorded.
Voice input level
(ADIN pin)
1/2VDD
Upper threshold
+Vvds
–Vvds
Lower threshold
Identified as voice
Start signal input
VDS pin
Voice triggered starting conditions
L
Voice triggered starting disabled
H
Voice triggered starting disabled
Voice detection threshold Vvds = VDD/32 (±160 mV)
The value in parentheses is for VDD = 5.12 V.
44/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
When a low level is applied to the ST pin, the MSM6688 goes to the standby state for voice. When detecting a
voiced input, it starts recording and the MON pin outputs a high level.
Start pulse
ST
(I)
SP
(I)
Stop pulse
MON (O)
Recording in progress
Standby for voice
Determined as voice
When a low level is applied to the SP pin during standby state for voice, the MSM6688 finishes the standby state
for voice and goes to the standby state for recording.
Start pulse
ST
(I)
SP
(I)
Stop pulse
Standby for
recording
Standby for voice
Standby for
recording
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Method of Temporarily Stopping Record/Playback by Pause Function
By applying a low pulse to the PAUSE pin during record/playback, record/playback operation can be stopped
temporarily. To resume record/playback, apply a low pulse to the ST pin. To stop record/playback, apply a low
pulse to the SP pin.
Start pulse
Start pulse
ST
(I)
Pause pulse
PAUSE (I)
Pause
Resume
Start pulse
ST
(I)
SP
(I)
Stop pulse
Pause pulse
PAUSE (I)
Pause
Record/Playback finished
When record/playback is resumed after temporary stop, the voice triggered starting circuit is not operated and
recording is started when a start low pulse is applied to SP pin.
46/167
ADPCM SOLID-STATE RECORDER IC MSM6688
SGC
SG
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
Speaker drive
amplifier
SASY
DROM
CS1CS2 VSS
DOUT
TEST
TAS
RWCK RDCK
TAS
SADY
SASX
OKI Semiconductor
DGND AGND
MON
NAR
XT
XT
SAS
SADY
VCC
SADX SADX
Circuit Diagram 1: Application circuit in standalone
mode with 8M bit serial registers
and 2M bit serial voice ROMs
MSM6685A
MOUT
MIN
CS3
CS4
MSM6685A
ROM
CA0
CA1
CA2
CA3
CA4
CA5
TEST NC
CS VSS
TEST
TEST
DI/O DIN
DOUT
SAS
MSM6685A
4.096 MHz
SW
Phrase
selector
CS1
CS2
VCC
SAD
TAS
TAS
RWCK RWC
WE WE
SAS
SADX
8M SERIAL REGISTER MSM6685A
PDMD
MCUM
VDS
DROM
DI/O
TAS
RWCK
WE
SADY
SAS
SADX
2M SERIAL VOICE ROM
MSM6596A-XXX
4B/3B
RSEL1
RSEL2
SAM1
SAM2
PDWN
RESET
PAUSE
SP
ST
DEL
REC/PLAY
DVDD DVDD’ AVDD
FEDL6688-6688L-04
MSM6688/6688L
APPLICATION CIRCUIT
The circuit diagram 1 shows an application circuit example where the MSM6688 is used in the stand-alone mode
and four 8M bit serial registers and two 2M bit serial voice ROMs also connected.
MSM6596A-XXX
+
+
47/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
(2) MICROCONTROLLER INTERFACE MODE (FOR MSM6688 (5 V VERSION)
AND MSM6688L (3 V VERSION))
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3-bit or 4-bit ADPCM
Built-in 12-bit AD converter
Built-in12-bit DA converter
Built-in microphone amplifier
Built-in low-pass filter
Attenuation characteristics –40 dB/oct
External only registers (for variable messages)
MSM6688 (5 V version)
- Serial registers, 32M bits maximum
One 4M bit serial register (MSM6684B) can be driven directly
Up to four 8M bit serial register (MSM6685A) can be driven directly
MSM6688L (3 V version)
- Serial registers, 4M bits maximum
One 4M bit serial register (MSM66V84B) can be driven directly
External only ROMs (for fixed messages)
- Serial voice ROMs, 4M bits maximum
1M bit serial voice ROM (MSM6595A) can be driven directly
2M bit serial voice ROM (MSM6596A) can be driven directly
3M bit serial voice ROM (MSM6597A) can be driven directly
Sampling frequency
4.0 kHz, 5.3 kHz, 6.4 kHz or 8.0 kHz (master clock frequency = 4.096 MHz)
8.0 kHz, 10.6 kHz, 12.8 kHz or 16.0 kHz (master clock frequency = 8.192 MHz)
Number of phrases
63 phrases for variable messages
63 phrases for fixed messages
Maximum recording time (when external 32M bit RAM is connected)
34 minutes (for 16K bps ADPCM)
23 minutes (for 24K bps ADPCM)
17 minutes (for 32K bps ADPCM)
Voice triggered starting function
Pause function
Master clock frequency: 4.096 to 8.192 MHz
Power supply voltage
MSM6688:
Single 5 V power supply
MSM6688L:
Single 3 V power supply
Package options:
56-pin plastic QFP
(QFP56-P-910-0.65-2K)
(MSM6688GS-2K)
56-pin plastic QFP
(QFP56-P-910-0.65-2K)
(MSM6688LGS-2K)
64-pin plastic TQFP
(TQFP64-P-1010-0.50-K)
(MSM6688LTS-K)
48/167
LIN
MOUT
MIN
XT
XT
MON
PDWN
ACON
MCUM
RESET
TEST
TEST
–
+
+
–
LOUT
Timing
Controller
OSC
Test
Circuit
AMON FIN
Status
Register
LPF
NAR VPM RPM BUSY
WR RD CE CE
12-bit
DAC
SG
Controller
SGC
SG
Circuit
I/O
Data
DGND
AGND
DVDD’
AVDD
DVDD
RSEL1
RSEL2
WE
CS1
CS2
CS3
CS4
TAS
RWCK
SADX
SADY
DI/O
DROM
OKI Semiconductor
AOUT FOUT ADIN
12-bit
ADC
ADPCM
Analyzer/Synthesizer
Address Controller
MCU I/F
D3 D2 D1 D0
FEDL6688-6688L-04
MSM6688/6688L
BLOCK DIAGRAM
Register
49/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
56
55
54
53
52
51
50
49
48
47
46
45
44
43
CE
RD
WR
RESET
NAR
MON
RWCK
DVDD
XT
XT
WE
DROM
DI/0
CS4
PIN CONFIGURATION (TOP VIEW)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CS3
CS2
CS1
SADX
SADY
TAS
SAS
PDWN
TEST
TEST
RSEL2
RSEL1
DGND
AGND
TEST
ADIN
FOUT
AOUT
AMON
FIN
DVDD’
AVDD
SG
SGC
LOUT
LIN
MOUT
MIN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D0
D1
D2
D3
BUSY
RPM
VPM
ACON
TEST
MCUM
CE
TEST
TEST
TEST
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CE
RD
WR
RESET
NAR
MON
NC
RWCK
DVDD
XT
XT
NC
WE
DROM
DI/0
CS4
56-Pin Plastic QFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CS3
NC
CS2
CS1
SADX
SADY
TAS
SAS
PDWN
NC
TEST
TEST
RSEL2
RSEL1
DGND
AGND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TEST
NC
ADIN
NC
FOUT
AOUT
FIN
AMON
AVDD
SG
SGC
LOUT
LIN
MOUT
MIN
NC
D0
D1
D2
D3
NC
BUSY
RPM
VPM
ACON
TEST
MCUM
NC
CE
TEST
TEST
TEST
NC: No connection
64-Pin Plastic TQFP
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
PIN DESCRIPTIONS
QFP
Pin
TQFP
Symbol
Type
Description
49
56
DVDD
—
21
—
DVDD’
—
22
25
AVDD
—
30
29
23
24
28
26
27
25
34
33
26
27
31
29
30
28
DGND
AGND
SG
SGC
MIN
LIN
MOUT
LOUT
—
—
Digital power supply pin. Insert a bypass capacitor of 0.1 µF or more
between this pin and the DGND pin.
Digital power supply pin
Analog power supply pin. Insert a bypass capacitor of 0.1 µF or
more between this pin and the AGND pin.
Digital ground pin
Analog ground pin
O
Output pin for analog circuit reference voltage (signal ground)
20
24
AMON
O
19
23
FIN
I
17
21
FOUT
O
16
19
ADIN
I
18
22
AOUT
O
39
38
44
43
SADX
SADY
O
36
41
SAS
O
37
42
TAS
O
50
57
RWCK
O
46
52
WE
O
44
50
DI/O
I/O
45
51
DROM
I
I
O
Inverting input pin of the built-in OP amplifier. Non-inverting input pin
is internally connected to SG (signal ground).
MOUT and LOUT are output pins of the built-in OP amplifier for MIN
and LIN, respectively.
This pin is connected to the LOUT pin in the recording mode and to
the DA converter output in the playback mode. Used to connect the
built-in LPF input (FIN pin).
Input pin of built-in LPF
Output pin of built-in LPF. Used to connect the AD converter input
(ADIN pin).
Input pin of the built-in 12-bit AD converter
Output pin of the built-in LPF. This pin outputs playback waveforms
and used to connect an external speaker drive amplifier.
(Serial Address Data) SADX is used to connect the SAD pin of each
external serial register and the SADX pin of each external serial
voice ROM. SADY is used to connect the SADY pin of each external
serial voice ROM. Outputs of starting address of read/write.
(Serial Address Strobe) Used to connect the SAS pin of external
serial register and the SASX and SASY pins of external serial voice
ROM Clock pin to write the serial address.
(Transfer Address Strobe) Used to connect the TAS pin of each
external serial register and serial voice ROM.
This pin outputs address strobe outputs to set the serial address
data from the SADX and SADY pins into the internal address
counter of each serial register and serial voice ROM.
(Read/Write Clock) Used to connect the RWCK pin of each external
serial register and the RDCK pin of each external serial voice ROM.
This pin outputs a clock to read data from or write it into each
external serial register.
(Write Enable) Used to connect the WE pin of each external serial
register. This pin outputs WE signal to select either read or write
mode.
(Data I/O) Used to connect the DIN and DOUT pins of DRAM and
serial register. This pin outputs the data to be written into the serial
register or inputs the data read from the serial registers.
(Data ROM) Used to connect the DOUT pin of each external serial
voice ROM.
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FEDL6688-6688L-04
OKI Semiconductor
QFP
40
41
42
43
Pin
TQFP
45
46
48
49
MSM6688/6688L
Symbol
Type
CS1
CS2
CS3
CS4
O
Description
(Chip Select) Used to connect the CS pin of serial register and the
CS (CS1, CS2, CS3) pins of each serial voice ROM.
(Register Select) These are used to select the number of external
serial registers.
31
32
35
36
RSEL1
RSEL2
I
10
11
MCUM
I
53
61
RESET
I
35
40
PDWN
I
1
2
3
4
1
2
3
4
D0
D1
D2
D3
I/O
54
62
WR
I
55
63
RD
I
56
11
64
13
CE
CE
I
5
6
BUSY
O
6
7
RPM
O
7
8
VPM
O
RSEL2
L
L
H
H
RSEL1
L
H
L
H
Number of serial registers
1
2
3
4
This pin is used to select either the stand-alone mode or the
microcontroller interface mode.
Low level: Stand-alone mode
High level: Microcontroller interface mode
A high input level at this pin causes the MSM6688/6688L to be
initialized and to go into the power down state.
(Power Down) When a low level is input to this pin, the MSM6688
goes to the power down state. Unlike the RESET pin, this pin does
not force to reset the MSM6688/6688L. When an low level is applied
to this PDWN pin during recording operation, the MSM6688/6688L is
halted, and will be maintained in the power down state while PDWN
is low. After this pin is restored to a high level, postprocessing for
recording will be performed.
Bi-directional data bus to transfer commands and data to and from
an external microcontroller.
Write pulse input pin. Inputting a low pulse to this WR pin causes a
command or data to be input via D0-D3 pins.
Read pulse input pin. Inputting a low pulse to this RD pin causes
status bits or data to be output via D0-D3 pins.
Chip enable input pins. When the CE pin is set to a low level or the
CE pin is set to a high level, the write pulse (WR), read pulse (RD)
can be accepted.
When the CE pin is set to a high level or CE pin is set to a low level,
the write pulse (WR) and read pulse (RD) cannot be accepted so
that data cannot be transferred to and from via D0-D3 pins.
Outputs a high level while a command is being executed. When this
pin is held high, do not apply any data to D0-D3 pins. The state of
this BUSY pin is the same as the contents of the BUSY bit of the
status register.
Outputs a high level during recording or playback operation. The
state of this RPM is the same as the contents of the RPM bit of the
status register.
Outputs a high level during the standby for voice after the start of
voice triggered recording and the record/playback is stopped
temporarily by inputting the PAUSE command. The state of this
VPM pin is the same as the contents of the VPM bit of the status
register.
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FEDL6688-6688L-04
OKI Semiconductor
Pin
QFP
52
TQFP
60
MSM6688/6688L
Symbol
NAR
Type
Description
O
This NAR bit indicates whether the phrase designation by the CHAN
command is enabled or disabled.
In the ROM playback operation, specify the next phrase after
making sure that the NAR output is high, and input the START
command.
8
9
ACON
I
Used to select the use or nonuse of the pop noise suppression
circuit at the analog output (AOUT) pin.
When low level, the pop noise suppression circuit is not used.
When high level, the pop noise suppression circuit is used.
47
54
XT
I
Used to connect an oscillator. When an external clock is used, input
the clock through this pin. At the power down state, this pin must be
set to the ground level.
48
55
XT
O
Used to connect an oscillator, when an external clock is used, this
pin must be left open.
51
59
MON
O
Outputs a high level while the record/playback operation is being
performed. Outputs a synchronizing clock while record/playback
activated by the EXT command is being performed.
TEST
TEST
I
Used to test the MSM6688/6688L. Input a low level to the TEST pin
and a high level to the TEST pin.
12-15, 34 14-17, 38
9, 33
10, 37
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
ABSOLUTE MAXIMUM RATINGS (for MSM6688 (5 V Version))
Parameter
Symbol
Condition
Power supply voltage
VDD
Ta = 25°C
–0.3 to +7.0
V
Input voltage
VIN
Ta = 25°C
–0.3 to VDD+0.3
V
TSTG
—
–55 to +150
°C
Storage temperature
Rating
Unit
RECOMMENDED OPERATING CONDITIONS (for R MSM6688 (5 V Version))
Parameter
Symbol
Condition
Range
Unit
VDD
DGND = AGND = 0 V
3.5 to 5.5 (Note 3)
V
Operating temperature
TOP
—
–40 to +85
°C
Master clock frequency
fOSC
—
4.0 to 8.192
MHz
Power supply voltage
ELECTRICAL CHARACTERISTICS (for MSM6688 (5 V Version))
DC Characteristics
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V (Note 3)
DGND = AGND = 0 V, Ta = –40 to +85°C
Symbol
Condition
Min.
Typ.
Max.
Unit
High input voltage
Parameter
VIH
—
0.8 × VDD
—
—
V
Low input voltage
VIL
—
—
—
0.2 × VDD
V
High output voltage
VOH
IOH = –40 µA
VDD – 0.3
—
—
V
Low output voltage
VOL
IOL = 2 mA
—
—
0.45
V
High input current (Note 1)
IIH1
VIH = VDD
—
—
10
µA
High input current (Note 2)
IIH2
VIH = VDD
—
—
20
µA
Low input current (Note 1)
IIL1
VIL = GND
–10
—
—
µA
Low input current (Note 2)
IIL2
VIL = GND
–20
—
—
µA
Operating current
consumption
IDD
fOSC = 8 MHz, no load
—
15
30
mA
During power down,
no load
—
—
10
µA
—
—
50
µA
Standby current
Consumption
IDDS
Ta = –40 to +70°C
During power down,
no load
Ta = –40 to +85°C
Notes: 1. Applies to all input pins excluding the XT pin.
2. Applies to the XT pin.
3. Recording and playback should be performed at a power supply voltage of 4.5 to 5.5 V.
For other operations such as backup for a serial register, the IC operates at 3.5 to 5.5 V.
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Analog Characteristics
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V
DGND = AGND = 0 V, Ta = –40 to +85°C
Parameter
DA output relative error
Symbol
Condition
Min.
Typ.
Max.
Unit
|VDAE|
No load
—
—
—
mV
FIN admissible input
voltage range
VFIN
—
1
—
VDD – 1
V
FIN input impedance
RFIN
—
1
—
—
MΩ
ADIN admissible input
voltage range
VADIN
—
0
—
VDD
V
ADIN input impedance
RADIN
—
1
—
—
MΩ
Op-amp open loop gain
GOP
fIN = 0 to 4 kHz
40
—
—
dB
Op-amp input impedance
RINA
—
1
—
—
MΩ
Op-amp load resistance
ROUTA
—
200
—
—
kΩ
AOUT load resistance
RAOUT
—
50
—
—
kΩ
FOUT load resistance
RFOUT
—
50
—
—
kΩ
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FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
AC Characteristics
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Symbol
RESET pulse width
RESET execution time
(Note 1) *
Min.
Typ.
Max.
Unit
tRST
1
—
—
µs
tREX
—
1
—
ms
PDWN low level time
*
tPDL
500
—
—
µs
PDWN high level time
*
tPDH
500
—
—
µs
Oscillating time after input of PDWN
*
tPX
125
—
500
µs
(Note 1) *
BUSY time after release of PDWN
tBPD
0.25
—
80
ms
RD pulse width
tRR
200
—
—
ns
Setup and hold time of CE and CE for RD
tCR
30
—
—
ns
Time from RD fall to data valid
tDRE
—
—
200
ns
Time from RD rise to data float
tDRF
—
10
50
ns
WR pulse width
tWW
200
—
—
ns
Setup and hold time of CE and CE for WR
tCW
30
—
—
ns
Data setup time to WR rise
tDWS
100
—
—
ns
Data hold time from WR rise
tDWH
30
—
—
ns
RD and WR disable time
tDRW
250
—
—
ns
tBR
—
—
1
ms
BUSY time after release of RESET
(Note 1) *
BUSY time after input of 1-nibble command
**
tB1
—
—
16
µs
BUSY time after input of 2-nibble command
**
tB2
—
—
16
µs
BUSY time after input of 3-nibble command
**
tB3
—
—
16
µs
BUSY time after input of 2-nibble or 3-nibble
command data
**
tBD
—
—
16
µs
*
tWBR
270
—
—
µs
WAIT time after output of BLKRD command block
data
*
tWDR
50
—
—
µs
BUSY time after input of ADRWR command
*
tBAW
—
—
270
µs
BUSY time after input of ADRWR command
address data
*
tBAD
—
—
50
µs
WAIT time after input of ADRRD command
*
tWAR
270
—
—
µs
WAIT time after output of ADRRD command
address data
*
tWDR
50
—
—
µs
Address control time at start of record/playback
*
tAD1
—
1
—
ms
WAIT time after input of BLKRD command
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
Note: 1. The oscillation startup stabilization time is added to tREX, tBPD and tBR.
The oscillation startup stabilization time is several tens of milliseconds for crystal oscillators
and is several hundreds of microseconds for ceramic oscillators.
56/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Time from input of
START command to
MON rise
Time from input of STOP
command to MON fall
Min.
Typ.
Max.
Unit
Flex record
*
tSTCM
—
—
50
ms
Flex playback
*
tSTCM
—
—
20
ms
Direct record/playback *
tSTCM
—
—
1
ms
ROM playback
*
tSTCM
—
—
1
ms
Flex record
*
tSPCM
—
—
80
ms
Flex playback
*
tSPCM
—
—
2
ms
Direct record/playback *
tSPCM
—
—
2
ms
ROM playback
tSPCM
—
—
2
ms
tSTCR
—
—
16
µs
tSPCR
—
—
2
ms
*
Time from input of START command to setting of
RPM bit
*
Time from input of STOP command to end of
record/playback
*
Time from input of STOP
command to release of
standby for voice
Symbol
Flex record
*
tSPCV
—
—
80
ms
Direct record
*
tSPCV
—
—
2
ms
tSTCN
—
—
16
µs
tMID
—
1.25
—
ms
tPSCP
—
—
16
µs
Time from input of START command during pause
to resetting of VPM bit
**
tSTCP
—
—
500
µs
Time from input of STOP command during pause
to resetting of VPM bit
tSPCP
—
—
500
µs
Time from input of START command to NAR bit
fall during continuos playback
*
Unvoiced time between phrases during continuous
playback
*
Time from input of PAUSE command to setting of
VPM bit
**
*
tWCRW
770
—
—
µs
WAIT time after input of REC command *
tWRC
16
—
—
µs
WAIT time after input of write data
tWWD
50
—
—
µs
WAIT time after input of command
CHRW
command
**
*
WAIT time after input of PLAY command *
tWPL
50
—
—
µs
WAIT time after input of STOP command
*
tWSP
50
—
—
µs
WAIT time after input of command
*
tWRW
16
—
—
µs
WAIT time after input of address
(2nd-5th nibbles)
*
tWA1
16
—
—
µs
tWA2
270
—
—
µs
DTRW and WAIT time after input of address
(6th nibble)
*
DTRD
commands WAIT time after input of REC command *
tWRC
16
—
—
µs
*
tWWD
50
—
—
µs
WAIT time after input of PLAY command *
tWPL
50
—
—
µs
WAIT time after input of STOP command *
tWSP
16
—
—
µs
WAIT time after input of write data
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
57/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
DVDD = DVDD’ = AVDD = 4.5 to 5.5 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Symbol
Min.
Typ.
Max.
Unit
WAIT time for deletion of all phrases after input of
DEL command
*
tWBLA
550
—
—
ms
WAIT time for deletion of a specified phase after
input of DEL command
*
tWBLI
70
—
—
ms
Time to start of DC level transition after input of
LEV command
*
tLV
—
—
16
µs
DC level transition time (GND to 1/2 VDD)
*
tAOR
—
64
—
ms
DC level transition time (1/2 VDD to GND)
*
tAOF
—
256
—
ms
tEM
—
—
330
µs
Time from input of EXT command to
MON rise
**
MON high level time
**
tMH
—
31
—
µs
MON low level time
**
tML
—
94
—
µs
Time from MON rise to RD pulse rise
during recording
**
tERD
—
—
120
µs
tEWR
—
—
120
µs
tWE1
16
—
—
µs
tESP
—
—
100
µs
tWEX
—
—
250
µs
Time from MON rise to WR pulse rise
EXT
during playback
**
command
Time from ADPCM data WR pulse to
input of STOP command during playback
**
Time from MON rise to input of STOP
command
**
Time from input of STOP command to
end of record/playback
**
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
58/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
ABSOLUTE MAXIMUM RATINGS (for MSM6688L (3 V Version))
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
VDD
Ta = 25°C
–0.3 to +7.0
V
Input voltage
VIN
Ta = 25°C
–0.3 to VDD+0.3
V
TSTG
—
–55 to +150
°C
Storage temperature
RECOMMENDED OPERATING CONDITIONS (for MSM6688L (3 V Version))
Parameter
Symbol
Condition
Range
Unit
VDD
DGND = AGND = 0 V
2.7 to 3.6
V
Operating temperature
TOP
—
–40 to +85
°C
Master clock frequency
fOSC
—
4.0 to 8.192
MHz
Power supply voltage
ELECTRICAL CHARACTERISTICS (for MSM6688L (3 V Version))
DC Characteristics
DVDD = DVDD’ = AVDD = 2.7 to 3.6 V
DGND = AGND = 0 V, Ta = –40 to +85°C
Symbol
Condition
Min.
Typ.
Max.
Unit
High input voltage
Parameter
VIH
—
0.85 × VDD
—
—
V
Low input voltage
VIL
—
—
—
0.15 × VDD
V
High output voltage
VOH
IOH = –40 µA
VDD – 0.3
—
—
V
Low output voltage
VOL
IOL = 2 mA
—
—
0.45
V
High input current (Note 1)
IIH1
VIH = VDD
—
—
10
µA
High input current (Note 2)
IIH2
VIH = VDD
—
—
20
µA
Low input current (Note 1)
IIL1
VIL = GND
–10
—
—
µA
Low input current (Note 2)
IIL2
VIL = GND
–20
—
—
µA
Operating current
consumption
IDD
fOSC = 8 MHz, no load
—
15
30
mA
During power down,
no load
—
—
15
µA
—
—
100
µA
Standby current
Consumption
IDDS
Ta = –40 to +70°C
During power down,
no load
Ta = –40 to +85°C
Notes: 1. Applies to all input pins excluding the XT pin.
2. Applies to the XT pin.
59/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Analog Characteristics
DVDD = DVDD’ = AVDD = 2.7 to 3.6 V
DGND = AGND = 0 V, Ta = –40 to +85°C
Parameter
DA output relative error
Symbol
Condition
Min.
Typ.
Max.
Unit
|VDAE|
No load
—
—
10
mV
FIN admissible input
voltage range
VFIN
—
1/4 × VDD
—
3/4 × VDD
V
FIN input impedance
RFIN
—
1
—
—
MΩ
ADIN admissible input
voltage range
VADIN
—
0
—
VDD
V
ADIN input impedance
RADIN
—
1
—
—
MΩ
Op-amp open loop gain
GOP
fIN = 0 to 4 kHz
40
—
—
dB
Op-amp input impedance
RINA
—
1
—
—
MΩ
Op-amp load resistance
ROUTA
—
200
—
—
kΩ
AOUT load resistance
RAOUT
—
50
—
—
kΩ
FOUT load resistance
RFOUT
—
50
—
—
kΩ
60/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
AC Characteristics
DVDD = DVDD’ = AVDD = 2.7 to 3.6 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Symbol
RESET pulse width
RESET execution time
(Note 1) *
Min.
Typ.
Max.
Unit
tRST
1
—
—
µs
tREX
—
1
—
ms
PDWN low level time
*
tPDL
500
—
—
µs
PDWN high level time
*
tPDH
500
—
—
µs
Oscillating time after input of PDWN
*
tPX
125
—
500
µs
(Note 1) *
BUSY time after release of PDWN
tBPD
0.25
—
80
ms
RD pulse width
tRR
200
—
—
ns
Setup and hold time of CE and CE for RD
tCR
30
—
—
ns
Time from RD fall to data valid
tDRE
—
—
200
ns
Time from RD rise to data float
tDRF
—
10
50
ns
WR pulse width
tWW
200
—
—
ns
Setup and hold time of CE and CE for WR
tCW
30
—
—
ns
Data setup time to WR rise
tDWS
100
—
—
ns
Data hold time from WR rise
tDWH
30
—
—
ns
RD and WR disable time
tDRW
250
—
—
ns
tBR
—
—
1
ms
BUSY time after release of RESET
(Note 1) *
BUSY time after input of 1-nibble command
**
tB1
—
—
16
µs
BUSY time after input of 2-nibble command
**
tB2
—
—
16
µs
BUSY time after input of 3-nibble command
**
tB3
—
—
16
µs
BUSY time after input of 2-nibble or 3-nibble
command data
**
tBD
—
—
16
µs
*
tWBR
270
—
—
µs
WAIT time after output of BLKRD command block
data
*
tWDR
50
—
—
µs
BUSY time after input of ADRWR command
*
tBAW
—
—
270
µs
BUSY time after input of ADRWR command
address data
*
tBAD
—
—
50
µs
WAIT time after input of ADRRD command
*
tWAR
270
—
—
µs
WAIT time after output of ADRRD command
address data
*
tWDR
50
—
—
µs
Address control time at start of record/playback
*
tAD1
—
1
—
ms
WAIT time after input of BLKRD command
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
Note: 1. The oscillation startup stabilization time is added to tREX, tBPD and tBR.
The oscillation startup stabilization time is several tens of milliseconds for crystal oscillators
and is several hundreds of microseconds for ceramic oscillators.
61/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
DVDD = DVDD’ = AVDD = 2.7 to 3.6 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Time from input of
START command to
MON rise
Time from input of STOP
command to MON fall
Min.
Typ.
Max.
Unit
Flex record
*
tSTCM
—
—
50
ms
Flex playback
*
tSTCM
—
—
20
ms
Direct record/playback *
tSTCM
—
—
1
ms
ROM playback
*
tSTCM
—
—
1
ms
Flex record
*
tSPCM
—
—
80
ms
Flex playback
*
tSPCM
—
—
2
ms
Direct record/playback *
tSPCM
—
—
2
ms
ROM playback
tSPCM
—
—
2
ms
tSTCR
—
—
16
µs
tSPCR
—
—
2
ms
tSPCV
—
—
80
ms
tSPCV
—
—
2
ms
tSTCN
—
—
16
µs
tMID
—
1.25
—
ms
tPSCP
—
—
16
µs
tSTCP
—
—
500
µs
tSPCP
—
—
500
µs
tWCRW
tWRC
tWWD
770
16
50
—
—
—
—
—
—
µs
µs
µs
*
Time from input of START command to setting of
RPM bit
*
Time from input of STOP command to end of
record/playback
*
Flex record
*
Time from input of STOP
command to release of
Direct record
*
standby for voice
Time from input of START command to NAR bit fall
during continuos playback
*
Unvoiced time between phrases during continuous
playback
*
Time from input of PAUSE command to setting of
VPM bit
**
Time from input of START command during pause
to resetting of VPM bit
**
Time from input of STOP command during pause to
resetting of VPM bit
**
CHRW
command
Symbol
WAIT time after input of command
*
WAIT time after input of REC command *
WAIT time after input of write data
*
WAIT time after input of PLAY command
*
WAIT time after input of STOP command *
tWPL
50
—
—
µs
tWSP
50
—
—
µs
WAIT time after input of command
tWRW
16
—
—
µs
tWA1
16
—
—
µs
*
WAIT time after input of address
(2nd-5th nibbles)
*
WAIT
time
after
input
of
address
DTRW
*
and DTRD (6th nibble)
commands WAIT time after input of REC command *
WAIT time after input of write data
*
WAIT time after input of PLAY command *
tWA2
270
—
—
µs
tWRC
tWWD
tWPL
16
50
50
—
—
—
—
—
—
µs
µs
µs
WAIT time after input of STOP command *
tWSP
16
—
—
µs
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
62/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
DVDD = DVDD’ = AVDD = 2.7 to 3.6 V
DGND = AGND = 0 V, Ta = –40 to +85°C
fOSC = 4.096 MHz, fSAMP = 8.0 kHz
Parameter
Symbol
Min.
Typ.
Max.
Unit
WAIT time for deletion of all phrases after input of
DEL command
*
tWBLA
550
—
—
ms
WAIT time for deletion of a specified phrase after
input of DEL command
tWBLI
70
—
—
ms
tLV
—
—
16
µs
*
Time to start of DC level transition after input of LEV
command
*
DC level transition time (GND to 1/2 VDD)
*
tAOR
—
64
—
ms
DC level transition time (1/2 VDD to GND)
*
tAOF
—
256
—
ms
tEM
—
—
330
µs
Time from input of EXT command to
MON rise
**
MON high level time
**
tMH
—
31
—
µs
MON low level time
**
tML
—
94
—
µs
Time from MON rise to RD pulse rise
during recording
**
tERD
—
—
120
µs
tEWR
—
—
120
µs
tWE1
16
—
—
µs
tESP
—
—
100
µs
tWEX
—
—
250
µs
Time from MON rise to WR pulse rise
EXT
during playback
**
command
Time from ADPCM data WR pulse to
input of STOP command during playback
**
Time from MON rise to input of STOP
command
**
Time from input of STOP command to
end of record/playback
**
Items with * are proportional to the period of master clock frequency fOSC.
Items with ** are proportional to the period of the master clock frequency fOSC, and are also
proportional to the sampling frequency fSAMP during record/playback.
63/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
TIMING DIAGRAMS
Reset Function
VDD
tRST
RESET (I)
tREX
BUSY (O)
Hi-Z
Undefined
Power down
Standby for
Reset operation
record/playback
in progress
64/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Power Down by the PDWN pin
tPDL
tPDH
PDWN (I)
tPX Note 1
XT
(I)
XT
(O)
Oscillation in progress
Oscillation in progress
tBPD
BUSY (O)
Hi-Z
RPM
(O)
Hi-Z
VPM
(O)
Hi-Z
NAR
(O)
Hi-Z
Power down
Postprocessing
Standby
WR and RD pulses are not accepted
Note: 1. When an external clock is used, apply a low level to the PDWN pin and then continue to
apply the external clock to the XT pin for tPX.
65/167
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
Data Read Timing (RD Pulse)
CE
(I)
CE
(I)
tCR
RD
tCR
(I)
tRR
tDRE
D0-D3
tDRF
(I/O)
Data Write Timing (WR Pulse)
CE
(I)
CE
(I)
tCW
WR
tCW
(I)
tWW
tDWS
D0-D3
tDWH
(I/O)
66/167
tB1:
tWBLA:
tWBL1:
Status register
BUSY bit
(I/O)
(I)
RD
D0-D3
(I)
WR
Command input
Status output
NOP, PAUSE, PLAY, REC, START, and STOP commands
DEL command (deletion of all phrases)
DEL command (deletion of a specified phrase)
tB1, tWBLA, tWBL1
Status output
tDRW
Inputting 1-Nibble Commands (NOP, PAUSE, PLAY, REC, START, STOP and DEL Commands)
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
67/167
Status output
tDRW
Data input
(2nd nibble)
tBD
Command input
(1st nibble)
tB2
The LEV command is used to specify the playback level.
See the timing diagram for DC level transition by the LEV command.
Status register
BUSY bit
(I/O)
(I)
RD
D0-D3
(I)
WR
Inputting 2-Nibble Commands (SAMP, VDS, and LEV Commands)
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
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(I)
(I/O)
RD
D0-D3
Status register
BUSY bit
(I)
WR
Status output
tDRW
Command input
(1st nibble)
tB3
Inputting 3-Nibble Commands (CHAN and BLKWR Commands)
Data input
(2nd nibble)
tBD
Data input
(3rd nibble)
tBD
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
69/167
Status output
Command input
(1st nibble)
tWBR
Data output
(2nd nibble)
tWDR
the RD pulse either after the waiting time tWBR or tWDR or after verifying the BUSY state at BUSY
output pin.
However, the status of the BUSY bit cannot be verified by inputting the RD pulse. Therefore, input
1. After making sure that the MSM6688/6688L is not in the busy state by checking the BUSY bit of
the status register, input the BLKRD command.
2. Then, the data is read according to the 2nd and 3rd nibble command.
Status register
BUSY bit
(I/O)
(I)
RD
D0-D3
(I)
WR
Inputting the BLKRD Command
Data output
(3rd nibble)
tWDR
Input of WR and RD
pulses enabled
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
70/167
(I/O)
(I)
(I)
Status
output
ADRWR command Address data
input (1st nibble)
input (2nd nibble)
tBAW
tBAD
Address data input
(3rd nibble)
tBAD
Address data input
(11th nibble)
Input of WR
tBAD
pulse enabled
•
Input the next WR pulse after the waiting time tBAW or tBAD.
1. After making sure that the MSM6688/6688L is not in the busy state by checking the BUSY bit of
the status register, input the ADRWR command.
2. Then, input 2nd-11th nibble address data after making sure that the MSM6688 is not in the BUSY
state by one of the following two methods.
• Check of the BUSY bit in the status register
Status register
BUSY bit
D0-D3
RD
WR
Inputting the ADRWR Command
FEDL6688-6688L-04
OKI Semiconductor
MSM6688/6688L
71/167
Status output
Command input
(1st nibble)
tWAR
Address data Address data
output
output
(2nd nibble)
(3rd nibble)
tWDR
Therefore, input the RD pulse either after the waiting time tWAR or tWDR or after verifying the BUSY
state at the BUSY output pin.
The state of the BUSY bit cannot be checked by the RD pulse.
1. After making sure that the MSM6688/6688L is not in the busy state by checking the BUSY bit of
the status register, input the ADRRD command.
2. Then, the address data is read according to 2nd through 11th nibble command.
Status register
BUSY bit
(I/O)
(I)
RD
D0-D3
(I)
WR
Inputting the ADRRD Command
Address data
output
(11th nibble)
tWDR
Input of WR and
RD pulses enabled
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(I)
(I/O)
(I)
WR
D0-D3
MON
(O)
tBR
tSTCR
Standby
tB1
Address control
tAD1
START command
tSTCM (Note)
Record/playback
tSPCR
tB1
Standby
Address control
(STOP
tSPCM (Note)
Power down
OKI Semiconductor
Note: tSTCM and tSPCM vary depending on the control mode for record/playback and on record or
playback mode.
Power down
AOUT
(playback)
NAR bit
RPM bit
BUSY bit
Status register
(I)
RESET
Timing for Record/Playback by START Command
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(I/O)
(O)
D0-D3
MON
Standby
tB1
tB1
tSPCV (Note)
Voice detected
Recording
tSPCR
tB1
Standby
(STOP command)
tSPCM
Address control
If the STOP command is input during standby for voice,
this state is changed to the standby for recording.
Address control
tAD1
(STOP command)
Standby for voice
tSTCR
START command
OKI Semiconductor
Note: tspcv varies depending on the recording mode (flex recording or direct recording).
NAR bit
VPM bit
RPM bit
BUSY bit
Status register
(I)
WR
Timing for Voice Triggered Recording
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(O)
(I/O)
(I)
AOUT
NAR bit
RPM bit
(O)
Status register
MON
D0-D3
WR
tSTCR
Standby
CHAN command
(1st phrase)
tSTCM
tAD1
tSTCN
tMID
Address control
START command
1st phrase playback
CHAN command
(2nd phrase)
Address control
START
d
Timing for Continuous ROM Playback by Input of Address Code
2nd phrase playback
Standby
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(O)
MON
VPM bit
RPM bit
BUSY bit
Status register
(I/O)
(I)
RD
D0-D3
(I)
WR
Standby
tSTCR
tB1
tB1
Pause
tPSCP
PAUSE
command
Record/playback
START
tSTCM command
Timing for Record/Playback Pause Operation by PAUSE Command
tSTCP
tB1
tB1
tPSCP
tSPCP
tB1
tSPCM
Standby
STOP command
Pause
PAUSE
command
Record/playback
START
command
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(I/O)
(I)
RD
D0-D3
(I)
WR
Command execution
tWCRW
tWRC
Write data
tWWD
Write access
REC
command
Timing for Data Transfer by CHRW Command
Read data
Read access
PLAY
command
tWPL
Next command
input enabled
STOP
command
tWSP
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(I)
RD
D0-D3 (I/O)
(I)
WR
DTRW
command
tWA2
Address input
X12 to X15
Dummy X4 to X7
“0h”
X0 to X3 X8 to X11
tWRW tWA1 tWA1 tWA1 tWA1
Timing for Data Transfer by DTRW Command
tWWD
Write access
REC
Write data
command
tWRC
Read access
PLAY
Read data
command
tWPL
STOP
command
tWSP
Next command
input enabled
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(I)
RD
D0-D3 (I/O)
(I)
WR
tWA2
Address input
DTRD
Dummy “0h”
Y address X4 to X7
command
X0 to X3 X8 to X11
tWRW tWA1 tWA1 tWA1 tWA1
Timing for Data Read by DTRD command
Read access
PLAY
Read data
command
tWPL
Input of next
command enabled
STOP
command
tWSP
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(I)
(I/O)
(O)
RD
D0-D3
MON
Power down
tEM
EXT
command
Standby
REC
command
tMH
tML
ADPCM data
Recording
tERD
tESP
ADPCM data
Standby
Next command
input enable
STOP command
Power down
tWEX
1. When reading the ADPCM data, input the RD pulse to satisfy time tERD from rise of MON to
rise of the rise of RD pulse.
2. Input the STOP command when the MON pin is “H”, after reading the ADPCM data. At that
time, it is required to satisfy time tESP from rise of MON to input of the STOP command.
(I)
WR
Notes:
(I)
RESET
Recording by EXT Command
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(I)
(I/O)
(O)
(O)
RD
D0-D3
MON
AOUT
Power down
Standby
GND level
1/2 VDD level
EXT
PLAY
command command
tEM
Status
output
tMH
tML
ADPCM data
Playback
tEWR
tESP
ADPCM data
Standby
GND level
1/2 VDD level
Next command
input enable
Power down
tWEX
STOP command
tWE1
1. When writing the ADPCM data, input the WR pulse to satisfy time tEWR from rise of MON to rise of the WR pulse.
2. Input the STOP command when the MON pin is “H”, after writing the ADPCM data. At that time,
it is required to satisfy time tESP from rise of MON to input of the STOP command, and interval tWE1 between the
WR pulse and the STOP command pulse.
3. Input the ADPCM data beginning with the top of a phrase every sampling period sequentially.
If the ADPCM data is input beginning with the second or following part of a phrase or with data missing, normal
(playback) waveforms cannot be regenerated.
(I)
WR
Notes:
(I)
RESET
Playback by EXT Command
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(I)
(I/O)
WR
D0-D3
AOUT
Power down
(O)
NAR bit
BUSY bit
Status register
(I)
RESET
Standby
tLV
LEV
command
GND level
PLAY
command
tAOR
DC level transition
Timing for DC Level Transition by LEV Command
Record/playback
tLV
LEV
command
1/2 VDD level
PLAY
command
DC level transition
Standby
GND level
tAOF
Power down
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FUNCTIONAL DESCRIPTION
Recording Time and Memory Capacity
The recording time depends on the memory capacity of the external serial registers, sampling frequency, and
ADPCM bit length, and is given by
1.024 × memory capacity (K bits)
Recording time =
(seconds)
sampling frequency (kHz) × bit length (bits)
4096
For example, if the sampling frequency is
kHz (= 5.333 kHz), ADPCM bit length is 3 bits, and four 8M
768
bit serial registers are used, the recording time can be obtained as follows.
1.024 × (8192 × 4 – 64)
= 2093 seconds
5.333 × 3
= 34 minutes 53 seconds
In the above equation, the memory capacity is obtained by subtracting the memory capacity (64K bits) for the
channel index area from the total memory capacity.
Recording time =
Connection of an Oscillator
Connect a ceramic oscillator or a crystal oscillator to XT and XT pins as shown below. The optimal load
capacities when connecting ceramic oscillators from MURATA MFG., KYOCERA CORPORATION, and TDK
CORPORATION are shown below for reference.
MSM6688
MSM6688L
XT
XT
C1
C2
1. MSM6688
Ceramic oscillator
MURATA MFG.
Type
CSTLS4M00G53-B0
(with capacitor)
CSTCR4M00G53-R0
(with capacitor)
CSTLS6M00G53-B0
(with capacitor)
CSTCR6M00G53-R0
(with capacitor)
CSTLS8M00G53-B0
(with capacitor)
CSTCC8M00G53-R0
(with capacitor)
Freq. (MHz)
Optimal load
capacity
C1 (pF)
C2 (pF)
Power supply
voltage (V)
Operating
temperature (°C)
3.5 to 5.5
–40 to +85
4.0
6.0
—
—
8.0
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MSM6688/6688L
Ceramic oscillator
KYOCERA CORP.
Type
KBR-4.0MSA
KBR-4.0MKS
(with capacitor)
Freq. (MHz)
Optimal load
capacity
C1 (pF)
C2 (pF)
Power supply
voltage (V)
Operating
temperature (°C)
3.5 to 5.5
–40 to +85
4.0
PBRC4.00A
PBRC4.00B
KBR-6.0MSA
KBR-6.0MKS
(with capacitor)
6.0
33
33
PBRC6.00A
PBRC6.00B
KBR-8.0M
PBRC8.00A
PBRC8.00B
8.0
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MSM6688/6688L
2. MSM6688L
Ceramic oscillator
Type
MURATA MFG.
CSTLS4M00G53-B0
(with capacitor)
CSTCR4M00G53-R0
(with capacitor)
CSTLS6M00G53-B0
(with capacitor)
CSTCR6M00G53-R0
(with capacitor)
CSTLS8M00G53-B0
(with capacitor)
CSTCC8M00G53-R0
(with capacitor)
Freq. (MHz)
Optimal load
capacity
C1 (pF)
C2 (pF)
Power supply
voltage (V)
Operating
temperature (°C)
4.0
6.0
—
—
2.7 to 3.6
–40 to +85
33
33
2.7 to 3.6
–40 to +85
33
33
—
—
33
33
—
—
2.7 to 3.6
–40 to +85
—
—
33
33
—
—
8.0
KBR-4.0MSB
KBR-4.0MKC
(with capacitor)
KYOCERA CORP.
PBRC4.00A
4.0
PBRC4.00B
(with capacitor)
KBR-6.0MSB
KBR-6.0MKC
(with capacitor)
PBRC6.00A
6.00
PBRC6.00B
(with capacitor)
KBR-8.0M
PBRC8.00A
PBRC8.00B
(with capacitor)
8.0
FCR4.0M5
TDK CORP.
FCR4.0MC5
(with 30pF capacitor)
4.0
FCR6.0M5
FCR6.0MC5
(with 30pF capacitor)
6.0
CCR6.0MC3
(with capacitor)
FCR8.0M2S
CCR8.0MC5
(with capacitor)
8.0
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MSM6688/6688L
Power Supply Wiring
As shown in the following diagram, supply the power to this MSM6688 from the same power source, but
separate the power supply wiring to the analog portion from that to the logic position.
+5 V
DVDD’ DVDD AVDD
MSM6688
MSM6688L
DGND AGND
The following connections are not permitted.
Analog power supply
Digital power supply
+5 V
DVDD DVDD’ AVDD
DVDD DVDD’
AVDD
Configuring SGC and SG pins
The internal equivalent circuit around the SGC and SG pins is shown below.
AVDD
MSM6688
MSM6688L
50 kΩ
(TYP)
+
–
SGC
50 kΩ
(TYP)
AGND
To OP amplifier,
LPF
SG
20 kΩ (TYP)
AGND
Power-down signal
Switch is open
at power-down
AGND
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The SG signal is a reference voltage (signal ground) for internal OP amplifiers and LPF.
Install a capacitor between the SGC pin and AGND and between the SG pin and AGND respectively in order to
make the SG signal noiseless. It is recommended to use an approx. 0.1 µF capacitor, which should be
determined after evaluating the tone quality.
It takes several ten msec until the DC levels such as the SG level of the analog circuit is stabilized after the
power-down mode is cancelled. The larger capacitance of a capacitor connected to SGC or SG requires the
longer time for stabilizing.
After the power-down mode is cancelled, enter voices after the DC levels for the analog circuit has been
stabilized.
When the device is in power-down mode, the output voltage of the SG pin becomes unstable. Therefore, SG
must not be supplied to external circuits.
Otherwise, power supply current may be leaked via the internal SG circuit.
Same is true for the SGC pin.
Analog Input Amplifier Circuit
This MSM6688 has two built-in operational amplifiers for amplifying the microphone output. Each OP amplifier
is provided with the inverting input pin and output pin. The analog circuit reference voltage SG (signal ground)
is connected internally to the non-inverting input of each OP amplifier.
For amplification, form an inverting amplifier circuit and adjust the amplification factor by using external
resistors as shown below.
VMO
VIN
– +
R2
R1
MIN
VLO
R3
MOUT
LIN
–
+ OP amp 1
SG
VLO=
R4
R3
VMO=
VDD
VLO
R4
VFIN (max.)
LOUT
1/2VDD
–
+ OP amp 2
R2 • R4
R1 • R3
VFIN (min.)
GND
VIN(V)
During recording, the output VLO of OP amp 2 is connected to the input FIN of the LPF. Adjust the amplification
factor by using the external resistors so that the VLO amplitude is within the FIN admissible input voltage (VFIN)
range.
If VLO exceeds the VFIN range, the LPF output waveform will be distorted.
The table below shows an example of the allowable FIN input voltage range for the MSM6688 and MSM6688L.
Allowable FIN input voltage range VFIN
Parameter
Power supply
voltage VDD
MSM6688
5V
1V
4V
3 Vp-p
MSM6688L
3V
0.75 V
2.25 V
1.5 Vp-p
Min.
Max.
Allowable FIN input
voltage
The value of the OP amplifier load resistance ROUTA is 200 kΩ minimum. Therefore the values of the inverting
amplifier circuit feedback resistors R2 and R4 should be 200 kΩ or more.
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When OP amplifier 1 is not used and OP amplifier 2 is used, the MIN pin must be connected to AGND or AVDD,
and the MOUT pin must be open.
Even if amplification is unnecessary, OP amplifier 2 must be always used.
Below is an example of an analog input amplifier circuit when the amplification factor is 1.
Input signal
AGND
(or AVDD)
MIN
SG
(200 kΩ)
R3
MOUT
–
+ OP amplifier 1
LIN
(200 kΩ)
R4
LOUT
–
+ OP amplifier 2
MSM6688
MSM6688L
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Connection of LPF Circuit Peripherals
The AMON pin is connected internally to the output of the amplifier circuit (LOUT pin) in the recording mode
and to the output of the built-in DA converter in the playback mode. Therefore, connect the AMON pin directly
to the input (FIN pin) of the built-in LPF.
Both the FOUT and AOUT pins are the output pins of the built-in LPF. Connect the FOUT pin to the input
(ADIN pin) of the built-in AD converter and connect the AOUT pin to an external speaker through an external
speaker drive amplifier.
In the MSM6688/6688L, the connection of each of the FOUT and AOUT pins is changed to one of the output of
the LPF, GND (ground) level, and SG (signal ground) level, depending on the operation status as shown below.
Analog pin
At power down
(RESET pin = H)
FOUT pin
AOUT pin
During operation (RESET pin = L)
Recording mode
Playback mode
GND level
LPF output
(recording waveform)
LPF output
GND level
SG level
LPF output
(playback waveform)
Speaker drive amplifier
LIN
LOUT
–
+
SG
AMON
AOUT
FIN
FOUT ADIN
Record
mode
Playback
mode
LPF
Playback
mode
–
+
Record mode
SG
GND
DAC
ADC
Power
down
–
+
Power down
GND
Note: This diagram shows the state of each switch during the recording operation.
LPF Characteristics
This MSM6688/6688L contains a fourth-order
switched-capacitor LPF.
The attenuation characteristic of this LPF is –40
dB/oct. The cut-off frequency and frequency
characteristics of this LPF vary in proportion to
the sampling frequency (fSAMP). The cut-off
frequency is preset to 0.4 times the sampling
frequency. The following graph depicts the
frequency characteristics of the LPF at fSAMP
= 8 kHz.
[dB] 20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
100
1K
10K
[Hz]
LPF Frequency Characteristics (fSAMP = 8.0 kHz)
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Full Scale of A/D and D/A Converters
Full scale of A/D and D/A converters
Parameter
Min. (V)
Max. (V)
Amplitude (Vp-p)
MSM6688
0
VDD
VDD
MSM6688L
1/4 × VDD
3/4 × VDD
1/2 × VDD
1. When the MSM6688 is used
VDD (5 V)
VDD–1 (4 V)
1
V (2.5 V)
2 DD
1 V (1 V)
0 V (0 V)
Full scale of A/D and D/A converters
LPF admissible input voltage range
Note:
Value in parentheses applies when VDD = 5.0 V.
2. When the MSM6688L is used
VDD (3 V)
3 V (2.25 V)
DD
4
1 V (1.5 V)
2 DD
1 V (0.75 V)
4 DD
0 V (0 V)
Full scale of A/D and D/A converters
LPF admissible input voltage range
Note:
Value in parentheses applies when VDD = 3.0 V.
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Reset Function
By applying a high level to the RESET pin, the MSM6688/6688L stops oscillation to minimize current
consumption and goes to the power-down state. At the same time, the control circuit is reset and initialized.
When this reset operation is performed, the record/playback condition, such as sampling frequency and ADPCM
bit length, and the data stored in the serial registers are set to the data stored just before the reset takes place. In
this case, the playback level is set to 0 dB amplitude.
If a high level is applied to the RESET pin during command execution or record/playback operation, the
MSM6688/6688L is set to the power-down state and initialized state. Internal data and voice data become
undefined.
The following shows the power-down state of the MSM6688/6688L.
(1) Oscillation is stopped and all operations of the internal circuit are halted.
(2) The current consumption is minimized. When an external clock is used, apply a ground (GND) level to the
XT pin at power down so that no current can flow into the oscillation circuit.
(3) D0-D3 pins constituting the data bus go to the high-impedance state, independent of the state of the RD,
CE, and CE pins.
(4) CS1-CS4 pins are set to a high level to minimize the current consumption of external serial registers and
serial voice ROMs.
(5) The state of the output pins and input/output pins are as follows.
Pin name
Power down mode
with RESET = “H”
Power down mode
with PDWN = “L”
SAS, TAS, CS1-CS4, RWCK
“H” level
“H” level
SADX, WE, NAR
“H” level
“H” level or “L” level
SADY
“L” level
“H” level or “L” level
MON
“L” level
“L” level
Hi-Z
Hi-Z
Hi-Z
“H” “L” or Hi-Z
GND level
GND level
D0-D3, BUSY, RPM, VPM
DI/O
AOUT, FOUT
After powering up the MSM6688/6688L, be sure to initialize it by applying a high level to the RESET pin.
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Power Down by the PDWN pin
By applying a low level to the PDWN pin, the MSM6688/6688L is set to the power-down state, in which the
frequency oscillation and all operations of internal circuits are halted. Unlike the reset operation by the RESET
input, the control circuit will not be initialized by this power-down operation.
The power-down operation will not affect the data in the internal control circuit and external serial registers.
Therefore, this power-down operation is useful when the battery backup takes place in case of power failure.
When PDWN goes to a low level during command execution, this execution of command is halted at the time
that power-down operation is performed. When PDWN becomes low during one of the following operations,
their respective operations will be performed after the power-down state is released (PDWN = H).
(1) When the MSM6688/6688L is powered down (PDWN = L) during the record/playback operation: The
record/playback operation is stopped. After the release of the power-down state, the postprocessing will be
performed. The end of the postprocessing can be verified by checking the BUSY bit and RPM bit of the
status register.
(2) When the MSM6688/6688L is powered down (PDWN = L) during the phrase deleting operation: The
phrase deleting operation is temporarily stopped and will be restarted after the release of the power-down
state. The end of the phrase deleting operation can be verified by checking the BUSY bit.
(3) When the MSM6688/6688L is powered down (PDWN = L) during the time the transition of the AOUT
output to a DC level by LEV command is in progress: This transition operation is temporarily stopped and
will be continued after the release of the power-down state. The end of the transition to a DC level can be
verified by checking the BUSY bit.
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Record/Playback Control Modes
There are four types of record/playback mode: flex record/playback, ROM playback by inputting address codes,
direct record/playback, and direct ROM playback modes. A desired record/playback control mode can be
selected by the command mode set in the SAMP command.
Record/playback
control mode
Flex
record/playback
ROM playback by
input of address
code
Direct
record/playback
Direct ROM
playback
Command mode
Mode 0
Mode 1
Mode 2
Mode 3
Number of phrases
63
255
64 (expandable)
As required
Addressing
Indirect addressing
by phrase
designation
Indirect addressing
by phrase
designation
Direct addressing
by ADRWR
command
Direct addressing
by ADRWR
command
Setting of recording
time
Setting by BLKWR
command
—
Setting by ADRWR
command
—
1. Flex record/playback
The recording area for each phrase is indirectly specified by phrase designation (CA0-CA5, 63 phrases). The
recording area for each phrase is controlled by the MSM6688/6688L, so that the address control load of the
microcontroller can be reduced.
The recording time is specified by the BLKWR command. During recording operation, the MSM6688/6688L
searches the memory areas that are not used by other phrases and writes the voice data on them. Therefore, the
phrase control by the microcontroller can be performed easily even in applications in which it is required to
perform phrase deletion and re-recording frequently.
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2. ROM playback by input of address codes
The playback area of each phrase of the fixed message is indirectly specified by phrase designation (CA0-CA7,
255 phrases).
The table containing the start address and stop address that indicate the playback area, sampling frequency and
ADPCM bit length, is written in the index area of the serial voice ROM.
3. Direct record/playback
The recording area for each phrases is specified directly by inputting the address set in the ADRWR command
from the microcontroller after a desired phrase has been specified by phrase designation (CA0-CA5, 64 phrases).
This means that the address control such as the allocation of memory capacity (recording time) for each phrases
is performed by the microcontroller.
This direct record/playback mode is suitable for the case where the number of phrases and the recording time
allocated to each phrase are fixed. If the table containing the start address and stop address of each phrase is
stored in the microcontroller or an external circuit, it becomes possible to perform record/playback of 65 or more
phrases.
4. Direct ROM playback
The playback area of each phrase for a fixed message is specified directly by inputting the address set in the
ADRWR command from the microcontroller. In this case, it is required to store the table containing the start and
stop addresses of each phrase, sampling frequency and ADPCM bit length in the microcontroller and the
external ROM.
If a serial voice ROM products for the MSM6388/MSM6588/6588L ADPCM solid state recorders are used for
the MSM6688/6688L, this direct ROM playback mode is applied.
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Data Configuration of External Serial Registers
The external RAM constitutes a virtual memory with a address space of (X addresses in the word direction) ×
(depth of 1K bits) through the DRAM interface (MSM6791).
This virtual memory is addressable only for X addresses in the word direction.
The external RAM is divided into the channel index area that stores the data for address control of each phrase
and the voice (ADPCM) data area.
The address space and channel index area in the flex record/playback mode are different from those in the direct
record/playback mode.
1. Address space allocation of external serial registers
1.1 Address space for the flex record/playback mode
In the flex record/playback mode, the total memory capacity of external serial registers is equally divided into
256 blocks that are addressable by 00h-FFh.
Each block is composed of multiple words each having the depth of 1K bits. X addresses in the word direction
are offset addresses in the blocks. The memory capacity of one block and the maximum address of X addresses
vary depending on the total memory capacity of serial registers externally connected.
RSEL2
L
L
H
H
RSEL1
L
H
L
H
8M bits (1)
16M bits (2)
24M bits (3)
32M bits (4)
32K bits
64K bits
128K bits
128K bits
16 kbps
2.0 seconds
4.1 seconds
8.2 seconds
8.2 seconds
24 kbps
1.4 seconds
2.7 seconds
5.5 seconds
5.5 seconds
32 kbps
1.0 seconds
2.0 seconds
4.1 seconds
4.1 seconds
Number of words of one block
[Offset address]
32 words
[00h-1Fh]
64 words
[00h-3Fh]
128 words
[00h-7Fh]
128 words
[00h-7Fh]
Number of initially available blocks
254 (FEh)
255 (FFh)
191 (BFh)
255 (FFh)
Total memory capacity
(Number of serial registers)
Memory capacity of one block
Recording time of one
block
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The storing method of 1K-bit ADPCM data in the Y direction varies depending on the ADPCM bit length (3-bit
ADPCM or 4-bit ADPCM).
(1) For 3-bit ADPCM, (3 bits × 340 samples + unused 4 bits = 1024 bits) are stored in the 1K-bit memory area.
One Y address is allocated to two ADPCM data samples, so that Y addresses are addressable by 00-A9h
(2) For 4-bit ADPCM, (4 bits × 256 samples = 1024 bits) are stored in the 1K-bit memory area.
One Y address is allocated to two ADPCM data samples, so that Y addresses are addressable by 00-7Fh
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Address Space Allocation of RAM
(Flex record/playback, 32M-bit)
Block (256 blocks ranging from 00h to FFh, 1 block = 128K bits)
Channel index area (64 words × 1K bits = 64K bits)
1K bits
X address
00h
01h
(offset address in one block, 128 words from 00h to 7Fh,
1 word = 1K bits)
8 Mbit
CS1
1K bits in the Y direction
00h
01h
02h
8 Mbit
CS2
40h
41h
128 words
3Eh
3Fh
1 block = 128 words × 1K bits
= 128K
7Eh
7Fh
8 Mbit
CS3
80h
81h
7Eh
7Fh
BEh
BFh
8 Mbit
CS4
C0h
C1h
FEh
FFh
Y Address
00h
For 3-bit
ADPCM
For 4-bit
ADPCM
01h
02h
6-bits 6-bits 6-bits
A7h
A8h
A9h
6-bits 6-bits 10-bits
00h
01h
7Eh
7Fh
8-bits
8-bits
8-bits
8-bits
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1.2 Address space allocation in the direct record/playback mode
In the direct record/playback mode, address control is performed by (X addresses in the word direction) × (1K
bit depth in the Y direction). The maximum address of X addresses in the word direction varies depending on the
total memory capacity of RAM externally connected. The header 64 words (64K bits) of the RAM are used as
the channel index area. Therefore, addresses after X address 0040h can be used as the voice data area.
RSEL2
L
L
L
H
H
RSEL1
L
L
H
L
H
Total memory
capacity
4M bits
8M bits
16M bits
24M bits
32M bits
No. of words
4K words
8K words
16K words
24K words
32K words
0000h-0FFFh
0000h-1FFFh
0000h-3FFFh
0000F-5FFFh
0000h-7FFFh
X address
The storage method of 1K-bit ADPCM data in the Y direction is identical to that for the flex record/playback
mode. For 3-bit ADPCM data, the storage locations are addressable by 00h-A9h, For 4-bit ADPCM data, the
storage locations are addressable by 00h-7Fh.
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Address Space Allocation of RAM
(Direct record/playback)
X address (32K words 0000h - 7FFFh, 1 word = 1K bits)
1K bits
8 Mbit
CS1
0000h
003Fh
0040h
Channel index area (64K words × 1K bits = 64K bits)
ADPCM (voice) data area
1K bits in the Y direction
1 word = 1K bits
1FFFh
2000h
Y address
8 Mbit
CS2
00h
For 3-bit
ADPCM
01h
02h
6-bits 6-bits 6-bits
A7h
A8h
A9h
6-bits 6-bits 10-bits
00h
01h
7Eh
7Fh
8-bits
8-bits
8-bits
8-bits
3FFFh
For 4-bit
ADPCM
8 Mbit
CS3
4000h
5FFFh
8 Mbit
CS4
6000h
7FFFh
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2. Channel index area of serial registers
2.1 Channel index area in the flex record/playback mode
In the flex record/playback mode, the channel index area for one phrase (1K bits) consists of 64K-bit address
data, 704-bit user data, and 256-bit address control block table. The address data consists of the number of
blocks, stop Y address, stop X address, start block, stop block, and PRED block. In the following, these areas are
summarized.
(1) Number of blocks: This area stores the number of blocks (recorded time) used for recording of one phrase.
Address ch00 stores the number of unused blocks (available blocks). This number of blocks can be read by
the BLKRD command. The recorded time for one phase and the unused capacity (available recording time)
of memory can be obtained.
(2) Stop Y address: This area stores the stop Y address of the phrase. A Y address location is addressable by
one of 00h-A9h for 3-bit ADPCM, and by one of 00h-7Fh for 4-bit ADPCM.
(3) Stop X address: This area stores the stop X address of a phrase. This X address is offset address of the
block. One X address has a 1K-bit memory area. The memory capacity of one block varies depending on
the number of serial registers connected externally, and addressing also varies accordingly.
(4) Start block and stop block: The total memory capacity of serial registers is equally divided into 256 blocks.
Addresses 00h-FFh are assigned to these blocks. The start block and stop block are stored in the start block
area and stop block area, respectively.
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(5) PRED block: This area stores the address of a block immediately before the stop block. In the flex
record/playback mode, each recording area is controlled on a per-block basis. Therefore, a phrase is not
always stored continuously in serial registers. For example, if a phrase is recorded in three blocks 03h,
04h and 07h. The PRED block stores 04h. This PRED block is used to change the stop block and stop X
address for deleting a tail part of the recorded phrase.
(6) User data: This user data area can be used by the user. The data can be written to and read from this area by
the CHRW command.
This user data area is provided independently for each phrase, so that it is useful to store the sampling
frequency, ADPCM bit length and recorded time.
ST0 ST1 ST2 ST3 ST4 ST5 ST6 ST7
(ST0-ST7)
Start block
PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7
(PR0-PR7)
PRED block
SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP7
(SP0-SP7)
Stop block
SPX0 SPX1 SPX2 SPX3 SPX4 SPX5 SPX6 SPX7
(SPX0-SPX7)
Stop X address
SPY0 SPY1 SPY2 SPU3 SPY4 SPY5 SPY6 SPY7
(SPY0-SPY7)
Stop Y address
Lower
BL0 BL1 BL2 BL3 BL4 BL5 BL6 BL7
(BL0-BL7)
Number of blocks
Upper
Unused
Start
block
Stop
block
Number of Stop Y
blocks address
Stop X
address
PRED
block
8 bits
8 bits
8 bits
8 bits
8 bits
Address
data
8 bits
64 bits
User data
704 bits
64 bits
1K-bit depth in the Y direction
16 bits
Block table
256 bits
(7) Block table: The block table is an area used for the block control.
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2.2 Channel index area in the direct record/playback mode
In the direct record/playback mode, the channel index area for one phrase (1K bits) consists of 64-bit address
data and 960-bit user data. The address data consists of the stop Y address, stop X address, start X address, and
unused area.
(1) Stop Y address: In the same manner as in the direct record/playback mode, the stop address can be
specified by one of 00h-A9h for 3-bit ADPCM and 00h-7Fh for 4-bit ADPCM.
(2) Start X address and stop X address: An X address is specified by 16 bits (15 effective bits). The 32K-word
X address space can be addressed by 000h-7FFFh.
(3) User data: In the same manner as in the direct record/playback mode, this user data area can be used by the
user. The data can be written to and read from this area by the CHRW command.
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(SPX0-SPX15)
(STX0-STX15)
Stop X address
Start X address
Stop
Y address
(SPY0-SPY7)
Stop
X address
8 bits
Stop Y address
16 bits
Address
data
64 bit
Unused
24 bits
Upper
STX0 STX1 STX2
STX3 STX4 STX5 STX6 STX7 STX8 STX9 STX10 STX11 STX12 STX13 STX14 STX15
SPX0 SPX1 SPX2 SPX3 SPX4 SPX5 SPX6 SPX7 SPX8 SPX9 SPX10 SPX11 SPX12 SPX13 SPX14 SPX15
SPY0 SPY1 SPY2 SPY3 SPY4 SPY5 SPY6 SPY7
Lower
Start
X address
16 bits
64 bits
User data
960 bits
Depth of 1K bits in the Y direction
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Data Configuration of External Serial Voice ROMs
The external serial voice ROMs are composed of (X addresses in the word direction) × (depth of 1K bits). The
addressing is possible only for X addresses in the word direction. The maximum address of the X addresses in
the word direction varies depending on the total memory capacity of the serial voice ROMs externally connected.
In the ROM playback by input of address code, the header 16 words (16K bits) are used as the channel index
area, so that the addresses after address 010h can be used as the voice data area.
Total memory capacity
(Number of ROMs)
ROM playback by
input of address code
Direct ROM playback
DTRD command
1M bits (1)
2M bits (2)
3M bits (3)
4M bits (4)
Number of
words
1008 words
2032 words
3056 words
4080 words
X address
010h-3FFh
010h-7FFh
010h-BFFh
010h-FFFh
Number of
words
1024 words
2048 words
3072 words
4096 words
X address
000h-3FFh
000h-7FFh
000h-BFFh
000h-FFFh
The method for storing the ADPCM data of 1K bits in the Y direction is identical to that for the record/playback
mode.
Addressing can be made by 00h-A9h for 3-bit ADPCM and 00h-7Fh for 4-bit ADPCM.
When reading data in the serial voice ROMs by the DTRD command, specify the X address and Y address and
then perform the read access operation. The address locations can be specified by 000h-FFFh in the same
manner as in the ROM playback. The area of 1K bits in the Y direction is equally divided into 16 of 64K bits
each, so that addressing can be performed by 0h-Fh.
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Address Space Allocation of Serial Voice ROMs
X address (4K words 000h-FFFh, 1 word = 1K bits)
1M serial voice ROM
CS1
1k bits
000h
00Fh
010h
Channel index area (required only for ROM playback by input of address code.
16 words × 1K bits = 16K bits)
ADPCM (voice) data
1K bits in the Y direction
1 word = 1K bits
1M serial voice ROM
CS3
1M serial voice ROM
CS2
3FFh
Y address
400h
00h
3-bit
ADPCM
01h 02h
A7h A8h
6 bits 6 bits 6 bits
A9h
6 bits 6 bits 10 bits
00h
01h
7Eh
7Fh
8 bits
8 bits
8 bits
8 bits
Eh
Fh
7FFh
800h
4-bit
ADPCM
Read by DTRD
command
0h
1h
64 bits
64 bits
2h
64 bits
1M serial voice ROM
CS4
BFFh
C00h
FFFh
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Command Description
The MSM6688/6688L is controlled by 19 types of commands via D0-D3 pins constituting the data bus and WR,
RD, CE, and CE control pins. The state of the MSM6688/6688L can be known by obtaining the contents of the
internal status register via the data bus or the output pins.
There are four command modes available: mode 0, mode 1, mode 2, and mode 3. Some commands need to set
the command mode before inputting them. The command mode can be selected by setting MOD0 bit and MOD1
bit of the SAMP command.
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1. Command list
Code
Command
Command function
D
3
D
2
D
1
D
0
NOP
0
0
0
0
(NON OPERATION)
Has no function.
PAUSE
0
0
0
1
(PAUSE)
Suspends record/playback temporarily.
PLAY
0
0
1
0
(PLAYBACK)
Sets playback mode.
REC
0
0
1
1
(RECORD)
Sets recording mode.
START
0
1
0
0
STOP
0
1
0
1
SAMP
0
1
1
0
CHAN
0
1
1
1
BLKWR
1
0
0
0
BLKRD
1
0
0
1
ADRWK
1
0
0
0
ADRRD
1
0
0
1
(START)
Starts record/playback.
(STOP)
Stops record/playback.
Stops execution of CHRW, DTRW, DTRD, and
EXT commands.
(SAMPLING
FREQUENCY)
Specifies the command mode and sampling
frequency, in conjunction with 1 nibble following
this command.
(CHANNEL)
Specifies a phrase, in conjunction with 2 nibbles
following this command.
(BLOCK WRITE)
Sets the number of recording blocks (recording
time) for the phrase, in conjunction with 2 nibble
following this command.
(BLOCK READ)
Reads the number of blocks (recording time) for
the phrase stored in the channel index area, in
conjunction with 2 nibbles following this command.
During execution of this command, the contents of
the status register cannot be read.
(ADDRESS WRITE)
Stores the start address and the stop address to
the channel index area, in conjunction with 10
nibbles following this command.
(ADDRESS READ)
Reads out the start address and the stop address
stored in the channel index area, in conjunction
with 10 nibbles following this command.
During execution of this command, the contents of
the status register cannot be read.
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Code
Command
CHRW
DTRW
DTRD
D
3
1
1
1
D
2
0
0
0
D
1
1
1
1
0
0
1
0
1
1
VDS
1
1
0
0
1
1
0
(CHANNEL READ
WRITE)
Reads out the user data stored in the channel
index area or writes the user data to the channel
index area by the read/write access operation
following this command.
(DATA READ
WRITE)
Transfers data to or from the external serial
registers through the data bus, by the address
designation in 5 nibbles following this command
and the read/write access operation.
(DATA READ)
Reads the data in the external serial voice ROMs
through the data bus, by the address designation
in 5 nibbles following this command and the
read/write access operation.
(EXTERNAL)
Performs record/playback by inputting/outputting
ADPCM data through the data bus, in conjunction
with the read/write access operation.
This command will be used when an SRAM or a
hard disk is used for storing voice data. Does not
control external serial registers and addresses.
(VOICE DETECT
SELECT)
Selects the ADPCM bit length and voice triggered
starting function, in conjunction with 1 nibble
following this command.
(DELETE)
Deletes the phrase specified by the CHAN
command. When ch00 is specified by the CHAN
command, all phrases are deleted by this
command.
(LEVEL)
Specifies the playback output level and the
transition of analog output (AOUT pin) to the DC
level, in conjunction of 1 nibble following this
command. This level is initialized by the RESET
input.
(NON OPERATION)
Has no function.
0
EXT
DEL
Command function
D
0
1
LEV
1
1
1
0
NOP
1
1
1
1
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2. Command format
MOD1
0
0
1
1
MOD0
0
1
0
1
Mode 0
Mode 1
Mode 2
Mode 3
Code
D
3
D
2
D
1
D
0
HEX
0
0
0
0
0h
NOP
NOP
NOP
NOP
0
0
0
1
1h
PAUSE
PAUSE
PAUSE
PAUSE
0
0
1
0
2h
PLAY
PLAY
PLAY
PLAY
0
0
1
1
3h
REC
REC
REC
REC
4h
START
(Flex record/
playback)
START
(ROM playback
by input of
address code)
START
(Direct record/
playback)
START
(Direct ROM
playback)
0
1
0
0
0
1
0
1
5h
STOP
STOP
STOP
STOP
0
1
1
0
6h
SAMP
SAMP
SAMP
SAMP
0
1
1
1
7h
CHAN
CHAN
CHAN
CHAN
1
0
0
0
8h
BLKWR
BLKWR
ADRWR
ADRWR
1
0
0
1
9h
BLKRD
BLKRD
ADRRD
ADRRD
1
0
1
0
Ah
CHRW
CHRW
DTRW
DTRD
1
0
1
1
Bh
EXT
EXT
EXT
EXT
1
1
0
0
Ch
VDS
VDS
VDS
VDS
1
1
0
1
Dh
DEL
DEL
DEL
DEL
1
1
1
0
Eh
LEV
LEV
LEV
LEV
1
1
1
1
Fh
NOP
NOP
NOP
NOP
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3. Command data format
Command
Code
HEX
D3
D2
D1
D0
Note
NOP
0h
0
0
0
0
1-nibble command
PAUSE
1h
0
0
0
1
1-nibble command
PLAY
2h
0
0
1
0
1-nibble command
REC
3h
0
0
1
1
1-nibble command
START
4h
0
1
0
0
1-nibble command
STOP
5h
0
1
0
1
1-nibble command
1st nibble
0
1
1
0
2-nibble command
2nd nibble
MOD1
MOD0
SA1
SA0
MOD1 MOD0
SAMP
6h
Command mode, sampling frequency
Command
mode
SA1
SA0
Sampling frequency
0
0
Mode 0
0
0
fOSC/1024 (4.0 kHz)
0
1
Mode 1
0
1
fOSC/768 (5.3 kHz)
1
0
Mode 2
1
0
fOSC/640 (6.4 kHz)
1
1
Mode 3
1
1
fOSC/512 (8.0 kHz)
Values in parentheses are for fOSC = 4.096 MHz.
1st nibble
CHAN
7h
0
1
1
1
3-nibble command
2nd nibble
CA3
CA2
CA1
CA0
3rd nibble
CA7
CA6
CA5
CA4
Phrase No.
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Phrase
No.
0
0
0
0
0
0
0
0
ch00
0
0
0
0
0
0
0
1
ch01
0
0
0
0
0
0
1
0
ch02
0
0
0
0
0
0
1
1
ch03
…
…
…
…
…
…
…
…
…
1
1
1
1
1
1
1
1
chFE
1
1
1
1
1
1
1
1
chFF
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Command
Code
HEX
BLKWR
8h
BLKRD
ADRWR
ADRRD
9h
8h
9h
MSM6688/6688L
D3
D2
D1
D0
1st nibble
1
0
0
0
2nd nibble
BL3
BL2
BL1
BL0
3rd nibble
BL7
BL6
BL5
BL4
1st nibble
1
0
0
1
2nd nibble
BL3
BL2
BL1
BL0
3rd nibble
BL7
BL6
BL5
BL4
1st nibble
1
0
0
0
2nd nibble
SPY3
SPY2
SPY1
SPY0
3rd nibble
SPY7
SPY6
SPY5
SPY4
4th nibble
SPX3
SPX2
SPX1
SPX0
5th nibble
SPX7
SPX6
SPX5
SPX4
6th nibble
SPX11
SPX10
SPX9
SPX8
7th nibble
SPX15
SPX14
SPX13
SPX12
8th nibble
STX3
STX2
STX1
STX0
9th nibble
STX7
STX6
STX5
STX4
10th nibble
STX11
STX10
STX9
STX8
11th nibble
STX15
STX14
STX13
STX12
1st nibble
1
0
0
1
2nd nibble
SPY3
SPY2
SPY1
SPY0
3rd nibble
SPY7
SPY6
SPY5
SPY4
4th nibble
SPX3
SPX2
SPX1
SPX0
5th nibble
SPX7
SPX6
SPX5
SPX4
6th nibble
SPX11
SPX10
SPX9
SPX8
7th nibble
SPX15
SPX14
SPX13
SPX12
8th nibble
STX3
STX2
STX1
STX0
9th nibble
STX7
STX6
STX5
STX4
10th nibble
STX11
STX10
STX9
STX8
11th nibble
STX15
STX14
STX13
STX12
Note
3-nibble command
Number of blocks
3-nibble command
Number of blocks
11-nibble command
Stop Y address
Stop X address
Start X address
11-nibble command
Stop Y address
Stop X address
Start X address
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Command
Code
HEX
D3
D2
D1
D0
CHRW
Ah
1
0
1
0
1-nibble command + read/write
access + STOP command
1st nibble
1
0
1
0
6-nibble command + read/write
access + STOP command
2nd nibble
0
0
0
0
Dummy nibble
3rd nibble
X3
X2
X1
X0
4th nibble
X7
X6
X5
X4
5th nibble
X11
X10
X9
X8
6th nibble
X15
X14
X13
X12
1st nibble
1
0
1
0
2nd nibble
Y3
Y2
Y1
Y0
3rd nibble
X3
X2
X1
X0
4th nibble
X7
X6
X5
X4
5th nibble
X11
X10
X9
X8
6th nibble
0
0
0
0
Dummy nibble
1
0
1
1
1-nibble command + read/write
access + STOP command
1st nibble
1
1
0
0
2-nibble command
2nd nibble
0
BIT
VD1
VD0
DTRW
DTRD
EXT
Ah
Ah
Bh
BIT
VDS
Ch
ADPCM bit
length
0
3 bits
1
4 bits
Note
X address
6-nibble command + read access +
STOP command
Y address
X address
ADPCM bit length, voice triggered
starting condition
VD1
VD0
0
0
0
1
1
0
1
1
Voice detection level VVDS
MSM6688
MSM6688L
(5 V version)
(3 V version)
Voice triggered
Voice triggered
starting disabled starting disabled
±VDD/128
±VDD/64
(±80 mV)*
(±24 mV)**
±VDD/64
±VDD/32
(±160 mV)*
(±48 mV)**
±VDD/32
±VDD/16
(±320 mV)*
(±96 mV)**
* Values in parentheses are for VDD = 5.12 V.
** Values in parentheses are for VDD = 3.072 V.
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Command
Code
HEX
DEL
Dh
LEV
NOP
MSM6688/6688L
D3
D2
D1
D0
1
1
0
1
ch00:
ch01-chFF:
1-nibble command
Deletion of all phrases
Deletion of a specified phrase
1st nibble
1
1
1
0
2nd nibble
LV1
LV0
PN1
PN0
2-nibble command
Playback level, transition to DC level
LV1
LV0
Playback
level
PN1
PN0
Transition to
DC level
0
0
0 dB
0
0
Disabled
0
1
0 dB
0
1
Disabled
Eh
Fh
Note
1
1
0
–6 dB
1
0
Transition from GND
to 1/2 VDD
1
1
–12 dB
1
1
Transition from
1/2 VDD to GND
1
1
1
1-nibble command
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4. Relationship between record/playback control modes and commands
Record/
playback
mode
Flex record/
playback
ROM playback
by input of
address code
Direct record/
playback
Direct ROM
playback
NOP
—
—
—
—
—
PAUSE
∆
∆
∆
∆
—
PLAY
⊗
—
⊗
—
⊗
REC
⊗
—
⊗
—
⊗
START
⊗
⊗
⊗
⊗
—
Command
EXT command
record/
playback
STOP
∆
∆
∆
∆
⊗
SAMP
⊗
⊗
⊗
⊗
⊗
Command mode
⊗
⊗
⊗
⊗
⊗
Sampling frequency
⊗
—
⊗
⊗
⊗
CHAN
⊗
⊗
⊗
⊗
—
BLKWR
⊗
—
—
—
—
BLKRD
∆
—
—
—
—
ADRWR
∆
—
⊗
⊗
—
ADRRD
∆
—
∆
—
—
CHRW
Data transfer command
DTRW
Data transfer command
DTRD
Data transfer command
EXT
—
—
—
—
⊗
VDS
⊗
—
⊗
⊗
⊗
ADPCM bit length
⊗
—
⊗
⊗
⊗
Voice triggered
starting condition
⊗
—
⊗
—
—
⊗
—
∆
—
—
Deletion of all
phrases
⊗
—
∆
—
—
Deletion of
a specified phrase
∆
—
∆
—
—
∆
∆
∆
∆
∆
DEL
LEV
Note:
⊗: Required command
∆: Effective command
—: Unnecessary command
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MSM6688/6688L
Status Register
The status register used in the MSM6688/6688L is a 4-bit status register. When a low level is applied to the RD
pin, the contents of the status register are output to D0-D3 pins to indicate the internal state of the
MSM6688/6688L. The contents of the status register are also output to the BUSY, RPM, VPM, and NAR pins.
D3
D2
D1
D0
NAR
VPM
RPM
BUSY
(1) BUSY bit
The BUSY bit set to a high level indicates that the MSM6688/6688L is executing RESET operation or command
processing operation. When BUSY bit is high, do not input any command from the microcontroller. While any
of data read commands is being executed, the state of the BUSY bit cannot be verified by inputting the RD pulse.
In this case, input a read command either after waiting a time longer than the duration of BUSY state or after
verifying the end of the busy state by the BUSY pin.
While the RESET operation is being executed, the BUSY bit is set to a high level, and it returns to a low level
after the end of the RESET operation. After a high level pulse is applied to the RESET pin to perform the
RESET operation, the BUSY bit is set to a high level during execution of the RESET operation. It goes to a low
level after the end of the RESET operation.
(2) RPM bit
The RPM bit goes to a high level during record/playback operation. While the RPM bit is high, do not input any
command except those indicated below. Otherwise, the state of the MSM6688/6688L becomes undefined.
NOP, PAUSE, STOP commands, START command for release of temporary stop and playback of next phrase,
CHAN command for specifying the next phrase during playback and LEV command for designation of playback
output level.
After a high level pulses is applied to the RESET pin to perform the RESET operation, the RPM bit goes to a
low level that is the initial state.
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(3) VPM bit
The VPM bit goes to a high level during standby for voice after start of the voice triggered recording and during
the time that record/playback is temporarily stopped by the PAUSE command.
When the VPM bit is high, do not apply any command except the STOP command and the START command for
release of temporary stop. Otherwise, the state of the MSM6688/6688L becomes undefined.
After a high level pulse is applied to the RESET pin to perform the reset operation, the VPM bit goes to a low
level that is the initial state.
(4) NAR bit
The NAR bit indicate the enabled or disabled state for phrase designation. When this bit is high, the phrase
designation by the CHAN command is enabled.
If it is desired to play back different phrases continuously during ROM playback, specify the next phrase and
input the START command after verifying that the NAR bit becomes high.
After a high level pulse is applied to the RESET pin to perform the reset operation, the NAR bit goes to a high
level that is the initial state.
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BUSY causing conditions
Release of reset operation
MSM6688/6688L
Symbol
BUSY state
duration
BUSY bit
verification
tREX
(Note 2) 1 ms
Possible
Input of RESET pulse
Note
Input of 1-nibble command
tB1
16 µs
Possible
NOP, PAUSE, PLAY,
REC, START, STOP
Input of 2-nibble command
tB2
16 µs
Possible
SAMP, VDS, LEV
Input of 3-nibble command
tB3
16 µs
Possible
CHAN, BLKWR
SAMP, VDS, LEV,
CHAN, BLDWR
tBD
16 µs
Possible
Input of command
tWBR
270 µs
Impossible
Output of block data
tWDR
50 µs
Impossible
Input of command
tBAW
270 µs
Possible
Input of address data
tBAD
50 µs
Possible
Input of command
tWAR
270 µs
Impossible
Output of address data
tWDR
50 µs
Impossible
tWCRW
770 µs
Possible
Input of REC command
tWRC
16 µs
Possible
(Note 1)
Input of write data
tWWD
50 µs
Possible
(Note 1)
Input of PLAY command
tWPL
50 µs
Impossible
Input of STOP command
tWSP
50 µs
Possible
(Note 1)
Input of 2-nibble or 3-nibble command data
BLKRD command
ADRWR command
ADRRD command
CHRW command
Input of command
DTRW and DTRD commands
Input of command
tWRW
16 µs
Possible
Input of address (2nd to 5th nibbles)
tWA1
16 µs
Possible
Input of address (6th nibble)
tWA2
270 µs
Possible
Input of REC command
tWRC
16 µs
Possible
(Note 1)
Input of write data
tWWD
50 µs
Possible
(Note 1)
Input of PLAY command
tWPL
50 µs
Impossible
Input of STOP command
tWSP
50 µs
Possible
(Note 1)
Input of DEL command (all phrases)
tWBLA
550 ms
Possible
Input of DEL command
(a specified phrase)
tWBL1
70 ms
Possible
Notes: 1. The BUSY state can be verified by the BUSY bit when only the data write access operation
is executed after the CHRW or DTRW command is input.
2. The BUSY state duration after release of RESET operation includes the oscillation startup
stabilization time. This oscillation startup stabilization time is several tens of milliseconds
for crystal oscillators and is several hundreds of microseconds for ceramic oscillators.
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Inputting the Commands
To input a command or data, apply the command or data to D0-D3 pins and then apply a low level pulse (WR
pulse) to the WR pin.
By inputting a low level pulse (RD pulse) to the RD pin, the contents of the status register or data will be output
via D0-D3 pins.
The CE pin is used to enable or disable the WR pulse and RD pulse. When a low-level is applied to this CE pin,
the enable state is present, so that WR and RD pulses can be accepted. When a high level is applied to this CE
pin, the disable state is present, so that WR and RD pulses cannot be accepted and, at the same time, D0-D3 pins
are placed in the high-impedance state.
The CE pin also has the same function as the CE pin. However, when high, this CE pin gives the enable state for
the WR and RD pulses, and when low, it gives the disable state. When D0-D3 pins are used exclusively for the
MSM6688/6688L, CE and CE pins can be fixed to a low level and a high level, respectively.
An equivalent circuit of the microcontroller interface section of the MSM6688/6688L is shown below.
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MSM6688/6688L
Status
register
4
4 Q
NAR
VPM
RPM
BUSY
4
D0-D3
RD
WR
4
4
4
SEL
4 Data
D Q
LD
RD pulse
WR pulse
CE
CE
PDWN
RESET
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The steps for inputting the commands are described below.
(1) Output the contents of the status register by applying the RD pulse (namely, by applying a low level pulse
to the RD pin). Verify that the BUSY bit is 0. If the BUSY bit is 1, input the RD pulse repeatedly until the
BUSY bit goes to 0. The BUSY state can also be verified through the BUSY pin.
(2) Set a command to D0-D3 pin and input the WR pulse.
(3) In case of a 2-nibble or 3-nibble command, verify that the BUSY bit of the status register is 0 in the same
way as in (1). Then, set the command data to D0-D3 pins and input the WR pulse. In this case, the WR
pulse can also be input after the waiting time that is longer than the BUSY state duration, instead of
verifying the BUSY bit of the status register.
CE
(I)
CE
(I)
WR
(I)
RD
(I)
D0-D3 (I/O)
BUSY
(O)
Status output
Command input
Status output
Busy state duration
Next command data
can be input
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1. Inputting a 2-nibble command
Input RD pulse
No
BUSY = 0?
Status output
Verification of BUSY bit
Yes
No
Input WR pulse
Input of the 1st nibble command
Input RD pulse
Status output
BUSY = 0?
Yes
Input WR pulse
Verification of BUSY bit
(or waiting for BUSY state duration)
Input of the 2nd nibble data
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Changes of Record/Playback Conditions
Record/playback condition
PDWN input
POWER ON
RESET input
Command input
Record/playback mode
Undefined
Unchanged
(Note 1)
Unchanged
REC command
→Record mode
PLAY command
→Playback mode
Command mode
Undefined
Unchanged
(Note 1)
Unchanged
Set by SAMP command
Sampling frequency
Undefined
Unchanged
(Note 1)
Unchanged
Set by SAMP command
Phrase No.
Undefined
Unchanged
(Note 1)
Unchanged
Set by CHAN command
Number of phrase recording
blocks
Undefined
Unchanged
(Note 1)
Unchanged
Set by BLKWR command
ADPCM bit length
Undefined
Unchanged
(Note 1)
Unchanged
Set by VDS command
Voice triggered level
Undefined
Unchanged
(Note 1)
Unchanged
Set by VDS command
Playback level
Undefined
0 dB
Unchanged
Set by LEV command
Data in serial registers
Undefined
Unchanged
(Note 1)
Unchanged
—
Note: 1. RESET is performed without synchronization with the clock.
When the RESET pulse is input during standby for commands, record/playback condition will
not be changed. When the RESET pulse is input during execution of a command, all
record/playback conditions may be changed and the data may become undefined.
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Setting and Confirming the Record/Playback Conditions
1. Specifying the control mode for record/playback (by the SAMP command)
Specify the control mode for record/playback by setting the command mode (using MOD1 and MOD0 bits) as
shown in the following table.
MOD1
MOD0
Command mode
Control mode for record/playback
0
0
Mode 0
Flex record/playback
0
1
Mode 1
ROM playback by input of address code
1
0
Mode 2
Direct record/playback
1
1
Mode 3
Direct ROM playback
2. Specifying the sampling frequency (by the SAMP command)
Specify the sampling frequency by setting SA0 and SA1 bit data of the SAMP command. The relationship
between the master oscillator frequency (fOSC), and sampling frequency (fSAMP) depends on the SA0 and SA1 bit
data of the SAMP command as shown in the following table.
SA1
SA0
Sampling frequency fSAMP
0
0
fOSC/1024 (4.0 kHz)
0
1
fOSC/768 (5.3 kHz)
1
0
fOSC/640 (6.4 kHz)
1
1
fOSC/512 (8.0 kHz)
( ) Values in parentheses are for fOSC = 4.096 MHz.
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3. Specifying the ADPCM bit length (by the VDS command)
Specify the ADPCM bit length by setting the BIT bit data of the VDS command as shown in the following table.
BIT
ADPCM bit length
0
3 bits
1
4 bits
4. Specifying the voice triggered starting (by the VDS command)
This MSM6688/6688L has the voice triggered starting function that starts recording when the level of voice
input exceeds a preset amplitude. Using the voice activated function, the unvoiced part prior to voice detection
will not be recorded, so that the memory capacity can be utilized efficiently.
The unvoiced parts in the middle of recording are not eliminated. In the voice triggered starting mode, recording
is started when a voice input exceeds the preset thresholds. Therefore, a consonant part with a low level may not
be recorded.
Voice input level
(ADIN pin)
1/2VDD
Upper threshold
+Vvds
–Vvds
Lower threshold
Identified as voice and recording start
Start signal input
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Specify the enable/disable of the voice triggered starting function and the voice detection level by VD0 and VD1
bit data of the VDS command as shown in the following table.
VD1
VD0
0
0
0
1
1
Voice detection level, Vvds
MSM6688 (5 V version)
MSM6688L (3 V version)
Voice triggered starting disabled
Voice triggered starting disabled
1
±VDD/64 (±80 mV) *
±VDD/128 (±24 mV) **
0
±VDD/32 (±160 mV) *
±VDD/64 (±48 mV) **
1
±VDD/16 (±320 mV) *
±VDD/32 (±96 mV) **
* Values in parentheses are for VDD = 5.12 V.
** Values in parentheses are for VDD = 3.072 V.
During standby for voice, the VPM bit of the status register is 1. This bit returns to 0 at the start of recording
after detection of voiced signal. The RPM bit is 1 during standby for voice and during recording.
WR
D0-D3
START command
STOP command
Status register
RPM bit
VPM bit
Standby for recording Standby for voice
Recording in progress
Standby for recording
Identified as voice
When the STOP command is input during standby for voice, standby for voice will be finished and changed to
standby for recording. If in the flex record/playback mode, the STOP command is input during standby for voice,
the contents of the specified phrase will be deleted.
WR
D0-D3
START command
STOP command
Status register
RPM bit
VPM bit
Standby for recording
Standby for voice
Standby for recording
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5. Specifying a phrase (by the CHAN command)
Specify a phrase by CA0-CA7 bit data of the CHAN command as shown in the following table.
CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
Phrase
No.
Flex record/
playback
ROM playback
by input of
address code
(Note 1)
Disabled
0
0
0
0
0
0
0
0
ch00
0
0
0
0
0
0
0
1
ch01
0
0
0
0
0
0
1
0
ch02
…
…
…
…
…
…
…
…
…
0
0
1
1
1
1
1
0
ch3E
0
0
1
1
1
1
1
1
ch3F
0
1
0
0
0
0
0
0
ch40
0
1
0
0
0
0
0
1
ch41
…
…
…
…
…
…
…
…
…
1
1
1
1
1
1
1
0
chFE
1
1
1
1
1
1
1
1
chFF
Enable
(63 phrases)
Direct record/
playback
Direct
ROM
playback
Enable
(64 phrases)
Enable
(Note 2)
Inhibit
Inhibit
Enable
(255 phrases)
Inhibit
Notes: 1. In the flex record/playback mode, ch00 cannot be used for recording/playback. This is a
special phrase only used for deletion of all phrases and control of unused blocks.
2. In the direct ROM playback mode, playback will be started after transferring the address
data to the channel index area of the serial registers. Therefore, it is required for direct
ROM playback to use a phrase unused for record/playback operation. Normally, phrase
ch3FH is used as the phrase dedicated for direct ROM playback.
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6. Specifying the number of phrase recording blocks (by the BLKWR command)
In the flex record/playback mode, set the number of blocks before starting the recording to specify the recording
time for a phrase. In this mode, the total memory capacity of serial registers connected externally is divided
equally into 256 blocks. Therefore, the memory capacity of one block varies depending on the number of serial
registers connected externally.
For example, when one 8M bit serial register is connected and recording is performed by 4-bit ADPCM and
8-kHz sampling, the memory capacity of one block and the recording time of one block are obtained as follows.
Memory capacity of one block =
Recording time/block =
=
8M bits
256
= 32K bits
Memory capacity of one block
sampling frequency × ADPMC bit length
32 × 1024 bits
8000 Hz × 4 bits
= Approximately 1 second
If it is desired to make recording for 10 seconds on a phrase in this example, 10 (0Ah) phrase recording blocks
are required.
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The number of phrase recording blocks can be specified by the BLKWR command and is stored in the
(corresponding) register in the MSM6688/6688L. The BLKWR command is enabled for command mode 0 or 1.
Therefore, before inputting this BLKWR command, it is required to set the corresponding command mode using
the SAMP command.
BL7
BL6
BL5
BL4
BL3
BL2
BL1
BL0
Number of phrase recording blocks
(HEX)
0
0
0
0
0
0
0
0
Input inhibit
0
0
0
0
0
0
0
1
1 (01h)
0
0
0
0
0
0
1
0
2 (02h)
0
0
0
0
0
0
1
1
3 (03h)
…
…
…
…
…
…
…
…
…
1
1
1
1
1
1
1
0
254 (FEh)
1
1
1
1
1
1
1
1
255 (FFh)
7. Reading the number of phrase recording blocks (by the BLKRD command)
The number of blocks for each phrase stored in the channel index area can be read by the read access operation
using the BLKRD command and two nibbles following this BLKRD command. In the flex record/playback
mode, the number of blocks (namely, the recording time) of the specified phrase can be obtained. In the BLKRD
command, the number of blocks is specified by a binary number consisting of BL0-BL7 in the same way as in
the BLKWR command.
Before inputting the BLKRD command, the command mode must be set to either mode 0 or mode 1 by using the
SAMP command.
(1) When ch00 phrase is specified: The number of unused blocks (or available blocks) is stored in address ch00
of the channel index area. Therefore, the unused and available memory capacity (or available recording
time) can be obtained.
(2) When one of ch01-ch3F is specified as a phrase: The number of blocks (or recording time) used by the
specified phrase can be obtained.
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BLKRD Command Flow Chart
SAMP command
Setting of common mode to mode 0 or mode 1 (MOD0, MOD1)
CHAN command
Phrase designation (CA0-CA7)
1st nibble
BLKRD command
2nd nibble
Wait for BUSY
state duration
Input RD pulse
Output of lower 4 bits of the number of blocks
3rd nibble
Wait for BUSY
state duration
Input RD pulse
Output of upper 4 bits of the number of blocks
Wait for BUSY state
duration
During execution of the BLKRD command, verification of the status register cannot be performed by input of
the RD pulse. When inputting the RD pulse for the 2nd nibble or 3rd nibble or inputting the next command after
the BLKRD command, input the RD pulse either after the waiting time longer than the BUSY state duration or
after verifying that the BUSY status is not present via the BUSY pin.
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8. Inputting/outputting the address data (by the ADRWR/ADRRD command)
In the direct record/playback mode or direct ROM playback, input the start address and stop address of a phrase
directly into the channel index area in the RAM by the ADRWR command.
The ADRRD command is used to read the address data stored in the channel index area.
The header 40 bits of each phrase of the channel index area can be accessed by the ADRWR or ADRRD
command. In the flex record/playback mode, these commands can be used to change the address data for
deleting the tail part of a recorded phrase.
Direct record/playback and
direct ROM playback
Flex record/playback
D3
D2
D1
D0
Contents
D3
D2
D1
D0
Contents
1st nibble
1
0
0
*
Command
1
0
0
*
Command
Stop Y
address
BL3
BL2
BL1
BL0
BL7
BL6
BL5
BL4
Number of
blocks
2ndnibble
SPY3
SPY2
SPY1
SPY0
3rd nibble
SPY7
SPY6
SPY5
SPY4
4th nibble
SPX3
SPX2
SPX1
SPX0
SPY3
SPY2
SPY1
SPY0
5th nibble
SPX7
SPX6
SPX5
SPX4
SPY7
SPY6
SPY5
SPY4
6th nibble
SPX11
SPX10
SPX9
SPX8
SPX3
SPX2
SPX1
SPX0
7th nibble
SPX15
SPX14
SPX13
SPX12
SPX7
SPX6
SPX5
SPX4
8th nibble
STX3
STX2
STX1
STX0
SP3
SP2
SP1
SP0
9th nibble
STX7
STX6
STX5
STX4
SP7
SP6
SP5
SP4
10th nibble
STX11
STX10
STX9
STX8
11th nibble
STX15
STX14
STX13
STX12
Stop X
address
Start X
address
PR3
PR2
PR1
PR0
PR7
PR6
PR5
PR4
Stop Y
address
Stop X
address
Stop block
PRED
block
Note: When the address data is input by the ADRWR command in the direct ROM playback mode,
the 7th nibble and the 11th nibble are dummy nibbles.
Therefore, input 0h data into SPX12-SPX15 (7th nibble) and STX12-STX15 (11th nibble).
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ADRWR Command Flow Chart
SAMP command
Setting of command mode to mode 2 or mode 3 (MOD = 1)
CHAN command
Phrase designation (CA0-CA7)
1st nibble
ADRWR command
Input of command after verification of BUSY state
2nd nibble
BUSY = 0?
Input WR pulse
BUSY bit verification
(or waiting for BUSY state duration or longer)
Input of address data
3rd nibble
4th nibble
10th nibble
11th nibble
BUSY = 0?
Input WR pulse
Verification of address data
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ADDRD Command Flow Chart
SAMP command
CHAN command
Setting of command mode to mode 2 or mode 3 (MOD0, MOD1)
Phrase designation (CA0-CA7)
1st nibble
ADRRD command
Input of command after verification of BUSY state
2nd nibble
Wait for BUSY
state duration
Input RD pulse
Output of address data
3rd nibble
4th nibble
10th nibble
11th nibble
Wait for BUSY
state duration
Input RD pulse
Output of address data
Wait for BUSY
state duration
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During execution of the ADRRD command, verification of the status register cannot be performed by input of
the RD pulse. When inputting the RD pulse for the 2nd nibble to 11th nibble or inputting the next command
after the ADRRD command, input the RD pulse either after the waiting time longer than the BUSY state
duration or after verifying that the BUSY status is not present via the BUSY pin.
9. Specifying the playback level (by the LEV command)
For playback, one of three output levels 0 dB, –6 dB and –12 dB can be selected. The playback level can be
specified by LV0 and LV1 bit data of the LEV command. If the LEV command is input during playback
operation, the playback level will be changed at the moment when the command is input. When the RESET
pulse is input, the playback output level is set 0 dB that is the initial state.
LV1
LV0
0
0
0 dB (equal to the voice data amplitude)
Playback level
0
1
0 dB (equal to the voice data amplitude)
1
0
–6 dB (one-half to the voice data amplitude)
1
1
–12 dB (one-fourth to the voice data amplitude)
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Flex Record/Playback Method
1. Deleting phrases
1.1 Deleting all phrases
To delete all phrases, specify ch00 by the CHAN command and input the DEL command. When all phrases are
deleted in this manner, “0” data is written into ch01-ch3F addresses of the channel index area of the serial
registers to place these addresses in the unrecorded state. The initial data for address control is written in ch00
address. Therefore, whenever the power is turned on, always perform the deletion of all phrases after inputting
the RESET pulse.
The deletion of all phrases causes the user data area ch00-ch3F to be cleared to all 0s. Note that when the data
was transferred to the channel index area by the CHRW command, this data is deleted by the deletion of all
phrases.
State of the channel index area
Phrases No.
ch00:
Address data
User data
Block table
Initial data
Cleared to all 0s
Initial data
ch01-ch3F
Cleared to all 0s
1.2 Deleting a specified phrase
To delete a specified phrase, specify one of ch0-ch3F by the CHAN command and input the DEL command. The
deleted phrase is placed in the unrecorded state. The channel index area for the specified phrase, including the
user data, is cleared to all 0s. The data stored in ch00 address for control of unused blocks is updated.
Phrase deletion flow chart
CHAN command
ch00
ch01-ch3F:
Deletion of all phrases
Deletion of a specified phrase
DEL command
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2. Method of recording in the flex record/playback mode
2.1 When only an 8M-bit serial register is used
(1) Before starting the recording operation in the flex record/playback mode, always perform the deletion of all
phrases after turning power on and resetting the MSM6688 by input of the RESET pulse. Otherwise, the
address control cannot be performed correctly.
(2) Input the record/playback conditions by the corresponding commands as follows.
VDS command:
SAMP command:
CHAN command:
BLKWR command:
REC command:
Specify the ADPCM bit length (BIT) and voice triggered starting (VD0, VD1).
Set the command mode to mode 0 (MOD0 = 0, MOD1 = 0) and specify the
sampling frequency (SA0, SA1).
Select phrases (CA0-CA5) from one of 63 phrases ch01-ch3F.
Specify the number of phrase recording blocks (BL0-BL7).
Set to the recording mode
(3) Input the START command to start recording
(4) When the number of blocks specified by the BLKWR command is reached or when all available blocks are
used for recording, recording is finished. The end of recording can be verified by the RPM bit of the status
register.
(5) To stop recording in the middle, input the STOP command. The contents of the block counter and the
contents of the address counter at this moment are automatically stored in the channel index area as the stop
block and the stop address, respectively.
In this case, make sure that recording is finished by examining the RPM bit before inputting the next
command.
(6) To continue recording, specify the record/playback conditions to be modified by the corresponding
commands and perform the steps (3)-(5).
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Flow Chart of Flex Recording in the Record/Playback Mode
CHAN command
Specify ch00.
DEL command
Delete all phrases.
VDS command
ADPCM bit length (BIT)
Voice triggered starting (VD0, VD1)
Set the command mode to mode 0 (MOD0 = 0, MOD1 = 0).
Specify the sampling frequency (SA0, SA1).
SAMP command
CHAN command
Select one of 63 phrases (CA0-CA5).
BLKWR command
Set the phrase recording time (BL0-BL7).
REC command
Set the recording mode.
START command
No
Input record/playback
conditions to be modified
by the corresponding
commands.
Start of recording
RPM = 1?
Verify the start of recording.
Yes
RPM = 0?
Yes
Verify the end of recording.
No
No
Stop recording?
Yes
STOP command
No
RPM = 0?
Stop of recording
Verify the end of recording.
Yes
Yes
Continue
recording?
No
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2.2 When 4M bit serial register is used
This IC’s memory capacity is divided into 256 blocks for address management. This allows the connection of an
8M-bit serial register only. When connecting a 4M-bit serial register, set pins RSEL1 and RSEL2 as if only an
8M-bit serial register were connected. Then, for actual usage, the 8M-bit serial register is replaced by a 4M-bit
serial register. Replacement by the 4M-bit serial register results in the occurrence of an address area prohibited
from being used. Thus, the CPU must control the address area so that it is not accessed.
The recording procedure is almost the same as for using only an 8M-bit serial register. Before recording,
however, the number of available blocks must be determined, and a number of blocks that does not exceed that
value must be set each time by the BLKWR command. The following gives the procedure for this setting.
BLKRD command
Calculate the number of available blocks
[(Number of remaining blocks) –(number of blocks for 4M bits)]
BLKWR command
Read the number of remaining blocks.
Calculated by the CPU.
Set a value not more than the number of
available blocks as the number of phrase
recording blocks.
The following example provides the number of blocks available when one 4M-bit serial register is connected and
the erasure of all phrases is followed by the first recording.
(Number of available blocks) = (number of remaining blocks) – (number of blocks for 4M bits)
4M bits
= (number of remaining blocks) – (
)
memory capacity for one block
4M bits
= 254 –
32K bits
= 254 – 128
= 126 (7Eh)
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The following table provides the memory configurations available when a 4M-bit serial register is used for flex
record/playback.
RSEL2
L
L
H
H
RSEL1
L
H
L
H
CS1
4 Mbit
8 Mbit
8 Mbit
8 Mbit
CS2
—
4 Mbit
8 Mbit
8 Mbit
CS3
—
—
4 Mbit
8 Mbit
CS4
—
—
—
4 Mbit
4 Mbit × 1
12 Mbit × 2
20 Mbit × 3
28 Mbit × 4
32 Kbit
64 Kbit
128 Kbit
128 Kbit
Serial register and
corresponding CS
signal
Total memory capacity
Memory capacity per block
Number of blocks for 4M bits
Initially available block (when only
an 8M-bit serial register is used)
128 (80h)
64 (40h)
32 (20h)
32 (20h)
126 (7Fh)
[254 (FEh)]
191 (BFh)
[255 (FFh)]
159 (9Fh)
[191 (BFh)]
223 (DFh)
[255 (FFh)]
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3. Playback method in the flex record/playback mode
(1) Input the record/playback conditions by the corresponding commands as follows.
VDS command:
SAMP command:
CHAN command:
LEV command:
PLAY command:
Specify the ADPCM bit length (BIT).
The voice triggered starting (VD0, VD1) is invalid for the playback operation.
Set the command mode to mode 0 (MOD0 = 0, MOD1= 0) and specify the
sampling frequency (SA0, SA1).
Select one of 63 phrases ch01-ch3F (CA0-CA5).
Specify the playback output level (LV0, LV1).
Set to the playback mode
(2) Input the START command to start the playback. The MSM6688/6688L fetches the contents of the block
table and the stop address of the specified phrase from the channel index area and starts the playback
operation.
(3) When the contents of the address counter coincide with the contents of the stop address register, playback is
finished. The end of playback is verified by the RPM bit of the status register.
(4) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished
by examining the RPM bit before inputting the next command.
(5) To continue playback, specify the record/playback conditions to be modified by the corresponding
commands and perform steps (2)-(4).
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Flow Chart of Playback in the Flex Record/Playback Mode
VDS command
ADPCM bit length (BIT)
SAMP command
Set the command mode to mode 0 (MOD0 = 0, MOD1 = 0).
Specify the sampling frequency (SA0, SA1).
CHAN command
Select one of 63 phrases (CA0-CA5).
LEV command
Set playback output level (LV0, LV1)
PLAY command
Set to the playback mode
START command
No
Start of playback
Verify the start of playback.
RPM = 1?
Yes
Input record/playback
conditions to be modified
by the corresponding
commands.
RPM = 0?
Yes
Verify the end of playback.
No
No
Stop playback?
Yes
STOP command
No
RPM = 0?
STOP of playback
Verify the end of playback.
Yes
Yes
Continue
playback?
No
This flow chart can apply to the playback operation in the direct record/playback mode, excluding that the
command mode is set to mode 2 by the SAMP command and one of 64 phrases (ch00-ch3F) can be selected by
the CHAN command in the direct record/playback mode.
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Direct Record/Playback Method
1. Recording method in the direct record/playback mode
(1) Input the record/playback conditions by the corresponding commands as follows.
VDS command:
SAMP command:
CHAN command:
ADRWR command:
REC command:
Specify the ADPCM bit length (BIT) and voice triggered starting (VD0, VD1).
Set the command mode to mode 2 (MOD = 0, MOD = 1) and specify the sampling
frequency (SA0, SA1).
Select one of 64 phases ch00-ch3F (CA0-CA5).
Input the start address and the stop address.
Set to the recording mode
(2) Input the START command to start the recording. The MSM6688/6688L fetches the start address and the
stop address of the specified phrase input by the ADRWR from the channel index area and stores them in
the address counter and the stop address register, respectively. Then it starts recording.
(3) When the contents of the address counter coincide with the contents of the stop address register, recording
is finished. Verity the end of recording by the RPM bit of the status register.
(4) To stop recording in the middle, input the STOP command. In this case, the contents of the address counter
is automatically stored in the channel index area as a new stop address. Make sure that recording is finished
by examining the RPM bit before inputting the next command.
(5) To continue recording, specify the record/playback conditions to be modified by the corresponding
commands and perform steps (2)-(4).
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Flow Chart of Recording in the Direct Record/Playback Mode
ADPCM bit length (BIT)
Voice triggered starting (VD0, VD1)
VDS command
SAMP command
Set the command mode to mode 2 (MOD0 = 0, MOD1 = 1).
Specify the sampling frequency (SA0, SA1).
CHAN command
Select one of 64 phrases (CA0-CA5).
ADRWR command
Input the start address and stop address.
REC command
Set the recording mode.
START command
No
Start of recording
RPM = 1?
Verify the start of recording.
Yes
Input record/playback
conditions to be modified
by the corresponding
commands.
RPM = 0?
Yes
Verify the end of recording.
No
No
Stop recording?
Yes
STOP command
No
RPM = 0?
Stop of recording
Verify the end of recording.
Yes
Yes
Continue
recording?
No
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2. Playback method in the direct record/playback mode
The playback method in the direct record/playback mode is similar to that in the flex record/playback mode,
excepting that in the direct playback mode, the command mode is specified to mode 2 by the SAMP command
and a phrase can be selected from a total of 64 phrases (ch00-ch3F) by the CHAN command.
(1) Input the record/playback conditions by the corresponding commands as follows.
VDS command:
SAMP command:
CHAN command:
LEV command:
PLAY command:
Specify the ADPCM bit length (BIT).
The voice triggered starting (VD0, VD1) is invalid for the playback operation.
Set the command mode to mode 2 (MOD = 0, MOD = 1) and specify the sampling
frequency (SA0, SA1).
Select one of 64 phrases ch00-ch3F (CA0-CA5).
Specify the playback output level (LV0, LV1).
Set the playback mode
(2) Input the START command to start the playback. The MSM6688/6688L fetches the start address and the
stop address of the specified phrase from the channel index area and stores them in the address counter and
the stop address register, respectively. Then it starts the playback operation.
(3) When the contents of the address counter coincide with the contents of the stop address register, playback is
finished. The end of playback is verified by the RPM bit of the status register.
(4) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished
by examining the RPM bit before inputting the next command.
(5) To continue playback, specify the record/playback conditions to be modified by the corresponding
commands and perform steps (2)-(4).
For the flow chart, refer to the flow chart of record/playback in the flex record/playback mode.
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ROM Playback by Inputting Address Code
1. Method of inputting commands
(1) Input the record/playback conditions by the corresponding commands as follows.
SAMP command:
CHAN command:
LEV command:
Set the command mode to mode 1 (MOD0 = 1, MOD1= 0).
The sampling frequency (SA0, SA1) is invalid.
Select one of 255 phrases ch01-chFF (CA0-CA7).
Specify the playback output level (LV0, LV1).
(2) Input the START command to start the playback. The MSM6688/6688L fetches the data of the start
address, stop address, sampling frequency, and ADPCM bit length of the specified phrase from the channel
index area of the serial voice ROMs and starts the playback operation.
(3) When the contents of the address counter coincide with the contents of the stop address register, playback is
finished. The end of playback is verified by the RPM bit of the status register.
(4) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished
by examining the RPM bit before inputting the next command.
(5) To continue playback, specify the record/playback conditions to be modified by the corresponding
commands and perform steps (2)-(4).
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Flow Chart of ROM Playback by Input of Address Code
SAMP command
Set the command mode to mode 1 (MOD0 = 1, MOD1 = 0).
CHAN command
Select one of 255 phrases (CA0-CA7).
LEV command
Set playback output level (LV0, LV1).
START command
No
Start of playback
RPM = 1?
Verify the start of playback.
Yes
Input record/playback
conditions to be modified
by the corresponding
commands.
RPM = 0?
Yes
Verify the end of playback.
No
No
Stop playback?
Yes
STOP command
No
RPM = 0?
STOP of playback
Verify the end of playback.
Yes
Yes
Continue
playback?
No
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2. Continuous ROM playback
The procedure for playback of different phrases such as the time signal continuously is described below. The
command inputting procedure for continuous ROM playback is basically equal to that for a single phrase. In this
case, during playback of a phrase, the next phrase to be played back can be specified by the NAR bit of the status
register. Continuous playback can also be performed by verifying the end of playback of each phrase using the
RPM, instead of use of the NAR bit. To make continuous playback using NAR bit perform the following
procedure.
(1) Specify a phrase by the CHAN command and input the START command to start playback. When the
START command is accepted, the NAR bit of the status register goes to 0.
(2) When the NAR bit is changed from 0 to 1 to indicate that the next phrase can be specified and inputted,
specify the next phrase to be played back by the CHAN command and input the START command. After
the START command is accepted, the NAR bit goes to 0 again.
(3) In the same way as mentioned above, repeat the designation of a phrase and input of the START command
verifying the state of the NAR bit.
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Flow Chart of Continuous ROM Playback
No
NAR = 1?
Verify whether a phrase can be specified or not.
Yes
CHAN command
Specify one of 255 phrases (CA0-CA7).
START command
The specified phrase is accepted.
No
NAR = 0?
Verify whether playback of the specified phrase is accepted or not.
Yes
Yes
Next phrase
to be played
back?
No
No
RPM = 0?
Verify the end playback.
Yes
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Direct ROM Playback Method
A technique for ROM to be accessed directly is used when the contents of a serial voice ROM prepared for the
MSM6388/6588/6588L are played back.
The channel index area is not provided at the header area of serial voice ROMs. Therefore, it is required to
prepare a ROM in the microcontroller or an external ROM to store the start and stop addresses, sampling
frequency, and ADPCM bit length of each phrase.
The start address and stop address of each phrase consists of 32 bits. These addresses are indicated in the voice
address corresponding list of the serial voice ROM.
For example, the addresses to provide the “Message + Cattle Voice (English)” are as shown in the following
table.
No.1
Voice words
Start X address
STX11-STX0
Stop X address
SPX11-SPX0
Stop Y address
SPY7-SPY0
Sampling
frequency fs
ADPCM
bit length
Message +
Cattle Voice
(English)
000h
010h
5Dh
6.4 kHz
4 bits
Before starting playback, the address data must be transferred to the channel index area of the status register
using the ADRWR command. In this case, a phrase that is not used for record/playback must be specified for
this direct ROM playback using the CHAN command. When recording a phrase in the flex record/playback
mode, ch00 is inhibited to specify. Normally, ch3F address is used as the phrase dedicated for direct ROM
playback.
(1) Input the record/playback conditions by the corresponding commands as follows.
VDS command:
SAMP command:
CHAN command:
ADRWR command:
Specify the ADPCM bit length (BIT).
The voice triggered starting (VD0, VD1) is invalid for the playback operation.
Set the command mode to mode 3 (MOD1 = 1, MOD0 = 1) and specify the
sampling frequency (SA0, SA1).
Select one of 64 phrases ch00-ch3F (CA0-CA5). Normally ch3F is used for
direct ROM playback.
Specify the start and stop addresses.
(2) Input the START command to start the ROM playback. The MSM6688/6688L fetches the start address and
the stop address of the specified phrase from the channel index area of the serial registers. Then it starts the
playback operation.
(3) To stop playback in the middle, input the STOP command. In this case, make sure that playback is finished
by examining the RPM bit.
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Flow Chart of Direct ROM Playback
VDS command
ADPCM bit length (BIT)
Set the command mode to mode 3 (MOD0 = 1, MOD1 = 1).
Specify the sampling frequency (SA0, SA1).
SAMP command
CHAN command
Select one of 64 phrases (CA0-CA5). Normally, specify ch3F.
ADRWR command
Input the start address and stop address.
START command
Start of playback
No
RPM = 1?
Verify the start of playback.
Yes
Input record/playback
conditions to be modified
by the corresponding
commands.
RPM = 0?
No
Verify the end of playback.
No
Stop
playback?
Yes
STOP command
No
Yes
RPM = 0?
Stop of playback
Verify the end of playback.
Yes
Yes
Continue
playback?
No
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Stopping Record/Playback Temporarily (by the PAUSE Command)
The record/playback operation in progress can be stopped temporarily by inputting the PAUSE command. The
record/playback operation stopped using the PAUSE command can be restarted by inputting the START
command. During temporary stop state, the VPM bit of the status register is 1 and the RPM bit keeps 1.
If the START command is input to restart the recording operation that is temporarily suspended by the PAUSE
command in the voice reiggered starting mode, the recording will be started immediately even in the state of
silence. The PAUSE command is invalid during record/playback standby state, temporarily stopped state, and
standby state for voice.
WR
D0-D3
Status register
START
command
PAUSE
command
START
command
STOP
command
RPM bit
VPM bit
Standby Record/playback
Temporarily stopped
Record/playback Standby
Immediately restarted even in
case of voice triggered starting
When the STOP command is input during temporarily stopped state, the record/playback operation is finished
and the MSM6688/6688L is placed in the standby state.
WR
D0-D3
Status register
START
command
PAUSE
command
STOP
command
RPM bit
VPM bit
Standby Record/standby
Temporarily stopped
Standby
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Transferring Data to/from External Memories
1. Method of transferring data to/from external serial registers (by the CHRW command)
The MSM6688/6688L can transfer data to/from the user area in the channel index area of external RAM using
the CHRW command. Before starting this data transfer operation, a desired phrase must be specified using the
CHAN command. The memory capacity for each phrase is 704 bits (176 nibbles) in the flex record/playback
mode and 960 bits (240 nibbles) in the direct record/playback mode. The read/write operation must be performed
for the data that does not exceed this memory capacity per phrase.
The contents of the user area for a specified phrase or for all phrases will be cleared to all 0s (0h data) using the
CHAN and DEL commands.
The following shows the procedure for inputting the CHRW command.
(1) Set the command mode to mode 0 or mode 1 (MOD1 = 0) using the SAMP command.
(2) Specify a phrase using the CHAN command.
(3) After inputting the CHAN command, wait for BUSY state duration. The end of the BUSY state duration
can also be verified by the BUSY bit of the status register.
(4) To write data, input the REC command and then input the data to be written by applying the WR pulse. It is
required to wait for the busy state duration between the contiguous WR pulses.
When the data writing operation is performed by inputting a single input of the CHRW command, the state
of the BUSY bit of the status register can be verified by inputting the RD pulse. When the data read
operation is performed with the data write operation, the state of the BUSY bit cannot be verified by
inputting the RD pulse.
(5) When reading data, wait for the BUSY state duration after inputting the PLAY command and then input the
RD pulse. With this operation, 4-bit data will be output via the data bus.
(6) To continue the data read or write operation, specify the read or write mode using the PLAY or REC
commands.
(7) To stop the data read/write operation, input the STOP command. After waiting for the BUSY state duration,
the next command can be input.
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Flow Chart of Data Transfer Using the CHRW Command
SAMP command
Set the command mode to mode 0 or mode 1 (MOD1=0).
CHAN command
Specify one of 64 phrases (CA0-CA5).
CHRW command
Wait for BUSY state
duration
Data write?
No
Yes (Data write)
(Data read)
REC command
PLAY command
Wait for BUSY state
duration
Wait for BUSY state
duration
Input WR pulse
Data input
Input RD pulse
Data output
Wait for BUSY state
duration
Yes
Continue data
transfer?
No
STOP command
Wait for BUSY state
duration
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2. Method of transferring data to and from external RAM (by the DTRW command)
The data transfer to/from external RAM is performed using the DTRW command. After inputting the DTRW
command, specify an address to be accessed for data read/write. The transfer of each 4-bit data is performed
from the starting nibble of the specified address. For the address space, refer to Section 1.2 “Address space
allocation in the direct record/playback mode” in “Data Configuration of External RAM.” The address
designation can be made only in the X direction and random address designation cannot be made in the Y
direction to select an arbitrary address in the Y direction.
With the input of a single DTRW command, continuous read/write operation can be made in the range of
addresses 8M bit (CS1, CS2, CS3, CS4). When the read/write operation is extended to two or more 8M bits
(CS1, CS2, CS3, CS4), it is necessary to stop temporarily the read/write operation each time the operation is
finished for one serial register, and set the address for another serial register using the DTRW command.
(1) Set the common mode to mode 2 (MOD0 = 0, MOD1 = 1).
(2) Input the DTRW command.
(3) Specify the X address in a serial register by inputting the WR pulse five times. Wait for the BUSY state
duration. The BUSY state can be verified by examining the state of the BUSY bit of the status register. The
2nd nibble of the DTRW command is a dummy nibble. Always input 0h data into the 2nd nibble.
(4) For data writing, input the REC command and input the data to be written by inputting the WR pulse. Wait
for the BUSY state duration between the contiguous WR pulses.
To make the data write operation by a single input of the DTRW command, the state of the BUSY bit can
be verified by inputting the RD pulse. When data write and data read operations are performed jointly, the
state at the BUSY bit cannot be verified using the RD pulse.
(5) To read data, input the PLAY command and then input the RD pulse after waiting for the BUSY state
duration. With this operation, 4-bit data will be output via the data bus.
(6) To continue data read/write operation, specify the read or write mode using the PLAY or REC command
and make data transfer operation.
(7) To finish the data read/write operation, input the STOP command. After waiting for the BUSY state
duration, the next command can be input.
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Flow Chart of Data Transfer Using the DTRW Command
SAMP command
Specify the command mode to mode 2 (MOD0 = 0, MOD1 = 1).
DTRW command
Input dummy nibble
(2nd nibble)
(0, 0, 0, 0)
Input X address
(3rd nibble)
(X0, X1, X2, X3)
Input X address
(4th nibble)
(X4, X5, X6, X7)
Input X address
(5th nibble)
(X8, X9, X10, X11)
Input X address
(6th nibble)
(X12, X13, X14, X15)
Wait for BUSY state
duration
Data write?
No
Yes (Data write)
(Data read)
REC command
PLAY command
Wait for BUSY state
duration
Wait for BUSY state
duration
Input WR pulse
Data input
Input RD pulse
Data output
Wait for BUSY state
duration
Yes
Continue
data transfer?
No
STOP command
Wait for BUSY state
duration
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3. Method of reading data from external serial voice ROMs (by the DTRD command)
The data from external serial voice ROMs can be read using the DTRD command. After inputting the DTRD
command, specify the address to be read. The data is read in groups of 4 bits from the specified address. For the
address space, refer to “Data Configuration of External Serial Voice ROMs.” The data can be addressed on a
64-bit basis.
With the input of a single DTRD command, continuous read/write operation can be made in the range of
addresses assigned to the same serial voice ROM. When the read/write operation is extended to two or more
serial voice ROMs, it is necessary to stop temporarily the read/write operation each time the operation is finished
for the serial voice ROM, and set the address for another serial voice ROM using the DTRD command.
The following shows the procedure for inputting the DTRD command.
(1) Set the command mode to mode 3 (MOD0 = 1, MOD1 = 1).
(2) Input the DTRD command.
(3) Specify the X address and Y address of the serial voice ROM by inputting the WR pulse five times. Then,
wait for the BUSY state duration. The 6th nibble is a dummy nibble. Always input 0h data into this 6th
nibble.
(4) Input the PLAY command and wait for the BUSY state duration. Then, input the RD pulse, so that 4-bit
data will be output via the data bus.
(5) To continue data read operation, perform the data read operation inputting the PLAY command and RD
pulse in the same way as mentioned above.
(6) To finish the data read operation input the STOP command. After waiting for the BUSY state duration, the
next command can be input.
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Flow Chart of Data Read Using the DTRD Command
SAMP command
Specify the command mode to mode 3 (MOD0 = 1, MOD1 = 1).
DTRD command
Input Y address
(2nd nibble)
(Y0, Y1, Y2, Y3)
Input lower bits of
X address (3rd nibble)
(X0, X1, X2, X3)
Input middle 4 bits of
X address (4th nibble)
(X4, X5, X6, X7)
Input upper 4 bits of
X address (5th nibble)
(X8, X9, X10, X11)
Input dummy nibble
(6th nibble)
(0, 0, 0, 0)
Wait for BUSY state
duration
PLAY command
Wait for BUSY state
duration
Input RD pulse
Data read
Wait for BUSY state
duration
Yes
Continue to
read data?
No
STOP command
Wait for BUSY state
duration
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Record/Playback by Inputting/Outputting Voice Data via Data Bus
When SRAMs (static RAMs) or other hardware memory products are used to store voice data, the
record/playback operation will be performed by using the EXT command. In the case of the record/playback
using the EXT command, voice data is directly input or output via the data bus in synchronization with the
sampling frequency. In this record/playback mode, the address control and the control of external RAM and
serial voice ROMs are not performed. Therefore, the microcontroller performs the recording time control and
address control. In this mode, temporary stop of record/playback operation by the PAUSE command and the
voice triggered starting cannot be performed.
1. Method of recording using the EXT command
(1) Input the record/playback conditions using the corresponding commands as shown below.
VDS command:
SAMP command:
REC command:
Set the ADPCM bit length (BIT).
Specify the disabled state of voice triggered starting (VD0 = 0, VD1 = 0).
Specify the sampling frequency (SA0, SA1).
The command mode (MOD0, MOD1) is invalid.
Set to the recording mode
(2) Input the EXT command to start the recording.
The sampling frequency clock is output via the MON pin.
(3) When the MON pin goes high, input the RD pulse to fetch the ADPCM data from the external memory via
the data bus. At that time, input the RD pulse to satisfy time tERD from rise of MON to rise of the RD pulse.
In the case of 3-bit ADPCM, the upper 3 bits (D3-D1 pins) are valid and the lower 1 bit (D0 pin) is invalid.
(4) Store the ADPCM data into the external memory such as SRAMs.
(5) Repeat steps (3) and (4) to continue the recording operation.
(6) Input the STOP command to stop the recording operation. Until the STOP command is input, the recording
operation will be continued without the limit for the recording time.
When the MON pin becomes “H” level, input the RD pulse to fetch the ADPCM data, and input the STOP
command to satisfy time tESP from rise of MON to input of the STOP command.
(7) During recording by the EXT command, the contents of the status register cannot be verified by the RD
pulse. Therefore, after inputting the STOP command, wait for the BUSY state duration and then input the
next command.
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Flow Chart of Recording Using the EXT Command
SAMP command
Specify the sampling frequency (SA0, SA1).
VDS command
Specify the ADPCM bit length (BIT).
REC command
Set to the recording mode
EXT command
Start the recording by EXT command.
Detection of the rising
edge of the pulse at
MON output pin
Input the RD pulse
Fetch ADPCM data from memory.
Store the ADPCM
data into memory
Store the ADPCM data into an external memory such as SRAM.
Yes
Continue
recording?
No
STOP command
End of recording by EXT command
Wait for BUSY
state duration
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2. Method of playback using the EXT command
(1) Input the record/playback conditions using the corresponding commands as shown below.
VDS command:
SAMP command:
PLAY command:
Set to the ADPCM bit length (BIT) specified for recording
Voice triggered starting becomes invalid.
Specify the sampling frequency (SA0, SA1).
The command mode (MOD0, MOD1) is invalid.
Set to the playback mode
(2) Input the EXT command to start the playback. The sampling frequency clock is output via the MON pin.
(3) When the MON pin goes high, the ADPCM data is ready to be fetched from an external memory such as an
SRAM.
(4) Input the WR pulse to fetch the ADPCM data from the external memory via the data bus. At that time,
input the WR pulse to satisfy time tEWR from rise of MON to rise of the WR pulse. In the case of 3-bit
ADPCM, the upper 3 bits (D3-D1 pins) are valid and the lower 1 bit (D0 pin) is invalid.
(5) Repeat steps (3) and (4) to continue the playback operation.
(6) Input the STOP command to stop the playback operation.
When the MON pin becomes “H”, input the WR pulse, input the ADPCM data, and input the STOP
command to satisfy time tESP from rise of MON to input of the STOP command, and interval tWE1 between
the WR pulse and the STOP command pulse.
Note:
Input the ADPCM data beginning with the top of a phrase every sampling period sequentially. If the
ADPCM data is input beginning with the second or following part of a phrase or with data missing,
normal (playback) waveforms cannot be regenerated.
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Flow Chart of Playback Using the EXT Command
SAMP command
Specify the sampling frequency (SA0, SA1).
VDS command
Specify the ADPCM bit length (BIT).
PLAY command
Set to the playback mode
EXT command
Start the playback by EXT command.
Detection of the rising
edge of the pulse at
MON output pin
Read ADPCM data
from memory
Input the WR pulse
Yes
Write the ADPCM data.
Continue
playback?
No
STOP command
Stop the playback by EXT command.
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Suppression of Pop Noise at AOUT Output (by the LEV Command)
The MSM6688/6688L has a on-chip pop noise suppression circuit to prevent pop nose from being generated due
to sharp changes of the DC level of the analog output (at the AOUT pin). The enabled or disabled state of this
pop noise suppression circuit can be selected using the ACON pin. When the ACON pin is low, this circuit is
disabled and when high, this circuit is enabled.
1. When the POP noise suppression circuit is disabled (ACON = low)
When the RESET pin is high, the DC level at the AOUT pin is the ground level, and when the RESET pin is low,
the DC level at the AOUT pin is the 1/2 VDD level. Each time the state of the RESET pin is changed, the DC
level is changed sharply and pop noise is generated.
RESET
1/2 VDD level
AOUT
GND level
GND level
Pop noise
Pop noise
Power down
Standby
Record/playback
Standby
Power down
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2. When the POP noise suppression circuit is enabled (ACON = high)
The transition of the DC level at the AOUT (analog output) pin is controlled using the LEV command. When the
RESET pulse (low) is applied to the RESET pin, the DC level at the AOUT output pin goes to the ground level.
If the pop noise suppression circuit is activated using the PN0 and PN1 bits of the 2nd nibble of the LEV
command, the DC level at the AOUT output pin will be changed from the ground level to the 1/2 VDD level or
from the 1/2 VDD level to the ground level slowly to prevent pop noise from being generated.
Before starting the record/playback operation, always set the DC level at the AOUT pin to the 1/2 VDD level
using the LEV command. When enabling the DC level transition function by the LEV command, first specify
the playback mode by the play command and then input the LEV command.
PN1
PN0
DC level transition
0
0
Disabled
0
1
Disabled
1
0
Transition from ground to 1/2 VDD
1
1
Transition from 1/2 VDD to ground
RESET
1/2 VDD level
AOUT
GND level
Power down
GND level
Record/playback
Transition
LEV command
Power down
Transition
LEV command
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ADPCM SOLID-STATE RECORDER IC MSM6688/6688L
SG
SGC
Speaker drive amplifier
SAS
SADY
SASX
VCC
DOUT
TEST
CS1CS2 VSS
DROM
SASY
TAS
TAS
RWCK
RDCK
SADY
SADX
OKI Semiconductor
DGND AGND
MON
NAR
MSM6685A
Circuit Diagram 1: Application circuit in
microcontroller interface mode with 8M bit
serial registers and 2M bit serial voice ROMs
MSM6685A
LOUT
AMON
FIN
FOUT
ADIN
AOUT
LIN
MOUT
MIN
CS4
CS3
CS2
CS1
MSM6685A
XT
XT
BUSY
RPM
VPM
ACON
TEST
TEST
TEST NC
CS VSS
TEST
TEST
DI/O DIN
DOUT
SAS
SADX
2M SERIAL VOICE ROM
MSM6596A-XXX
4.096 MHz
MICROCONTROLLER
DROM
DI/O
VCC
SAD
TAS TAS
RWCK RWCK
WE WE
SAS
SADX
8M SERIAL REGISTER
MCUM
RSEL1
RSEL2
CE
PDWN
TAS
RWCK
WE
SADY
SAS
SADX
MSM6685A
RESET
RD
WR
CE
D3
D2
D1
D0
DVDD DVDD’ AVDD
FEDL6688-6688L-04
MSM6688/6688L
APPLICATION CIRCUIT
The circuit diagram 1 shows an application circuit example where the MSM6688/6688L is used in the
microcontroller interface mode and four 8M bit serial registers and two 2M bit serial voice ROMs are connected.
MSM6596A-XXX
+
+
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PACKAGE DIMENSIONS
(Unit: mm)
QFP56-P-910-0.65-2K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.43 TYP.
4/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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(Unit: mm)
TQFP64-P-1010-0.50-K
Mirror finish
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Solder plating (≥5µm)
0.26 TYP.
4/Oct. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
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REVISION HISTORY
Document
No.
E2D0026-39-23
FEDL6688-6688L-04
Date
Feb. 1999
Mar. 12, 2002
Page
Previous Current
Edition
Edition
―
―
28
28
81
81
82
82
Description
Third edition
Changed contents of the tables for ceramic
oscillators
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical
improvements. Before using the product, please make sure that the information being referred to is
up-to-date.
2.
The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3.
When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4.
Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.
5.
Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party’s right which may result
from the use thereof.
6.
The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires
special or enhanced quality and reliability characteristics nor in any system or application where the failure
of such system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.
7.
Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8.
No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2002 Oki Electric Industry Co., Ltd.
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