CY7C128A 2K x 8 Static RAM Features • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 660 mW (commercial) — 688 mW (military—20 ns) • Low standby power — 110 mW (20 ns) • TTL-compatible inputs and outputs • Capable of withstanding greater than 2001V electrostatic discharge • VIH of 2.2V Functional Description provided by an active LOW Chip Enable (CE), and active LOW Output Enable (OE) and three-state drivers. The CY7C128A has an automatic power-down feature, reducing the power consumption by 83% when deselected. Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. Data on the eight I/O pins (I/O0 through I/O7) is written into the memory location specified on the address pins (A0 through A10). Reading the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the eight I/O pins. The I/O pins remain in high-impedance state when Chip Enable (CE) or Output Enable (OE) is HIGH or Write Enable (WE) is LOW. The CY7C128A utilizes a die coat to insure alpha immunity. The CY7C128A is a high-performance CMOS static RAM organized as 2048 words by 8 bits. Easy memory expansion is Pin Configurations Logic Block Diagram DIP/SOJ/SOIC Top View I/O0 INPUT BUFFER I/O3 I/O4 A4 A3 A2 A1 A0 I/O0 I/O1 I/O5 CE WE I/O6 POWER DOWN COLUMN DECODER I/O7 OE A3 A2 A1 A0 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 C128A–2 A5 A6 A7 VCC A8 128 x 16 x 8 ARRAY LCC Top View 3 2 1 24 23 4 22 5 21 6 20 7 7C128A 19 8 18 9 17 10 16 11 12 13 14 15 I/O 2 GND I/O 3 I/O 4 I/O 5 A6 A5 A4 1 24 23 2 22 3 4 21 5 20 6 19 7C128A 18 7 17 8 9 16 10 15 11 14 12 13 I/O2 SENSE AMPS A8 A7 I/O1 ROW DECODER A10 A9 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND C128A–1 A9 WE OE A10 CE I/O7 I/O6 C128A–3 Selection Guide 7C128A-15 15 120 40 - Maximum Access Time (ns) Maximum Operating Commercial Current (mA) Military Maximum Standby Commercial Current (mA) Military Cypress Semiconductor Corporation Document #: 38-05028 Rev. ** • 7C128A-20 20 120 125 20 20 3901 North First Street • 7C128A-25 25 120 125 20 20 San Jose • 7C128A-35 35 120 125 20 20 7C128A-45 45 120 125 20 20 CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C128A Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current.................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Commercial 0°C to +70°C 5V ± 10% DC Input Voltage............................................ –3.0V to +7.0V Military[1] –55°C to +125°C 5V ± 10% Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions 7C128A-15 7C128A-20 7C128A-25 Min. Min. Min. Max. 2.4 Max. 2.4 Max. 2.4 Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC 2.2 VCC 2.2 VCC VIL Input LOW Voltage[3] –0.5 0.8 –0.5 0.8 –0.5 IIX Input Load Current GND < VI < VCC –10 +10 –10 +10 IOZ Output Leakage Current GND < VI < VCC Output Disabled –10 +10 –10 +10 IOS Output Short CircuitCurrent[4] VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max. IOUT = 0 mA Com’l ISB1 Automatic CE Power-Down Current Max. VCC, CE > VIH, Min. Duty Cycle = 100% Com’l Automatic CE Power-Down Current Max. VCC, CE1 >VCC–0.3V, V N > VCC–0.3V or VIN < 0.3V Com’l ISB2 Mil Mil Mil 0.4 Min. Max. 2.4 VOH 0.4 7C128A-35,45 0.4 Unit V 0.4 V 2.2 VCC V 0.8 –0.5 0.8 V –10 +10 –10 +10 µA –10 +10 –10 +10 µA –300 –300 –300 –300 mA 120 120 120 120 mA - 125 125 125 40 40 20 20 - 40 40 20 40 20 20 20 - 20 20 20 mA mA Capacitance[5] Parameter CIN Description Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 Unit pF 10 pF Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. VIL (min.) = –3.0V for pulse durations less than 30 ns. 4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05028 Rev. ** Page 2 of 10 CY7C128A AC Test Loads and Waveforms R1 481Ω 5V R1 481Ω 5V OUTPUT ALL INPUT PULSES OUTPUT R2 255 Ω 30 pF INCLUDING JIG AND SCOPE 3.0V R2 255 Ω 5 pF INCLUDING JIG AND SCOPE (a) GND 90% 10% 90% 10% ≤ 5 ns ≤ 5 ns (b) C128A–5 C128A–4 Equivalent to: THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V Switching Characteristics Over the Operating Range[2, 6] Parameter Description 7C128A-15 7C128A-20 7C128A-25 7C128A-35 7C128A-45 Min. Min. Min. Min. Min. Max. Max. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time 15 20 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 15 20 25 tDOE OE LOW to Data Valid 10 10 12 tLZOE OE LOW to Low Z 15 5 tHZOE OE HIGH to High Z tLZCE CE LOW to Low Z[8] tHZCE CE HIGH to High Z[7, 8] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 20 5 3 [7] 25 8 8 8 0 15 35 10 0 20 ns 35 45 ns 15 20 ns 5 12 ns 15 5 15 0 20 ns 3 5 10 ns 45 3 5 8 45 5 3 5 0 25 5 3 5 35 15 0 20 ns ns ns ns 25 ns WRITE CYCLE[9] tWC Write Cycle Time 15 20 20 25 40 ns tSCE CE LOW to Write End 12 15 20 25 30 ns tAW Address Set-Up to Write End 12 15 20 25 30 ns tHA Address Hold from Write End 0 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 0 ns tPWE WE Pulse Width 12 15 15 20 20 ns tSD Data Set-Up to Write End 10 10 10 15 15 ns tHD Data Hold from Write End 0 0 0 0 0 ns [7] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z 7 5 7 5 7 5 10 5 15 5 ns ns Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05028 Rev. ** Page 3 of 10 CY7C128A Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C128A–6 Read Cycle No. 2[10, 12] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C128A–7 Write Cycle No. 1 (WE Controlled)[9, ] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATAIN VALID DATA IN tHZWE DATA I/O tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED C128A–8 Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected. OE, CE = VIL. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write. Document #: 38-05028 Rev. ** Page 4 of 10 CY7C128A Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[9, 13, 14] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tHD tSD DATA IN VALID DATA IN tHZWE HIGH IMPEDANCE DATA I/O DATA UNDEFINED C128A–9 Notes: 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 NORMALIZED ICC, ISB 1.2 ICC 1.0 0.8 0.6 0.4 0.0 4.0 4.5 5.0 ICC 0.8 0.6 0.4 VCC = 5.0V VIN = 5.0V 0.2 ISB 0.2 1.0 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.6 1.4 1.3 NORMALIZED tAA NORMALIZED tAA 125 1.2 1.1 TA = 25°C 1.0 1.4 1.2 1.0 VCC = 5.0V 0.8 0.9 4.5 5.0 5.5 SUPPLY VOLTAGE(V) Document #: 38-05028 Rev. ** OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 VCC =5.0V TA = 2 5°C) 60 40 20 0 0.0 AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE(V) 0.8 4.0 25 6.0 0.6 –55 25 125 AMBIENT TEMPERATURE(°C) 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT (mA) NORMALIZED ICC, ISB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 VCC =5.0V TA = 25°C 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) Page 5 of 10 CY7C128A Typical DC and AC Characteristics (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING NORMALIZED I CC vs. CYCLE TIME 30.0 1.4 2.5 25.0 1.3 2.0 1.5 1.0 0.5 0.0 0.0 20.0 15.0 10.0 VCC = 4.5V TA = 25°C 5.0 1.0 2.0 3.0 4.0 5.0 0.0 0 200 SUPPLY VOLTAGE(V) 400 600 800 1000 CAPACITANCE (pF) NORMALIZED ICC 3.0 DELTA t AA (ns) NORMALIZED IPO TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE VCC = 5.0V TA = 25°C VIN = 0.5V 1.2 1.1 1.0 0.9 0.8 0 10 20 30 40 CYCLE FREQUENCY (MHz) Ordering Information Speed (ns) 15 20 25 35 45 Ordering Code CY7C128A-15PC CY7C128A-15VC CY7C128A-15SC CY7C128A-20PC CY7C128A-20VC CY7C128A-20SC CY7C128A-20DMB CY7C128A-20LMB CY7C128A-25PC CY7C128A-25VC CY7C128A-25SC CY7C128A-25DMB CY7C128A-35PC CY7C128A-35VC CY7C128A-35SC CY7C128A-35DMB CY7C128A-45PC CY7C128A-45VC CY7C128A-45SC CY7C128A-45DMB CY7C128A-45LMB Document #: 38-05028 Rev. ** Package Name P13 V13 S13 P13 V13 S13 D14 L53 P13 V13 S13 D14 P13 V13 S13 D14 P13 V13 S13 D14 L53 Package Type 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Pin Rectangular Leadless Chip Carrier 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Lead (300-Mil) Molded DIP 24-Lead Molded SOJ 24-Lead (300-Mil) Molded SOIC 24-Lead (300-Mil) CerDIP 24-Pin Rectangular Leadless Chip Carrier Operating Range Commercial Commercial Military Commercial Military Commercial Military Commercial Military Page 6 of 10 CY7C128A MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups VOH 1, 2, 3 VOL 1, 2, 3 VIH 1, 2, 3 VIL Max. 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 ISB 1, 2, 3 Switching Characteristics Parameter Subgroups READ CYCLE tRC 7, 8, 9, 10, 11 tAA 7, 8, 9, 10, 11 tOHA 7, 8, 9, 10, 11 tACE 7, 8, 9, 10, 11 tDOE 7, 8, 9, 10, 11 WRITE CYCLE tWC 7, 8, 9, 10, 11 tSCE 7, 8, 9, 10, 11 tAW 7, 8, 9, 10, 11 tHA 7, 8, 9, 10, 11 tSA 7, 8, 9, 10, 11 tPWE 7, 8, 9, 10, 11 tSD 7, 8, 9, 10, 11 tHD 7, 8, 9, 10, 11 Document #: 38-05028 Rev. ** Page 7 of 10 CY7C128A Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A 51-80031 24-Pin Rectangular Leadless Chip Carrier L53 51-80066 Document #: 38-05028 Rev. ** Page 8 of 10 CY7C128A Package Diagrams (continued) 24-Lead (300-Mil) Molded DIP P13/P13A 51-85013-A 24-Lead (300-Mil) Molded SOJ V13 51-85030-A Document #: 38-05028 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C128A Document Title: CY7C128A 2K x 8 Static RAM Document Number: 38-05028 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106814 09/10/01 SZV Change from Spec number: 38-00094 to 38-05028 Document #: 38-05028 Rev. ** Page 10 of 10