Product Folder Order Now Support & Community Tools & Software Technical Documents bq25700A SLUSCQ8 – MAY 2017 bq25700A SMBus Multi-Chemistry Battery Buck-Boost Charge Controller With System Power Monitor and Processor Hot Monitor • • • • • • • • Charge 1- to 4-Cell Battery From Wide Range of Input Sources – 3.5-V to 24-V Input Operating Voltage – Supports USB2.0, USB 3.0, USB 3.1 (Type C), and USB_PD Input Current Settings – Seamless Transition Between Buck and Boost Operation – Input Current and Voltage Regulation (IDPM and VDPM) Against Source Overload Power/Current Monitor for CPU Throttling – Comprehensive PROCHOT Profile, IMVP8 Compliant – Input and Battery Current Monitor – System Power Monitor, IMVP8 Compliant Narrow-VDC (NVDC) Power Path Management – Instant-On With No Battery or Deeply Discharged Battery – Battery Supplements System When Adapter is Fully-Loaded – Ideal Diode Operation in Supplement Mode Power Up USB Port From Battery (USB OTG) – Output 4.48-V to 20.8-V Compatible With USB PD – Output Current Limit up to 6.35 A 800-kHz or 1.2-MHz Programmable Switching Frequency for 1-µH to 2.2-µH Low Profile Inductor Host Control Interface for Flexible System Configuration – SMBus (bq25700A) Port for Optimal System Performance and Status Reporting – Hardware Pin to Set Input Current Limit Without EC Control High Accuracy Regulation and Monitor – ±0.5% Charge Voltage Regulation – ±2% Input/Charge Current Regulation – ±2% Input/Charge Current Monitor – ±5% Power Monitor Safety – Thermal Shutdown – Input, System, Battery Overvoltage Protection – MOSFET Inductor Overcurrent Protection Low Battery Quiescent Current • • Input Current Optimizer (ICO) to Extract Max Input Power Charge Any Battery Chemistry: Li+, LiFePO4, NiCd, NiMH, Lead Acid Package: 32-Pin 4 × 4 WQFN 2 Applications • • • Ultra-Books, Notebooks, Detachable, and Tablet PCs and Power Bank Industrial and Medical Equipment Portable Equipment With Rechargeable Batteries 3 Description The bq25700A is a synchronous NVDC battery buckboost charge controller, offering low component count, high efficiency solution for space-constraint, multi-chemistry battery charging applications. The NVDC-1 configuration allows the system to be regulated at battery voltage, but not drop below system minimum voltage. The system keeps operating even when the battery is completely discharged or removed. When load power exceeds input source rating, the battery goes into supplement mode and prevents the input source from being overloaded. The bq25700A charges battery from a wide range of input sources including USB adapter, high voltage USB PD sources and traditional adapters. Device Information PART NUMBER PACKAGE bq25700A (1) BODY SIZE (NOM) WQFN (32) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Diagram VSYS Adapter 3.5V ± 24V BATT (1S-4S) Q1 Q2 Q3 Q4 SW1BTST1BTST2SW2 HIDRV2 HIDRV1 LODRV1 LODRV2 SYS VBUS ACN BATDRV bq25700A ACP SRP SRN IADPT, IBAT, PSYS, PROCHOT • 1 • SMBus 1 Features Host Copyright © 2017, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq25700A SLUSCQ8 – MAY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (Continued) ........................................ Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 8.5 Programming .......................................................... 29 8.6 Register Map........................................................... 31 1 1 1 2 3 4 7 9 9.1 Application Information .......................................... 64 9.2 Typical Application .................................................. 64 10 Power Supply Recommendations ..................... 72 11 Layout................................................................... 73 11.1 Layout Guidelines ................................................. 73 11.2 Layout Example .................................................... 73 Absolute Maximum Ratings ...................................... 7 ESD Ratings ............................................................ 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 Electrical Characteristics........................................... 8 Timing Requirements .............................................. 16 Typical Characteristics ........................................... 17 12 Device and Documentation Support ................. 75 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Detailed Description ............................................ 20 8.1 8.2 8.3 8.4 Overview ................................................................ Functional Block Diagram ...................................... Feature Description................................................. Device Functional Modes........................................ Application and Implementation ........................ 64 20 21 22 28 Device Support .................................................... Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 75 75 75 75 75 75 75 13 Mechanical, Packaging, and Orderable Information ........................................................... 76 4 Revision History 2 DATE REVISION NOTES May 2017 * Initial release. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 5 Description (Continued) During power up, the charger sets converter to buck, boost or buck-boost configuration based on input source and battery conditions. The charger automatically transits among buck, boost and buck-boost configuration without host control. In the absence of an input source, the bq25700A supports On-the-Go (OTG) function from 1- to 4-cell battery to generate 4.48 V to 20.8 V on VBUS. During OTG mode, the charger regulates output voltage and output current. The bq25700A monitors adapter current, battery current and system power. The flexibly programmed PROCHOT output goes directly to CPU for throttle back when needed. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 3 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 6 Pin Configuration and Functions SW1 HIDRV1 BTST1 LODRV1 REGN PGND LODRV2 BTST2 32 31 30 29 28 27 26 25 RSN Package 32-Pin WQFN Top View VBUS 1 24 HIDRV2 ACN 2 23 SW2 ACP 3 22 VSYS CHRG_OK 4 21 BATDRV EN_OTG 5 20 SRP ILIM_HIZ 6 19 SRN VDDA 7 18 CELL_BATPRESZ IADPT 8 17 COMP2 Thermal 13 14 15 16 SCL CMPIN CMPOUT COMP1 11 PROCHOT 12 10 PSYS SDA 9 IBAT Pad Pin Functions PIN NAME NUMBER I/O DESCRIPTION ACN 2 PWR Input current sense resistor negative input. The leakage on ACP and ACN are matched. The series resistors on the ACP and ACN pins are placed between sense resistor and filter cap. Refer to Application and Implementation for ACP/ACN filter design. ACP 3 PWR Input current sense resistor positive input. The leakage on ACP and ACN are matched. The series resistors on the ACP and ACN pins are placed between sense resistor and filter cap. Refer to Application and Implementation for ACP/ACN filter design. BATDRV 21 O P-channel battery FET (BATFET) gate driver output. It is shorted to VSYS to turn off the BATFET. It goes 10 V below VSYS to fully turn on BATFET. BATFET is in linear mode to regulate VSYS at minimum system voltage when battery is depleted. BATFET is fully on during fast charge and supplement mode. BTST1 30 PWR Buck mode high side power MOSFET driver power supply. Connect a 0.047-µF capacitor between SW1 and BTST1. The bootstrap diode between REGN and BTST1 is integrated. BTST2 25 PWR Boost mode high side power MOSFET driver power supply. Connect a 0.047-μF capacitor between SW2 and BTST2. The bootstrap diode between REGN and BTST2 is integrated. CELL_BATPRESZ 4 18 I Submit Documentation Feedback Battery cell selection pin for 1–4 cell battery setting. CELL_BATPRESZ pin is biased from VDDA. CELL_BATPRESZ pin also sets SYSOVP threshold to 5 V for 1-cell, 12 V for 2-cell , 18.5 V for 3-cell, and 19.5 for 4-cell. CELL_BATPRESZ pin is pulled below VCELL_BATPRESZ_FALL to indicate battery removal. The device exits LEARN mode, and disables charge. REG0x15() goes back to default. Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Pin Functions (continued) PIN NAME CHRG_OK NUMBER 4 I/O DESCRIPTION O Open drain active high indicator to inform the system good power source is connected to the charger input. Connect to the pullup rail via 10-kΩ resistor. When VBUS rises above 3.5V or falls below 24.5V, CHRG_OK is HIGH after 50ms deglitch time. When VBUS is falls below 3.2 V or rises above 26 V, CHRG_OK is LOW. CMPIN 14 I Input of independent comparator. The independent comparator compares the voltage sensed on CMPIN pin to internal reference, and its output is on CMPOUT pin. Internal reference, output polarity and deglitch time is selectable by SMBus. With polarity HIGH (REG0x30[6] = 1), place a resistor between CMPIN and CMPOUT to program hysteresis. With polarity LOW (REG0x30[6] = 0), the internal hysteresis is 100 mV. If the independent comparator is not in use, tie CMPIN to ground. CMPOUT 15 I Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup supply rail. Internal reference, output polarity and deglitch time are selectable by SMBus. COMP2 17 I Buck boost converter compensation pin 2. Refer to bq25700 EVM schematic for COMP2 pin RC network. COMP1 16 I Buck boost converter compensation pin 1. Refer to bq25700 EVM schematic for COMP1 pin RC network. EN_OTG 5 I Active HIGH to enable OTG mode. When EN_OTG pin is HIGH and REG0x32[13] is HIGH, OTG can be enabled, refer to USB On-The-Go (OTG) for details of how to enable OTG function HIDRV1 31 O Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET gate. HIDRV2 24 O Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET gate. IADPT 8 O Buffered adapter current output. V(IADP) = 20 or 40 × (V(ACP) – V(ACN)). With ratio selectable in REG0x12[4]. Place a resistor from the IADPT pin to ground corresponding to inductor in use. For 2.2 µH, the resistor is 137 kΩ. Place 100-pF or less ceramic decoupling capacitor from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V. IBAT 9 O Buffered battery current selected by SMBus. V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) for charge current, or V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) for discharge current, with ratio selectable in REG0x12[3]. Place 100-pF or less ceramic decoupling capacitor from IBAT pin to ground. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V. ILIM_HIZ 6 I Input current limit input. Program ILIM_HIZ voltage by connecting a resistor divider from supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40 × IDPM × RAC, in which IDPM is the target input current. The input current limit used by the charger is the lower setting of ILIM_HIZ pin and REG0x3F(). When the pin voltage is below 0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage is above 0.8 V, the device is out of Hi-Z mode. LODRV1 29 O Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET gate. LODRV2 26 O Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET gate. PGND 27 GND PROCHOT 11 O Active low open drain output of processor hot indicator. It monitors adapter input current, battery discharge current, and system voltage. After any event in the PROCHOT profile is triggered, a minimum 10-ms pulse is asserted. The pulse width is adjustable in REG0x33[5:2]. PSYS 10 O Current mode system power monitor. The output current is proportional to the total power from the adapter and battery. The gain is selectable through SMBus. Place resistor from PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output voltage is clamped below 3.3 V. Place a capacitor in parallel with resistor for filtering. REGN 28 PWR SCL 13 I SDA 12 I/O Copyright © 2017, Texas Instruments Incorporated Device power ground. 6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS above VVBUS_CONVEN. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power ground. REGN pin output is for power stage gate drive. SMBus clock input. Connect to clock line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to SMBus specifications. SMBus open-drain data I/O. Connect to data line from the host controller or smart battery. Connect a 10-kΩ pullup resistor according to SMBus specifications. Submit Documentation Feedback 5 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Pin Functions (continued) PIN NAME SRN NUMBER 19 I/O DESCRIPTION PWR Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with optional 0.1-μF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched. For reverse battery plug-in protection, 10-Ω series resistors are placed on SRP and SRN. SRP 20 PWR Charge current sense resistor positive input. Connect 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering. The leakage current on SRP and SRN are matched. For reverse battery plug-in protection, 10-Ω series resistors are placed on SRP and SRN. Connect SRP pin with optional 0.1-uF ceramic capacitor to GND for common-mode filtering. SW1 32 PWR Buck mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET. SW2 23 PWR Boost mode high side power MOSFET driver source. Connect to the source of the high side n-channel MOSFET. VBUS 1 PWR Charger input voltage. An input low pass filter of 1Ω and 0.47 µF (minimum) is recommended. VDDA 7 PWR Internal reference bias pin. Connect a 10-Ω resistor from REGN to VDDA and a 1-μF ceramic capacitor from VDDA to power ground. VSYS 22 PWR Charger system voltage sensing. The system voltage regulation limit is programmed in REG0x15() and REG0x3E(). Thermal pad – – 6 Submit Documentation Feedback Exposed pad beneath the IC. Analog ground and power ground star-connected near the IC's ground. Always solder thermal pad to the board, and have vias on the thermal pad plane connecting to power ground planes. It also serves as a thermal pad to dissipate the heat. Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX SRN, SRP, ACN, ACP, VBUS, VSYS, BATDRV –0.3 30 SW1, SW2 –2.0 30 BTST1, BTST2, HIDRV1, HIDRV2 –0.3 36 LODRV1, LODRV2 (2% duty cycle) –4.0 7 HIDRV1, HIDRV2 (2% duty cycle) –4.0 36 SW1, SW2 (2% duty cycle) –4.0 30 SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ, LODRV1, LODRV2, VDDA, COMP1, COMP2, CMPIN, CMPOUT, EN_OTG –0.3 7 PROCHOT –0.3 5.5 IADPT, IBAT, PSYS –0.3 3.6 BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2 –0.3 7 SRP-SRN, ACP-ACN –0.5 0.5 Junction temperature range, TJ –40 155 °C Storage temperature, Tstg –40 155 °C Voltage Differential voltage (1) (2) UNIT V V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT ACN, ACP, VBUS 0 24 SRN, SRP, VSYS, BATDRV 0 19.2 –2 24 BTST1, BTST2, HIDRV1, HIDRV2 0 30 SDA, SCL, REGN, CHRG_OK, CELL_BATPRESZ, ILIM_HIZ, LODRV1, LODRV2, VDDA, COMP1, COMP2, CMPIN, CMPOUT 0 6.5 PROCHOT 0 5.3 IADPT, IBAT, PSYS 0 3.3 BTST1-SW1, BTST2-SW2, HIDRV1-SW1, HIDRV2-SW2 0 6.5 –0.35 0.35 Junction temperature, TJ –40 125 °C Operating free-air temperature, TA –40 85 °C SW1, SW2 Voltage Differential voltage SRP-SRN, ACP-ACN Copyright © 2017, Texas Instruments Incorporated V V Submit Documentation Feedback 7 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 7.4 Thermal Information bq25700A THERMAL METRIC (1) RSN (WQFN) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 37.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 26.1 °C/W RθJB Junction-to-board thermal resistance 7.8 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 7.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.5 Electrical Characteristics over TJ = –40 to 125°C (unless otherwise noted) PARAMETER VINPUT_OP TEST CONDITIONS Input voltage operating range MIN TYP MAX UNIT 3.5 26 V 1.024 19.2 V REGULATION ACCURACY MAX SYSTEM VOLTAGE REGULATION VSYSMAX_RNG System voltage regulation, measured on VSYS REG0x15() = 0x41A0H (16.800 V) VSYSMAX_ACC System voltage regulation accuracy (charge disable) REG0x15() = 0x3130H (12.592 V) VSRN + 160 mV –2% V 2% VSRN + 160 mV –2% V 2% VSRN + 160 mV V REG0x15() = 0x20D0H (8.400 V) –3% REG0x15() = 0x1060H (4.192 V) –3% 3% 1.024 19.2 3% VSRN + 160 mV V MINIMUM SYSTEM VOLTAGE REGULATION VSYSMIN_RNG System voltage regulation, measured on VSYS REG0x3E() = 0x3000H VSYSMIN_REG_ACC Minimum system voltage regulation accuracy (charge enable, VBAT below REG0x3E() setting) REG0x3E() = 0x2400H REG0x3E() = 0x1800H REG0x3E() = 0x0E00H 12.288 –2% V V 2% 9.216 –2% V 2% 6.144 –3% V 3% 3.584 –3% V 4% CHARGE VOLTAGE REGULATION VBAT_RNG Battery voltage regulation 1.024 REG0x15() = 0x41A0H VBAT_REG_ACC Battery voltage regulation accuracy (charge enable) (0°C to 85°C) REG0x15() = 0x3130H REG0x15() = 0x20D0H REG0x15() = 0x1060H 8 Submit Documentation Feedback 19.2 16.8 –0.5% V 0.5% 12.592 –0.5% V 0.5% 8.4 –0.6% V 0.6% 4.192 –1.1% V V 1.2% Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 81.28 mV CHARGE CURRENT REGULATION IN FAST CHARGE VIREG_CHG_RNG Charge current regulation differential voltage range VIREG_CHG = VSRP – VSRN REG0x14() = 0x1000H ICHRG_REG_ACC Charge current regulation REG0x14() = 0x0800H accuracy 10-mΩ current sensing resistor, VBAT above REG0x14() = 0x0400H 0x3E() setting (0°C to 85°C) REG0x14() = 0x0200H 0 4096 –3% mA 2% 2048 –4% mA 3% 1024 –5% mA 6% 512 –12% mA 12% CHARGE CURRENT REGULATION IN LDO MODE ICLAMP Pre-charge current clamp CELL 2s-4s 384 mA CELL 1 s, VSRN < 3 V 384 mA CELL 1 s, 3 V < VSRN < VSYSMIN 2 REG0x14() = 0x0180H 384 2S-4S –15% 1S –25% REG0x14() = 0x0100H IPRECHRG_REG_ACC Pre-charge current regulation 2S-4S accuracy with 10-Ω SRP/SRN series resistor, VBAT below 1S REG0x3E() setting (0°C to REG0x14() = 0x00C0H 85°C) 2S-4S 1S ILEAK_SRP_SRN mA 15% 25% 256 –20% mA 20% –35% 35% 192 –25% mA 25% –50% REG0x14() = 0x0080H 2S-4S A 50% 128 mA –30% 30% –12 10 µA 0.5 64 mV REG0x3F() = 0x4FFFH 3820 4000 mA REG0x3F() = 0x3BFFH 2830 3000 mA REG0x3F() = 0x1DFFH 1350 1500 mA REG0x3F() = 0x09FFH 340 500 mA –16 10 µA 1 4 V SRP, SRN leakage current mismatch (0°C to 85°C) INPUT CURRENT REGULATION VIREG_DPM_RNG Input current regulation differential voltage range IDPM_REG_ACC Input current regulation accuracy (–40°C to 105°C) with 10-Ω ACP/ACN series resistor VIREG_DPM = VACP – VACN ILEAK_ACP_ACN ACP, ACN leakage current mismatch VIREG_DPM_RNG_ILIM Voltage Range for input current regulation IDPM_REG_ACC_ILIM VILIM_HIZ = 2.6 V Input Current Regulation Accuracy on ILIM_HIZ pin VILIM_HIZ = 2.2 V VILIM_HIZ = 1 V + 40 × IDPM × VILIM_HIZ = 1.6 V RAC, with 10-Ω ACP/ACN series resistor VILIM_HIZ = 1.2 V ILEAK_ILIM ILIM_HIZ pin leakage 3800 4000 4200 mA 2800 3000 3200 mA 1300 1500 1700 mA 300 500 700 mA –1 1 µA 3.2 19.52 V INPUT VOLTAGE REGULATION VIREG_DPM_RNG Input voltage regulation range Voltage on VBUS Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 9 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN REG0x3B()=0x3C80H TYP 18688 –2% VDPM_REG_ACC Input voltage regulation accuracy MAX REG0x3B()=0x1E00H mV 2% 10880 –2.5% REG0x3B()=0x0500H UNIT mV 2.5% 4480 mV –3% 5% 0 81.28 mV OTG CURRENT REGULATION VIOTG_REG_RNG Input current regulation differential voltage range IOTG_ACC Input current regulation accuracy with 50-mA LSB, with 10-Ω ACP/ACN series resistor VIREG_DPM = VACP – VACN REG0x3C() = 0x3C00H 2800 3000 3200 mA REG0x3C() = 0x1E00H 1300 1500 1700 mA REG0x3C() = 0x0A00H 300 500 700 mA 20.8 V OTG VOLTAGE REGULATION VIREG_DPM_RNG Input voltage regulation range Voltage on VBUS REG0x3D()=0x3CC0H VOTG_REG_ACC OTG voltage regulation accuracy REG0x3D()=0x1D80H REG0x3D()=0x0240H 4.48 20.032 –2% V 2% 12.032 –2% V 2% 5.056 –3% V 3% REFERENCE AND BUFFER REGN REGULATOR VREGN_REG REGN regulator voltage (0 mA–60 mA) VVBUS = 10 V 5.7 6 6.3 V VDROPOUT REGN voltage in drop out mode VVBUS = 5 V, ILOAD = 20 mA 3.8 4.3 4.6 V IREGN_LIM_Charging REGN current limit when converter is enabled VVBUS = 10 V, force VREGN = 4V 50 65 CREGN REGN output capacitor required for stability ILOAD = 100 µA to 50 mA 2.2 µF CVDDA REGN output capacitor required for stability ILOAD = 100 µA to 50 mA 1 µF mA QUIESCENT CURRENT IBAT_BATFET_ON IAC_SW_LIGHT_buck 10 System powered by battery. BATFET on. ISRN + ISRP + ISW2+ IBTST2 + ISW1 + IBTST1+ ACP + IACN + IVBUS + IVSYS Input current during PFM in buck mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST + ISW2 + IBTST2 Submit Documentation Feedback VBAT = 18 V, REG0x12[15] = 1, in low power mode 22 45 µA VBAT = 18 V, REG0x12[15] = 0, REG0x30[14:13] = 01, REGN off 105 175 µA VBAT=18 V, REG0x12[15] = 0, REG0x30[14:13] = 10, REGN off 60 90 µA VBAT = 18 V, REG0x12[15] = 0, REG0x30[12] = 0, REGN on, EN_PSYS 860 1150 VBAT = 18 V, REG0x12[15] = 0, REG0x30[12] = 1, REGN on 960 VIN = 20 V, VBAT = 12.6 V, 3 s, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.2 µA 1250 mA Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IAC_SW_LIGHT_boost Input current during PFM in boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST2 + ISW2 + IBTST2 VIN = 5 V, VBAT = 8.4 V, 2 s, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.7 mA IAC_SW_LIGHT_buckboost Input current during PFM in buck boost mode, no load, IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST1 + ISW2 + IBTST2 VIN = 12 V, VBAT = 12 V, REG0x12[10] = 0; MOSFET Qg = 4 nC 2.4 mA VBAT = 8.4 V, VBUS = 5 V, 800-kHz switching frequency, MOSFET Qg = 4 nC 3 VBAT = 8.4 V, VBUS = 12 V, 800-kHz switching frequency, MOSFET Qg = 4 nC 4.2 VBAT = 8.4 V, VBUS = 20 V, 800-kHz switching frequency, MOSFET Qg = 4 nC 6.2 IOTG_STANDBY Quiescent current during PFM in OTG mode IVBUS + IACP + IACN + IVSYS + ISRP + ISRN + ISW1 + IBTST2 + ISW2 + IBTST2 VACP/N_OP Input common mode range VIADPT_CLAMP IADPT output clamp voltage IIADPT IADPT output current AIADPT VIADPT_ACC Input current sensing gain Input current monitor accuracy Voltage on ACP/ACN 3.1 3.2 3.3 V V mA V(IADPT) / V(ACP-ACN), REG0x12[4] = 0 20 V/V V(IADPT) / V(ACP-ACN), REG0x12[4] = 1 40 V/V V(ACP-ACN) = 40.96 mV –2% 2% V(ACP-ACN) = 20.48 mV –3% 3% V(ACP-ACN) =10.24 mV –6% 6% V(ACP-ACN) = 5.12 mV –10% 10% Maximum output load capacitance VSRP/N_OP Battery common mode range VIBAT_CLAMP IBAT output clamp voltage IIBAT IBAT output current AIBAT V(IBAT) / V(SRN-SRP), Charge and discharge current REG0x12[3] = 0, sensing gain on IBAT pin V(IBAT) / V(SRN-SRP), REG0x12[3] = 1, Voltage on SRP/SRN 2.5 3.05 3.2 100 pF 18 V 3.3 V 1 mA 8 V/V 16 V/V V(SRN-SRP) = 40.96 mV –2% 2% Charge and discharge current V(SRN-SRP) = 20.48 mV monitor accuracy on IBAT pin V(SRN-SRP) =10.24 mV –3% 4% V(SRN-SRP) = 5.12 mV CIBAT_MAX 26 1 CIADPT_MAX IIBAT_CHG_ACC 3.8 mA –6% 6% –12% 12% Maximum output load capacitance 100 pF SYSTEM POWER SENSE AMPLIFIER VPSYS PSYS output voltage range 0 3.3 V IPSYS PSYS output current 0 160 µA APSYS PSYS system gain Copyright © 2017, Texas Instruments Incorporated V(PSYS) / (P(IN)+ P(BAT)), REG0x30[9] = 1 1 Submit Documentation Feedback µA/W 11 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER VPSYS_ACC VPSYS_CLAMP PSYS gain accuracy (REG0x30[9] = 1) TEST CONDITIONS MIN Adapter only with system power = 19.5 V / 45 W, TA = 0 to 85°C –5% 5% Adapter only with system power = 19.5 V / 45 W, TA = –40 to 125°C –7% 6% Battery only with system power = 11 V / 44 W, TA = 0 to 85°C –5% 5% Battery only with system power = 11 V / 44 W, TA = –40 to 125°C –6% 6% 3 3.3 V PSYS clamp voltage TYP MAX UNIT COMPARATOR VBUS UNDER VOLTAGE LOCKOUT COMPARATOR VVBUS_UVLOZ VBUS undervoltage rising threshold VBUS rising 2.34 2.55 2.77 V VVBUS_UVLO VBUS undervoltage falling threshold VBUS falling 2.2 2.4 2.6 V VVBUS_UVLO_HYST VBUS undervoltage hysteresis VVBUS_CONVEN VBUS converter enable rising threshold VBUS rising 3.2 3.5 3.9 V VVBUS_CONVENZ VBUS converter enable falling VBUS falling threshold 2.9 3.2 3.5 V VVBUS_CONVEN_HYST VBUS converter enable hysteresis 150 mV 400 mV BATTERY UNDER VOLTAGE LOCKOUT COMPARATOR VVBAT_UVLOZ VBAT undervoltage rising threshold VSRN rising 2.35 2.55 2.75 V VVBAT_UVLO VBAT undervoltage falling threshold VSRN falling 2.2 2.4 2.6 V VVBAT_UVLO_HYST VBAT undervoltage hysteresis VVBAT_OTGEN VBAT OTG enable rising threshold VSRN rising 3.3 3.55 3.75 V VVBAT_OTGENZ VBAT OTG enable falling threshold VSRN falling 3 3.2 3.4 V VVBAT_OTGEN_HYST VBAT OTG enable hysteresis 150 mV 350 mV VBUS UNDER VOLTAGE COMPARATOR (OTG MODE) VVBUS_OTG_UV VBUS undervoltage falling threshold tVBUS_OTG_UV VBUS undervoltage deglitch time As percentage of REG0x3B() 85.0% 7 ms VBUS OVER VOLTAGE COMPARATOR (OTG MODE) VVBUS_OTG_OV VBUS overvoltage rising threshold tVBUS_OTG_OV VBUS Over-Voltage Deglitch Time VBAT_SYSMIN_RISE LDO mode to fast charge mode threshold, VSRN rising as percentage of 0x3E() VBAT_SYSMIN_FALL LDO mode to fast charge mode threshold, VSRN falling as percentage of 0x3E() 12 Submit Documentation Feedback As percentage of REG0x3B() 105% 10 98% 100% ms 102% 97.5% Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER VBAT_SYSMIN_HYST Fast charge mode to LDO mode threshold hysteresis TEST CONDITIONS MIN as percentage of 0x3E() TYP MAX UNIT 2.5% BATTERY LOWV COMPARATOR (Pre-charge to Fast Charge Thresold for 1S) VBATLV_FALL BATLOWV falling threshold 1s 2.80 V VBATLV_RISE BATLOWV rising threshold 3.00 V VBATLV_RHYST BATLOWV hysteresis 200 mV INPUT OVER-VOLTAGE COMPARATOR (ACOVP) VACOV_RISE VBUS overvoltage rising threshold VBUS rising 25 26 27 V VACOV_FALL VBUS overvoltage falling threshold VBUS falling 24 24.5 25 V VACOV_HYST VBUS overvoltage hysteresis 1.5 V tACOV_RISE_DEG VBUS overvoltage rising deglitch VBUS rising to stop converter 100 µs tACOV_FALL_DEG VBUS overvoltage falling deglitch VBUS falling to start converter 1 ms INPUT OVER CURRENT COMPARATOR (ACOC) VACOC ACP to ACN rising threshold, w.r.t. ILIM2 in REG0x33[15:11] Voltage across input sense resistor rising, Reg0x31[2] = 1 VACOC_FLOOR Measure between ACP and ACN VACOC_CEILING 195% 210% 225% Set IDPM to minimum 44 50 56 mV Measure between ACP and ACN Set IDPM to maximum 172 180 188 mV tACOC_DEG_RISE Rising deglitch time Deglitch time to trigger ACOC 250 µs tACOC_RELAX Relax time Relax time before converter starts again 250 ms SYSTEM OVER-VOLTAGE COMPARATOR (SYSOVP) VSYSOVP_RISE System overvoltage rising threshold to turn off converter VSYSOVP_FALL System overvoltage falling threshold ISYSOVP Discharge current when SYSOVP stop switching was triggered 1s 4.85 5 5.1 2s 11.7 12 12.2 3s 19 19.5 20 4s 19 19.5 20 1s 4.8 2s 11.5 3s 19 4s 19 on SYS 20 V V mA BAT OVER-VOLTAGE COMPARATOR (BATOVP) Overvoltage rising threshold as percentage of VBAT_REG in REG0x15() 1 s, 4.2 V 102.5% 104% 106% VBATOVP_RISE 2s-4s 102.5% 104% 105% Overvoltage falling threshold as percentage of VBAT_REG in REG0x15() 1s 100% 102% 104% VBATOVP_FALL 2s-4s 100% 102% 103% Overvoltage hysteresis as percentage of VBAT_REG in REG0x15() 1s 2% VBATOVP_HYST 2s-4s 2% IBATOVP Discharge current during BATOVP Copyright © 2017, Texas Instruments Incorporated on SRP and SRN 20 Submit Documentation Feedback mA 13 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER tBATOVP_RISE TEST CONDITIONS MIN Overvoltage rising deglitch to turn off BATDRV to disable charge TYP MAX 20 UNIT ms CONVERTER OVER-CURRENT COMPARATOR (Q2) VOCP_limit_Q2 Converter Over-Current Limit VOCP_limit_SYSSH ORT_Q2 System Short or SRN<2.5 V Reg0x31[5]=1 150 Reg0x31[5]=0 210 Reg0x31[5]=1 45 Reg0x31[5]=0 60 mV mV CONVERTER OVER-CURRENT COMPARATOR (ACX) VOCP_limit_Q3 Converter Over-Current Limit VOCP_limit_SYSSH ORT_Q3 System Short or SRN<2.5 V Reg0x31[4]=1 150 Reg0x31[4]=0 280 Reg0x31[4]=1 90 Reg0x31[4]=0 150 mV mV THERMAL SHUTDOWN COMPARATOR TSHUT_RISE Thermal shutdown rising temperature Temperature increasing 155 °C TSHUTF_FALL Thermal shutdown falling temperature Temperature reducing 135 °C TSHUT_HYS Thermal shutdown hysteresis 20 °C tSHUT_RDEG Thermal shutdown rising deglitch 100 µs tSHUT_FHYS Thermal shutdown falling deglitch 12 ms VSYS PROCHOT COMPARATOR Reg0x33[7:6] = 00, 1 s 2.85 Reg0x33[7:6] = 00, 2–4 s 5.75 Reg0x33[7:6] = 01, 1 s VSYS_PROCHOT VSYS threshold falling threshold Reg0x33[7:6] = 01, 2–4 s V 2.95 3.1 3.25 V 5.8 5.95 6.1 V Reg0x33[7:6] = 10, 1 s 3.3 V 6.25 V Reg0x33[7:6] = 11, 1 s 3.5 V Reg0x33[7:6] = 11, 2–4 s 6.5 V 8 µs Reg0x33[7:6] = 10, 2–4 s tSYS_PRO_RISE_DEG V VSYS rising deglitch for throttling ICRIT PROCHOT COMPARATOR VICRIT_PRO Input current rising threshold for throttling as 10% above ILIM2 (REG0x33[15:11]) Reg0x33[15:11] = 00000 105% 110% 116% Reg0x33[15:11] = 01001 142% 150% 156% 105% 110% 116% INOM PROCHOT COMPARATOR VINOM_PRO INOM rising threshold as 10% above IIN (REG0x3F()) IDCHG PROCHOT COMPARATOR VIDCHG_PRO IDCHG threshold for throttling Reg0x34[15:10] =001100 for IDSCHG of 6 A 6272 95% mA 102% INDEPENDENT COMPARATOR VINDEP_CMP 14 Independent comparator threshold Submit Documentation Feedback Reg0x30[7] = 1, CMPIN falling 1.17 1.2 1.23 V Reg0x30[7] = 0, CMPIN falling 2.27 2.3 2.33 V Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER VINDEP_CMP_HYS Independent comparator hysteresis TEST CONDITIONS MIN Reg0x3B[6] = 0, CMPIN falling TYP MAX 100 UNIT mV POWER MOSFET DRIVER PWM OSCILLATOR AND RAMP FSW PWM switching frequency Reg0x12[9] = 0 1020 1200 1380 kHz Reg0x12[9] = 1 680 800 920 kHz 8.5 10 11.5 V BATFET GATE DRIVER (BATDRV) VBATDRV_ON Gate drive voltage on BATFET VBATDRV_DIODE Drain-source voltage on BATFET during ideal diode operation RBATDRV_ON Measured by sourcing 10-µA current to BATDRV RBATDRV_OFF Measured by sinking 10-µA current from BATDRV 30 3 mV 4 6 kΏ 1.2 2.1 kΏ PWM HIGH SIDE DRIVER (HIDRV Q1) RDS_HI_ON_Q1 High side driver (HSD) turnon VBTST1 – VSW1 = 5 V resistance RDS_HI_OFF_Q1 High side driver turnoff resistance VBTST1 – VSW1 = 5 V VBTST1_REFRESH Bootstrap refresh comparator falling threshold voltage VBTST1 – VSW1 when low side refresh pulse is requested 6 3.2 Ω 1.3 2.2 Ω 3.7 4.6 V PWM HIGH SIDE DRIVER (HIDRV Q4) RDS_HI_ON_Q4 High side driver (HSD) turnon VBTST2 – VSW2 = 5 V resistance RDS_HI_OFF_Q4 High side driver turnoff resistance VBTST2 – VSW2 = 5 V VBTST2_REFRESH Bootstrap refresh comparator falling threshold voltage VBTST2 – VSW2 when low side refresh pulse is requested 6 3.3 Ω 1.5 2.4 Ω 3.7 4.6 V PWM LOW SIDE DRIVER (LODRV Q2) RDS_LO_ON_Q2 Low side driver (LSD) turnon resistance VBTST1 – VSW1 = 5.5 V 6 RDS_LO_OFF_Q2 Low side driver turnoff resistance VBTST1 – VSW1 = 5.5 V 1.7 Ω 2.6 Ω PWM LOW SIDE DRIVER (LODRV Q3) RDS_LO_ON_Q3 Low side driver (LSD) turnon resistance VBTST2 – VSW2 = 5.5 V 7.6 RDS_LO_OFF_Q3 Low side driver turnoff resistance VBTST2 – VSW2 = 5.5 V 2.9 Ω 4.6 Ω INTERNAL SOFT START During Charge Enable SSSTEP_DAC Soft Start Step Size 64 mA SSSTEP_DAC Soft Start Step Time 8 µs INTEGRATED BTST DIODE (D1) VF_D1 Forward bias voltage IF = 20 mA at 25°C VR_D1 Reverse breakdown voltage IR = 2 µA at 25°C 0.8 V 20 V INTEGRATED BTST DIODE (D2) VF_D2 Forward bias voltage IF = 20 mA at 25°C VR_D2 Reverse breakdown voltage IR = 2 µA at 25°C 0.8 V 20 V PWM DRIVERS TIMING Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 15 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Electrical Characteristics (continued) over TJ = –40 to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERFACE LOGIC INPUT (SDA, SCL, EN_OTG) VIN_ LO Input low threshold SMBus VIN_ HI Input high threshold SMBus (bq25700A) 0.8 2.1 V V LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT) VOUT_ VOUT_ LO Output saturation voltage 5-mA drain current LEAK Leakage current V=7V 0.4 –1 1 V mA LOGIC OUTPUT OPEN DRAIN SDA VOUT_ VOUT_ LO_SDA Output Saturation Voltage 5 mA drain current LEAK_SDA Leakage Current V = 7V 0.4 –1 1 V mA LOGIC OUTPUT OPEN DRAIN CHRG_OK VOUT_ LO_CHRG_OK VOUT_ LEAK _CHRG_OK Output Saturation Voltage 5 mA drain current Leakage Current V = 7V 0.4 –1 1 V mA LOGIC OUTPUT OPEN DRAIN CMPOUT VOUT_ LO_CMPOUT VOUT_ LEAK _CMPOUT Output Saturation Voltage 5 mA drain current Leakage Current V = 7V 0.4 –1 V 1 mA 300 mV 1 mA LOGIC OUTPUT OPEN DRAIN (PROCHOT) VOUT_ LO_PROCHOT Output saturation voltage 50-Ω pullup to 1.05 V / 5-mA load VOUT_ LEAK_PROCHOT Leakage current V = 5.5 V –1 0.8 ANALOG INPUT (ILIM_HIZ) VHIZ_ LO Voltage to get out of HIZ mode ILIM_HIZ pin rising VHIZ_ HIGH Voltage to enable HIZ mode ILIM_HIZ pin falling V 0.4 V ANALOG INPUT (CELL_BATPRESZ) VCELL_4S 4S REGN = 6 V, as percentage of REGN 68.4% 75% VCELL_3S 3S REGN = 6 V, as percentage of REGN 51.7% 55% 65% VCELL_2S 2S REGN = 6 V, as percentage of REGN 35% 40% 49.1% VCELL_1S 1S REGN = 6 V, as percentage of REGN 18.4% 25% 31.6% VCELL_BATPRESZ_RISE Battery is present VCELL_BATPRESZ_FALL Battery is removed 18% CELL_BATPRESZ falling 15% ANALOG INPUT (COMP1, COMP2) ILEAK_COMP1 COMP1 Leakage –120 120 nA ILEAK_COMP2 COMP2 Leakage –120 120 nA 7.6 Timing Requirements MIN TYP MAX UNIT SMBus TIMING CHARACTERISTICS tr SCLK/SDATA rise time tf SCLK/SDATA fall time tW(H) SCLK pulse width high 4 tW(L) SCLK Pulse Width Low 4.7 µs tSU(STA) Setup time for START condition 4.7 µs tH(STA) START condition hold time after which first clock pulse is generated 4 µs 16 Submit Documentation Feedback 1 µs 300 ns 50 µs Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Timing Requirements (continued) MIN TYP MAX UNIT tSU(DAT) Data setup time 250 ns tH(DTA) Data hold time 300 ns tSU(STOP) Setup time for STOP condition 4 µs t(BUF) Bus free time between START and STOP condition 4.7 FS(CL) Clock Frequency 10 100 KHz 35 ms µs HOST COMMUNICATION FAILURE ttimeout SMBus bus release timeout (1) 25 tBOOT Deglitch for watchdog reset signal 10 Watchdog timeout period, ChargeOption() bit [14:13] = 01 (2) 35 tWDI Watchdog timeout period, ChargeOption() bit bit [14:13] = 10 (2) Watchdog timeout period, ChargeOption() bit bit [14:13] = 11 (2) (default) (1) (2) ms 44 53 s 70 88 105 s 140 175 210 s Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35 ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms). User can adjust threshold via SMBus ChargeOption() REG0x12. 90 90 85 85 80 80 Efficiency (%) Efficiency (%) 7.7 Typical Characteristics 75 70 VOUT = 6.1 V VOUT = 8.4 V VOUT = 9.2 V VOUT = 12.5 V 65 75 70 VOUT = 6.1 V VOUT = 8.4 V VOUT = 9.2 V VOUT = 12.5 V 65 60 60 0 0.01 0.02 0.03 Output Current (A) 0.04 0.05 0 0.01 0.02 0.03 Output Current (A) D001 VIN = 5 V 0.04 0.05 D001 VIN = 12 V Figure 1. Light Load Efficiency Figure 2. Light Load Efficiency 90 96 94 85 Efficiency (%) Efficiency (%) 92 80 75 70 88 86 84 VOUT = 6.1 V VOUT = 8.4 V VOUT = 9.2 V VOUT = 12.5 V 65 90 VOUT = 3.7 V VOUT = 7.4 V VOUT = 11.1 V VOUT = 14.8 V 82 60 80 0 0.01 0.02 0.03 Output Current (A) 0.04 VIN = 20 V Figure 3. Light Load Efficiency Copyright © 2017, Texas Instruments Incorporated 0.05 0 1 D001 2 3 4 Output Current (A) 5 6 D001 VIN = 5 V Figure 4. System Efficiency Submit Documentation Feedback 17 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 98 98 96 96 94 94 92 92 Efficiency (%) Efficiency (%) Typical Characteristics (continued) 90 88 86 VOUT = 3.7 V VOUT = 7.4 V VOUT = 11.1 V VOUT = 14.8 V 84 82 90 88 86 VOUT = 3.7 V VOUT = 7.4 V VOUT = 11.1 V VOUT = 14.8 V 84 82 80 80 0 1 2 3 4 Output Current (A) 5 6 0 1 2 D001 VIN = 9 V 5 6 D001 VIN = 12 V Figure 5. System Efficiency Figure 6. System Efficiency 98 96 96 94 94 VOTG = 5 V VOTG = 12 V VOTG = 20 V 92 92 Efficiency (%) Efficiency (%) 3 4 Output Current (A) 90 88 86 82 88 86 84 VOUT = 3.7 V VOUT = 7.4 V VOUT = 11.1 V VOUT = 14.8 V 84 90 82 80 80 0 1 2 3 4 Output Current (A) 5 6 0 1 2 3 Output Current (A) D001 4 5 D001 VIN = 20 V Figure 7. System Efficiency Figure 8. OTG Efficiency with 1S Battery 96 98 94 96 94 Efficiency (%) Efficiency (%) 92 90 88 86 84 88 86 VOTG = 5 V VOTG = 12 V VOTG = 20 V 82 80 80 0 1 2 3 4 Output Current (A) 5 Figure 9. OTG Efficiency with 2S Battery 18 90 84 VOTG = 5 V VOTG = 12 V VOTG = 20 V 82 92 Submit Documentation Feedback 6 D001 0 1 2 3 4 Output Current (A) 5 6 D001 Figure 10. OTG Efficiency with 3S Battery Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Typical Characteristics (continued) 98 96 Efficiency (%) 94 92 90 88 86 84 VOTG = 5 V VOTG = 12 V VOTG = 20 V 82 80 0 1 2 3 4 Output Current (A) 5 6 D001 Figure 11. OTG Efficiency with 4S Battery Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 19 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8 Detailed Description 8.1 Overview The bq25700A is a buck boost NVDC (narrow voltage DC) charge controller for multi-chemistry portable applications such as notebook, detachable, ultrabook, tablet and other mobile devices with rechargeable batteries. It provides seamless transition between converter operation modes (buck, boost, or buck boost), fast transient response, and high light load efficiency. The bq25700A supports wide range of power sources, including USB PD ports, legacy USB ports, traditional ACDC adapters, etc. It takes input voltage from 3.5 V to 24 V, and charges battery of 1-4 series. It also supports USB On-The-Go (OTG) to provide 4.48V to 20.8V output at USB port. The bq25700A features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter overloading. During battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. If system power demand temporarily exceeds adapter rating, the bq25700A supports NVDC architecture to allow battery discharge energy to supplement system power. For details, refer to System Voltage Regulation section. In order to be compliant with Intel IMVP8 compliant system, the bq25700A includes PSYS function to monitor the total platform power from adapter and battery. Besides PSYS, it provides both an independent input current buffer (IADPT) and a battery current buffer (IBAT) with highly accurate current sense amplifiers. If the platform power exceeds the available power from adapter and battery, a PROCHOT signal is asserted to CPU so that the CPU optimizes its performance to the power available to the system. The SMBus controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements. 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.2 Functional Block Diagram CHRG_OK 4 CHRG_OK_DRV ** programmable in register EN_REGN 50ms Rising Deglitch 3.9V VBUS bq25700A Block Diagram 50ms Rising Deglitch 1 VREF_CMP** CMP_DEG** ACOVP 26V 14 CMPIN 15 CMPOUT VREF_VDPM or VREF_VOTG 16 VSNS_VDPM or VSYS_VOTG EN_HIZ ILIM_HIZ 6 ACP 2 ACN 3 IADPT 8 IBAT 9 Decoder 17 VREF_ILIM COMP1 COMP2 VSYS VREF_IDPM, or VREF_IOTG 20X** LDO Mode Gate Control VSNS_IDPM, or VSNS_IOTG VSNS_ICHG Loop Selector and Error Amplifier PWM VREF_ICHG 20 SRN 19 BATDRV 30 BTST1 31 HIDRV1 32 SW1 VSNS_IDCHG 16X SRP 21 VSYS-10V 20X** 7 EN_REGN VSNS_ICHG REGN LDO 28 VDDA REGN EN_HIZ VREF_VBAT EN_LEARN VSNS_VBAT EN_CHRG EN_LDO EN_OTG VSYS 22 PWM Driver Logic 29 LODRV1 27 PGND 25 BTST2 24 HIDRV2 23 SW2 26 LODRV2 Decoder 18 CELL_BATPRESZ Processor Hot 11 PROCHOT VREF_VSYS VSNS_VSYS VSNS_VSYS ACN PSYS 10 VSNS_VBAT VSNS_ICHG (ACP-ACN) SRN VSNS_IDCHG VSNS_IDPM (SRN-SRP) VSNS_VDPM SDA SCL EN_OTG 12 13 5 SMBUS Interface ChargeOption0() ChargeOption1() ChargeOption2() ChargeCurrent() ChargeVoltage() InputCurrent() InputVoltage() MinSysVoltage() OTGVoltage() OTGCurrent() Over Current Over Voltage Detect EN_HIZ EN_LEARN BATPRESZ EN_LDO EN_CHRG CELL_CONFIG EN_OTG VREF_VSYS Loop Regulation Reference VREF_VBAT VREF_ICHG VREF_IDPM VREF_VDPM VREF_IOTG VREF_VOTG IADPT IBAT VSYS CHRG_OK Copyright © 2017, Texas Instruments Incorporated Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 21 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.3 Feature Description 8.3.1 Power-Up from Battery Without DC Source If only battery is present and the voltage is above VVBAT_UVLOZ, the BATFET turns on and connects battery to system. By default, the charger is in low power mode (REG0x12[15] = 1) with lowest quiescent current. The LDO stays off. When device moves to performance mode (REG0x12[15] = 0), The host enables IBAT buffer through SMBus to monitor discharge current. For PSYS, PROCHOT or independent comparator, REGN LDO is enabled for an accurate reference. 8.3.2 Power-Up From DC Source When an input source plugs in, the charger checks the input source voltage to turn on LDO and all the bias circuits. It sets the input current limit before the converter starts. The power-up sequence from DC source is as follows: 1. 50 ms after VBUS above VVBUS_CONVEN, enable 6 V LDO and CHRG_OK goes HIGH 2. Input voltage and current limit setup 3. Battery CELL configuration 4. 150 ms after VBUS above VVBUS_CONVEN, converter powers up. 8.3.2.1 CHRG_OK Indicator CHRG_OK is an active HIGH open drain indicator. It indicates the charger is in normal operation when the following conditions are valid: • VBUS is above VVBUS_CONVEN • VBUS is below VACOV • No MOSFET/inductor fault 8.3.2.2 Input Voltage and Current Limit Setup After CHRG_OK goes HIGH, the charger sets default input current limit in REG0x3F() to 3.30 A. The actual input current limit is the lower setting of REG0x3F() and ILIM_HIZ pin. Charger initiates a VBUS voltage measurement without load (VBUS at noLoad). The default VINDPM threshold is VBUS at noLoad – 1.28 V. After input current and voltage limits are set, the charger device is ready to power up. The host can always update input current and voltage limit based on input source type. 8.3.2.3 Battery Cell Configuration CELL_BATPRESZ pin is biased with resistors from REGN to CELL_BATPRESZ to GND. After VDDA LDO is activated, the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. Refer to Electrical Characteristics for CELL setting thresholds. Table 1. Battery Cell Configuration CELL COUNT PIN VOLTAGE w.r.t. VDDA BATTERY VOLTAGE (REG0x15) SYSOVP 4S 75% 16.800V 19.5V 3S 55% 12.592V 18.5V 2S 40% 8.400V 12V 1S 25% 4.192V 5V 8.3.2.4 Device Hi-Z State The charger enters Hi-Z mode when ILIM_HIZ pin voltage is below 0.4 V or REG0x32[15] is set to 1. During Hi-Z mode, the input source is present, and the charger is in the low quiescent current mode with REGN LDO enabled. 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.3.3 USB On-The-Go (OTG) The device supports USB OTG operation to deliver power from the battery to other portable devices through USB port. The OTG mode output voltage is set in REG0x3B(). The OTG mode output current is set in REG0x3C(). The OTG operation can be enabled if the conditions are valid: • Valid battery voltage is set REG0x15() • OTG output voltage is set in REG0x3B() and output current is set in REG0x3C() • EN_OTG pin is HIGH and REG0x32[12] = 1 • VBUS is below VVBUS_UVLO • 10 ms after the above conditions are valid, converter starts and VBUS ramps up to target voltage. CHRG_OK pin goes HIGH if REG0x12[11] = 1. 8.3.4 Converter Operation The charger employs a synchronous buck-boost converter that allows charging from a standard 5-V or a highvoltage power source. The charger operates in buck, buck-boost and boost mode. The buck-boost can operate uninterruptedly and continuously across the three operation modes. Table 2. MOSFET Operation 8.3.4.1 MODE BUCK BUCK-BOOST Q1 Switching Switching BOOST ON Q2 Switching Switching OFF Q3 OFF Switching Switching Q4 ON Switching Switching Inductor Setting through IADPT Pin The charger reads the inductor value through the IADPT pin. Table 3. Inductor Setting on IADPT Pin INDUCTOR IN USE RESISTOR ON IADPT PIN 1 µH 93 kΩ 2.2 µH 137 kΩ 3.3 µH 169 kΩ 8.3.4.2 Continuous Conduction Mode (CCM) With sufficient charge current, the inductor current does not cross 0, which is defined as CCM. The controller starts a new cycle with ramp coming up from 200 mV. As long as error amplifier output voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds error amplifier output voltage, HSFET turns off and lowside MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on keeps the power dissipation low and allows safe charging at high currents. 8.3.4.3 Pulse Frequency Modulation (PFM) In order to improve converter light-load efficiency, the bq25700A switches to PFM control at light load when inductor current is less than 500 mA. The effective switching frequency will decrease accordingly when system load decreases. The minimum frequency can be limit to 25 kHz (ChargeOption0() bit[10]=1). To have higher light load efficiency, set EN_OOA bit low (Chargeoption0() bit[10] = 0). Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 23 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.3.5 Current and Power Monitor 8.3.5.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT) As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current during forward charging, or output current during OTG (IADPT) and the charge/discharge current (IBAT). IADPT voltage is 20× or 40× the differential voltage across ACP and ACN. IBAT voltage is 8x/16× (during charging), or 8×/16× (during discharging) of the differential across SRP and SRN. After input voltage or battery voltage is above UVLO, IADPT output becomes valid. To lower the voltage on current monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be achieved. • V(IADPT) = 20 or 40 × (V(ACP) – V(ACN)) during forward mode, or 20 or 40 × (V(ACN) – V(ACP)) during reverse OTG mode. • V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) during forward mode. • V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) during forward mode, or reverse OTG mode. A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The CSA output voltage is clamped at 3.3 V. 8.3.5.2 High-Accuracy Power Sense Amplifier (PSYS) The charger monitors total system power. During forward mode, the input adapter powers system. During reverse OTG mode, the battery powers the system and VBUS output. The ratio of PSYS current and total power KPSYS can be programmed in REG0x30[9] with default 1 μA/W. The input and charge sense resistors (RAC and RSR) are programmed in REG0x30[11:10]. PSYS voltage can be calculated with Equation 1 where IIN>0 when adapter is in forward charging, and IBAT>0 when the battery is in discharge when the battery is in discharge. VPSYS RPSYS u KPSYS (VACP u IIN VBAT u IBAT ) (1) For proper PSYS functionality, RAC and RSR values are limited to 10 mΩ and 20 mΩ. 8.3.6 Input Source Dynamic Power Manage Refer to Input Current and Input Voltage Registers for Dynamic Power Management. 8.3.7 Two-Level Adapter Current Limit (Peak Power Mode) Usually adapter can supply current higher than DC rating for a few milliseconds to tens of milliseconds. The charger employs two-level input current limit, or peak power mode, to fully utilize the overloading capability and minimize battery discharge during CPU turbo mode. Peak power mode is enabled in REG0x31[13]. The DC current limit, or ILIM1, is the same as adapter DC current, set in REG0x3F(). The overloading current, or ILIM2, is set in REG0x33[15:11], as in percentage of ILIM1. When the charger detects input current surge and battery discharge due to load transient, it applies ILIM2 for TOVLD in REG0x31[15:14], first, and then ILIM1 for up to TMAX – TOVLD time. TMAX is programmed in REG0x31[9:8]. After TMAX, if the load is still high, another peak power cycle starts. Charging is disabled during TMAX,; once TMAX, expires, charging continues. 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 ICRIT ILIM2 ILIM1 TOVLD TOVLD TMAX IVBUS ISYS IBAT Battery Discharge PROCHOT Figure 12. Two-Level Adapter Current Limit Timing Diagram 8.3.8 Processor Hot Indication When CPU is running turbo mode, the system peak power may exceed available power from adapter and battery together. The adapter current and battery discharge peak current, or system voltage drop is indications that system power are too high. The charger processor hot function monitors these events, and PROCHOT pulse is asserted. Once CPU receives PROCHOT pulse from charger, it slows down to reduce system power. The processor hot function monitors these events, and PROCHOT pulse is asserted. The PROCHOT triggering events include: • ICRIT: adapter peak current, as 110% of ILIM2 • INOM: adapter average current (110% of input current limit) • IDCHG: battery discharge current • VSYS: system voltage on VSYS • Adapter Removal: upon adapter removal (CHRG_OK pin HIGH to LOW) • Battery Removal: upon battery removal (CELL_BATPRESZ pin goes LOW) • CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW) The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are programmable through SMBus. Each triggering event can be individually enabled in REG0x34[6:0]. When any event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms programmable in 0x33[4:3]. At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 25 bq25700A SLUSCQ8 – MAY 2017 www.ti.com ICRIT IADP Adjustable Deglitch 1.05V INOM IDCHG 50 Ω PROCHOT Ref_DCHG 10 ms Debounce Ref 10 ms VSRP <0.3V 20 µs Deglitch CELL_BATPRESZ (one shot on pin falling edge) CMPOUT CHRG_OK (one shot on pin falling edge) Copyright © 2017, Texas Instruments Incorporated Figure 13. PROCHOT Profile 8.3.8.1 PROCHOT During Low Power Mode During low power mode (REG0x12[15] = 1), the charger offers a low quiescent current (~150 µA) Low power PROCHOT function uses the independent comparator to monitor battery discharge current and system voltage, and assert PROCHOT to CPU. Below lists the register setting to enable PROCHOT during low power mode. • REG0x12[15] = 1 • REG0x34[5:0] = 000000 • REG0x30[6:4] = 100 • Independent comparator threshold is always 1.2 V • When REG0x30[14] = 1, charger monitors discharge current. Connect CMPIN to voltage proportional to IBAT pin. PROCHOT triggers from HIGH to LOW when CMPIN voltage falls below 1.2 V. • When REG0x30[13] = 1, charger monitors system voltage. Connect CMPIN to voltage proportional to system. PROCHOT triggers from HIGH to LOW when CMPIN voltage rises above 1.2 V. 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 PROCHOT 1.2 V Voltage v VSYS Independent Comparator CMPIN Voltage v (VSRN ± VSRP) bq2570x Copyright © 2017, Texas Instruments Incorporated Figure 14. PROCHOT Low Power Mode Implementation 8.3.8.2 PROCHOT Status REG0x21[6:0] reports which event in the profile triggers PROCHOT by setting the corresponding bit to 1. The status bit can be reset back to 0 after it is read by host, and current PROCHOT event is no longer active. Assume there are two PROCHOT events, event A and event B. Event A triggers PROCHOT first, but event B is also active. Both status bits will be HIGH. At the end of the 10 ms PROCHOT pulse, if PROCHOT is still active (either by A or B), the PROCHOT pulse is extended. 8.3.9 Device Protection 8.3.9.1 Watchdog Timer The charger includes watchdog timer to terminate charging if the charger does not receive a write MaxChargeVoltage() or write ChargeCurrent() command within 175 s (adjustable via REG0x12[14:13]). When watchdog timeout occurs, all register values are kept unchanged except ChargeCurrent() resets to zero. Battery charging is suspended. Write MaxChargeVoltage() or write ChargeCurrent() commands must be re-sent to reset watchdog timer and resume charging. Writing REG0x12[14:13] = 00 to disable watchdog timer also resumes charging. 8.3.9.2 Input Overvoltage Protection (ACOV) The charger has fixed ACOV voltage. When VBUS pin voltage is higher than ACOV, it is considered as adapter over voltage. CHRG_OK will be pulled low, and converter will be disabled. As system falls below battery voltage, BATFET will be turned on. When VBUS pin voltage falls below ACOV, it is considered as adapter voltage returns back to normal voltage. CHRG_OK is pulled high by external pull up resistor. The converter resumes if enable conditions are valid. 8.3.9.3 Input Overcurrent Protection (ACOC) If the input current exceeds the 1.25× or 2× (REG0x31[2]) of ILIM2_VTH (REG0x33[15:11]) set point, converter stops switching. After 300 ms, converter starts switching again. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 27 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.3.9.4 System Overvoltage Protection (SYSOVP) When the converter starts up, the bq25700 reads CELL pin configuration and sets MaxChargeVoltage() and SYSOVP threshold (1s – 5 V, 2s – 12 V, 3s – 18.5 V, 4s – 19.5V). Before REGx15() is written by the host, the battery configuration will change with CELL pin voltage. When SYSOVP happens, the device latches off the converter. REG20[4] is set as 1. The user can clear latch-off by either writing 0 to the SYSOVP bit or removing and plugging in the adapter again. After latch-off is cleared, the converter starts again. 8.3.9.5 Battery Overvoltage Protection (BATOVP) Battery over-voltage may happen when battery is removed during charging or the user plugs in a wrong battery. The BATOVP threshold is 104% (1 s) or 102% (2 s to 4 s) of regulation voltage set in REG0x15(). 8.3.9.6 Battery Short If BAT voltage falls below SYSMIN during charging, the maximum current is limited to 384 mA. 8.3.9.7 Thermal Shutdown (TSHUT) The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As added level of protection, the charger converter turns off for selfprotection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shut down, the LDO current limit is reduced to 16 mA and REGN LDO stays off. When the temperature falls below 135°C, charge can be resumed with soft start. 8.4 Device Functional Modes 8.4.1 Forward Mode When input source is connected to VBUS, bq25700A is in forward mode to regulate system and charge battery. 8.4.1.1 System Voltage Regulation with Narrow VDC Architecture The bq25700A employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by MinSystemVoltage(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage. When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode). As the battery voltage rises above the minimum system voltage, BATFET is fully on when charging or in supplement mode and the voltage difference between the system and battery is the VDS of BATFET. System voltage is regulated 160 mV above battery voltage when BATFET is off (no charging or no supplement current). See System Voltage Regulation for details on system voltage regulation and register programming. 8.4.1.2 Battery Charging The bq25700A charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. Based on CELL_BATPREZ pin setting, the charger sets default battery voltage 4.2V/cell to ChargeVoltage(), or REG0x15(). According to battery capacity, the host programs appropriate charge current to ChargeCurrent(), or 0x14(). When battery is full or battery is not in good condition to charge, host terminates charge by setting 0x12[0] to 1, or setting ChargeCurrent() to zero. See Feature Description for details on register programming. 8.4.2 USB On-The-Go The bq25700A supports USB OTG functionality to deliver power from the battery to other portable devices through USB port (reverse mode). The OTG output voltage is compliant with USB PD specification, including 5 V, 9 V, 15 V, and 20 V (REG0x3B()). The output current regulation is compliant with USB type C specification, including 500 mA, 1.5 A, 3 A and 5 A (REG0x3C()). Similar to forward operation, the device switches from PWM operation to PFM operation at light load to improve efficiency. 28 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.5 Programming The charger supports battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in . The SMBUS address is 12h (0001001_X), where X is the read/write bit. The ManufacturerID and DeviceID registers are assigned identify the charger device. The ManufacturerID register command always returns 40h. 8.5.1 SMBus Interface The bq25700A device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq25700A device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq25700A device uses the SMBus read-word and write-word protocols (shown in Table 4 and Table 5) to communicate with the smart battery. The device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH). SMBus communication starts when VCC is above V(UVLO). The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-tohigh transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 15 and Figure 16 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq25700A supports the charger commands listed in Table 4. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 29 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Programming (continued) 8.5.1.1 SMBus Write-Word and Read-Word Protocols Table 4. Write-Word Format S (1) (2) (1) (2) (3) (4) (5) (6) SLAVE ADDRESS (1) (1) (3) W ACK COMMAND BYTE (1) ACK 7 bits 1b MSB LSB 0 1b 8 bits 0 MSB LSB (4) (5) LOW DATA BYTE (1) ACK 1b 8 bits 0 MSB LSB (4) (5) HIGH DATA BYTE (1) ACK 1b 8 bits 1b 0 MSB LSB 0 (4) (5) P (4) (5) (1) (6) Master to slave S = Start condition or repeated start condition W = Write bit (logic-low) Slave to master (shaded gray) ACK = Acknowledge (logic-low) P = Stop condition Table 5. Read-Word Format S (1) (2) (1) (2) (3) (4) (5) (6) (7) (8) W ACK COMMAND ACK S (1) SLAVE R (1) ACK LOW DATA ACK (4) (5) (4) (5) (2) (1) (5) BYTE (1) ADDRESS (1) (6) (4) (5) BYTE (4) SLAVE ADDRESS (1) (1) (3) 7 bits 1b 1b 8 bits 1b 7 bits 1b 1b 8 bits MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB HIGH DATA BYTE (4) NACK 1b 8 bits 1b 0 MSB LSB 1 (1) (7) P (1) (8) Master to slave S = Start condition or repeated start condition W = Write bit (logic-low) Slave to master (shaded gray) ACK = Acknowledge (logic-low) R = Read bit (logic-high) NACK = Not acknowledge (logic-high) P = Stop condition 8.5.1.2 Timing Diagrams A B C D E F G H I J K L M tLOW tHIGH SMBCLK SMBDATA tSU:STA tHD:STA tSU:DAT tHD:DAT tHD:DAT tSU:STO tBUF A = Start condition H = LSB of data clocked into slave B = MSB of address clocked into slave I = Slave pulls SMBDATA line low C = LSB of address clocked into slave J = Acknowledge clocked into master D = R/W bit clocked into slave K = Acknowledge clock pulse E = Slave pulls SMBDATA line low L = Stop condition, data executed by slave F = ACKNOWLEDGE bit clocked into master M = New start condition G = MSB of data clocked into slave Figure 15. SMBus Write Timing 30 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 A B C D E F G H I J K tLOW tHIGH SMBCLK SMBDATA tSU:STA tHD:STA tHD:DAT tSU:DAT A = START CONDITION tSU:DAT E = SLAVE PULLS SMBDATA LINE LOW tSU:STO tBUF I = ACKNOWLEDGE CLOCK PULSE A = Start condition G = MSB of data clocked into master B = MSB of address clocked into slave H = LSB of data clocked into master C = LSB of address clocked into slave I = Acknowledge clock pulse D = R/W bit clocked into slave J = Stop condition E = Slave pulls SMBDATA line low K = New start condition F = ACKNOWLEDGE bit clocked into master Figure 16. SMBus Read Timing 8.6 Register Map Table 6. Charger Command Summary SMBus ADDR REGISTER NAME TYPE DESCRIPTION LINKS 12h ChargeOption0() R/W Charge Option 0 Go 14h ChargeCurrent() R/W 7-bit charge current setting LSB 64 mA, Range 8128 mA Go 15h MaxChargeVoltage() R/W 11-bit charge voltage setting LSB 16 mV, Default: 1S-4192mV, 2S-8400mV, 3S-12592mV, 4S-16800mV Go 30h ChargeOption1() R/W Charge Option 1 Go 31h ChargeOption2() R/W Charge Option 2 Go 32h ChargeOption3() R/W Charge Option 3 Go 33h ProchotOption0() R/W PROCHOT Option 0 Go 34h ProchotOption1() R/W PROCHOT Option 1 Go 35h ADCOption() R/W ADC Option Go 20h ChargerStatus() R Charger Status Go 21h ProchotStatus() R Prochot Status Go 22h IIN_DPM() R 7-bit input current limit in use LSB: 50 mA, Range: 50 mA - 6400 mA Go 23h ADCVBUS/PSYS() R 8-bit digital output of input voltage, 8-bit digital output of system power PSYS: Full range: 3.06 V, LSB: 12 mV VBUS: Full range: 3.2 V - 19.52 V, LSB 64 mV Go 24h ADCIBAT() R 8-bit digital output of battery charge current, 8-bit digital output of battery discharge current ICHG: Full range 8.128 A, LSB 64 mA IDCHG: Full range: 32.512 A, LSB: 256 mA Go Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 31 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Register Map (continued) Table 6. Charger Command Summary (continued) SMBus ADDR REGISTER NAME TYPE DESCRIPTION LINKS 25h ADCIINCMPIN() R 8-bit digital output of input current, 8-bit digital output of CMPIN voltage POR State - IIN: Full range: 12.75 A, LSB 50 mA CMPIN: Full range 3.06 V, LSB: 12 mV Go 26h ADCVSYSVBAT() R 8-bit digital output of system voltage, 8-bit digital output of battery voltage VSYS: Full range: 2.88 V - 19.2 V, LSB: 64 mV VBAT: Full range : 2.88 V - 19.2 V, LSB 64 mV Go 3Bh OTGVoltage() R/W 8-bit OTG voltage setting LSB 64 mV, Range: 4480 – 20800 mV Go 3Ch OTGCurrent() R/W 7-bit OTG output current setting LSB 50 mA, Range: 0 A – 6350 mA Go 3Dh InputVoltage() R/W 8-bit input voltage setting LSB 64 mV, Range: 3200 mV – 19520 mV Go 3Eh MinSystemVoltage() R/W 6-Bit minimum system voltage setting LSB: 256 mV, Range: 1024 mV - 16182 mV Default: 1S-3.584V, 2S-6.144V, 3S-9.216V, 4S12.288V Go 3Fh IIN_HOST() R/W 6-bit Input current limit set by host LSB: 50 mA, Range: 0 mA - 6350 mA Go FEh ManufacturerID() R Manufacturer ID - 0x0040H Go FFh DeviceAddress() R Device Address ID Go 32 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.1 Setting Charge and PROCHOT Options 8.6.1.1 ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh] Figure 17. ChargeOption0 Register (SMBus address = 12h) [reset = E20Eh] 15 EN_LWPWR 14 13 12 IDPM_AUTO_ DISABLE R/W 11 OTG_ON_ CHRGOK R/W 10 EN_OOA 9 PWM_FREQ 8 Reserved R/W R/W R/W 5 EN_LEARN R/W 4 IADPT_GAIN R/W 3 IBAT_GAIN R/W 2 EN_LDO R/W 1 EN_IDPM R/W 0 CHRG_INHIBIT R/W WDTMR_ADJ R/W R/W 7 6 Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions SMBus BIT 15 FIELD TYPE RESET DESCRIPTION EN_LWPWR R/W 1b Low Power Mode Enable 0b: Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, current/power monitor buffer and comparator follow register setting. 1b: Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. ADC is not available in Low Power Mode. Independent comparator can be enabled by setting either REG0X30()[14] or [13] to 1. <default at POR> 14-13 WDTMR_ADJ R/W 11b WATCHDOG Timer Adjust Set maximum delay between consecutive SMBus write of charge voltage or charge current command. If device does not receive a write on the REG0x15() or the REG0x14() within the watchdog time period, the charger will be suspended by setting the REG0x14() to 0 mA. After expiration, the timer will resume upon the write of REG0x14(), REG0x15() or REG0x12[14:13]. The charger will resume if the values are valid. 00b: Disable Watchdog Timer 01b: Enabled, 5 sec 10b: Enabled, 88 sec 11b: Enable Watchdog Timer, 175 sec <default at POR> 12 IDPM_AUTO_ DISABLE R/W 0b IDPM Auto Disable When CELL_BATPRESZ pin is LOW, the charger automatically disables the IDPM function by setting EN_IDPM (REG0x12[1]) to 0. The host can enable IDPM function later by writing EN_IDPM bit (REG0x12[1]) to 1. 0b: Disable this function. IDPM is not disabled when CELL_BATPRESZ goes LOW. <default at POR> 1b: Enable this function. IDPM is disabled when CELL_BATPRESZ goes LOW. 11 OTG_ON_ CHRGOK R/W 0b Add OTG to CHRG_OK Drive CHRG_OK to HIGH when the device is in OTG mode. 0b: Disable <default at POR> 1b: Enable 10 EN_OOA R/W 0b Out-of-Audio Enable 0b: No limit of PFM burst frequency <default at POR> 1b: Set minimum PFM burst frequency to above 25 kHz to avoid audio noise Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 33 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Table 7. ChargeOption0 Register (SMBus address = 12h) Field Descriptions (continued) SMBus BIT 9 FIELD TYPE RESET DESCRIPTION PWM_FREQ R/W 1b Switching Frequency Two converter switching frequencies. One for small inductor and the other for big inductor. Recommend 800 kHz with 2.2 µH or 3.3 µH, and 1.2 MHz with 1 µH or 1.5 µH. 0b: 1200 kHz 1b: 800 kHz <default at POR> 8 Reserved R/W 0b Reserved Table 8. ChargeOption0 Register (SMBus address = 12h) Field Descriptions SMBus BIT 7-6 5 FIELD TYPE RESET DESCRIPTION Reserved R/W 00b Reserved EN_LEARN R/W 0b LEARN function allows the battery to discharge while the adapter is present. It calibrates the battery gas gauge over a complete discharge/charge cycle. When the battery voltage is below battery depletion threshold, the system switches back to adapter input by the host. When CELL_BATPRESZ pin is LOW, the device exits LEARN mode and this bit is set back to 0. 0b: Disable LEARN Mode <default at POR> 1b: Enable LEARN Mode 4 IADPT_GAIN R/W 0b IADPT Amplifier Ratio The ratio of voltage on IADPT and voltage across ACP and ACN. 0b: 20× <default at POR> 1b: 40× 3 IBAT_GAIN R/W 1b IBAT Amplifier Ratio 0b: 8× 1b: 16× <default at POR> 2 EN_LDO R/W 1b LDO Mode Enable When battery voltage is below minimum system voltage (REG0x3E()), the charger is in pre-charge with LDO mode enabled. 0b: Disable LDO mode, BATFET fully ON. Precharge current is set by battery pack LDO. The system is regulated by the MaxChargeVoltage register. 1b: Enable LDO mode, Precharge current is set by the ChargeCurrent register and clamped below 384 mA (2 cell – 4 cell) or 2A (1 cell). The system is regulated by the MinSystemVoltage register. <default at POR> 1 EN_IDPM R/W 1b IDPM Enable Host writes this bit to enable IDPM regulation loop. When the IDPM is disabled by the charger (refer to IDPM_AUTO_DISABLE), this bit goes LOW. 0b: IDPM disabled 1b: IDPM enabled <default at POR> 0 CHRG_INHIBIT R/W 0b Charge Inhibit When this bit is 0, battery charging will start with valid values in the MaxChargeVoltage register and the ChargeCurrent register. 0b: Enable Charge <default at POR> 1b: Inhibit Charge 34 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.1.2 ChargeOption1 Register (SMBus address = 30h) [reset = 211h] Figure 18. ChargeOption1 Register (SMBus address = 30h) [reset = 211h] 15 EN_IBAT R/W 14 13 EN_PROCHOT_LPWR R/W 7 CMP_REF 6 CMP_POL R/W R/W 12 EN_PSYS R/W 11 RSNS_RAC R/W 10 RSNS_RSR R/W 9 PSYS_RATIO R/W 8 Reserved R/W 4 3 FORCE_ LATCHOFF R/W 2 Reserved 1 EN_SHIP_ DCHG R/W 0 AUTO_ WAKEUP_EN R/W 5 CMP_DEG R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9. ChargeOption1 Register (SMBus address = 30h) Field Descriptions SMBus FIELD BIT 15 EN_IBAT TYPE RESET DESCRIPTION R/W 0b IBAT Enable Enable the IBAT output buffer. In low power mode (REG0x12[15] = 1), IBAT buffer is always disabled regardless of this bit value. 0b Turn off IBAT buffer to minimize Iq <default at POR> 1b: Turn on IBAT buffer 14-13 EN_PROCHOT _LPWR R/W 00b Enable PROCHOT during battery only low power mode With battery only, enable IDCHG or VSYS in PROCHOT with low power consumption. Do not enable this function with adapter present. Refer to PROCHOT During Low Power Mode for more details. 00b: Disable low power PROCHOT <default at POR> 01b: Enable IDCHG low power PROCHOT 10b: Enable VSYS low power PROCHOT 11b: Reserved 12 EN_PSYS R/W 0b PSYS Enable Enable PSYS sensing circuit and output buffer (whole PSYS circuit). In low power mode (REG0x12[15] = 1), PSYS sensing and buffer are always disabled regardless of this bit value. 0b: Turn off PSYS buffer to minimize Iq <default at POR> 1b: Turn on PSYS buffer 11 RSNS_RAC R/W 0b Input sense resistor RAC 0b: 10 mΩ <default at POR> 1b: 20 mΩ 10 RSNS_RSR R/W 0b Charge sense resistor RSR 0b: 10 mΩ <default at POR> 1b: 20 mΩ 9 PSYS_RATIO R/W 1b PSYS Gain Ratio of PSYS output current vs total input and battery power with 10-mΩ sense resistor. 0b: 0.25 µA/W 1b: 1 µA/W <default at POR> 8 Reserved R/W 0b Reserved Table 10. ChargeOption1 Register (SMBus address = 30h) Field Descriptions SMBus FIELD BIT 7 CMP_REF TYPE RESET DESCRIPTION R/W 0b Independent Comparator Reference Independent comparator internal reference. 0b: 2.3 V <default at POR> 1b: 1.2 V Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 35 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Table 10. ChargeOption1 Register (SMBus address = 30h) Field Descriptions (continued) SMBus FIELD BIT 6 CMP_POL TYPE RESET DESCRIPTION R/W 0b Independent Comparator Polarity Independent comparator output polarity 0b: When CMPIN is above internal threshold, CMPOUT is LOW (internal hysteresis) <default at POR> 1b: When CMPIN is below internal threshold, CMPOUT is LOW (external hysteresis) 5-4 CMP_DEG R/W 01b Independent Comparator Deglitch Time Independent comparator deglitch time, only applied to the falling edge of CMPOUT (HIGH → LOW). 00b: Independent comparator is disabled 01b: Independent comparator is enabled with output deglitch time 1 µs <default at POR> 10b: Independent comparator is enabled with output deglitch time of 2 ms 11b: Independent comparator is enabled with output deglitch time of 5 sec 3 FORCE_LATCHOFF R/W 0b Force Power Path Off When comparator triggers, charger turns off Q1 and Q4 (same as disable converter) so that the system is disconnected from the input source. At the same time, CHRG_OK signal goes to LOW to notify the system. 0b: Disable this function <default at POR> 1b: Enable this function 2 Reserved R/W 0b Reserved 1 EN_SHIP_DCHG R/W 0b Discharge SRN for Shipping Mode When this bit is 1, discharge SRN pin down below 3.8 V in 140 ms. When 140 ms is over, this bit is reset to 0. 0b: Disable shipping mode <default at POR> 1b: Enable shipping mode 0 AUTO_WAKEUP_EN R/W 1b Auto Wakeup Enable When this bit is HIGH, if the battery is below minimum system voltage (REG0x3E()), the device will automatically enable 128 mA charging current for 30 mins. When the battery is charged up above minimum system voltage, charge will terminate and the bit is reset to LOW. 0b: Disable 1b: Enable <default at POR> 36 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.1.3 ChargeOption2 Register (SMBus address = 31h) [reset = 2B7] Figure 19. ChargeOption2 Register (SMBus address = 31h) [reset = 2B7] 15 14 PKPWR_TOVLD_DEG R/W 7 EN_EXTILIM R/W 6 EN_ICHG _IDCHG R/W 13 EN_PKPWR_ IDPM R/W 12 EN_PKPWR_ VSYS R/W 11 PKPWR_ OVLD_STAT R/W 10 PKPWR_ RELAX_STAT R/W 9 8 PKPWR_TMAX[1:0] 5 Q2_OCP 4 ACX_OCP 3 EN_ACOC 2 ACOC_VTH 1 EN_BATOC 0 BATOC_VTH R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. ChargeOption2 Register (SMBus address = 31h) Field Descriptions SMBus BIT 15-14 FIELD TYPE RESET DESCRIPTION PKPWR_ TOVLD_DEG R/W 00b Input Overload time in Peak Power Mode 00b: 1 ms <default at POR> 01b: 2 ms 10b: 10 ms 11b: 20 ms 13 EN_PKPWR_IDPM R/W 0b Enable Peak Power Mode triggered by input current overshoot If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b. 0b: Disable peak power mode triggered by input current overshoot <default at POR> 1b: Enable peak power mode triggered by input current overshoot. 12 EN_PKPWR_VSYS R/W 0b Enable Peak Power Mode triggered by system voltage under-shoot If REG0x31[13:12] are 00b, peak power mode is disabled. Upon adapter removal, the bits are reset to 00b. 0b: Disable peak power mode triggered by system voltage under-shoot <default at POR> 1b: Enable peak power mode triggered by system voltage under-shoot. 11 PKPWR_ OVLD_STAT R/W 0b Indicator that the device is in overloading cycle. Write 0 to get out of overloading cycle. 0b: Not in peak power mode. <default at POR> 1b: In peak power mode. 10 PKPWR_ RELAX_STAT R/W 0b Indicator that the device is in relaxation cycle. Write 0 to get out of relaxation cycle. 0b: Not in relaxation cycle. <default at POR> 1b: In relaxation mode. 9-8 PKPWR_ TMAX[1:0] R/W 10b Peak power mode overload and relax cycle time. When REG0x31[15:14] is programmed longer than REG0x31[9:8], there is no relax time. 00b: 5 ms 01b: 10 ms 10b: 20 ms <default at POR> 11b: 40 ms Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 37 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Table 12. ChargeOption2 Register (SMBus address = 31h) Field Descriptions SMBus BIT 7 FIELD TYPE RESET DESCRIPTION EN_EXTILIM R/W 1b Enable ILIM_HIZ pin to set input current limit 0b: Input current limit is set by REG0x3F. 1b: Input current limit is set by the lower value of ILIM_HIZ pin and REG0x3F. <default at POR> 6 EN_ICHG _IDCHG R/W 0b 5 Q2_OCP R/W 1b 0b: IBAT pin as discharge current. <default at POR> 1b: IBAT pin as charge current. Q2 OCP threshold by sensing Q2 VDS 0b: 210 mV 1b: 150 mV <default at POR> 4 ACX_OCP R/W 1b Input current OCP threshold by sensing ACP-ACN. 0b: 280 mV 1b: 150 mV <default at POR> 3 EN_ACOC R/W 0b ACOC Enable Input overcurrent (ACOC) protection by sensing the voltage across ACP and ACN. Upon ACOC (after 100-µs blank-out time), converter is disabled. 0b: Disable ACOC <default at POR> 1b: ACOC threshold 125% or 200% ICRIT 2 ACOC_VTH R/W 1b ACOC Limit Set MOSFET OCP threshold as percentage of IDPM with current sensed from RAC. 0b: 125% of ICRIT 1b: 200% of ICRIT <default at POR> 1 EN_BATOC R/W 1b BATOC Enable Battery discharge overcurrent (BATOC) protection by sensing the voltage across SRN and SRP. Upon BATOC, converter is disabled. 0b: Disable BATOC 1b: BATOC threshold 125% or 200% PROCHOT IDCHG <default at POR> 0 BATOC_VTH R/W 1b Set battery discharge overcurrent threshold PROCHOT battery discharge current limit. as percentage of 0b: 125% of PROCHOT IDCHG 1b: 200% of PROCHOT IDCHG <default at POR> 38 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.1.4 ChargeOption3 Register (SMBus address = 32h) [reset = 0h] Figure 20. ChargeOption3 Register (SMBus address = 32h) [reset = 0h] 15 EN_HIZ 14 RESET_REG 12 EN_OTG R/W 13 RESET_ VINDPM R/W R/W 7 10 R/W 11 EN_ICO_MOD E R/W 6 5 4 3 2 9 Reserved 8 R/W 1 BATFETOFF_ HIZ R/W Reserved R/W 0 PSYS_OTG_ IDCHG R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 13. ChargeOption3 Register (SMBus address = 32h) Field Descriptions SMBus FIELD BIT 15 EN_HIZ TYPE RESET DESCRIPTION R/W 0b Device Hi-Z Mode Enable When the charger is in Hi-Z mode, the device draws minimal quiescent current. With VBUS above UVLO. REGN LDO stays on, and system powers from battery. 0b: Device not in Hi-Z mode <default at POR> 1b: Device in Hi-Z mode 14 RESET_REG R/W 0b Reset Registers All the registers go back to the default setting except the VINDPM register. 0b: Idle <default at POR> 1b: Reset all the registers to default values. After reset, this bit goes back to 0. 13 RESET_VINDPM R/W 0b Reset VINDPM Threshold 0b: Idle 1b: Converter is disabled to measure VINDPM threshold. After VINDPM measurement is done, this bit goes back to 0 and converter starts. 12 EN_OTG R/W 0b OTG Mode Enable Enable device in OTG mode when EN_OTG pin is HIGH. 0b: Disable OTG <default at POR> 1b: Enable OTG mode to supply VBUS from battery. 11 EN_ICO_MODE R/W 0b Enable ICO Algorithm 0b: Disable ICO algorithm. <default at POR> 1b: Enable ICO algorithm. 10-8 Reserved R/W 000b Reserved Table 14. ChargeOption3 Register (SMBus address = 32h) Field Descriptions SMBus FIELD BIT 7-2 1 TYPE RESET DESCRIPTION Reserved R/W 000000b Reserved BATFETOFF_ HIZ R/W 0b Control BATFET during HIZ mode. 0b: BATFET on during Hi-Z 1b: BATFET off during Hi-Z 0 PSYS_OTG_ IDCHG R/W 0b PSYS function during OTG mode. 0b: PSYS as battery discharge power minus OTG output power 1b: PSYS as battery discharge power only Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 39 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.1.5 ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h] Figure 21. ProchotOption0 Register (SMBus address = 33h) [reset = 04A54h] 15-11 ILIM2_VTH R/W 7-6 VSYS_VTH R/W 5 EN_PROCHOT _EXT R/W 10-9 ICRIT_DEG R/W 4-3 PROCHOT_WIDTH R/W 2 PROCHOT_ CLEAR R/W 8 Reserved R/W 1 INOM_DEG 0 Reserved R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15. ProchotOption0 Register (SMBus address = 33h) Field Descriptions SMBus FIELD BIT 15-11 ILIM2_VTH TYPE RESET DESCRIPTION R/W 01001b ILIM2 Threshold 5 bits, percentage of IDPM in 0x3FH. Measure current between ACP and ACN. Trigger when the current is above this threshold: 00001b - 11001b: 110% - 230%, step 5% 11010b - 11110b: 250% - 450%, step 50% 11111b: Out of Range (Ignored) Default 150%, or 01001 10-9 ICRIT_DEG R/W 01b ICRIT Deglitch time ICRIT threshold is set to be 110% of ILIM2. Typical ICRIT deglitch time to trigger PROCHOT. 00b: 15 µs 01b: 100 µs <default at POR> 10b: 400 µs (max 500 us) 11b: 800 µs (max 1 ms) 8 Reserved R/W 0b Reserved Table 16. ProchotOption0 Register (SMBus address = 33h) Field Descriptions SMBus FIELD BIT 7-6 VSYS_VTH TYPE RESET DESCRIPTION R/W 01b VSYS Threshold Measure on VSYS with fixed 20-µs deglitch time. Trigger when SYS pin voltage is below the threshold. 00b: 5.75 V (2-4 s) or 2.85 V (1 s) 01b: 6 V (2-4 s) or 3.1 V (1 s) <default at POR> 10b: 6.25 V (2-4 s) or 3.35 V (1 s) 11b: 6.5 V (2-4 s) or 3.6 V (1 s) 5 EN_PROCHOT _EXT R/W 0b When pulse extension is enabled, keep the PROCHOT pin voltage LOW until host writes 0x33[2] = 0. 0b: Disable pulse extension <default at POR> 1b: Enable pulse extension 4-3 PROCHOT _WIDTH R/W 10b PROCHOT Pulse Width PROCHOT Pulse Extension Enable Minimum PROCHOT pulse width when REG0x33[5] = 0 00b: 100 µs 01b: 1 ms 10b: 10 ms <default at POR> 11b: 5 ms 40 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Table 16. ProchotOption0 Register (SMBus address = 33h) Field Descriptions (continued) SMBus FIELD BIT 2 PROCHOT _CLEAR TYPE RESET DESCRIPTION R/W 1b PROCHOT Pulse Clear Clear PROCHOT pulse when 0x33[5] = 1. 0b: Clear PROCHOT pulse and drive PROCHOT pin HIGH. 1b: Idle <default at POR> 1 INOM_DEG R/W 0b INOM Deglitch Time INOM is always 10% above IDPM in 0x3FH. Measure current between ACP and ACN. Trigger when the current is above this threshold. 0b: 1 ms (must be max) <default at POR> 1b: 50 ms (max 60 ms) 0 Reserved R/W Copyright © 2017, Texas Instruments Incorporated 0b Reserved Submit Documentation Feedback 41 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.1.6 ProchotOption1 Register (SMBus address = 34h) [reset = 8120h] Figure 22. ProchotOption1 Register (SMBus address = 34h) [reset = 8120h] 15-10 IDCHG_VTH R/W 7 Reserved R/W 6 PROCHOT_PR OFILE_IC R/W 9-8 IDCHG_DEG R/W 5 PP_ICRIT 4 PP_INOM 3 PP_IDCHG 2 PP_VSYS 1 PP_BATPRES 0 PP_ACOK R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17. ProchotOption1 Register (SMBus address = 34h) Field Descriptions SMBus BIT 15-10 FIELD TYPE RESET DESCRIPTION IDCHG_VTH R/W 000000b IDCHG Threshold 6 bit, range, range 0 A to 32256 mA, step 512 mA. Measure current between SRN and SRP. Trigger when the discharge current is above the threshold. If the value is programmed to 0 mA, PROCHOT is always triggered. Default: 16384 mA or 100000 9-8 IDCHG_DEG R/W 01b IDCHG Deglitch Time 00b: 1.6 ms 01b: 100 µs <default at POR> 10b: 6 ms 11b: 12 ms Table 18. ProchotOption1 Register (SMBus address = 34h) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 7 Reserved R/W 0b Reserved 6 PROCHOT _PROFILE_COMP R/W 0b PROCHOT Profile When all the REG0x34[6:0] bits are 0, PROCHOT function is disabled. Bit6 Independent comparator 0b: disable <default at POR> 1b: enable 5 PROCHOT _PROFILE_ICRIT R/W 1b 4 PROCHOT _PROFILE_INOM R/W 0b 3 PROCHOT _PROFILE_IDCHG R/W 0b 2 PROCHOT _PROFILE_VSYS R/W 0b 1 PROCHOT _PROFILE_BATPRES R/W 0b 0b: disable 1b: enable <default at POR> 0b: disable <default at POR> 1b: enable 0b: disable <default at POR> 1b: enable 0b: disable <default at POR> 1b: enable 0b: disable <default at POR> 1b: enable (one-shot falling edge triggered) If BATPRES is enabled in PROCHOT after the battery is removed, it will immediately send out one-shot PROCHOT pulse. 42 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Table 18. ProchotOption1 Register (SMBus address = 34h) Field Descriptions (continued) SMBus BIT 0 FIELD TYPE RESET DESCRIPTION PROCHOT _PROFILE_ACOK R/W 0b 0b: disable <default at POR> 1b: enable ChargeOption0[15] = 0 to assert PROCHOT pulse after adapter removal. If PROCHOT_PROFILE_ACOK is enabled in PROCHOT after the adapter is removed, it will be pulled low. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 43 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.1.7 ADCOption Register (SMBus address = 35h) [reset = 2000h] Figure 23. ADCOption Register (SMBus address = 35h) [reset = 2000h] 15 ADC_CONV 14 ADC_START R/W R/W 13 ADC_ FULLSCALE R/W 7 EN_ADC_ CMPIN R/W 6 EN_ADC_ VBUS R/W 5 EN_ADC_ PSYS R/W 12-8 Reserved R/W 4 EN_ADC_ IIN R/W 3 EN_ADC_ IDCHG R/W 2 EN_ADC_ ICHG R/W 1 EN_ADC_ VSYS R/W 0 EN_ADC_ VBAT R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC is disabled in low power mode. When enabling ADC, the device exit low power mode at battery only. Table 19. ADCOption Register (SMBus address = 35h) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 15 ADC_CONV R/W 0b Typical ADC conversion time is 10 ms. 0b: One-shot update. Do one set of conversion updates to registers REG0x23(), REG0x24(), REG0x25(), and REG0x26() after ADC_START = 1. 1b: Continuous update. Do a set of conversion updates to registers REG0x23(), REG0x24(), REG0x25(), and REG0x26() every 1 sec. 14 ADC_START R/W 0b 0b: No ADC conversion 1b: Start ADC conversion. After the one-shot update is complete, this bit automatically resets to zero 13 ADC_ FULLSCALE R/W 1b ADC input voltage range. When input voltage is below 5 V, or battery is 1S, full scale 2.04 V is recommended. 0b: 2.04 V 1b: 3.06 V <default at POR> 12-8 Reserved R/W 00000b Reserved Table 20. ADCOption Register (SMBus address = 35h) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 7 EN_ADC_CMPIN R/W 0b 0b: Disable <default at POR> 6 EN_ADC_VBUS R/W 0b 5 EN_ADC_PSYS R/W 0b 4 EN_ADC_IIN R/W 0b 3 EN_ADC_IDCHG R/W 0b 2 EN_ADC_ICHG R/W 0b 1 EN_ADC_VSYS R/W 0b 1b: Enable 0b: Disable <default at POR> 1b: Enable 0b: Disable <default at POR> 1b: Enable 0b: Disable <default at POR> 1b: Enable 0b: Disable <default at POR> 1b: Enable 0b: Disable <default at POR> 1b: Enable 0b: Disable <default at POR> 1b: Enable 0 EN_ADC_VBAT R/W 0b 0b: Disable <default at POR> 1b: Enable 44 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.2 Charge and PROCHOT Status 8.6.2.1 ChargerStatus Register (SMBus address = 20h) [reset = 0000h] Figure 24. ChargerStatus Register (SMBus address = 20h) [reset = 0000h] 15 AC_STAT R 14 ICO_DONE R 13 Reserved R 12 IN_VINDPM R 11 IN_IINDPM R 10 IN_FCHRG R 9 IN_PCHRG R 8 IN_OTG R 7 Fault ACOV 6 Fault BATOC 5 Fault ACOC 3 Reserved 2 Fault Latchoff R R R 4 SYSOVP_ STAT R R R 1 Fault_OTG_ OVP R 0 Fault_OTG_ OCP R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21. ChargerStatus Register (SMBus address = 20h) Field Descriptions SMBus BIT 15 FIELD TYPE RESET DESCRIPTION AC_STAT R 0b Input source status, same as CHRG_OK bit 0b: Input not present 1b: Input is present 14 ICO_DONE R 0b After the ICO routine is successfully executed, the bit goes 1. 0b: ICO is not complete 1b: ICO is complete 13 Reserved R 0b Reserved 12 IN_VINDPM R 0b 0b: Charger is not in VINDPM during forward mode, or voltage regulation during OTG mode 1b: Charger is in VINDPM during forward mode, or voltage regulation during OTG mode 11 IN_IINDPM R 0b 10 IN_FCHRG R 0b 9 IN_PCHRG R 0b 8 IN_OTG R 0b 0b: Charger is not in IINDPM 1b: Charger is in IINDPM 0b: Charger is not in fast charge 1b: Charger is in fast charger 0b: Charger is not in pre-charge 1b: Charger is in pre-charge 0b: Charger is not in OTG 1b: Charge is in OTG Table 22. ChargerStatus Register (SMBus address = 20h) Field Descriptions SMBus BIT 7 FIELD TYPE RESET DESCRIPTION Fault ACOV R 0b The faults are latched until a read from host. 0b: No fault 1b: ACOV 6 Fault BATOC R 0b The faults are latched until a read from host. 0b: No fault 1b: BATOC 5 Fault ACOC R 0b The faults are latched until a read from host. 0b: No fault 1b: ACOC Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 45 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Table 22. ChargerStatus Register (SMBus address = 20h) Field Descriptions (continued) SMBus BIT 4 FIELD TYPE RESET DESCRIPTION SYSOVP_STAT R 0b SYSOVP Status and Clear When the SYSOVP occurs, this bit is HIGH. During the SYSOVP, the converter is disabled. After the SYSOVP is removed, the user must write a 0 to this bit or unplug the adapter to clear the SYSOVP condition to enable the converter again. 0b: Not in SYSOVP <default at POR> 1b: In SYSOVP. When SYSOVP is removed, write 0 to clear the SYSOVP latch. 3 Reserved R 0b Reserved 2 Fault Latchoff R 0b The faults are latched until a read from host. 0b: No fault 1b: Latch off (REG0x30[3]) 1 Fault_OTG_OVP R 0b The faults are latched until a read from host. 0b: No fault 1b: OTG OVP 0 Fault_OTG_UCP R 0b The faults are latched until a read from host. 0b: No fault 1b: OTG OCP 46 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.2.2 ProchotStatus Register (SMBus address = 21h) [reset = 0h] Figure 25. ProchotStatus Register (SMBus address = 21h) [reset = 0h] 15-8 Reserved R 7 Reserved 6 STAT_COMP 5 STAT_ICRIT 4 STAT_INOM 3 STAT_IDCHG 2 STAT_VSYS R R R R R R 1 STAT_Battery_ Removal R 0 STAT_Adapter _Removal R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23. ProchotStatus Register (SMBus address = 21h) Field Descriptions SMBus BIT 15-8 FIELD TYPE RESET DESCRIPTION Reserved R 0000000 0b Reserved Table 24. ProchotStatus Register (SMBus address = 21h) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 7 Reserved R 0b Reserved 6 STAT_COMP R 0b 0b: Not triggered 1b: Triggered 5 STAT_ICRIT R 0b 4 STAT_INOM R 0b 3 STAT_IDCHG R 0b 2 STAT_VSYS R 0b 1 STAT_Battery_Removal R 0b 0 STAT_Adapter_Removal R 0b 0b: Not triggered 1b: Triggered 0b: Not triggered 1b: Triggered 0b: Not triggered 1b: Triggered 0b: Not triggered 1b: Triggered 0b: Not triggered 1b: Triggered 0b: Not triggered 1b: Triggered Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 47 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.3 ChargeCurrent Register (SMBus address = 14h) [reset = 0h] To set the charge current, write a 16-bit ChargeCurrent() command (REG0x14()) using the data format listed in Table 25 and Table 26. With 10-mΩ sense resistor, the charger provides charge current range of 64 mA to 8.128 A, with a 64-mA step resolution. Upon POR, ChargeCurrent() is 0 A. Any conditions for CHRG_OK low except ACOV will reset ChargeCurrent() to zero. CELL_BATPRESZ going LOW (battery removal) will reset the ChargeCurrent() register to 0 A. Charge current is not reset in ACOC, TSHUT, power path latch off (REG0x30[1]), and SYSOVP. A 0.1-µF capacitor between SRP and SRN for differential mode filtering is recommended; an optional 0.1-µF capacitor between SRN and ground, and an optional 0.1-µF capacitor between SRP and ground for common mode filtering. Meanwhile, the capacitance on SRP should not be higher than 0.1 µF in order to properly sense the voltage across SRP and SRN for cycle-by-cycle current detection. The SRP and SRN pins are used to sense voltage drop across RSR with default value of 10 mΩ. However, resistors of other values can also be used. For a larger sense resistor, a larger sense voltage is given, and a higher regulation accuracy; but, at the expense of higher conduction loss. If current sensing resistor value is too high, it may trigger an over current protection threshold because the current ripple voltage is too high. In such a case, either a higher inductance value or a lower current sensing resistor value should be used to limit the current ripple voltage level. A current sensing resistor value no more than 20 mΩ is suggested. Figure 26. ChargeCurrent Register With 10-mΩ Sense Resistor (SMBus address = 14h) [reset = 0h] 15 14 Reserved 13 12 Charge Current, bit 6 R/W 11 Charge Current, bit 5 R/W 10 Charge Current, bit 4 R/W 9 Charge Current, bit 3 R/W 8 Charge Current, bit 2 R/W 5 Reserved 4 3 2 Reserved 1 0 R/W 7 Charge Current, bit 1 R/W 6 Charge Current, bit 0 R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION Reserved R/W 000b Not used. 1 = invalid write. 12 Charge Current, bit 6 R/W 0b 0 = Adds 0 mA of charger current. 11 Charge Current, bit 5 R/W 0b 10 Charge Current, bit 4 R/W 0b 9 Charge Current, bit 3 R/W 0b 8 Charge Current, bit 2 R/W 0b 15-13 1 = Adds 4096 mA of charger current. 0 = Adds 0 mA of charger current. 1 = Adds 2048 mA of charger current. 0 = Adds 0 mA of charger current. 1 = Adds 1024 mA of charger current. 0 = Adds 0 mA of charger current. 1 = Adds 512 mA of charger current. 0 = Adds 0 mA of charger current. 1 = Adds 256 mA of charger current. Table 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions SMBus BIT 7 FIELD TYPE RESET DESCRIPTION Charge Current, bit 1 R/W 0b 0 = Adds 0 mA of charger current. 1 = Adds 128 mA of charger current. 48 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Table 26. Charge Current Register (14h) With 10-mΩ Sense Resistor (SMBus address = 14h) Field Descriptions (continued) SMBus BIT 6 FIELD TYPE RESET DESCRIPTION Charge Current, bit 0 R/W 0b 0 = Adds 0 mA of charger current. 1 = Adds 64 mA of charger current. 5-0 8.6.3.1 Reserved R/W 000000b Not used. Value Ignored. Battery Pre-Charge Current Clamp During pre-charge, BATFET works in linear mode or LDO mode (default REG0x12[2] = 1). For 2-4 cell battery, the system is regulated at minimum system voltage in REG0x3E() and the pre-charge current is clamped at 384 mA. For 1 cell battery, the pre-charge to fast charge threshold is 3 V, and the pre-charge current is clamped at 384 mA. However, the BATFET stays in LDO mode operation till battery voltage is above minimum system voltage (~3.6 V). During battery voltage from 3 V to 3.6 V, the fast charge current is clamped at 2 A. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 49 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.4 MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting] To set the output charge voltage, write a 16-bit ChargeVoltage register command (REG0x15()) using the data format listed in Table 27 and Table 28. The charger provides charge voltage range from 1.024 V to 19.200 V, with 16-mV step resolution. Any write below 1.024 V or above 19.200 V is ignored. Upon POR or when charge is disabled, the system is regulated at the MaxChargeVoltage register. Upon POR, REG0x15() is by default set as 4192 mV for 1 s, 8400 mV for 2 s, 12592 mV for 3 s or 16800 mV for 4 s. After CHRG_OK, if host writes REG0x14() before REG0x15(), the charge will start after the write to REG0x14().If the battery is different from 4.2 V/cell, the host has to write to REG0x15() before REG0x14() for correct battery voltage setting. Writing REG0x15() to 0 will set REG0x15() to default value on CELL_BATPRESZ pin, and force REG0x14() to zero to disable charge. The SRN pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1 µF recommended) as close to the device as possible to decouple high frequency noise. Figure 27. MaxChargeVoltage Register (SMBus address = 15h) [reset value based on CELL_BATPRESZ pin setting] 15 Reserved R/W 14 Max Charge Voltage, bit 10 R/W 13 Max Charge Voltage, bit 9 R/W 12 Max Charge Voltage, bit 8 R/W 11 Max Charge Voltage, bit 7 R/W 10 Max Charge Voltage, bit 6 R/W 9 Max Charge Voltage, bit 5 R/W 8 Max Charge Voltage, bit 4 R/W 7 Max Charge Voltage, bit 3 R/W 6 Max Charge Voltage, bit 2 R/W 5 Max Charge Voltage, bit 1 R/W 4 Max Charge Voltage, bit 0 R/W 3 2 1 0 Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 15 Reserved R/W 0b Not used. 1 = invalid write. 14 Max Charge Voltage, bit 10 R/W 0b 0 = Adds 0 mV of charger voltage. 13 Max Charge Voltage, bit 9 R/W 0b 12 Max Charge Voltage, bit 8 R/W 0b 11 Max Charge Voltage, bit 7 R/W 0b 10 Max Charge Voltage, bit 6 R/W 0b 9 Max Charge Voltage, bit 5 R/W 0b 8 Max Charge Voltage, bit 4 R/W 0b 1 = Adds 16384 mV of charger voltage. 0 = Adds 0 mV of charger voltage. 1 = Adds 8192 mV of charger voltage 0 = Adds 0 mV of charger voltage. 1 = Adds 4096 mV of charger voltage. 0 = Adds 0 mV of charger voltage. 1 = Adds 2048 mV of charger voltage. 0 = Adds 0 mV of charger voltage. 1 = Adds 1024 mV of charger voltage. 0 = Adds 0 mV of charger voltage. 1 = Adds 512 mV of charger voltage. 0 = Adds 0 mV of charger voltage. 1 = Adds 256 mV of charger voltage. Table 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions SMBus BIT 7 FIELD TYPE RESET DESCRIPTION Max Charge Voltage, bit 3 R/W 0b 0 = Adds 0 mV of charger voltage. 1 = Adds 128 mV of charger voltage. 50 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Table 28. MaxChargeVoltage Register (SMBus address = 15h) Field Descriptions (continued) SMBus BIT FIELD TYPE RESET DESCRIPTION 6 Max Charge Voltage, bit 2 R/W 0b 0 = Adds 0 mV of charger voltage. 5 Max Charge Voltage, bit 1 R/W 0b 4 Max Charge Voltage, bit 0 R/W 0b Reserved R/W 0000b 1 = Adds 64 mV of charger voltage. 0 = Adds 0 mV of charger voltage. 1 = Adds 32 mV of charger voltage. 0 = Adds 0 mV of charger voltage. 1 = Adds 16 mV of charger voltage. 3-0 Copyright © 2017, Texas Instruments Incorporated Not used. Value Ignored. Submit Documentation Feedback 51 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.5 MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting] To set the minimum system voltage, write a 16-bit MinSystemVoltage register command (REG0x3E()) using the data format listed in Table 29 and Table 30. The charger provides minimum system voltage range from 1.024 V to 16.128 V, with 256-mV step resolution. Any write below 1.024 V or above 16.128 V is ignored. Upon POR, the MinSystemVoltage register is 3.584 V for 1 S, 6.144 V for 2 S and 9.216 V for 3 S, and 12.288 V for 4 S. Figure 28. MinSystemVoltage Register (SMBus address = 3Eh) [reset value based on CELL_BATPRESZ pin setting] 15 14 13 Min System Voltage, bit 5 R/W 12 Min System Voltage, bit 4 R/W 11 Min System Voltage, bit 3 R/W 10 Min System Voltage, bit 2 R/W 9 Min System Voltage, bit 1 R/W 8 Min System Voltage, bit 0 R/W 6 5 4 3 2 1 0 Reserved R/W 7 Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions SMBus BIT 15-14 13 FIELD TYPE RESET DESCRIPTION Reserved R/W 00b Not used. 1 = invalid write. Min System Voltage, bit 5 R/W 0b 0 = Adds 0 mV of system voltage. 1 = Adds 8192 mV of system voltage. 12 Min System Voltage, bit 4 R/W 0b 0 = Adds 0 mV of system voltage. 1 = Adds 4096mV of system voltage. 11 Min System Voltage, bit 3 R/W 0b 10 Min System Voltage, bit 2 R/W 0b 9 Min System Voltage, bit 1 R/W 0b 8 Min System Voltage, bit 0 R/W 0b 0 = Adds 0 mV of system voltage. 1 = Adds 2048 mV of system voltage. 0 = Adds 0 mV of system voltage. 1 = Adds 1024 mV of system voltage. 0 = Adds 0 mV of system voltage. 1 = Adds 512 mV of system voltage. 0 = Adds 0 mV of system voltage. 1 = Adds 256 mV of system voltage. Table 30. MinSystemVoltage Register (SMBus address = 3Eh) Field Descriptions SMBus BIT 7-0 FIELD TYPE RESET DESCRIPTION Reserved R/W 0000000 0b Not used. Value Ignored. 8.6.5.1 System Voltage Regulation The device employs Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG0x3E(). Even with a deeply depleted battery, the system is regulated above the minimum system voltage with BATFET. When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is regulated above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on when charging or in supplement mode and the voltage difference between the system and battery is the VDS of BATFET. System voltage is regulated 160 mV above battery voltage when BATFET is off (no charging or no supplement current). When BATFET is removed, the system node VSYS is shorted to SRP. Before the converter starts operation, LDO mode needs to be disabled. The following sequence is required to configure charger without BATFET. 1. Before adapter plugs in, put the charger into HIZ mode. (either pull pin 6 ILIM_HIZ to ground, or set 52 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com 2. 3. 4. 5. 6. SLUSCQ8 – MAY 2017 REG0x32[15] to 1) Set 0x12[2] to 0 to disable LDO mode. Set 0x30[0] to 0 to disable auto-wakeup mode. Check if battery voltage is properly programmed (REG0x15) Set pre-charge/charge current (REG0x14) Put the device out of HIZ mode. (Release ILIM_HIZ from ground and set REG0x32[15]=0). In order to prevent any accidental SW mistakes, the host sets low input current limit (a few hundred milliamps) when device is out of HIZ. 8.6.6 Input Current and Input Voltage Registers for Dynamic Power Management The charger supports Dynamic Power Management (DPM). Normally, the input power source provides power for the system load or to charge the battery. When the input current exceeds the input current setting, or the input voltage falls below the input voltage setting, the charger decreases the charge current to provide priority to the system load. As the system current rises, the available charge current drops accordingly toward zero. If the system load keeps increasing after the charge current drops down to zero, the system voltage starts to drop. As the system voltage drops below the battery voltage, the battery will discharge to supply the heavy system load. 8.6.6.1 Input Current Registers To set the maximum input current limit, write a 16-bit IIN_HOST register command (REG0x3F()) using the data format listed in Table 31 and Table 32. When using a 10-mΩ sense resistor, the charger provides an inputcurrent limit range of 50 mA to 6400 mA, with 50-mA resolution. The default current limit is 3.3 A. Due to the USB current setting requirement, the register setting specifies the maximum current instead of the typical current. Upon adapter removal, the input current limit is reset to the default value of 3.3 A. The register offset is 50 mA. With code 0, the input current limit is 50 mA. The ACP and ACN pins are used to sense RAC with the default value of 10 mΩ. However, resistors of other values can also be used. For a larger sense resistor, a larger sense voltage is given and a higher regulation accuracy, but at the expense of higher conduction loss. Instead of using the internal DPM loop, the user can build up an external input current regulation loop and have the feedback signal on the ILIM_HIZ pin. VILIM _ HIZ = 1V + 40 ´ (VACP - VACN ) = 1 + 40 ´ IDPM ´ R AC (2) In order to disable ILIM_HIZ pin, the host can write to 0x31[7] to disable ILIM_HIZ pin, or pull ILIM_HIZ pin above 4.0 V. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 53 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.6.1.1 IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4000h] Figure 29. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) [reset = 4100h] 15 Reserved R/W 14 Input Current set by host, bit 6 R/W 13 Input Current set by host, bit 5 R/W 12 Input Current set by host, bit 4 R/W 11 Input Current set by host, bit 3 R/W 10 Input Current set by host, bit 2 R/W 9 Input Current set by host, bit 1 R/W 8 Input Current set by host, bit 0 R/W 7 6 5 4 3 2 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 15 Reserved R/W 0b Not used. 1 = invalid write. 14 Input Current set by host, bit 6 R/W 1b 0 = Adds 0 mA of input current. 1 = Adds 3200 mA of input current. 13 Input Current set by host, bit 5 R/W 0b 0 = Adds 0 mA of input current. 1 = Adds 1600 mA of input current. 12 Input Current set by host, bit 4 R/W 0b 11 Input Current set by host, bit 3 R/W 0b 10 Input Current set by host, bit 2 R/W 0b 9 Input Current set by host, bit 1 R/W 0b 8 Input Current set by host, bit 0 R/W 0b 0 = Adds 0 mA of input current. 1 = Adds 800 mA of input current. 0 = Adds 0 mA of input current. 1 = Adds 400 mA of input current. 0 = Adds 0 mA of input current. 1 = Adds 200 mA of input current. 0 = Adds 0 mA of input current. 1 = Adds 100 mA of input current. 0 = Adds 0 mA of input current. 1 = Adds 50 mA of input current. Table 32. IIN_HOST Register With 10-mΩ Sense Resistor (SMBus address = 3Fh) Field Descriptions SMBus BIT 7-0 54 FIELD TYPE RESET DESCRIPTION Reserved R 0000000 0b Not used. Value Ignored. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.6.1.2 IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h] IIN_DPM register reflects the actual input current limit programmed in the register, either from host or from ICO. After ICO, the current limit used by DPM regulation may differ from the IIN_HOST register settings. The actual DPM limit is reported in REG0x22(). The register offset is 50 mA. With code 0, the input current limit read-back is 50 mA. Figure 30. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) [reset = 0h] 15 Reserved R 14 13 12 11 10 9 8 Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in Input Current in DPM, bit 6 DPM, bit 5 DPM, bit 4 DPM, bit 3 DPM, bit 2 DPM, bit 1 DPM, bit 0 R R R R R R R 7 6 5 4 3 2 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 15 Reserved R 0b Not used. 1 = invalid write. 14 Input Current in DPM, bit 6 R 0b 0 = Adds 0 mA of input current. 13 Input Current in DPM, bit 5 R 0b 12 Input Current in DPM, bit 4 R 0b 1 = Adds 3200 mA of input current. 0 = Adds 0 mA of input current. 1 = Adds 1600 mA of input current. 0 = Adds 0 mA of input current. 1 = Adds 800mA of input current 11 Input Current in DPM, bit 3 R 0b 0 = Adds 0 mA of input current. 1 = Adds 400 mA of input current. 10 Input Current in DPM, bit 2 R 0b 0 = Adds 0 mA of input current. 1 = Adds 200 mA of input current. 9 Input Current in DPM, bit 1 R 0b 8 Input Current in DPM, bit 0 R 0b 0 = Adds 0 mA of input current. 1 = Adds 100 mA of input current. 0 = Adds 0 mA of input current. 1 = Adds 50 mA of input current. Table 34. IIN_DPM Register With 10-mΩ Sense Resistor (SMBus address = 022h) Field Descriptions SMBus BIT 7-0 FIELD TYPE RESET DESCRIPTION Reserved R 00000000b Not used. Value Ignored. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 55 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.6.1.3 InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V] To set the input voltage limit, write a 16-bit InputVoltage register command (REG0x3D()) using the data format listed in Table 35 and Table 36. If the input voltage drops more than the InputVoltage register allows, the device enters DPM and reduces the charge current. The default offset voltage is 1.28 V below the no-load VBUS voltage. The DC offset is 3.2 V (0000000). Figure 31. InputVoltage Register (SMBus address = 3Dh) [reset = VBUS-1.28V] 15 14 13 Input Voltage, bit 7 R/W 12 Input Voltage, bit 6 R/W 11 Input Voltage, bit 5 R/W 10 Input Voltage, bit 4 R/W 9 Input Voltage, bit 3 R/W 8 Input Voltage, bit 2 R/W 6 Input Voltage, bit 0 R/W 5 4 3 2 1 0 Reserved R/W 7 Input Voltage, bit 1 R/W Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 35. InputVoltage Register (SMBus address = 3Dh) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION Reserved R/W 00b Not used. 1 = invalid write. 13 Input Voltage, bit 7 R/W 0b 0 = Adds 0 mV of input voltage. 12 Input Voltage, bit 6 R/W 0b 11 Input Voltage, bit 5 R/W 0b 10 Input Voltage, bit 4 R/W 0b 9 Input Voltage, bit 3 R/W 0b 8 Input Voltage, bit 2 R/W 0b 15-14 1 = Adds 8192 mV of input voltage. 0 = Adds 0 mV of input voltage. 1 = Adds 4096mV of input voltage. 0 = Adds 0 mV of input voltage. 1 = Adds 2048 mV of input voltage. 0 = Adds 0 mV of input voltage. 1 = Adds 1024 mV of input voltage. 0 = Adds 0 mV of input voltage. 1 = Adds 512 mV of input voltage. 0 = Adds 0 mV of input voltage. 1 = Adds 256 mV of input voltage. Table 36. InputVoltage Register (SMBus address = 3Dh) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 7 Input Voltage, bit 1 R/W 0b 0 = Adds 0 mV of input voltage. 6 Input Voltage, bit 0 R/W 0b Reserved R/W 000000b 1 = Adds 128 mV of input voltage. 0 = Adds 0 mV of input voltage. 1 = Adds 64 mV of input voltage 5-0 56 Submit Documentation Feedback Not used. Value Ignored. Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.7 OTGVoltage Register (SMBus address = 3Bh) [reset = 0h] To set the OTG output voltage limit, write to REG0x3B() using the data format listed in Table 37 and Table 38. The DC offset is 4.48 V (0000000). Figure 32. OTGVoltage Register (SMBus address = 3Bh) [reset = 0h] 15 14 13 OTG Voltage, bit 7 R/W 12 OTG Voltage, bit 6 R/W 11 OTG Voltage, bit 5 R/W 10 OTG Voltage, bit 4 R/W 9 OTG Voltage, bit 3 R/W 8 OTG Voltage, bit 2 R/W 6 OTG Voltage, bit 0 R/W 5 4 3 2 1 0 Reserved R/W 7 OTG Voltage, bit 1 R/W Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 37. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION Reserved R/W 00b Not used. 1 = invalid write. 13 OTG Voltage, bit 7 R/W 0b 0 = Adds 0 mV of OTG voltage. 12 OTG Voltage, bit 6 R/W 0b 15-14 1 = Adds 8192 mV of OTG voltage. 0 = Adds 0 mV of OTG voltage. 1 = Adds 4096 mV of OTG voltage. 11 OTG Voltage, bit 5 R/W 0b 0 = Adds 0 mV of OTG voltage. 1 = Adds 2048 mV of OTG voltage. 10 OTG Voltage, bit 4 R/W 0b 0 = Adds 0 mV of OTG voltage. 1 = Adds 1024 mV of OTG voltage. 9 OTG Voltage, bit 3 R/W 0b 8 OTG Voltage, bit 2 R/W 0b 0 = Adds 0 mV of OTG voltage. 1 = Adds 512 mV of OTG voltage. 0 = Adds 0 mV of OTG voltage. 1 = Adds 256 mV of OTG voltage. Table 38. OTGVoltage Register (SMBus address = 3Bh) Field Descriptions SMBus BIT 7 FIELD TYPE RESET DESCRIPTION OTG Voltage, bit 1 R/W 0b 0 = Adds 0 mV of OTG voltage. 1 = Adds 128 mV of OTG voltage. 6 OTG Voltage, bit 0 R/W 0b 0 = Adds 0 mV of OTG voltage. 1 = Adds 64 mV of OTG voltage. 5-0 Reserved Copyright © 2017, Texas Instruments Incorporated R/W 000000b Not used. Value Ignored. Submit Documentation Feedback 57 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.8 OTGCurrent Register (SMBus address = 3Ch) [reset = 0h] To set the OTG output current limit, write to REG0x3C() using the data format listed in Table 39 and Table 40. Figure 33. OTGCurrent Register (SMBus address = 3Ch) [reset = 0h] 15 Reserved R/W 14 OTG Current set by host, bit 6 R/W 13 OTG Current set by host, bit 5 R/W 12 OTG Current set by host, bit 4 R/W 11 OTG Current set by host, bit 3 R/W 10 OTG Current set by host, bit 2 R/W 9 OTG Current set by host, bit 1 R/W 8 OTG Current set by host, bit 0 R/W 7 6 5 4 3 2 1 0 Reserved R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 39. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION 15 Reserved R/W 0b Not used. 1 = invalid write. 14 OTG Current set by host, bit 6 R/W 0b 0 = Adds 0 mA of OTG current. 1 = Adds 3200 mA of OTG current. 13 OTG Current set by host, bit 5 R/W 0b 0 = Adds 0 mA of OTG current. 1 = Adds 1600mA of OTG current. 12 OTG Current set by host, bit 4 R/W 0b 11 OTG Current set by host, bit 3 R/W 0b 10 OTG Current set by host, bit 2 R/W 0b 9 OTG Current set by host, bit 1 R/W 0b 8 OTG Current set by host, bit 0 R/W 0b 0 = Adds 0 mA of OTG current. 1 = Adds 800 mA of OTG current. 0 = Adds 0 mA of OTG current. 1 = Adds 400 mA of OTG current. 0 = Adds 0 mA of OTG current. 1 = Adds 200 mA of OTG current. 0 = Adds 0 mA of OTG current. 1 = Adds 100 mA of OTG current. 0 = Adds 0 mA of OTG current. 1 = Adds 50 mA of OTG current. Table 40. OTGCurrent Register (SMBus address = 3Ch) Field Descriptions SMBus BIT 7-0 58 FIELD TYPE RESET DESCRIPTION Reserved R/W 00000000 b Not used. Value Ignored. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.9 ADCVBUS/PSYS Register (SMBus address = 23h) • PSYS: Full range: 3.06 V, LSB: 12 mV • VBUS: Full range: 3200 mV to 19520 mV, LSB: 64 mV Figure 34. ADCVBUS/PSYS Register (SMBus address = 23h) 15 14 13 12 11 10 9 8 R R R R R R R R 7 6 5 4 3 2 1 0 R R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 41. ADCVBUS/PSYS Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 15-8 R 8-bit Digital Output of Input Voltage 7-0 R 8-bit Digital Output of System Power Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 59 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.10 ADCIBAT Register (SMBus address = 24h) • ICHG: Full range: 8.128 A, LSB 64: mA • IDCHG: Full range: 32.512 A, LSB: 256 mA Figure 35. ADCIBAT Register (SMBus address = 24h) 15 14 13 12 11 10 9 8 Reserved R R R R R R R 7 6 5 4 3 2 1 0 Reserved R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 42. ADCIBAT Register Field Descriptions BIT FIELD TYPE 15 Reserved R Not used. Value ignored. R 7-bit Digital Output of Battery Charge Current R Not used. Value ignored. R 7-bit Digital Output of Battery Discharge Current 14-8 7 Reserved 6-0 60 Submit Documentation Feedback RESET DESCRIPTION Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.11 ADCIINCMPIN Register (SMBus address = 25h) • IIN: Full range: 12.75 A, LSB: 50 mA • CMPIN: Full range: 3.06 V, LSB: 12 mV Figure 36. ADCIINCMPIN Register (SMBus address = 25h) 15 14 13 12 11 10 9 8 R R R R R R R R 7 6 5 4 3 2 1 0 R R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 43. ADCIINCMPIN Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 15-8 R 8-bit Digital Output of Input Current 7-0 R 8-bit Digital Output of CMPIN voltage Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 61 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 8.6.12 ADCVSYSVBAT Register (SMBus address = 26h) (reset = ) • VSYS: Full range: 2.88 V to 19.2 V, LSB: 64 mV • VBAT: Full range: 2.88 V to 19.2 V, LSB: 64 mV Figure 37. ADCVSYSVBAT Register (SMBus address = 26h) (reset = ) 15 14 13 12 11 10 9 8 R R R R R R R R 7 6 5 4 3 2 1 0 R R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 44. ADCVSYSVBAT Register Field Descriptions BIT 62 FIELD TYPE RESET DESCRIPTION 15-8 R 8-bit Digital Output of System Voltage 7-0 R 8-bit Digital Output of Battery Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 8.6.13 ID Registers 8.6.13.1 ManufactureID Register (SMBus address = FEh) [reset = 0040h] Figure 38. ManufactureID Register (SMBus address = FEh) [reset = 0040h] 15-0 MANUFACTURE_ID R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 45. ManufactureID Register Field Descriptions SMBus BIT 15-0 FIELD TYPE MANUFACTURE_ID R RESET DESCRIPTION (READ ONLY) 40h 8.6.13.2 Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h] Figure 39. Device ID (DeviceAddress) Register (SMBus address = FFh) [reset = 0h] 15-8 Reserved R 7-0 DEVICE_ID R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 46. Device ID (DeviceAddress) Register Field Descriptions SMBus BIT FIELD TYPE RESET DESCRIPTION (READ ONLY) 15-8 Reserved R 0b Reserved 7-0 DEVICE_ID R 0b SMBus: 79h Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 63 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The bq2570xEVM-732 evaluation module (EVM) is a complete charger module for evaluating the bq25700A. The application curves were taken using the bq2570xEVM-732. Refer to the EVM user's guide (SLUUBG6) for EVM information. 9.2 Typical Application VSYS 6x10PF 2.2uH RAC=10m: RSR=10m: ADAPTER : 6x10PF 10nF 1PF Optional snubber 10: Q1 Q2 Q3 47nF 10: BATT Q4 47nF 1: 15nF 15nF HIDRV2 SW1 BTST1 BTST2 SW2 HIDRV1 LODRV2 VBUS LODRV1 SYS 470nF BATDRV ACN SRP ACP 10: REGN SRN REGN VDDA ILIM_HIZ 1uF 2.2±3.3uF GND bq25700A VDDA 350k: CELL_BATPRESZ 250k: COMP1 COMP2 IADPT IBAT PSYS CHRG_OK 50: PROCHOT SDA SCL 1.05V 30k: 100pF 100pF 100k: CMPOUT EN_OTG CMPIN 10k: To CPU 10k: 3.3V or 1.8V 10k: 10k: Host (SMBus) Copyright © 2017, Texas Instruments Incorporated Figure 40. Application Diagram 9.2.1 Design Requirements DESIGN PARAMETER Input Voltage (1) Input Current Limit 3.5 V < Adapter Voltage < 24 V (1) Battery Charge Voltage (2) (1) (2) 64 EXAMPLE VALUE 3.2 A for 65 W adapter 8400 mV for 2s battery Refer to adapter specification for settings for Input Voltage and Input Current Limit. Refer to battery specification for settings. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Typical Application (continued) DESIGN PARAMETER EXAMPLE VALUE Battery Charge Current (2) 3072 mA for 2s battery Minimum System Voltage (2) 614 mV for 2s battery 9.2.2 Detailed Design Procedure The parameters are configurable using the evaluation software. The simplified application circuit (see Figure 40, as the application diagram) shows the minimum component requirements. Inductor, capacitor, and MOSFET selection are explained in the rest of this section. Refer to the EVM user's guide (SLUUBG6) for the complete application schematic. 9.2.2.1 Input Snubber and Filter for Voltage Spike Damping During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second order system. The voltage spike at VBUS pin maybe beyond IC maximum voltage rating and damage IC. The input filter must be carefully designed and tested to prevent over voltage event on VBUS pin. There are several methods to damp or limit the over voltage spike during adapter hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level. However these two solutions may not have low cost or small size. A cost effective and small size solution is shown in Figure 41. The R1 and C1 are composed of a damping RC network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used for reverse voltage protection for VBUS pin. C2 is VBUS pin decoupling capacitor and it should be placed as close as possible to VBUS pin. C2 value should be less than C1 value so R1 can dominate the equivalent ESR value to get enough damping effect. R2 is used to limit inrush current of D1 to prevent D1 getting damage when adapter hot plug-in. R2 and C2 should have 10 µs time constant to limit the dv/dt on VBUS pin to reduce inrush current when adapter hot plug in. R1 has high inrush current. R1 package must be sized enough to handle inrush current power loss according to resistor manufacturer’s data sheet. The filter components' value always need to be verified with real application and minor adjustments may need to fit in the real application circuit. D1 Adapter connector R1(2010) 2W C1 2.2mF R2(0805) 1W VBUS pin C2 0.47-1mF Figure 41. Input Filter 9.2.2.2 ACP-ACN Input Filter The bq25700A has average current mode control. The input current sensing through ACP/ACN is critical to recover inductor current ripple. Parasitic inductance on board will generate high frequency ringing on ACP-ACN which overwhelms converter sensed inductor current information, so it is difficult to manage parasitic inductance created based on different PCB layout. Bigger parasitic inductance will generate bigger sense current ringing which will cause the average current control loop to go into oscillation. For real system board condition, we suggest to use below circuit design to get best result and filter noise induced from different PCB parasitic factor. With time constant of filter from 47 nsec to 200 nsec, the filtering on ringing is effective and in the meantime, the delay of on the sensed signal is small and therefore poses no concern for average current mode control. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 65 bq25700A SLUSCQ8 – MAY 2017 www.ti.com RAC 4~6x10uF (0805) Q1 RACN 10ohm RACP 10ohm CDIFF Open CACP 15nF ACP 1nF+10nF (0402) CACN 15nF ACN HIDRV1 bq2570x Copyright © 2017, Texas Instruments Incorporated Figure 42. ACN-ACP Input Filter 9.2.2.3 Inductor Selection The bq25700A has two selectable fixed switching frequency. Higher switching frequency allows the use of smaller inductor and capacitor values. Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ³ ICHG + (1/2) IRIPPLE (3) The inductor ripple current in buck operation depends on input voltage (VIN), duty cycle (DBUCK = VOUT/VIN), switching frequency (fS) and inductance (L): V ´ D ´ (1 - D) IRIPPLE_BUCK = IN fS ´ L (4) During boost operation, the duty cycle is: DBOOST = 1 – (VIN/VBAT) and the ripple current is: IRIPPLE_BOOST = (VIN × DBOOST) / (fS × L) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging voltage range is from 9 V to 12.6 V for 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives the maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12 V to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current. Usually inductor ripple is designed in the range of (20 – 40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. 9.2.2.4 Input Capacitor Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5 in buck mode. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current occurs where the duty cycle is closest to 50% and can be estimated by Equation 5: ICIN = ICHG ´ 66 D × (1 - D) Submit Documentation Feedback (5) Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred for 19 V - 20 V input voltage. Minimum 4 - 6 pcs of 10-µF 0805 size capacitor is suggested for 45 - 65 W adapter design. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. See the manufacturer's datasheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. 9.2.2.5 Output Capacitor Output capacitor also should have enough ripple current rating to absorb output switching ripple current. In buck mode the output capacitor RMS current is given: To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 kHz and 20 kHz. The preferred ceramic capacitor is 25-V X7R or X5R for output capacitor. Minimum 6 pcs of 10-µF 0805 size capacitor is suggested to be placed by the inductor. Place the capacitors after Q4 drain. Place minimum 10 µF after the charge current sense resistor for best stability. Ceramic capacitors show a dc-bias effect. This effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a dc bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. 9.2.2.6 Power MOSFETs Selection Four external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6 V of gate drive voltage. 30 V or higher voltage rating MOSFETs are preferred for 19 V - 20 V input voltage. Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For the top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, RDS(ON), and the gate-to-drain charge, QGD. For the bottom side MOSFET, FOM is defined as the product of the MOSFET's on-resistance, RDS(ON), and the total gate charge, QG. FOMtop = RDS(on) x QGD; FOMbottom = RDS(on) x QG (6) The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same package size. The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance (RDS(ON)), input voltage (VIN), switching frequency (fS), turn on time (ton) and turn off time (toff): 1 Ptop = D ´ ICHG2 ´ RDS(on) + ´ VIN ´ ICHG ´ (t on + t off ) ´ f s 2 (7) The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100°C junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn-off times are given by: Q Q t on = SW , t off = SW Ion Ioff (8) where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS): 1 QSW = QGD + ´ QGS 2 (9) Gate driving current can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total turn-on gate resistance (Ron) and turn-off gate resistance (Roff) of the gate driver: Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 67 bq25700A SLUSCQ8 – MAY 2017 Ion = www.ti.com VREGN - Vplt Ron , Ioff = Vplt Roff (10) The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode: Pbottom = (1 - D) x ICHG 2 x RDS(on) (11) When charger operates in non-synchronous mode, the bottom-side MOSFET is off. As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The body diode power loss depends on its forward voltage drop (VF), non-synchronous mode charging current (INONSYNC), and duty cycle (D). PD = VF x INONSYNC x (1 - D) (12) The maximum charging current in non-synchronous mode can be up to 0.25 A for a 10-mΩ charging current sensing resistor or 0.5 A if battery voltage is below 2.5 V. The minimum duty cycle happens at lowest battery voltage. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current. 9.2.3 Application Curves CH1: VBUS CH1: VBUS CH2: VDDA CH2: VDDA CH3: CHRG_OK CH3: CHRG_OK CH4: VSYS CH4: VSYS 2-cell without battery 2-cell without battery Figure 43. Power Up from 20 V Figure 44. Power Up from 5 V CH1: VBUS CH1: VBUS CH2: SW1 CH2: SW1 CH3: SW2 CH3: SW2 CH4: VSYS with 9Vos CH4: IL 3-cell VBAT = 10 V Figure 45. Power Off from 12 V 68 Submit Documentation Feedback VBUS 5 V to 20 V Figure 46. System Regulation Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 CH2: SW1 CH1: HIDRV1 CH2: SW1 CH3: LODRV1 CH3: SW2 CH1: IL CH4: IL VBUS = 20 V, VSYS = 10 V, ISYS = 200 mA Figure 47. PFM Operation Figure 48. PWM Operation CH2: SW2 CH2: SW1 CH1: HIDRV2 CH3: SW2 CH3: LODRV2 CH4: IL CH4: IL VBUS = 5 V, VBAT = 10 V Figure 49. Switching During Boost Mode CH1: VSYS VBUS = 12 V, VBAT = 12 V Figure 50. Switching During Buck Boost Mode CH1: VSYS CH2: IIN CH2: IIN CH3: ISYS VBUS = 12 V/3.3 A, 3-cell, VSYS = 9 V, Without battery Figure 51. System Regulation in Buck Mode Copyright © 2017, Texas Instruments Incorporated CH3: ISYS VBUS = 9 V/3.3 A, 3-cell, VSYS = 9 V, Without battery Figure 52. System Regulation in Buck Boost Mode Submit Documentation Feedback 69 bq25700A SLUSCQ8 – MAY 2017 www.ti.com CH1: VSYS CH2: IIN CH2: IIN CH3: ISYS CH4: IBAT CH3: ISYS VBUS = 5 V/3.3 A, 3-cell, VSYS = 9 V, Without battery Figure 53. System Regulation in Boost Mode CH2:IIN VBUS = 20 V/3.3 V, VBAT = 7.5 V Figure 54. Input Current Regulation in Buck Mode CH1: EN_OTG CH2: VBUS CH3:ISYS CH4:IBAT VBUS = 5 V/3.3 V, VBAT = 7.5 V Figure 55. Input Current in Boost Mode VBUS = 5 V Figure 56. OTG Power Up from 8 V Battery CH1: SCL CH1: SCL CH2: VBUS CH2: VBUS CH3: SW2 CH3: SW2 VBAT = 10 V, VBUS 5 V to 20 V, IOTG = 500 mA Figure 57. OTG Voltage Ramp Up 70 Submit Documentation Feedback Figure 58. OTG Power Off Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 CH2: VBUS CH3: IVBUS VBAT = 10 V, VBUS = 20 V Figure 59. OTG Load Transient Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 71 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 10 Power Supply Recommendations The valid adapter range is from 3.5 V (VVBUS_CONVEN) to 24 V (ACOV) with at least 500-mA current rating. When CHRG_OK goes HIGH, the system is powered from adapter through the charger. When adapter is removed, the system is connected to battery through BATFET. Typically the battery depletion threshold should be greater than the minimum system voltage so that the battery capacity can be fully utilized for maximum battery life. 72 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 11 Layout 11.1 Layout Guidelines The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Layout Example section) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. 1. Place the input capacitor as close as possible to the supply of the switching MOSFET and ground connections. Use a short copper trace connection. These parts must be placed on the same layer of PCB using vias to make this connection. 2. The device must be placed close to the gate pins of the switching MOSFET. Keep the gate drive signal traces short for a clean MOSFET drive. The device can be placed on the other side of the PCB of switching MOSFETs. 3. Place an inductor input pin as close as possible to the output pin of the switching MOSFET. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the device in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 61 for Kelvin connection for best current accuracy). Place a decoupling capacitor on these traces next to the device. 5. Place an output capacitor next to the sensing resistor output and ground. 6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. Use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath the device, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. 8. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0-Ω resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible). 9. Decoupling capacitors must be placed next to the device pins. Make trace connection as short as possible. 10. It is critical that the exposed power pad on the backside of the device package be soldered to the PCB ground. 11. The via size and number should be enough for a given current path. See the EVM design (SLUUBG6) for the recommended component placement with trace and via locations. For WQFN information, see SLUA271. 11.2 Layout Example 11.2.1 Layout Consideration of Current Path PHASE VIN C1 High Frequency Current Path L1 R1 VBAT BAT GND C2 Figure 60. High Frequency Current Path Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 73 bq25700A SLUSCQ8 – MAY 2017 www.ti.com Layout Example (continued) 11.2.2 Layout Consideration of Short Circuit Protection Charge Current Direction R SNS To Inductor To Capacitor and battery Current Sensing Direction To SRP and SRN pin Figure 61. Sensing Resistor PCB Layout 74 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated bq25700A www.ti.com SLUSCQ8 – MAY 2017 12 Device and Documentation Support 12.1 Device Support 12.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: • Semiconductor and IC Package Thermal Metrics Application Report SPRA953 • bq2570x Evaluation Module User's Guide SLUUBG6 • QFN/SON PCB Attachment Application Report SLUA271 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 75 bq25700A SLUSCQ8 – MAY 2017 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 76 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 24-May-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) BQ25700ARSNR ACTIVE QFN RSN 32 3000 TBD Call TI Call TI -40 to 85 BQ 25700A BQ25700ARSNT ACTIVE QFN RSN 32 250 TBD Call TI Call TI -40 to 85 BQ 25700A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-May-2017 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ25700ARSNR QFN RSN 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ25700ARSNT QFN RSN 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ25700ARSNR QFN RSN 32 3000 367.0 367.0 35.0 BQ25700ARSNT QFN RSN 32 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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