AD AD8557ARZ Digitally programmable sensor signal amplifier Datasheet

Digitally Programmable
Sensor Signal Amplifier
AD8557
FEATURES
APPLICATIONS
Automotive sensors
Pressure and position sensors
Precision current sensing
Thermocouple amplifiers
Industrial weigh scales
Strain gages
FUNCTIONAL BLOCK DIAGRAM
VDD
VCLAMP
VDD
A4
VNEG
A1
R4
P3
R6
VSS
R1
VSS
VDD
P1
A3
R3
VOUT
VDD
A2
VPOS
P2
VSS
R2
R5
VDD
R7
P4
VSS
DIGIN
06013-001
Very low offset voltage: 12 μV maximum over temperature
Very low input offset voltage drift: 65 nV/°C maximum
High CMRR: 96 dB minimum
Digitally programmable gain and output offset voltage
Gain range from 28 to 1300
Qualified for automotive applications
Single-wire serial interface
Stable with any capacitive load
SOIC_N and LFCSP_VQ packages
2.7 V to 5.5 V operation
VSS
Figure 1.
GENERAL DESCRIPTION
The AD8557 is a zero drift, sensor signal amplifier with digitally
programmable gain and output offset. Designed to easily and
accurately convert variable pressure sensor and strain bridge
outputs to a well-defined output voltage range, the AD8557
accurately amplifies many other differential or single-ended
sensor outputs. The AD8557 uses the Analog Devices, Inc.
patented low noise auto-zero and DigiTrim® technologies to
create an accurate and flexible signal processing solution in a
compact footprint.
Gain is digitally programmable in a wide range from 28 to 1300
through a serial data interface. Gain adjustment can be fully
simulated in circuit and then permanently programmed with
reliable polyfuse technology. Output offset voltage is also
digitally programmable and is ratiometric to the supply voltage.
also includes a pull-up current source at the input pins and a
pull-down current source at the VCLAMP pin. Output
clamping set via an external reference voltage allows the
AD8557 to drive lower voltage ADCs safely and accurately.
When used in conjunction with an ADC referenced to the same
supply, the system accuracy becomes immune to normal supply
voltage variations. Output offset voltage can be adjusted with a
resolution of better than 0.4% of the difference between VDD
and VSS. A lockout trim after gain and offset adjustment
further ensures field reliability.
The AD8557 is fully specified from −40°C to +125°C.
Operating from single-supply voltages of 2.7 V to 5.5 V, the
AD8557 is offered in an 8-lead SOIC_N, and a 4 mm × 4 mm,
16-lead LFCSP_VQ.
In addition to extremely low input offset voltage and input
offset voltage drift and very high dc and ac CMRR, the AD8557
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.
AD8557
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 14
Applications ....................................................................................... 1
Gain Values ................................................................................. 15
Functional Block Diagram .............................................................. 1
Open Wire Fault Detection ....................................................... 16
General Description ......................................................................... 1
Shorted Wire Fault Detection ................................................... 16
Revision History ............................................................................... 2
Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 16
Specifications..................................................................................... 3
Device Programming ................................................................. 16
Absolute Maximum Ratings ............................................................ 5
Outline Dimensions ....................................................................... 21
Thermal Resistance ...................................................................... 5
Ordering Guide .......................................................................... 22
ESD Caution .................................................................................. 5
Automotive Products ................................................................. 22
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
6/11—Rev. B to Rev. C
Added EPAD Note to Figure 3 and Table 5................................... 6
Changes to Open Wire Fault Detection Section and Table 8 ... 16
7/10—Rev. A to Rev. B
Changes to Features Section and Figure 1..................................... 1
Changes to Figure 45 ...................................................................... 14
Changes to Simulation Mode Section and Programming
Mode Section................................................................................... 18
Changes to Ordering Guide .......................................................... 22
Added Automotive Products Section........................................... 22
1/08—Rev. 0 to Rev. A
Changes to Theory of Operation Section .................................... 14
Changes to Determining Optimal Gain and Offset
Codes Section .................................................................................. 20
5/07—Revision 0: Initial Version
Rev. C | Page 2 of 24
AD8557
SPECIFICATIONS
VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VOUT = 2.5 V, gain = 28, TA = −40°C to +125°C, unless otherwise specified.
Table 1.
Parameter
INPUT STAGE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Symbol
VOS
TCVOS
IB
IOS
CMRR
Linearity
Differential Gain Accuracy
Differential Gain Accuracy
Differential Gain Temperature Coefficient
DAC
Accuracy
Ratiometricity
Output Offset
Temperature Coefficient
VCLAMP
Clamp Input Bias Current
Clamp Input Voltage Range
OUTPUT STAGE
Short-Circuit Current
Output Voltage, Low
Output Voltage, High
POWER SUPPLY
Supply Current
Min
10
VCM = 0.9 V to 3.6 V, AV = 28
VCM = 0.9 V to 3.6 V, AV = 1300
VOUT = 0.2 V to 3.4 V
VOUT = 0.2 V to 4.8 V
Second stage gain = 10 to 70
Second stage gain = 100 to 250
Second stage gain = 10 to 250
0.6
75
96
ICLAMP
Typ
Max
Unit
2
27
18
1
12
65
25
4
3.8
μV
nV/°C
nA
nA
V
dB
dB
ppm
ppm
%
%
ppm/°C
85
112
20
1000
15
Offset codes = 8 to 248
Offset codes = 8 to 248
Offset codes = 8 to 248
0.7
50
5
20
1.25 V to 5.0 V
ISC
ISC
VOL
VOH
Source
Sink
RL = 10 kΩ to 5 V
RL = 10 kΩ to 0 V
ISY
VPOS = VNEG = 2.5 V,
VDAC code = 128, VOUT = 2.5 V
VDD = 2.7 V to 5.5 V
PSRR
Settling Time
NOISE PERFORMANCE
Input Referred Noise
Low Frequency Noise
Total Harmonic Distortion
ts
GBP
en p-p
THD
1.6
2.5
40
0.8
35
80
%
ppm
mV
ppm FS/°C
5.0
nA
V
200
1.25
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Gain Bandwidth Product
DIGITAL INTERFACE
Input Current
DIGIN Pulse Width to Load 0
DIGIN Pulse Width to Load 1
Time Between Pulses at DIGIN
DIGIN Low
DIGIN High
DIGOUT Logic 0
DIGOUT Logic 1
Conditions
40
−45
55
−25
30
4.94
1.8
mA
125
dB
First gain stage, TA = 25°C
Second gain stage, TA = 25°C
To 0.1%, 4 V output step
2
8
8
MHz
MHz
µs
f = 1 kHz, TA = 25°C
f = 0.1 Hz to 10 Hz, TA = 25°C
VIN = 16.75 mV rms, f = 1 kHz,
TA = 25°C
32
0.5
−100
nV/√Hz
µV p-p
dB
105
2
tw0
tw1
tws
mA
mA
mV
V
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
Rev. C | Page 3 of 24
0.05
50
10
10
0.2 × VDD
0.8 × VDD
0.2 × VDD
0.8 × VDD
µA
µs
µs
µs
V
V
V
V
AD8557
VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VOUT = 1.35 V, gain = 28, TA = −40°C to +125°C, unless otherwise specified.
Table 2.
Parameter
INPUT STAGE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Symbol
VOS
TCVOS
IB
IOS
CMRR
Linearity
Differential Gain Accuracy
Differential Gain Temperature Coefficient
DAC
Accuracy
Ratiometricity
Output Offset
Temperature Coefficient
VCLAMP
Input Bias Current
Input Voltage Range
OUTPUT STAGE
Short-Circuit Current
ICLAMP
10
VCM = 0.9 V to 1.5 V, AV = 28
VCM = 0.9 V to 1.5 V, AV = 1300
VOUT = 0.2 V to 1.8 V
VOUT = 0.2 V to 2.5 V
Second stage gain = 10 to 250
Second stage gain = 10 to 250
0.6
71
96
Typ
Max
Unit
2
12
65
25
4
1.5
µV
nV/°C
nA
nA
V
dB
dB
ppm
ppm
%
ppm/°C
18
1
82
112
20
1000
15
0.7
50
5
20
1.25 V to 2.7 V
ISC
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Gain Bandwidth Product
PSRR
ISY
GBP
ts
en p-p
THD
tw0
tw1
tws
Source
Sink
RL = 10 kΩ to 2.7 V
RL = 10 kΩ to 0 V
VPOS = VNEG = 1.35 V,
VDAC code = 128, VOUT = 1.35 V
VDD = 2.7 V to 5.5 V
1.6
40
0.8
35
80
%
ppm
mV
ppm FS/°C
2.7
nA
V
200
1.25
VOL
VOH
NOISE PERFORMANCE
Input Referred Noise
Low Frequency Noise
Total Harmonic Distortion
DIGITAL INTERFACE
Input Current
DIGIN Pulse Width to Load 0
DIGIN Pulse Width to Load 1
Time Between Pulses at DIGIN
DIGIN Low
DIGIN High
DIGOUT Logic 0
DIGOUT Logic 1
Min
Offset codes = 8 to 248
Offset codes = 8 to 248
Offset codes = 8 to 248
Output Voltage, Low
Output Voltage, High
POWER SUPPLY
Supply Current
Settling Time
Conditions
15
−12
25
−7
30
2.64
mA
mA
mV
V
1.8
mA
125
dB
First gain stage, TA = 25°C
Second gain stage, TA = 25°C
To 0.1%, 2 V output step,
TA = 25°C
2
8
8
MHz
MHz
µs
f = 1 kHz
f = 0.1 Hz to 10 Hz
VIN = 16.75 mV rms, f = 1 kHz
32
0.5
−100
nV/√Hz
µV p-p
dB
2
µA
µs
µs
µs
V
V
V
V
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
Rev. C | Page 4 of 24
105
0.05
50
10
10
0.2 × VDD
0.8 × VDD
0.2 × VDD
0.8 × VDD
AD8557
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage1
Output Short-Circuit Duration to
VSS or VDD
ESD (Human Body Model)
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature
1
Rating
6V
VSS − 0.3 V to VDD + 0.3 V
±6.0 V
Indefinite
2000 V
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for LFCSP_VQ packages.
Table 4. Thermal Resistance
Package Type
8-Lead SOIC_N (R)
16-Lead LFCSP_VQ (CP)
ESD CAUTION
Differential input voltage is limited to ±5.0 V or ± the supply voltage,
whichever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 5 of 24
θJA
158
44
θJC
43
31.5
Unit
°C/W
°C/W
AD8557
8
VSS
7
VOUT
TOP VIEW
6 VCLAMP
(Not to Scale)
5 VPOS
VNEG 4
DIGIN 3
13 DVSS
12 VOUT
11
NC
10 VCLAMP
9
NC
VPOS 8
TOP VIEW
(Not to Scale)
NC 5
AD8557
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO AVSS (PIN 14) OR LEFT UNCONNECTED.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
06013-002
VDD 1
DIGOUT 2
14 AVSS
AD8557
VNEG 6
NC 7
DIGIN 4
PIN 1
INDICATOR
Figure 2. 8-Lead SOIC_N Pin Configuration
06013-003
NC 1
DIGOUT 2
NC 3
15 DVDD
16 AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 16-Lead LFCSP_VQ Pin Configuration
Table 5. Pin Function Descriptions
SOIC_N
1
2
3
4
5
6
7
8
Pin No.
LFCSP_VQ
2
4
6
8
10
12
13, 14
15, 16
1, 3, 5, 7, 9, 11
EPAD
Mnemonic
VDD
DIGOUT
DIGIN
VNEG
VPOS
VCLAMP
VOUT
VSS
DVSS, AVSS
DVDD, AVDD
NC
EPAD
Description
Positive Supply Voltage.
In read mode, this pin functions as a digital output.
Digital Input.
Negative Amplifier Input (Inverting Input).
Positive Amplifier Input (Noninverting Input).
Set Clamp Voltage at Output.
Amplifier Output.
Negative Supply Voltage.
Negative Supply Voltage.
Positive Supply Voltage.
Do Not Connect.
Exposed Pad. The exposed pad should be connected to AVSS (Pin 14) or left unconnected.
Rev. C | Page 6 of 24
AD8557
TYPICAL PERFORMANCE CHARACTERISTICS
20
180
VSY = 5V
160
140
10
NUMBER OF AMPLIFIERS
+125°C
5
+25°C
0
–5
–40°C
–10
–15
120
100
80
60
40
20
0
1
2
3
4
5
COMMON-MODE VOLTAGE (V)
0
06013-004
–20
–10
–8
–6
–4
–2
0
2
4
6
8
06013-007
INPUT OFFSET VOLTAGE (µV)
15
10
INPUT OFFSET VOLTAGE (µV)
Figure 7. Input Offset Voltage Distribution, VSY = 2.7 V
Figure 4. Input Offset Voltage vs. Common-Mode Voltage, VSY = 5 V
15
10
VSY = 2.7V
10
6
4
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
8
+125°C
2
0
+25°C
–2
–4
–40°C
–6
5
5V
0
–5
2.7V
–10
0
1.0
0.5
1.5
2.0
2.5
COMMON-MODE VOLTAGE (V)
–15
–50
06013-005
–10
–25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
Figure 5. Input Offset Voltage vs. Common-Mode Voltage, VSY = 2.7 V
06013-008
–8
Figure 8. Input Offset Voltage vs. Temperature
180
30
160
25
NUMBER OF AMPLIFIERS
120
100
80
60
40
20
15
10
5
0
–10
–8
–6
–4
–2
0
2
4
6
8
INPUT OFFSET VOLTAGE (µV )
10
0
0
5
10
15
20
25
30
35
40
45
50
55
60
TCVOS (nV/°C)
Figure 9. TCVOS at VSY = 5 V, −40°C ≤TA ≤ +125°C
Figure 6. Input Offset Voltage Distribution, VSY = 5 V
Rev. C | Page 7 of 24
65
06013-009
20
06013-006
NUMBER OF AMPLIFIERS
140
AD8557
0.5
35
30
25
0.1
20
IOS (nA)
NUMBER OF AMPLIFIERS
0.3
15
–0.1
10
–0.3
0
5
10
15
20
25
30
35
40
45
50
55
60
–0.5
–50
06013-010
0
65
TCVOS (nV/°C)
–25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
Figure 10. TCVOS at VSY = 2.7 V, −40°C ≤ TA ≤ +125°C
06013-012
5
Figure 13. Input Offset Current vs. Temperature
3.0
20
–40°C
DIGITAL INPUT CURRENT (µA)
INPUT BIAS CURRENT (nA)
2.5
18
–IB 5V
16
+IB 5V
14
+125°C
2.0
+25°C
1.5
1.0
0.5
0
25
50
75
100
125
150
175
0
1
2
3
4
5
DIGITAL INPUT VOLTAGE (V)
Figure 11. Input Bias Current at VPOS, VNEG vs. Temperature,
VSY = 5 V, 2.7 V
Figure 14. Digital Input Current vs. Digital Input Voltage (Pin 4)
100
1000
+125°C
VCLAMP CURRENT (nA)
+25°C
10
1
100
–40°C
0
1
2
3
4
COMMON-MODE VOLTAGE (V)
5
10
0
1
2
3
4
VCLAMP VOLTAGE (V)
Figure 15. VCLAMP Current over Temperature at VSY = 5 V
vs. VCLAMP Voltage
Figure 12. Input Bias Current at VPOS, VNEG
vs. Common-Mode Voltage, TA = 25°C
Rev. C | Page 8 of 24
5
06013-015
VSY = 5V
0.1
06013-013
INPUT BIAS CURRENT (nA)
TEMPERATURE (°C)
0
06013-011
–25
06013-014
VSY = 5V
12
–50
AD8557
1000
120
+25°C
80
CMRR (dB)
VCLAMP CURRENT (nA)
100
+125°C
100
–40°C
HIGH GAIN +1300
60
LOW GAIN +28
40
VSY = 2.7V
0.5
0
1.0
1.5
2.0
2.5
3.0
VCLAMP VOLTAGE (V)
0
0.1
06013-016
10
1
10
1000
100
FREQUENCY (kHz)
Figure 16. VCLAMP Current over Temperature at VSY = 2.7 V
vs. VCLAMP Voltage
06013-019
20
Figure 19. CMRR vs. Frequency, VSY = 5 V
120
2.0
100
1.5
HIGH GAIN +1300
CMRR (dB)
ISY (mA)
80
1.0
60
LOW GAIN +28
40
0.5
1
2
3
5
4
6
VSY (V)
0
0.1
06013-017
0
1
100
1000
175
FREQUENCY (kHz)
Figure 20. CMRR vs. Frequency, VSY = 2.7 V
Figure 17. Supply Current (ISY) vs. Supply Voltage
150
3.0
130
2.5
CMRR GAIN +28
110
2.0
CMRR GAIN +448
1.5
CMRR (dB)
ISY 5V
ISY 2.7V
90
CMRR GAIN +1300
70
1.0
50
0.5
0
–50
30
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
175
10
–50
06013-018
ISY (mA)
10
06013-020
0
06013-021
20
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 21. CMRR vs. Temperature at Different Gains, VSY = 5 V
Figure 18. Supply Current (ISY) vs. Temperature
Rev. C | Page 9 of 24
AD8557
140
CMRR GAIN +448
100
CMRR (dB)
CMRR GAIN +1300
80
60
40
0
–50
–25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
RANGE 12.5mV
CH1 10.0mV
M 1.00s
A CH1
–2.80mV
Figure 25. Low Frequency Input Voltage Noise 0.1 Hz to 10 Hz, VSY = 2.7 V
Figure 22. CMRR vs. Temperature at Different Gains, VSY = 2.7 V
REF 502µV
5dB/DIV
1
06013-022
20
CHANNEL 1
16.6mV p-p
06013-025
VOLTAGE NOISE, GAIN = 28 × 1000
CMRR GAIN +28
120
MARKER 20 000.0Hz
1.89µV/√Hz
70
VSY = 5V
60
HIGH GAIN +1300 62.28dB
50
GAIN (dB)
40
30
LOW GAIN +28 28.9dB
20
10
0
START .0 Hz
RBW 100Hz
VBW 300Hz
STOP 1 000 000.0Hz
ST 900s
1
06013-023
–20
0.1
10
100
1k
10k
FREQUENCY (kHz)
Figure 23. Input Voltage Noise Density vs. Frequency (0 Hz to 1000 kHz)
06013-026
–10
Figure 26. Closed-Loop Gain vs. Frequency Measured at Output Pin, VSY = 5 V
70
VSY = 2.7V
HIGH GAIN +1300 62.28dB
50
CHANNEL 1
15.2mV p-p
40
GAIN (dB)
VOLTAGE NOISE, GAIN = 28 × 1000
60
1
30
LOW GAIN +28 28.9dB
20
10
0
M 1.00s
A CH1
–2.80mV
–20
0.1
1
10
100
FREQUENCY (kHz)
Figure 24. Low Frequency Input Voltage Noise, 0.1 Hz to 10 Hz, VSY = 5 V
1k
10k
06013-027
CH1 10.0mV
06013-024
–10
Figure 27. Closed-Loop Gain vs. Frequency Measured at Output Pin, VSY = 2.7 V
Rev. C | Page 10 of 24
AD8557
10
VSY = 5V
OUTPUT VOLTAGE (V)
1
SOURCE
SINK
0.1
1
0.01
0.1
1
10
100
LOAD CURRENT (mA)
CH2 1.0V
CH1 2.0V
M 100µs
A CH1
800mV
T 23.80%
06013-042
0.001
0.01
06013-028
2
Figure 31. Power-On Response at 125°C
Figure 28. Output Voltage to Supply Rail vs. Load Current
100
ILIMSINK 5V
50
ISC (mA)
ILIMSINK 2.7V
0
1
ILIMSRC 2.7V
ILIMSRC 5V
–50
–25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
CH1 2.0V
CH2 1.0V
M 100µs
A CH1
800mV
T 23.80%
06013-043
–100
–50
06013-029
2
Figure 32. Power-On Response at −40°C
Figure 29. Output Short-Circuit vs. Temperature
175
PSRR 2.7V TO 5.5V
PSRR (dB)
160
1
145
130
115
CH2 1.0V
M 100µs
A CH1
T 23.80%
800mV
100
–50
06013-041
CH1 2.0V
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 33. PSRR vs. Temperature
Figure 30. Power-On Response at 25°C
Rev. C | Page 11 of 24
150
175
06013-030
2
AD8557
140
120
PSRR (dB)
100
GAIN = +1300
80
2
60
GAIN = +28
40
0.1
0.1
1
100
10
FREQUENCY (kHz)
CH2 1.0V
M 10.0µs
A CH2
0V
T 23.20%
06013-044
0
0.01
06013-031
20
Figure 37. Large Signal Response, CL = 0 pF
Figure 34. PSRR vs. Frequency
CHANNEL 3
+OVER
5.967%
CHANNEL 3
–OVER
6.878%
M 10.0µs
A CH3
12.0mV
T 24.20%
06013-032
CH3 50.0mV
CH2 1.0V
M 10.0µs
A CH2
T 23.20%
0V
06013-045
2
3
Figure 38. Large Signal Response, CL = 5 nF
Figure 35. Small Signal Response, VSY = 5 V, CL = 100 pF
60
CHANNEL 3
+OVER
98.13%
50
CHANNEL 3
–OVER
54.94%
VSY = 5V
GAIN = +28
40
ZOUT (dB)
30
3
20
10
0
M 10.0µs
A CH2
480µV
T 24.20%
–20
0.1
06013-033
CH3 50.0mV
1
10
100
FREQUENCY (kHz)
Figure 36. Small Signal Response, VSY = 5 V, CL = 15 nF
Figure 39. Output Impedance vs. Frequency
Rev. C | Page 12 of 24
1000
06013-034
–10
AD8557
VSY = ±2.5V
GAIN = +1300
TA = 25°C
VSY = ±2.5V
GAIN = +28
TA = 25°C
1
1
CH2 2.00V
M 1.00µs
A CH1
57.0mV
06013-035
CH1 50.0mV
CH1 50.0mV
CH2 2.00V
M 1.00µs
A CH1
–21.0mV
T 4.00µs
06013-038
2
2
Figure 43. Positive Overload Recovery (Gain = 1300)
Figure 40. Positive Overload Recovery
10
5
1
2
VSY = ±2.5V
GAIN = +28
TA = 25°C
THD + N (%)
1
0.5
0.2
0.1
2
0.05
CH2 2.00V
M 10.0µs
A CH1
–5.80mV
0.01
20
50
100
200
500
1k
2k
FREQUENCY (Hz)
Figure 41. Negative Overload Recovery
Figure 44. THD + N vs. Frequency
VSY = ±2.5V
GAIN = +1300
TA = 25°C
1
CH1 10.0mV
CH2 2.00V
M 10.0µs
A CH1
10.8mV
T 10.00%
06013-037
2
Figure 42. Negative Overload Recovery (Gain = 1300)
Rev. C | Page 13 of 24
5k
10k
20k
06013-046
CH1 10.0mV
06013-036
0.02
AD8557
THEORY OF OPERATION
 Code 


127 
 5.2  
GAIN1 ≈ 2.8 × 

 2.8 
(1)
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the
differential amplifier. A3 is an auto-zeroed op amp that minimizes input offset errors and also includes an output buffer. P3
and P4 are digital potentiometers, which allow the second stage
gain to be varied from 10 to 250 in eight steps (see Table 7). R4,
R5, R6, R7, P3, and P4 each have a similar temperature coefficient,
so the second stage gain temperature coefficient is lower than
100 ppm/°C. The output stage of A3 is supplied from a buffered
version of VCLAMP instead of VDD, allowing the positive
swing to be limited.
to be monotonic. To preserve the ratiometric nature of the input
signal, the DAC references are driven from VSS and VDD, and
the DAC output can swing from VSS (Code 0) to VDD (Code
255). The 8-bit resolution is equivalent to 0.39% of the difference
between VDD and VSS, for example, 19.5 mV with a 5 V supply.
The DAC output voltage (VDAC) is given approximately by
 Code + 0.5 
VDAC ≈ 
(VDD − VSS ) + VSS
 256

(2)
where the temperature coefficient of VDAC is lower than
200 ppm/°C.
The amplifier output voltage (VOUT) is given by
VOUT = GAIN (VPOS − VNEG ) + VDAC
(3)
where GAIN is the product of the first and second stage gains.
A4 implements a voltage buffer, which provides the positive
supply to the output stage of A3. Its function is to limit VOUT
to a maximum value, useful for driving analog-to-digital
converters (ADC) operating on supply voltages lower than
VDD. The input to A4, VCLAMP, has a very high input
resistance. It should be connected to a known voltage and not
be left floating. However, the high input impedance allows the
clamp voltage to be set using a high impedance source, such as a
potential divider. If the maximum value of VOUT does not
need to be limited, VCLAMP should be connected to VDD.
An 8-bit digital-to-analog converter (DAC) is used to generate a
variable offset for the amplifier output. This DAC is guaranteed
Rev. C | Page 14 of 24
VDD
VCLAMP
VDD
A4
VNEG
A1
R4
P3
R6
VSS
R1
VSS
VDD
P1
A3
R3
VOUT
VDD
A2
VPOS
P2
VSS
R2
R5
VDD
R7
P4
VSS
DIGIN
VSS
Figure 45. Functional Schematic
06013-047
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiometers, guaranteed to be monotonic. Programming P1 and P2
allows the first stage gain to be varied from 2.8 to 5.2 with 7-bit
resolution (see Table 6 and Equation 1), giving a fine gain
adjustment resolution of 0.49%. Because R1, R2, R3, P1, and P2
each have a similar temperature coefficient, the first stage gain
temperature coefficient is lower than 100 ppm/°C.
AD8557
GAIN VALUES
Table 6. First Stage Gain vs. First Stage Gain Code
First Stage
Gain Code
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
First Stage Gain
2.800
2.814
2.827
2.841
2.855
2.869
2.883
2.897
2.911
2.926
2.940
2.954
2.969
2.983
2.998
3.012
3.027
3.042
3.057
3.072
3.087
3.102
3.117
3.132
3.147
3.163
3.178
3.194
3.209
3.225
3.241
3.257
First Stage
Gain Code
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
First Stage Gain
3.273
3.289
3.305
3.321
3.337
3.353
3.370
3.386
3.403
3.419
3.436
3.453
3.470
3.487
3.504
3.521
3.538
3.555
3.573
3.590
3.608
3.625
3.643
3.661
3.679
3.697
3.715
3.733
3.751
3.770
3.788
3.806
First Stage
Gain Code
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
First Stage Gain
3.825
3.844
3.863
3.881
3.900
3.919
3.939
3.958
3.977
3.997
4.016
4.036
4.055
4.075
4.095
4.115
4.135
4.156
4.176
4.196
4.217
4.237
4.258
4.279
4.300
4.321
4.342
4.363
4.384
4.406
4.427
4.449
First Stage
Gain Code
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
First Stage Gain
4.471
4.493
4.515
4.537
4.559
4.581
4.603
4.626
4.649
4.671
4.694
4.717
4.740
4.763
4.786
4.810
4.833
4.857
4.881
4.905
4.929
4.953
4.977
5.001
5.026
5.050
5.075
5.100
5.125
5.150
5.175
5.200
Table 7. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code
Second Stage Gain Code
0
1
2
3
4
5
6
7
Second Stage Gain
10
16
25
40
63
100
160
250
Minimum Combined Gain
28.0
44.8
70.0
112.0
176.4
280.0
448.0
700.0
Rev. C | Page 15 of 24
Maximum Combined Gain
52.0
83.2
130.0
208.0
327.6
520.0
832.0
1300.0
AD8557
OPEN WIRE FAULT DETECTION
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a comparator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 1.1 V. If VNEG > (VDD − 1.1 V) or
VPOS > (VDD − 1.1 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 10 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 16 nA
and matched to within 3 nA. If the inputs to A1 or A2 are
accidentally left floating, as with an open wire fault, IP1 and IP2
pull them to VDD, which would cause VOUT to swing to VSS,
allowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, defined in the previous section. In
this way, the VOUT pin is shorted to VSS when a floating input
is detected. Table 9 lists the currents used.
Table 9. Floating Fault Detection at VPOS, VNEG,
and VCLAMP
Pin
VPOS
VNEG
VCLAMP
Digital Interface
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of
inadvertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.
The AD8557 provides fault detection in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 46 shows
the voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Table 8 lists the voltage levels shown in
Figure 46.
VCLAMP
VNEG
VDD
VDD
VDD
ERROR
ERROR
VINH
VINH
NORMAL
NORMAL
A short pulse at DIGIN from low to high and back to low again,
such as between 50 ns and 10 µs long, loads a 0 into a shift
register. A long pulse at DIGIN, such as 50 µs or longer, loads a
1 into the shift register. The time between pulses should be at
least 10 µs. Assuming VSS = 0 V, voltages at DIGIN between
VSS and 0.2 × VDD are recognized as a low, and voltages at
DIGIN between 0.8 × VDD and VDD are recognized as a high.
A timing diagram example, Figure 47, shows the waveform for
entering Code 010011 into the shift register.
NORMAL
ERROR
ERROR
ERROR
VINL
VSS
VSS
06013-039
VCLL
VINL
VSS
Figure 46. Voltage Regions at VPOS, VNEG, and VCLAMP
that Trigger a Fault Condition
Table 8. Typical VINL, VINH, and VCLL Values
(VDD = 5 V)
Voltage
VINH
VINL
VCLL
Min (V)
3.9
0.195
1.0
Max (V)
4.2
0.55
1.2
Goal of Current
Pull VPOS above VINH
Pull VNEG above VINH
Pull VCLAMP below VCLL
DEVICE PROGRAMMING
SHORTED WIRE FAULT DETECTION
VPOS
Typical Current
16 nA pull-up
16 nA pull-up
0.2 µA pull-down
VOUT Condition
Short to VDD fault detection
Short to VSS fault detection
Short to VSS fault detection
tWS
tW1
tWS
tWS
tW0
tW1
tW0
tW0
tWS
tW1
tWS
CODE
0
1
0
0
1
Figure 47. Timing Diagram for Code 010011
Rev. C | Page 16 of 24
1
06013-040
WAVEFORM
AD8557
Table 10. Timing Specifications
Timing Parameter
tw0
tw1
tws
Description
Pulse width for loading 0 into shift register
Pulse width for loading 1 into shift register
Width between pulses
Specification
Between 50 ns and 10 µs
≥50 µs
≥10 µs
Table 11. 38-Bit Serial Word Format
Field No.
0
1
Bits
0 to 11
12 to 13
2
14 to 15
3
4
16 to 17
18 to 25
5
26 to 37
Description
12-bit start of packet 1000 0000 0001
2-bit function
00: change sense current
01: simulate parameter value
10: program parameter value
11: read parameter value
2-bit parameter
00: second stage gain code
01: first stage gain code
10: output offset code
11: other functions
2-bit dummy 10
8-bit value
Parameter 00 (second stage gain code): 3 LSBs used
Parameter 01 (first stage gain code): 7 LSBs used
Parameter 10 (output offset code): all 8 bits used
Parameter 11 (other functions)
Bit 0 (LSB): master fuse
Bit 1: fuse for production test at Analog Devices
12-bit end of packet 0111 1111 1110
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 µs, the 38-bit serial word transfers
in 2.3 ms. Table 11 summarizes the word format.
Field 0 and Field 5 are the start-of-packet field and end-ofpacket field, respectively. Matching the start-of-packet field with
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding
of the other fields.
Field 3 breaks up the data and ensures that no data combination
can inadvertently trigger the start-of-packet and end-of-packet
fields. Field 0 should be written first and Field 5 written last.
Within each field, the MSB must be written first and the LSB
written last. The shift register features power-on reset to minimize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.
Initial State
Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Table 12).
Table 12. Initial State Before Programming
Second Stage Gain Code = 0
First stage gain code = 0
Output offset code = 0
Master fuse = 0
Second Stage Gain = 10
First stage gain = 2.8
Output offset = VSS
Master fuse not blown
When power is applied to a device, parameter values are taken
either from internal registers, if the master fuse is not blown,
or from the polysilicon fuses, if the master fuse is blown.
Programmed values have no effect until the master fuse is
blown. The internal registers feature power-on reset, so the
unprogrammed devices enter a known state after power-up.
Power-on reset occurs when VDD is between 0.7 V and 2.2 V.
Rev. C | Page 17 of 24
AD8557
Simulation Mode
The simulation mode allows any parameter to be temporarily
changed. These changes are retained until the simulated value is
reprogrammed, the power is removed, or the master fuse is
blown. Parameters are simulated by setting Field 1 to 01,
selecting the desired parameter in Field 2, and selecting the
desired value for the parameter in Field 4. Note that a value of
11 for Field 2 is ignored during the simulation mode. Examples
of temporary settings follow:

Setting the second stage gain code (Parameter 00) to 011
and the second stage gain to 40 produces:
1000 0000 0001 01 00 10 0000 0011 0111 1111 1110

Setting the first stage gain code (Parameter 01) to 000 1011
and the first stage gain to 4.166 produces:
1000 0000 0001 01 01 10 0000 1011 0111 1111 1110
A first stage gain of 2.954 with a second stage gain of 40
gives a total gain of 118.16. This gain has a maximum
tolerance of 2.5%.

Set the output offset code (Parameter 10) to 0100 0000
and the output offset to 1.260 V when VDD = 5 V and
VSS = 0 V. This output offset has a maximum tolerance
of 0.8%:
1000 0000 0001 01 10 10 0100 0000 0111 1111 1110
Programming Mode
Intact fuses give a bit value of 0. Bits with a desired value of 1
need to have the associated fuse blown. Because a relatively
large current is needed to blow a fuse, only one fuse can be
reliably blown at a time. Thus, a given parameter value may
need several 38-bit words to allow reliable programming.
A 5.75 V (±0.25 V) supply is required when blowing fuses to
minimize the on resistance of the internal MOS switches that
blow the fuse. The power supply voltage must not exceed the
absolute maximum rating and must be able to deliver 250 mA
of current.
At least 10 μF (tantalum type) of decoupling capacitance is
needed across the power pins of the device during programming. The capacitance can be on the programming apparatus as
long as it is within 2 inches of the device being programmed.
An additional 0.1 μF (ceramic type) in parallel with the 10 μF is
recommended within ½ inch of the device being programmed.
A minimum period of 1 ms should be allowed for each fuse to
blow. There is no need to measure the supply current during
programming.
The best way to verify correct programming is to use the read
mode to read back the programmed values. Then, remeasure
the gain and offset to verify these values. Programmed fuses
have no effect on the gain and output offset until the master
fuse is blown. After blowing the master fuse, the gain and
output offset are determined solely by the blown fuses, and the
simulation mode is permanently deactivated.
Parameters are programmed by setting Field 1 to 10, selecting
the desired parameter in Field 2, and selecting a single bit with
the value 1 in Field 4.
As an example, suppose the user wants to permanently set the
second stage gain to 40. Parameter 00 needs to have the value
0000 0011 assigned. Two bits have the value 1, so two fuses need
to be blown. Because only one fuse can be blown at a time, this
code can be used to blow one fuse:
1000 0000 0001 10 00 10 0000 0010 0111 1111 1110
The MOS switch that blows the fuse closes when the complete
packet is recognized, and opens when the start-of-packet,
dummy, or end-of-packet fields are no longer valid. After 1 ms,
this second code is entered to blow the second fuse:
1000 0000 0001 10 00 10 0000 0001 0111 1111 1110
To permanently set the first stage gain to a nominal value of
2.954, Parameter 01 needs to have the value 000 1011 assigned.
Three fuses need to be blown, and the following codes are used,
with a 1 ms delay after each code:
1000 0000 0001 10 01 10 0000 1000 0111 1111 1110
1000 0000 0001 10 01 10 0000 0010 0111 1111 1110
1000 0000 0001 10 01 10 0000 0001 0111 1111 1110
To permanently set the output offset to a nominal value of
1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs
to have the value 0100 0000 assigned. If one fuse needs to be
blown, use the following code:
1000 0000 0001 10 10 10 0100 0000 0111 1111 1110
Finally, to blow the master fuse to deactivate the simulation
mode and prevent further programming, use code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110
There are a total of 20 programmable fuses. Because each fuse
requires 1 ms to blow, and each serial word can be loaded in
2.3 ms, the maximum time needed to program the fuses can be
as low as 66 ms.
Read Mode
The values stored by the polysilicon fuses can be sent to the
DIGOUT pin to verify correct programming. Normally, the
DIGOUT pin is only connected to the second gain stage output.
During read mode, however, the DIGOUT pin is also connected
to the output of a shift register to allow the polysilicon fuse
contents to be read. Because VOUT is a buffered version of
DIGOUT, VOUT also outputs a digital signal during read mode.
Read mode is entered by setting Field 1 to 11 and selecting the
desired parameter in Field 2. Field 4 is ignored. The parameter
value, stored in the polysilicon fuses, is loaded into an internal
shift register, and the MSB of the shift register is connected to
the DIGOUT pin. Pulses at DIGIN shift out the shift register
contents to the DIGOUT pin, allowing the 8-bit parameter
value to be read after seven additional pulses; shifting occurs on
the falling edge of DIGIN. An eighth pulse at DIGIN disconnects
DIGOUT from the shift register and terminates the read mode.
Rev. C | Page 18 of 24
AD8557
If a parameter value is less than eight bits long, the MSBs of the
shift register are padded with 0s.
For example, to read the second stage gain, this code is used:
1000 0000 0001 11 00 10 0000 0000 0111 1111 1110
Because the second stage gain parameter value is only three bits
long, the DIGOUT pin has a value of 0 when this code is
entered, and remains 0 during four additional pulses at DIGIN.
The fifth, sixth, and seventh pulses at DIGIN return the 3-bit
value at DIGOUT, the seventh pulse returns the LSB. An eighth
pulse at DIGIN terminates the read mode.
Programming Procedure
For reliable fuse programming, it is imperative to follow the
programming procedure requirements, especially the proper
supply voltage during programming:
1.
When programming the AD8557, the temperature of the
device must be between 10°C to 40°C.
2.
Set VDD and VSS to the desired values in the application.
Use simulation mode to test and determine the desired
codes for the second stage gain, first stage gain, and output
offset. The nominal values for these parameters are shown
in Table 6, Table 7, Equation 2, and Equation 3; use the
codes corresponding to these values as a starting point.
However, because actual parameter values for given codes
vary from device to device, some fine tuning is necessary
for the best possible accuracy.
Sense Current
A sense current is sent across each polysilicon fuse to determine
whether it has been blown. When the voltage across the fuse is
less than approximately 1.5 V, the fuse is considered not blown,
and Logic 0 is output from the OTP cell. When the voltage
across the fuse is greater than approximately 1.5 V, the fuse is
considered blown, and Logic 1 is output.
One way to choose these values is to set the output offset to
an approximate value, such as Code 128 for midsupply, to
allow the required gain to be determined. Then, set the
second stage gain so the minimum first stage gain (Code 0)
gives a lower gain than required, and the maximum first
stage gain (Code 127) gives a higher gain than required.
After choosing the second stage gain, the first stage gain
can be chosen to fine tune the total gain. Finally, the output
offset can be adjusted to give the desired value. After
determining the desired codes for second stage gain, first
stage gain, and output offset, the device is ready for
permanent programming.
When the AD8557 is manufactured, all fuses have a low
resistance. When a sense current is sent through the fuse, a
voltage less than 0.1 V is developed across the fuse. This is
much lower than 1.5 V, so Logic 0 is output from the OTP cell.
When a fuse is electrically blown, it should have a very high
resistance. When the sense current is applied to the blown fuse,
the voltage across the fuse should be larger than 1.5 V, so
Logic 1 is output from the OTP cell.
It is theoretically possible, though very unlikely, for a fuse to
be incompletely blown during programming, assuming the
required conditions are met. In this situation, the fuse could
have a medium resistance, neither low nor high, and a voltage of
approximately 1.5 V could be developed across the fuse. Thus,
the OTP cell could output Logic 0 or Logic 1, depending on
temperature, supply voltage, and other variables.
To detect this undesirable situation, the sense current can be
lowered by a factor of 4 using a specific code. The voltage developed across the fuse would then change from 1.5 V to 0.38 V,
and the output of the OTP would be a Logic 0 instead of the
expected Logic 1 from a blown fuse. Correctly blown fuses would
still output a Logic 1. In this way, incorrectly blown fuses can be
detected. Another specific code would return the sense current
to the normal (larger) value. The sense current cannot be
permanently programmed to the low value. When the AD8557
is powered up, the sense current defaults to the high value.
Note that once a programming attempt has been made for
any fuse, there should be no further attempt to blow that
fuse. If a fuse does not program to the expected state,
discard the unit. The expected incidence rate of attempted
but unblown fuses is very small when following the proper
programming procedure and conditions.
3.
Set VSS to 0 V and VDD to 5.75 V (±0.25 V). Power
supplies should be capable of supplying 250 mA at the
required voltage and properly bypassed as described in the
Programming Mode section. Use program mode to
permanently enter the desired codes for the first stage gain,
second stage gain, and output offset. Blow the master fuse
to allow the AD8557 to read data from the fuses and to
prevent further programming.
4.
Set VDD and VSS to the desired values in the application.
Use read mode with low sense current followed by high
sense current to verify programmed codes.
5.
Measure gain and offset to verify correct functionality.
The low sense current code is
1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110
The normal (high) sense current code is
1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110
Rev. C | Page 19 of 24
AD8557
Determining Optimal Gain and Offset Codes
9.
First, determine the desired gain:
10. Calculate the error (in the number of the first stage gain
codes) CEG2 = EG2/0.00489.
1.
Determine the desired gain, GA (using the measurements
obtained from the simulation).
2.
Use Table 7 to determine G2, the second stage gain, such
that (2.8 × 1.05) < (GA/G2) < (5.2/1.05). This ensures the
first and last codes for the first stage gain are not used,
thereby allowing enough first stage gain codes within each
second stage gain range to adjust for the 3% accuracy.
Next, set the second stage gain:
Calculate the error (in relative terms) EG2 = GC/GA − 1.
11. Set the first stage gain code to CG1 − CEG1 − CEG2. The
resulting gain should be within one code of GA.
Finally, determine the desired output offset:
1.
Determine the desired output offset OA (using the
measurements obtained from the simulation).
2.
Use Equation 2 to set the output offset code CO1 such that
the output offset is nominally OA.
3.
Measure the output offset (OB). OB should be within
3% of OA.
1.
Use the simulation mode to set the second stage gain to G2.
2.
Set the output offset to allow the AD8557 gain to be
measured, for example, use Code 128 to set it to midsupply.
3.
Use Table 6 or Equation 1 to set the first stage gain code
CG1, so the first stage gain is nominally GA/G2.
4.
Calculate the error (in relative terms) EO1 = OB/OA − 1.
5.
4.
Measure the resulting gain (GB). GB should be within
3% of GA.
Calculate the error (in the number of the output offset
codes) CEO1 = EO1/0.00392.
6.
Set the output offset code to CO1 − CEO1.
5.
Calculate the first stage gain error (in relative terms)
EG1 = GB/GA − 1.
7.
Measure the output offset (OC). OC should be closer to OA
than to OB.
6.
Calculate the error (in the number of the first stage gain
codes) CEG1 = EG1/0.00489.
8.
Calculate the error (in relative terms) EO2 = OC/OA − 1.
9.
7.
Set the first stage gain code to CG1 − CEG1.
Calculate the error (in the number of the output offset
codes) CEO2 = EO2/0.00392.
8.
Measure the gain (GC). GC should be closer to GA than to GB.
10. Set the output offset code to CO1 − CEO1 − CEO2. The
resulting offset should be within one code of OA.
Rev. C | Page 20 of 24
AD8557
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
45°
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 48. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
4.00
BSC SQ
0.60 MAX
0.60 MAX
13
12° MAX
1.00
0.85
0.80
0.65 BSC
TOP
VIEW
12
0.50
0.40
0.30
0.80 MAX
0.65 TYP
(BOTTOM VIEW)
9
8
5
4
0.25 MIN
1.95 BSC
0.05 MAX
0.02 NOM
SEATING
PLANE
2.50
2.35 SQ
2.20
EXPOSED
PAD
3.75
BSC SQ
0.35
0.30
0.25
PIN 1
INDICATOR
1
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 49. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-10)
Dimensions shown in millimeters
Rev. C | Page 21 of 24
082008-A
PIN 1
INDICATOR
16
AD8557
ORDERING GUIDE
Model 1
AD8557ACPZ-R2
AD8557ACPZ-REEL
AD8557ACPZ-REEL7
AD8557ARZ
AD8557ARZ-REEL
AD8557ARZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package Option
CP-16-10
CP-16-10
CP-16-10
R-8
R-8
R-8
Z = RoHS Compliant Part.
AUTOMOTIVE PRODUCTS
The AD8557 models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. C | Page 22 of 24
AD8557
NOTES
Rev. C | Page 23 of 24
AD8557
NOTES
©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06013-0-6/11(C)
Rev. C | Page 24 of 24