IRF IRF7834PBF Synchronous mosfet for notebook processor power Datasheet

PD - 95292
IRF7834PbF
Applications
l Synchronous MOSFET for Notebook
Processor Power
l Synchronous Rectifier MOSFET for
Isolated DC-DC Converters in
Networking Systems
l Lead-Free
HEXFET® Power MOSFET
VDSS
:
Qg (typ.)
30V 4.5m @VGS = 10V
1
8
S
2
7
S
3
6
4
5
S
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l 20V VGS Max. Gate Rating
RDS(on) max
G
29nC
A
A
D
D
D
D
SO-8
Top View
Absolute Maximum Ratings
Parameter
Max.
Units
Drain-to-Source Voltage
30
V
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
16
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
160
PD @TA = 25°C
Power Dissipation
2.5
VDS
VGS
ID @ TA = 25°C
ID @ TA = 70°C
19
c
PD @TA = 70°C
f
Power Dissipation f
TJ
Linear Derating Factor
Operating Junction and
TSTG
Storage Temperature Range
A
W
1.6
0.02
-55 to + 150
W/°C
°C
Thermal Resistance
Parameter
RθJL
RθJA
g
Junction-to-Ambient fg
Junction-to-Drain Lead
Notes  through
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Typ.
Max.
Units
–––
20
°C/W
–––
50
are on page 10
1
9/21/04
IRF7834PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
BVDSS
Drain-to-Source Breakdown Voltage
∆ΒVDSS/∆TJ
RDS(on)
V
Conditions
30
–––
–––
VGS = 0V, ID = 250µA
Breakdown Voltage Temp. Coefficient
–––
0.023
–––
V/°C Reference to 25°C, ID = 1mA
Static Drain-to-Source On-Resistance
–––
3.6
4.5
mΩ
–––
4.4
5.5
VGS = 10V, ID = 19A
VGS = 4.5V, ID = 16A
VGS(th)
Gate Threshold Voltage
1.35
–––
2.25
V
∆VGS(th)
Gate Threshold Voltage Coefficient
–––
- 5.2
–––
mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
µA
VDS = 24V, VGS = 0V
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
IGSS
gfs
Qg
Forward Transconductance
e
e
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = -20V
85
–––
–––
Total Gate Charge
–––
29
44
S
Qgs1
Pre-Vth Gate-to-Source Charge
–––
7.5
–––
Qgs2
Post-Vth Gate-to-Source Charge
–––
2.7
–––
Qgd
Gate-to-Drain Charge
–––
9.8
–––
ID = 16A
Qgodr
–––
9.0
–––
See Fig. 16
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
12.5
–––
Qoss
Output Charge
–––
19
–––
td(on)
Turn-On Delay Time
–––
13.7
–––
tr
Rise Time
–––
14.3
–––
td(off)
Turn-Off Delay Time
–––
18
–––
tf
Fall Time
–––
5.0
–––
Ciss
Input Capacitance
–––
3710
–––
Coss
Output Capacitance
–––
810
–––
Crss
Reverse Transfer Capacitance
–––
350
–––
VDS = 15V, ID = 16A
VDS = 15V
nC
nC
VGS = 4.5V
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
e
ID = 16A
ns
Clamped Inductive Load
VGS = 0V
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
EAS
Parameter
Single Pulse Avalanche Energy
IAR
Avalanche Current
c
d
Typ.
Max.
Units
–––
25
mJ
–––
16
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
3.1
ISM
(Body Diode)
Pulsed Source Current
–––
–––
160
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
trr
Reverse Recovery Time
–––
21
32
ns
Qrr
Reverse Recovery Charge
–––
13
20
nC
2
c
Conditions
MOSFET symbol
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 16A, VGS = 0V
e
TJ = 25°C, IF = 16A, VDD = 15V
di/dt = 100A/µs
e
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IRF7834PbF
1000
VGS
TOP
10V
4.5V
3.8V
3.5V
3.3V
3.0V
2.8V
BOTTOM 2.5V
100
10
2.5V
1
> 60µs PULSE WIDTH
Tj = 25°C
0.1
100
2.5V
10
> 60µs PULSE WIDTH
Tj = 150°C
1
0.1
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000.00
ID, Drain-to-Source Current (Α)
VGS
10V
4.5V
3.8V
3.5V
3.3V
3.0V
2.8V
BOTTOM 2.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
100.00
T J = 150°C
10.00
1.00
T J = 25°C
0.10
VDS = 10V
> 60µs PULSE WIDTH
0.01
2.0
3.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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4.0
ID = 20A
VGS = 10V
1.0
0.5
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF7834PbF
100000
12
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
VGS, Gate-to-Source Voltage (V)
ID= 16A
C rss = C gd
C, Capacitance (pF)
C oss = C ds + C gd
10000
Ciss
1000
Coss
Crss
VDS= 24V
VDS= 15V
10
8
6
4
2
0
100
1
10
0
100
10
20
30
40
50
60
70
QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100.0
T J = 150°C
10.0
T J = 25°C
1.0
100
10
1
100µsec
Tc = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
10msec
0.1
0.1
0.2
0.4
0.6
0.8
1.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1msec
1.2
0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF7834PbF
2.2
VGS(th) Gate threshold Voltage (V)
20
ID , Drain Current (A)
16
12
8
4
0
1.8
ID = 250µA
1.4
1.0
25
50
75
100
125
150
-75
-50
-25
T J , Junction Temperature (°C)
0
25
50
75
100
125
150
T J , Temperature ( °C )
Fig 10. Threshold Voltage Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
100
Thermal Response ( Z thJA )
D = 0.50
0.20
0.10
10
0.05
0.02
0.01
1
τJ
0.1
SINGLE PULSE
( THERMAL RESPONSE )
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
Ri (°C/W)
R4
R4
τC
τ
τ2
τ1
τ3
τ2
τ3
τ4
τ4
Ci= τi/Ri
Ci= i/Ri
τi (sec)
1.1659
0.000184
9.9439
0.153919
25.520
1.7486
13.380
49
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
RDS(on), Drain-to -Source On Resistance ( mΩ)
IRF7834PbF
100
EAS, Single Pulse Avalanche Energy (mJ)
20
ID = 20A
16
12
8
T J = 125°C
4
T J = 25°C
0
2.0
4.0
6.0
8.0
10.0
ID
5.9A
6.7A
BOTTOM 16A
TOP
80
60
40
20
0
25
VGS, Gate-to-Source Voltage (V)
50
75
100
125
150
Starting T J, Junction Temperature (°C)
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13c. Maximum Avalanche Energy
Vs. Drain Current
15V
LD
VDS
L
VDS
DRIVER
+
VDD -
D.U.T
RG
IAS
VGS
20V
tp
+
V
- DD
D.U.T
A
VGS
0.01Ω
Pulse Width < 1µs
Duty Factor < 0.1%
Fig 13a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
Fig 14a. Switching Time Test Circuit
VDS
90%
10%
VGS
I AS
Fig 13b. Unclamped Inductive Waveforms
6
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
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IRF7834PbF
D.U.T
Driver Gate Drive
P.W.
+
ƒ
+
‚
-
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 16. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 17. Gate Charge Waveform
7
IRF7834PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgs 2
Qgd
⎞ ⎛
⎞
+⎜I ×
× Vin × f ⎟ + ⎜ I ×
× Vin × f ⎟
ig
ig
⎝
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF7834PbF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
D
5
A
8
7
6
5
6
H
0.25 [.010]
1
2
3
A
4
MAX
MIN
.0532
.0688
1.35
1.75
A1 .0040
e
e1
0.25
.0098
0.10
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BASIC
1.27 BASIC
.025 BASIC
0.635 BASIC
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
K x 45°
A
C
y
0.10 [.004]
8X b
0.25 [.010]
MAX
b
e1
6X
MILLIMETERS
MIN
A
E
INCHES
DIM
B
A1
8X L
8X c
7
C A B
F OOTPRINT
NOT ES :
1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994.
8X 0.72 [.028]
2. CONT ROLLING DIMENS ION: MILLIMET ER
3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA.
5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006].
6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010].
6.46 [.255]
7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO
A S UBST RAT E.
3X 1.27 [.050]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET )
INT ERNAT IONAL
RECT IFIER
LOGO
XXXX
F7101
DAT E CODE (YWW)
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
Y = LAS T DIGIT OF T HE YEAR
WW = WEEK
A = AS S EMBLY S IT E CODE
LOT CODE
PART NUMBER
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9
IRF7834PbF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.19mH
RG = 25Ω, IAS = 16A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board
Rθ is measured at TJ approximately 90°C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualifications Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/04
10
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