Renesas HD49338F Cds/pga & 12-bit a/d converter Datasheet

HD49338F/HF
CDS/PGA & 12-bit A/D Converter
REJ03F0107-0100Z
Rev.1.0
Apr 20, 2004
Description
The HD49338F/HF is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 12-bit A/D converter in a single chip.
Functions
Correlated double sampling
PGA
Offset compensation
Serial interface control
12-bit ADC
Operates using only the 3 V voltage
Corresponds to switching mode of power dissipation and operating frequency
Power dissipation: 150 mW (Typ), maximum frequency: 36 MHz
Power dissipation: 100 mW (Typ), maximum frequency: 25 MHz
ADC direct input mode
Y-IN direct input mode
QFP 48-pin package
Features
Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling.
The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and
registers.
High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier.
Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change and
the CCD offset in the CDS (correlated double sampling) amplifier input.
PGA, standby mode, etc., is achieved via a serial interface.
High precision is provided by a 12-bit-resolution A/D converter.
Rev.1.0, Apr 20, 2004, page 1 of 22
HD49338F/HF
ADCIN
AVSS
Y IN
AVDD
BIAS
BLKC
CDSIN
BLKFB
BLKSH
AVDD
AVSS
AVSS
Pin Arrangement
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
42
19
43
18
44
17
16
45
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
DVDD
(NC)
SPSIG
SPBLK
OBP
PBLK
DVDD
DVDD
ADCLK
DVSS
DVSS
DRDVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
VRM
VRT
VRB
DVDD
DVSS
OEB
DVDD
DVDD
DVSS
CS
SDATA
SCK
(Top view)
Pin Description
Symbol
Description
1
D0
Digital output (LSB)
O
D
2 to 11
D1 to D10
Digital output
O
D
12
13
D11
DRDVDD
Digital output (MSB)
Output buffer power supply (3 V)
O
—
D
D
14
15
DVSS
DVSS
Digital ground (0 V)
Digital ground (0 V)
—
—
D
D
16
17
ADCLK
DVDD
ADC conversion clock input pin
Digital power supply (3 V)
I
—
D
D
18
19
DVDD
PBLK
Digital power supply (3 V)
Preblanking input pin
—
I
D
D
20
21
OBP
SPBLK
Optical black pulse input pin
Black level sampling clock input pin
I
I
D
D
22
23
SPSIG
NC
Signal level sampling clock input pin
No connection pin
I
—
D
—
24
25
DVDD
AVSS
Output power supply (3 V)
Analog ground (0 V)
—
—
D
A
26
27
AVSS
AVDD
Analog ground (0 V)
Analog power supply (3 V)
—
—
A
A
28
29
BLKSH
BLKFB
Black level S/H pin
Black level FB pin
—
—
A
A
30
31
CDSIN
BLKC
CDS input pin
Black level C pin
I
—
A
A
Rev.1.0, Apr 20, 2004, page 2 of 22
I/O
Analog(A) or
Digital(D)
Pin No.
HD49338F/HF
Pin Description (cont.)
Pin No.
Symbol
Description
I/O
Analog(A) or
Digital(D)
32
BIAS
Internal bias pin
Connect a 33 kΩ resistor between BIAS and AVSS.
—
A
33
34
AVDD
Y IN
Analog power supply (3 V)
Y input pin
—
—
A
A
35
36
AVSS
ADCIN
Analog ground (0 V)
ADC input pin
—
—
A
A
37
VRM
—
A
38
VRT
Reference voltage pin 1
Connect a 0.1 µF ceramic capacitor between VRM and AVSS.
Reference voltage pin 3
Connect a 0.1 µF ceramic capacitor between VRT and AVSS.
—
A
39
VRB
—
A
40
DVDD
Reference voltage pin 2
Connect a 0.1 µF ceramic capacitor between VRB and AVSS.
Digital power supply (3 V)
—
D
41
42
DVSS
1
OEB *
Digital ground (0 V)
Digital output enable pin
—
—
D
D
43
44
DVDD
DVDD
Digital power supply (3 V)
Digital power supply (3 V)
—
—
D
D
45
46
DVSS
CS
Digital ground (0 V)
Serial interface control input pin
—
I
D
D
47
48
SDATA
SCK
Serial data input pin
Serial clock input pin
I
I
D
D
Note:
1. With pull-down resistor.
Rev.1.0, Apr 20, 2004, page 3 of 22
HD49338F/HF
Input/Output Equivalent Circuit
Pin Name
Digital output
Equivalent Circuit
DVDD
D0 to D11
DIN
Digital
output
STBY
Digital input
DVDD
ADCLK, OBP,
SPBLK, SPSIG,
CS, SCK, SDATA,
PBLK, OEB
Digital
input
*1
Note: Only OEB is pulled down to about 70 kΩ.
Analog
CDSIN
Internally
connected
to VRT
AVDD
CDSIN
ADCIN
AVDD
Internally
connected
to VRM
ADCIN
Y IN
AVDD
Y IN
+
−
BLKSH, BLKFB
AVDD
+
−
BLKFB
VRT, VRM, VRB
VRT
VRM
VRB
AVDD
+
−
+
−
BIAS
AVDD
BIAS
Rev.1.0, Apr 20, 2004, page 4 of 22
BLKSH
HD49338F/HF
16 18 19
DVSS
AVSS
DRDVDD
DVDD
AVDD
SPSIG
SPBLK
ADCLK
Block Diagram
31 16 18 19 19
42 OEB
ADCIN 27
Y IN 26
Timing
generator
11 D11
10 D10
PBLK 26
BLKSH 28
CDS
9 D9
12 bit
ADC
PGA
Output latch circuit
CDSIN 26
BLKC 28
BLKFB 29
DC offset
compensation
circuit
Serial
interface
Bias
generator
8 D8
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
D1
SCK
BIAS
VRT
Rev.1.0, Apr 20, 2004, page 5 of 22
VRB
32 34 33
VRM
35
CS
44 45 43
SDATA
17
OBP
D0
HD49338F/HF
Internal Functions
Functional Description
CDS input
CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 56 LSB to 304 LSB by resister during the OB period.
Gain can be adjusted using 10 bits of register (0.033 dB steps) within the range from –2.36 dB to 31.40 dB. *1
ADC input
The center level of the input signal is clamped at 2048 LSB (Typ).
Gain can be adjusted using 10 bits of register (0.00446 times steps) within the range from 0.57 times (–4.86 dB) to
5.14 times (14.22 dB). *1
Y-IN input
The input signal is clamped at 280 LSB (Typ) by SYNC Tip clamp.
Automatic offset calibration of PGA and ADC
DC offset compensation feedback for CCD and CDS
Pre-blanking
CDS input operation is protected by separating it from the large input signal.
Digital output is fixed at 32 LSB.
Digital output enable function
Note: 1. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
ADCIN
PG
AMP
CDS
AMP
C2
CDSIN
C1
SH
AMP
Gain setting
(register)
Current
DAC
VRT
BLKFB
BLKSH
D0 to D11
12-bit
ADC
DAC
Offset
calibration
logic
Clamp data
(register) DC offset
feedback
logic
BLKC
C4
OBP
C3
Figure 1 HD49338F/HF Functional Block Diagram
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.
Rev.1.0, Apr 20, 2004, page 6 of 22
HD49338F/HF
2. PGA Circuit
The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 10 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 1023.
In CDSIN mode: Gain = (–2.36 dB + 0.033 dB) × N (LOG linear).
In ADCIN mode: Gain = (0.57 times + 0.00446 times) × N (linear).
Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
3. Automatic Offset Calibration Function and Black-Level Clamp Data Setting
The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (56
LSB to 304 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register 1 is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).
4. DC Offset Compensation Feedback Function
Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (∆Gain/∆H) per 1 H of the feedback loop is given by the following equation. 1H is
the one cycle of the OBP.
∆Gain/∆H = 0.078/(fclk × C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)
Example: When fclk = 20 MHz and C3 = 1.0 µF, ∆Gain/∆H = 0.0039
When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(∆Gain/∆H) must be one or lower. If it is two or more, oscillation occurs.
The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 64 LSB, the high-speed lead-in operation continues,
and when the offset error is 64 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. See table 2.
Table 1 Loop Gain Multiplication Factor during
High-Speed Lead-In Operation
HGain-Nsel
(register settings)
[0]
[1]
L
L
H
L
L
H
H
H
Multiplication
Factor N
4
8
16
32
Table 2 High-Speed Lead-In Operation
Cancellation Time
HGstop-Hsel
(register settings)
[0]
[1]
L
L
H
L
L
H
H
H
Cancellation
Time
1H
2H
4H
8H
5. Pre-Blanking Function
During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (56 to 304 LSB).
Rev.1.0, Apr 20, 2004, page 7 of 22
HD49338F/HF
PBLK
MINV
LINV
TEST1
TEST0
OEB
STBY
6. ADC Digital Output Control Function
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.
Table 3
ADC Digital Output Functions
ADC Digital Output
D11 D10 D9 D8 D7 D6 D5 D4 D3
H
X
X
X
X
X
X Hi-Z
L
H
X
X
X
X
X Hi-Z
L
L
L
L
L
H Same as in table 4.
L
H
H D11 is inverted in table 4.
H
L
H D10 to D0 are inverted in table 4.
H
H
H D11 to D0 are inverted in table 4.
X
X
L Output code is set up to Clamp Level.
H
L
L
H Same as in table 5.
L
H
H D11 is inverted in table 5.
H
L
H D10 to D0 are inverted in table 5.
H
H
H D11 to D0 are inverted in table 5.
X
X
L Output code is set up to Clamp Level.
H
L
H
L
H
L
H
L
H
H
X
L
L
X
L
L
H
L
H
L
H
L
H
L
H
X
H
H
L
H
L
H
L
H
L
H
L
X
L
H
L
H
L
H
L
H
L
H
H
X
Notes: 1. STBY, TEST, LINV, and MINV are set by register.
2. Mode setting for the OEB and the PBLK are done by external input pins.
3. The polarity of the PBLK pin when the register setting is SPinv is low.
Table 4
D1
D0
Operating Mode
Low-power wait state
Output Hi-Z
Normal operation
Pre-blanking
Normal operation
L
L
H
H
H
H
L
L
L
L
H
H
Pre-blanking
Test mode
ADC Output Code
Output Pin
Output Steps
codes
Table 5
D2
D11
L
L
L
L
L
L
L
D10
L
L
L
L
L
L
L
D9
L
L
L
L
L
L
L
D8
L
L
L
L
L
L
L
D7
L
L
L
L
L
L
L
D6
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
L
D4
L
L
L
L
L
L
L
D3
L
L
L
L
L
L
L
D2
L
L
L
L
H
H
H
D1
L
L
H
H
L
L
H
D0
L
H
L
H
L
H
L
2047
2048
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
4092
4093
4094
4095
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
0
1
2
3
4
5
6
ADC Output Code (TEST1)
Output Pin
Output Steps
codes
D11
L
L
L
L
L
L
L
D10
L
L
L
L
L
L
L
D9
L
L
L
L
L
L
L
D8
L
L
L
L
L
L
L
D7
L
L
L
L
L
L
L
D6
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
L
D4
L
L
L
L
L
L
L
D3
L
L
L
L
L
L
L
D2
L
L
L
L
H
H
H
D1
L
L
H
H
H
H
L
D0
L
H
H
L
L
H
H
2047
2048
L
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
4092
4093
4094
4095
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
H
L
0
1
2
3
4
5
6
Rev.1.0, Apr 20, 2004, page 8 of 22
HD49338F/HF
7. Adjustment of Black-Level S/H Response Frequency Characteristics
The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in table 6.
Table 6
SHSW CR Time Constant Setting
SHSW-fsel (Register setting)
[0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3]
L L L L H L L L L H L L H H L L L L H L H L H L L H H L H H H L
2.20 nsec 2.30 nsec 2.51 nsec 2.64 nsec 2.93 nsec 3.11 nsec 3.52 nsec 3.77 nsec
CR Time Constant (Typ)
(cutoff frequency conversion) (72 MHz) (69 MHz) (63 MHz) (60 MHz) (54 MHz) (51 MHz) (45 MHz) (42 MHz)
SHSW-fsel (Register setting)
[0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3]
L L L H H L L H L H L H H H L H L L H H H L H H L H H H H H H H
CR Time Constant (Typ)
4.40 nsec 4.80 nsec 5.87 nsec 6.60 nsec 8.80 nsec 10.6 nsec 17.6 nsec 26.4 nsec
(cutoff frequency conversion) (36 MHz) (33 MHz) (27 MHz) (24 MHz) (18 MHz) (15 MHz) (9 MHz)
(6 MHz)
8. The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external 31st pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.
Table 7
BLKC
31
C4
SHAMP Frequency Characteristics Setting
LoPwr
(Register setting)
"Lo"
[0]
H
[1]
L
SHA-fsel (Register setting)
[0]
[1]
L
H
75 MHz
13000 pF
(300 pF)
32 MHz
22000 pF
(750 pF)
116 MHz
10000 pF
(270 pF)
"Hi"
49 MHz
15000 pF
(620 pF)
Note: Upper line : SHAMP cutoff frequency (Typ)
Middle line : Standard value of C4 (maximum value is not defined)
Lower line : Minimum value of C4 (do not set below this value)
Rev.1.0, Apr 20, 2004, page 9 of 22
[0]
H
[1]
H
56 MHz
18000 pF
(360 pF)
24 MHz
27000 pF
(820 pF)
HD49338F/HF
Timing Chart
Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used.
0
1
2
~
11
12
13
• When CDSIN input mode is used
N
CDSIN
N+1
N+2
N+11
N+12
N+13
SPBLK
SPSIG
ADCLK
D0 to D11
N−12
N−11
N−10
N−1
N
• When ADCIN input mode is used
N+1
N
ADCIN
N+13
N+12
N+2
N+11
N+10
ADCLK
D0 to D11
N−11
N−10
N−1
N
N+1
Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low.
Figure 2 Output Timing Chart when CDSIN and ADCIN Input Modes are Used
The ADC output (D0 to D11) is output at the rising edge of the ADCLK in both modes.
Pipe-line delay is twelve clock cycles when CDSIN is used and eleven when ADCIN is used.
In ADCIN input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0, Apr 20, 2004, page 10 of 22
HD49338F/HF
Detailed Timing Specifications
Detailed Timing Specifications when CDSIN Input Mode is Used
Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.
Black
level
Signal
level
CDSIN
(2)
(3)
(1)
SPBLK
Vth
(5)
(4)
SPSIG
Vth
(6)
(7)
(8)
ADCLK
Vth
(9)
(10)
D0 to D11
Note: 1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities
of the SPBLK and the SPSIG are inverted.)
Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used
Table 8
Timing Specifications when the CDSIN Input Mode is Used
No.
Timing
Symbol
Min
Typ
Max
Unit
(1)
Black-level signal fetch time
tCDS1
—
(1.5)
—
ns
(2)
SPBLK low period *
tCDS2
Typ × 0.8
1/4fCLK
Typ × 1.2
ns
(3)
(4)
Signal-level fetch time
1
SPSIG low period *
tCDS3
tCDS4
—
Typ × 0.8
(1.5)
1/4fCLK
—
Typ × 1.2
ns
ns
(5)
(6)
SPBLK rising to SPSIG rising time *
1
SPSIG rising to ADCLK rising inhibition time *
tCDS5
tCDS6
Typ × 0.85
1
1/2fCLK × 0.90
5
Typ × 1.00
9
ns
ns
(7), (8)
(9)
ADCLK tWH min./tWL min.
ADCLK rising to digital output hold time
tCDS7, 8
tCHLD9
11
3
—
7
—
—
ns
ns
(10)
ADCLK rising to digital output delay time
tCOD10
—
16
24
ns
Note:
1
1
1. SPBLK and SPSIG polarities when serial data Spinv bit is set to low.
OBP Detailed Timing Specifications
Figure 4 shows the OBP detailed timing specifications.
The OB period is from the fifth to the twelfth clock cycle after the OB pulse is input. The average of the black signal
level is taken for eight input cycles during the OB period and becomes the clamp level (DC standard).
OB period *1
CDSIN
N
N+1
N+5
N+12
N+13
OBP
OB pulse > 2 clock cycles
This edge is used, when OBP pulse-width period is clamp-on.
When serial data OBPinv bit is set to low
(When the OBPinv is set to high, the polarity of the OBP is inverted.)
Note: 1. Shifts ±1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
Rev.1.0, Apr 20, 2004, page 11 of 22
HD49338F/HF
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Vth
VOH
Digital output
(D0 to D11)
ADC
data
ADC
data
Clamp level
VOL
ADCLK × 12 clocks
(shifts one clock cycle depending
on the PBLK input timing)
When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)
tPBLK
ADCLK × 2 clocks
Figure 5 Detailed Timing Specifications at Pre-Blanking
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
ADCIN
(1)
(2)
(3)
ADCLK
Vth
(4)
(5)
D0 to D11
VDD/2
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
Table 9
Timing Specifications when ADCIN Input Mode is Used
No.
Timing
Symbol
Min
Typ
Max
Unit
(1)
Signal fetch time
tADC1
—
(6)
—
ns
(2), (3)
(4)
ADCLK tWH min./tWL min.
ADCLK rising to digital output hold time
tADC2, 3
tAHLD4
Typ × 0.85
10
1/2fADCLK
14.5
Typ × 1.15
—
ns
ns
(5)
ADCLK rising to digital output delay time
tAOD5
—
23.5
31.5
ns
Detailed Timing Specifications for Digital Output-Enable Control
Figure 7 shows the detailed timing specifications for digital output enable control. When the OEB pin is set to high,
output disable mode is entered, and the output state becomes High-Z.
tLZ, tZL
measurement load
DVDD
OEB Vth
DVDD
2 kΩ
DVDD/2
Digital output
(D0 to D11)
tLZ
tZL
10 pF
VOL
DVSS
VOH
tHZ, tZH
measurement load
DVDD/2
tHZ
tZH
10 pF
DVSS
DVSS
Figure 7 Detailed Timing Specifications for Digital Output Enable Control
Rev.1.0, Apr 20, 2004, page 12 of 22
2 kΩ
DVSS
HD49338F/HF
Serial Interface Specifications
Table 10
Serial Data Function List
Resister 0
Resister 1
Resister 2
Resister 3
Resister 4 to 7
Test Mode (can not be used)
DI 00 (LSB)
Low
High
Low
High
Low to High
DI 01
Low
Low
High
High
Low to High
DI 02
Low
Low
Low
Low
High
DI 03
PGA gain setting (LSB) *5 SLP Low: Normal operation mode Clamp-level [0] (LSB)
High: Sleep mode
DI 04
PGA gain setting *5
STBY Low: Normal operation mode Clamp-level [1]
High: Standby mode
DI 05
PGA gain setting *5
Output mode setting (LINV)
Clamp-level [2]
Gray code [1]
DI 06
PGA gain setting *5
Output mode setting (MINV)
Clamp-level [3]
Average4, 4 lines average
DI 07
PGA gain setting *5
Output mode setting (TEST0) Clamp-level [4] (MSB)
DI 08
PGA gain setting *5
SHA-fsel [0] (LSB)
DI 09
PGA gain setting *5
SHA-fsel [1] (MSB)
DI 10
PGA gain setting *5
DI 11
DI 12
DI 13
DI 14
SHAMP
frequency HGstop-Hsel [0]
characteristics
HGstop-Hsel [1]
switching
YC-Bias off
Gray code [0] (TEST1)
Gray_test [0]
High-speed Gray_test [1]
lead-in
cancellation
Gray_test [2]
time
Cannot be used. *7
All low
HGain-Nsel [0] High-speed
lead-in
SHSW
gain
PGA gain setting *5
SHSW-fsel [1]
frequency HGain-Nsel [1] multiplication
characteristics
PGA gain setting (MSB) *5 SHSW-fsel [2]
LoPwr Low: Normal mode
High: Low power mode
switching
SPinv,
X
SHSW-fsel [3] (MSB)
SPSIG/SPBLK/PBLK inversion
Cannot be used. *8 Low
YSEL Low: CDSIN input mode
High: YIN input mode
Cannot be used. *8 Low
DI 15 (MSB) CSEL Low: CDSIN input mode
High: YIN input mode
CS
SHSW-fsel [0] (LSB)
Cannot be used. *7
All low
Latches SDATA
at SCK rising edge
tINT1
OBPinv, OBP inversion
Cannot be used. *8 Low
Cannot be used. *8 High
Cannot be used. *8 Low
RESET Low: Reset mode
Cannot be used. *8 High
High: Normal operation mode
Data is determined
at CS rising edge
fSCK
tINT2
SCK
tsu
SDATA
tho
DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Figure 8 Serial Interface Timing Specifications
2 byte continuous communications.
SDATA is latched at SCK rising edge.
Insert 16 clocks of SCK while CS is low.
Data is invalid if data transmission is aborted during transmission.
The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
7. This bit is used for the IC testing, and cannot be used by the user.
Please do not set up in addition to "ALL Low".
8. This bit is used for the IC testing, and cannot be used by the user.
It is set to the state on the right of a column when RESET bit is set to low. The register
3 should transmit by setup on the right of a column.
Notes: 1.
2.
3.
4.
5.
6.
Rev.1.0, Apr 20, 2004, page 13 of 22
Timing Specifications
Min
Max
fSCK

5 MHz
tINT1, 2
50 ns

tsu
50 ns

50 ns
tho

HD49338F/HF
Explanation of Serial Data of CDS Part
Serial data of CDS part has the following functions.
PGA gain (D5 to D12 of register 0)
Details are referred to page 6 block diagram.
At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.
(1.0 V)
(1023)
(2.0 V)
(1.0 V)
CDS
PGA
ADC
0 dB when set N = 18 which correspond to 2.36 dB
(1) Level dia explain
2V
CDS
PGA
1023
ADC
(CDS = 0 dB)
3.64 dB + 0.132 dB × N
(2) Level dia on the circuit
Figure 9 Level Dia of PGA
CSEL (D15 of register 0)
Data = 0: Select CDSIN
Data = 1: Select ADCIN
0
1
STD1[7:0] (L)
STD2[15:8] (H)
D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
SLP
0
STBY
Address
1
0
LINV
1
MINV
1
test0
1
test_I2
SHSW_fsel
SHA_fsel
SLP and STBY (D3, D4 of register 1)
SLP:
Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.
Output mode (D5 to D7 of register 1 and D4 of register 3)
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.
SHA-fsel (D8 to D9 of register 1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the
double cut off frequency point with using.
SHSW-fsel (D10 to D13 of register 1)
It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
9. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.
Rev.1.0, Apr 20, 2004, page 14 of 22
HD49338F/HF
Clamp (D3 to D7 of register 2)
Determine the OB part level with digital code of ADC output.
Clamp level = setting data × 2 + 14
Default data is 9 = 32 LSB.
HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2)
Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/–1 to previous field, its switch to high speed leading mode.
Low_PWR (D12 of register 2)
Switch circuit current and frequency characteristic.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
SPinv (D13 of register 2)
SPSIG/SPBLK/PBLK input signal inverted switching.
Data = 1: Normal
Data = 0: Inverted
Reset (D15 of register 2)
Software reset.
Data = 1: Normal
Data = 0: Reset
Offset calibration should be done when starting up with using this bit. Details are referred to page 19.
C_Bias_off (D3 of register 3)
Center bias is turned off in ADCIN mode.
Data = 0: Normally on
Data = 1: Off
Ave_4H (D6 of register 3)
Clamp detection data is averaged 4H.
Data = 0: 1H
Data = 1: Averaged 4H
Differential Code and Gray Code (D4 to D5 and D7 to D9 of register 3)
Gray code (D4 to D5 of register 3)
DC output code can be change to following type.
Gray Code [1]
0
0
1
1
Gray Code [0]
0
1
0
1
Output Code
Binary code
Gray code
Differential encoded binary
Differential encoded gray
Serial data setting items (D7 to D9 of register 3)
Setting Bit
Gray_test[0]
Gray_test[1]
Gray_test[2]
Setting Contents
Standard data output timing control signal
(Refer to the following table)
ADCLK polar with OBP. (Lo→Positive edge, HI→Negative edge)
• Standard data output timing
Gray_test[1]
Low
Low
High
High
Gray_test[0]
Low
High
Low
High
Rev.1.0, Apr 20, 2004, page 15 of 22
Standard Data Output Timing
Third and fourth
Fourth and fifth
Fifth and sixth
Sixth and seventh
HD49338F/HF
Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 11 indicates the timing specifications.
10
Differential SW(D5)
ADC
+
−
2clk_DL
Carry bit
round
Standard data
control signal
(D9,D8,D7)
Gray SW(D4)
Standard
data
selector
10-bit
output
Gray→Binary
conversion
Figure 10 Differential Code, Gray Code Circuit
(In case of select the positive edge of ADCLK with D8)
ADCLK
OBP
(In case of select the positive polar)
(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)
1
Digital output
Differential data
2
3
4
5
6
Standard
data
7
8
9
10
Differential data
Figure 11 Differential Code Timing Specifications
To use differential code, complex circuit is necessary at DSP side.
From ADC
Gray →
Binary
D9
Carry bit
round
Standard data
control signal
Standard
data
selector
2clk_DL
(1) Differential coded
D7
D7
D0
D0
(2) Gray → Binary conversion
Figure 12 Complex Circuit Example
Rev.1.0, Apr 20, 2004, page 16 of 22
D8
D9
D8
11
HD49338F/HF
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Power supply voltage
Analog input voltage
VDD(max)
VIN(max)
4.1
–0.3 to AVDD +0.3
V
V
Digital input voltage
Operating temperature
VI(max)
Topr
–0.3 to DVDD +0.3
–10 to +75
V
°C
Power dissipation
Storage temperature
Pt(max)
Tstg
400
–55 to +125
mW
°C
Power supply voltage range (HD49338HF)
Power supply voltage range (HD49338F)
Vopr
2.85 to 3.3
2.70 to 3.3
V
Notes: 1. VDD indicates AVDD and DVDD.
2. AVDD and DVDD must be commonly connected outside the IC. When they are separated by a noise filter, the
potential difference must be 0.3 V or less at power on, and 0.1 V or less during operation.
Electrical Characteristics
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
Items Common to CDSIN and ADCIN Input Modes
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Power supply voltage
range
VDD
2.85
3.00
3.30
V
LoPwr = low
Conversion frequency
fCLK low
5.5
—
25
MHz
LoPwr = high
fCLK hi
25
—
36
MHz
LoPwr = low
VIH
DVDD
2.0 × 3.0
—
DVDD
V
VIL
0
—
DVDD
0.8 × 3.0
V
Digital input pins
other than CS,
SCK and SDATA
VIH2
DVDD
2.25 × 3.0
—
DVDD
V
CS, SCK, SDATA
VIL2
0
—
DVDD
0.6 × 3.0
V
Digital output voltage
VOH
DVDD –0.5
—
—
V
VOL
—
—
0.5
V
IOL = +1 mA
Digital input current
IIH
—
—
50
µA
VIH = 3.0 V
IIH2
—
—
250
µA
VIH = 3.0 V
IIL
–50
—
—
µA
VIL = 0 V
IOZH
—
—
50
µA
VOH = VDD
IOZL
–50
—
—
µA
VOL = 0 V
ADC resolution
RES
12
12
12
bit
ADC integral linearity
INL
—
(8)
—
LSBp-p
fCLK = 20 MHz
ADC differential linearity+
DNL+
—
0.6
0.95
LSB
fCLK = 20 MHz
*1
ADC differential linearity–
DNL–
–0.95
–0.6
—
LSB
fCLK = 20 MHz
*1
Sleep current
ISLP
–100
0
100
µA
Digital input pin is
set to 0 V, output
pin is open
Standby current
ISTBY
—
3
5
mA
Digital I/O pin is set
to 0 V
Digital output Hi-Z
delay time
tHZ
—
—
100
ns
tLZ
—
—
100
ns
RL = 2 kΩ,
CL = 10 pF
tZH
—
—
100
ns
tZL
—
—
100
ns
Digital input voltage
Digital output current
IOH = –1 mA
Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.
2. Values within parentheses ( ) are for reference.
Rev.1.0, Apr 20, 2004, page 17 of 22
Remarks
See figure 7
HD49338F/HF
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AVDD = 3.0 V, DVDD = 3.0 V, and RBIAS = 33 kΩ)
Items for CDSIN Input Mode
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Consumption current (1)
IDD1
—
57
68
mA
LoPwr = low
fCLK = 36 MHz
Consumption current (2)
IDD2
—
37
46
mA
LoPwr = high
fCLK = 250 MHz
CCD offset tolerance range
VCCD
(–100)
—
(100)
mV
Timing specifications (1)
tCDS1
—
(1.5)
—
ns
Timing specifications (2)
tCDS2
Typ × 0.8
1/4fCLK
Typ × 1.2
ns
Timing specifications (3)
tCDS3
—
(1.5)
—
ns
Timing specifications (4)
tCDS4
Typ × 0.8
1/4fCLK
Typ × 1.2
ns
Timing specifications (5)
tCDS5
Typ × 0.85
1/2fCLK × 0.90
Typ × 1.00
ns
Timing specifications (6)
tCDS6
1
5
9
ns
Timing specifications (7)
tCDS7
11
—
—
ns
Timing specifications (8)
tCDS8
11
—
—
ns
Timing specifications (9)
tCHLD9
3
7
—
ns
Timing specifications (10)
tCOD10
—
16
24
ns
Clamp level
CLP(00)
—
(56)
—
LSB
CLP(09)
—
(128)
—
LSB
CLP(31)
—
(304)
—
LSB
PGA gain at CDS input
AGC(0)
–4.4
–2.4
–0.4
dB
AGC(256)
4.1
6.1
8.1
dB
AGC(512)
12.5
14.5
16.5
dB
AGC(768)
21.0
23.0
25.0
dB
AGC(1023)
29.4
31.4
33.4
dB
Remarks
See table 8
CL = 10 pF
Note : Values within parentheses ( ) are for reference.
Items for ADCIN Input Mode
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Consumption current (3)
IDD3
—
39
49
mA
LoPwr = low
fCLK = 36 MHz
Consumption current (4)
IDD4
—
21
26
mA
LoPwr = high
fCLK = 20 MHz
Timing specifications (11)
tADC1
—
(6)
—
ns
Timing specifications (12)
tADC2
Typ × 0.85
1/2fADCLK
Typ × 1.15
ns
Timing specifications (13)
tADC3
Typ × 0.85
1/2fADCLK
Typ × 1.15
ns
Timing specifications (14)
tAHLD4
—
14.5
—
ns
Timing specifications (15)
tAOD5
—
23.5
31.5
ns
Input current at ADC input
IINCIN
–110
—
110
µA
Clamp level at ADC input
OF2
—
(2048)
—
LSB
Clamp level at YIN input
OF1
—
(280)
—
LSB
PGA gain at ADC input
GSL(0)
0.45
0.57
0.72
Times
GSL(256)
1.36
1.71
2.16
Times
GSL(512)
2.27
2.86
3.60
Times
GSL(768)
3.18
4.00
5.04
Times
GSL(1023)
4.08
5.14
6.47
Times
Note : Values within parentheses ( ) are for reference.
Rev.1.0, Apr 20, 2004, page 18 of 22
Remarks
See table 9
CL = 10 pF
VIN = 1.0 V to 2.0 V
HD49338F/HF
Operation Sequence at Power On
Must be stable within the operating
power supply voltage range
VDD
SPBLK
Start control SPSIG
of TG and
ADCLK
camera DSP etc.
1 ms or more
Prohibition
period
High-speed pulse is the right phase
OBP is started within this period
OBP is the right phase
OBP
2 ms or more
HD49338F/HF
serial data transfer
(1) Register 2 setting
0 ms
or more
(3) Registers 0
(2) Register 2 setting
and 1 settings
2 ms or more
RESET bit
Automatic offset
calibration
RESET = "Low"
(RESET mode)
RESET = "High"
(RESET cancellation)
(4)Offset calibration
(automatically starts
after RESET
cancellation)
Ends after
40000 clock cycles
The following describes the above serial data transfer. For details on registers 0, 1, and 2, refer to table 10.
(1) Register 2 setting
(2) Register 2 setting
: Set all bits in register 2 to the usage condition, and set the RESET bit to low.
: Cancel the RESET mode by setting the register 2 RESET bit to high.
Do not change other register 2 settings. Offset calibration starts automatically.
(3) Register 0 and 1 settings : After the offset calibration is terminated, set registers 0 and 1.
(4) Please perform an offset calibration in the period which avoided PBLK of V.
Rev.1.0, Apr 20, 2004, page 19 of 22
HD49338F/HF
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity.
2. This product has been developed for consumer applications, and should not be used in non-consumer applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to
prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be
inserted between the ground and power supply.
4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter,
the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.
5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure
below.
Analog
+3.0V
Digital
+3.0V
Noise filter
AVDD
DVDD
HD49338F/HF
AVSS
DVSS
Noise filter
DVDD
Example of noise filter
AVDD
HD49338F/HF
DVSS
AVSS
100 µH
0.01 µF
0.01 µF
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system
set grounds, connect to the analog system.
7. When VDD is specified in the data sheet, this indicates AVDD and DVDD.
8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power
supply or ground pins or left open to prevent crosstalk in adjacent analog pins.
9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of
bending than Fe-type lead material, careful handling is necessary.
10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as
solder dipping cannot be used.
11. Serial communication should not be performed during the effective video period, since this will result in degraded
picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the
HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked.
12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in
accordance with the power-on operating sequence (see page 16).
Rev.1.0, Apr 20, 2004, page 20 of 22
HD49338F/HF
Example of Recommended External Circuit
• At CDS Input
R10
R11
R12
R13
R14
C13
0.1
100
100
100
100
100
from
Timing generator
C12 C11
0.1 0.1
C10
0.1
DVDD
(NC)
SPSIG
SPBLK
OBP
PBLK
DVDD
DVDD
ADCLK
DVSS
DVSS
DRDVDD
24 23 22 21 20 19 18 17 16 15 14 13
25 AVSS
26 AVSS
from CCD out
C14 0.1
27 AVDD
28 BLKSH
C1
2
1 µ C3* 1 µ
29 BLKFB
C4*1
30 CDSIN
31 BLKC
R15 33 k
32 BIAS
C15 0.1
33 AVDD
34 Y IN
HD49338F/HF
(CDS/PGA+ADC)
VRM
VRT
VRB
DVDD
DVSS
OEB
DVDD
DVDD
DVSS
CS
SDATA
SCK
35 AVSS
36 ADCIN
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
12
11
10
9
8
6
5
4
3
2
1
L2
47 µ
37 38 39 40 41 42 43 44 45 46 47 48
C16
47/6
L1
47 µ
to
Camera
signal
processor
7
C21
47/6
C17 C18 C19 C20
0.1 0.1 0.1 0.1
GND
C21 C22
0.1 0.1
Serial data input
3.0 V
Notes: 1. For C4, see table 5.
2. For C3, see page 8 "DC Offset Compensation Feedback Function".
• At ADC/Yin Input
from
Timing generator
C12 C11
0.1 0.1
C13
0.1
DVDD
(NC)
SPSIG
SPBLK
OBP
PBLK
DVDD
DVDD
ADCLK
DVSS
DVSS
DRDVDD
24 23 22 21 20 19 18 17 16 15 14 13
25 AVSS
C14 0.1
26 AVSS
27 AVDD
28 BLKSH
29 BLKFB
30 CDSIN
31 BLKC
R15 33 k
32 BIAS
C15 0.1
33 AVDD
34 Y IN
with Y input
+
−
C23 0.47
HD49338F/HF
(CDS/PGA+ADC)
35 AVSS
VRM
VRT
VRB
DVDD
DVSS
OEB
DVDD
DVDD
DVSS
CS
SDATA
SCK
36 ADCIN
with ADC input
C2 2.2/16
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
12
11
10
9
8
6
5
4
3
2
1
L2
47 µ
37 38 39 40 41 42 43 44 45 46 47 48
C16
47/6
L1
47 µ
C21
47/6
C17 C18 C19 C20
0.1 0.1 0.1 0.1
GND
C21 C22
0.1 0.1
3.0 V
Note: External circuit is same as above except for ADC/Y input.
Rev.1.0, Apr 20, 2004, page 21 of 22
to
Camera
signal
processor
7
Serial data input
Unit: R: Ω
C: F
HD49338F/HF
Package Dimensions
As of January, 2003
Unit: mm
24
48
13
12
0.75
0.10
*Dimension including the plating thickness
Base material dimension
Rev.1.0, Apr 20, 2004, page 22 of 22
M
1.40
1.70 Max
0.08
*0.17 ± 0.05
0.15 ± 0.04
1
*0.21 ± 0.05
0.19 ± 0.04
0.5
37
0.13 +0.09
–0.05
9.0 ± 0.2
9.0 ± 0.2
7.0
36
25
1.00
0.75
0˚ – 8˚
0.50 ± 0.10
Package Code
JEDEC
JEITA
Mass (reference value)
FP-48C
—
Conforms
0.2 g
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