StrongIRFET
IRFH7446PbF
HEXFET® Power MOSFET
Applications
l Brushed Motor drive applications
l BLDC Motor drive applications
l PWM Inverterized topologies
l Battery powered circuits
l Half-bridge and full-bridge topologies
l Synchronous rectifier applications
l Resonant mode power supplies
l OR-ing and redundant power switches
l DC/DC and AC/DC converters
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l RoHS Compliant containing no Lead, no Bromide,
and no Halogen
Package Type
IRFH7446PBF
PQFN 5mm x 6mm
PQFN 5mm x 6mm
Standard Pack
Form
Quantity
Tape and Reel
4000
Tape and Reel
400
8.0
ID (Package Limited)
85A
c
Orderable part number
Note
IRFH7446TRPBF
IRFH7446TR2PBF
EOL notice #259
125
ID = 50A
7.0
Limited By Package
100
6.0
5.0
T J = 125°C
4.0
3.0
75
50
25
2.0
T J = 25°C
1.0
0
4
6
8
10
12
14
16
18
20
25
Fig 1. Typical On-Resistance vs. Gate Voltage
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50
75
100
125
150
T C , Case Temperature (°C)
VGS, Gate -to -Source Voltage (V)
1
40V
2.5mΩ
3.3mΩ
117A
PQFN 5X6 mm
ID, Drain Current (A)
RDS(on), Drain-to -Source On Resistance (m Ω)
Base Part Number
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
Fig 2. Maximum Drain Current vs. Case Temperature
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IRFH7446PbF
Absolute Maximum Ratings
Symbol
Parameter
Max.
117
Units
c
74c
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Package Limited)
85
IDM
Pulsed Drain Current
468
PD @TC = 25°C
Maximum Power Dissipation
d
A
78
W
Linear Derating Factor
0.63
W/°C
VGS
Gate-to-Source Voltage
± 20
V
TJ
Operating Junction and
-55 to + 150
TSTG
Storage Temperature Range
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy
EAS (Thermally limited)
Single Pulse Avalanche Energy
IAR
Avalanche Current
EAR
Repetitive Avalanche Energy
d
e
l
°C
78
mJ
152
See Fig. 14, 15, 22a, 22b
d
A
mJ
Thermal Resistance
Symbol
RθJC (Bottom)
RθJC (Top)
Parameter
Junction-to-Case
Typ.
k
Junction-to-Case k
j
Junction-to-Ambient j
Junction-to-Ambient
RθJA
RθJA (<10s)
–––
Max.
1.6
–––
31
–––
35
–––
23
Units
°C/W
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Units
40
–––
–––
V
Breakdown Voltage Temp. Coefficient
–––
0.032
–––
V/°C
Reference to 25°C, ID = 1.0mA
Static Drain-to-Source On-Resistance
–––
2.5
3.3
mΩ
VGS = 10V, ID = 50A
–––
3.8
–––
mΩ
VGS = 6.0V, ID
3.9
V
μA
V(BR)DSS
Drain-to-Source Breakdown Voltage
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
Gate Threshold Voltage
2.2
–––
IDSS
Drain-to-Source Leakage Current
–––
–––
1.0
–––
–––
150
Gate-to-Source Forward Leakage
–––
–––
100
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
1.5
–––
IGSS
RG
Notes:
Calculated continuous current based on maximum allowable
junction temperature. Current is limited to 71A by source bond
technology. Note that current limitations arising from heating of
the device leads may occur with some lead mounting
arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.062mH
RG = 50Ω, IAS = 50A, VGS =10V.
ISD ≤ 50A, di/dt ≤ 1123A/μs, VDD ≤ V(BR)DSS, TJ ≤ 150°C.
2
Conditions
VGS = 0V, ID = 250μA
g
= 50A g
d
VDS = VGS, ID = 100μA
VDS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
Ω
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1 inch square 2 oz copper pad on 1.5 x 1.5 in. board of
FR-4 material.
Rθ is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50Ω, IAS = 18A,VGS =10V
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IRFH7446PbF
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
gfs
Forward Transconductance
159
–––
–––
S
Qg
Total Gate Charge
–––
65
98
nC
Qgs
Gate-to-Source Charge
–––
16
–––
VDS =20V
Qgd
Gate-to-Drain ("Miller") Charge
–––
23
–––
VGS = 10V
Qsync
Total Gate Charge Sync. (Qg - Qgd)
–––
42
–––
ID = 50A, VDS = 20V, VGS = 10V
VDS = 10V, ID = 50A
ID = 50A
g
td(on)
Turn-On Delay Time
–––
11
–––
tr
Rise Time
–––
37
–––
td(off)
Turn-Off Delay Time
–––
33
–––
RG = 2.7Ω
tf
Fall Time
–––
26
–––
VGS = 10V
Ciss
Input Capacitance
–––
3174
–––
Coss
Output Capacitance
–––
479
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
332
–––
ƒ = 1.0 MHz
Coss eff. (ER)
Effective Output Capacitance (Energy Related)
–––
637
–––
VGS = 0V, VDS = 0V to 32V
Coss eff. (TR)
Effective Output Capacitance (Time Related)
–––
656
–––
VGS = 0V, VDS
Min.
Typ.
–––
–––
Max.
85
ns
VDD = 20V
ID = 30A
pF
g
VGS = 0V
i
= 0V to 32V h
Diode Characteristics
Symbol
IS
Parameter
Continuous Source Current
c
Units
A
(Body Diode)
(Body Diode)
d
–––
–––
468
D
A
integral reverse
G
S
p-n junction diode.
VSD
Diode Forward Voltage
dv/dt
Peak Diode Recovery
trr
Reverse Recovery Time
–––
18
–––
Qrr
Reverse Recovery Charge
–––
5.0
–––
–––
6.9
–––
IRRM
Reverse Recovery Current
–––
0.50
–––
3
MOSFET symbol
showing the
Pulsed Source Current
ISM
Conditions
f
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–––
0.9
1.3
V
–––
–––
TJ = 25°C, IS = 50A, VGS = 0V
2.6
–––
V/ns
16
–––
ns
TJ = 25°C
VR = 34V,
TJ = 125°C
IF = 50A
nC
TJ = 25°C
di/dt = 100A/μs
A
TJ = 25°C
g
TJ = 150°C, IS = 50A, VDS = 40V
g
TJ = 125°C
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IRFH7446PbF
1000
1000
100
BOTTOM
10
4.5V
100
BOTTOM
4.5V
10
≤60μs PULSE WIDTH
≤60μs PULSE WIDTH
Tj = 150°C
Tj = 25°C
1
1
0.1
1
10
100
0.1
V DS, Drain-to-Source Voltage (V)
100
1.8
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 4. Typical Output Characteristics
1000
T J = 150°C
100
T J = 25°C
10
VDS = 10V
≤60μs PULSE WIDTH
1.0
ID = 50A
VGS = 10V
1.6
1.4
1.2
1.0
0.8
0.6
3
4
5
6
7
8
14.0
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
C iss = C gs + Cgd, C ds SHORTED
C rss = C gd
C oss = C ds + Cgd
10000
Ciss
Coss
Crss
1000
20 40 60 80 100 120 140 160
Fig 6. Normalized On-Resistance vs. Temperature
Fig 5. Typical Transfer Characteristics
100000
-60 -40 -20 0
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
Fig 3. Typical Output Characteristics
100
ID= 50A
12.0
VDS= 32V
VDS= 20V
10.0
8.0
6.0
4.0
2.0
0.0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
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0
10
20
30
40
50
60
70
80
90
QG, Total Gate Charge (nC)
Fig 8. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFH7446PbF
1000
10000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
T J = 150°C
T J = 25°C
10
1000
100μsec
100
1msec
10
10msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
VGS = 0V
1.0
0.1
0.0
0.4
0.8
1.2
1.6
2.0
0.1
1
VSD, Source-to-Drain Voltage (V)
10
100
VDS, Drain-to-Source Voltage (V)
Fig 10. Maximum Safe Operating Area
Fig 9. Typical Source-Drain Diode
Forward Voltage
0.50
50
Id = 1.0mA
0.45
0.40
48
0.35
46
Energy (μJ)
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
DC
44
0.30
0.25
0.20
0.15
0.10
42
0.05
0.00
40
-60 -40 -20 0
-5
20 40 60 80 100 120 140 160
0
T J , Temperature ( °C )
10 15 20 25 30 35 40 45
VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage
RDS(on), Drain-to -Source On Resistance ( mΩ)
5
Fig 12. Typical COSS Stored Energy
140
VGS = 5.0V
VGS = 6.0V
120
VGS = 7.0V
VGS = 8.0V
100
VGS =10V
80
60
40
20
0
0
100
200
300
400
500
ID, Drain Current (A)
Fig 13. Typical On-Resistance vs. Drain Current
5
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IRFH7446PbF
Thermal Response ( Z thJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 14. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Avalanche Current (A)
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Δ Tj = 125°C and
Tstart =25°C (Single Pulse)
10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 125°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
80
70
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 50A
60
50
40
30
20
10
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 16. Maximum Avalanche Energy vs. Temperature
6
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IRFH7446PbF
7
IF = 30A
V R = 34V
6
4.0
TJ = 25°C
TJ = 125°C
5
3.5
3.0
IRRM (A)
VGS(th), Gate threshold Voltage (V)
4.5
ID = 100μA
ID = 1.0mA
ID = 1.0A
2.5
4
3
2
2.0
1
0
1.5
-75 -50 -25
0
25
50
0
75 100 125 150
200
T J , Temperature ( °C )
600
800
1000
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig 17. Threshold Voltage vs. Temperature
7
100
IF = 50A
V R = 34V
6
IF = 30A
V R = 34V
80
TJ = 25°C
TJ = 125°C
QRR (nC)
5
IRRM (A)
400
diF /dt (A/μs)
4
3
TJ = 25°C
TJ = 125°C
60
40
2
20
1
0
0
0
200
400
600
800
1000
0
200
diF /dt (A/μs)
400
600
800
1000
diF /dt (A/μs)
Fig. 20 - Typical Stored Charge vs. dif/dt
Fig. 19 - Typical Recovery Current vs. dif/dt
100
IF = 50A
V R = 34V
QRR (nC)
80
TJ = 25°C
TJ = 125°C
60
40
20
0
0
200
400
600
800
1000
diF /dt (A/μs)
7
Fig. 21 - Typical Stored Charge vs. dif/dt
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IRFH7446PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
20V
VGS
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
8
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
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IRFH7446PbF
PQFN 5x6 Outline "E" Package Details
PQFN 5x6 Outline "G" Package Details
For more information on board mounting, including footprint and stencil recommendation, please refer to
application note AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf
For more information on package inspection techniques, please refer to application note AN-1154:
http://www.irf.com/technical-info/appnotes/an-1154.pdf
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
9
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IRFH7446PbF
PQFN 5x6 Part Marking
INTERNATIONAL
RECTIFIER LOGO
DATE CODE
XXXX
XYWWX
XXXXX
ASSEMBLY
SITE CODE
(Per SCOP 200-002)
PIN 1
IDENTIFIER
PART NUMBER
(“4 or 5 digits”)
MARKING CODE
(Per Marking Spec)
LOT CODE
(Eng Mode - Min last 4 digits of EATI#)
(Prod Mode - 4 digits of SPN code)
PQFN 5x6 Tape and Reel
REEL DIMENSIONS
TAPE DIMENSIONS
CODE
Ao
Bo
Ko
W
P1
DES CRIPTION
Dimension des ign to accommodate the component width
Dimension des ign to accommodate the component lenght
Dimension des ign to accommodate the component thickness
Overall width of the carrier tape
Pitch between s ucces s ive cavity centers
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Note: All dimens ion are nominal
Package
T ype
Reel
Diameter
(Inch)
QT Y
Reel
Width
W1
(mm)
Ao
(mm)
Bo
(mm)
Ko
(mm)
P1
(mm)
W
(mm)
Pin 1
Quadrant
5 X 6 PQF N
13
4000
12.4
6.300
5.300
1.20
8.00
12
Q1
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
10
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IRFH7446PbF
Qualification information†
Indus trial
(per JE DE C JE S D47F guidelines ) ††
Qualification level
Moisture Sensitivity Level
MS L1
(per JE DE C J-S TD-020D†† )
PQFN 5mm x 6mm
RoHS compliant
Yes
Qualification standards can be found at International Rectifiers web site: http://www.irf.com/product-info/reliability/
Applicable version of JEDEC standard at the time of product release.
Revision History
Date
Comment
1/17/2014 • Updated ordering information to reflect the End-Of-Life (EOL) of the mini-reel option (EOL notice #259).
2/19/2015
6/2/2015
7/7/2015
• Updated EAS (L =1mH) = 152mJ on page 2
• Updated note 10 “Limited by TJmax , starting TJ = 25°C, L = 1mH, RG = 50Ω, IAS = 18A, VGS =10V”. on page 2
• Updated package outline for “option E” and added package outline for “option G” on page 9.
• Updated "IFX" logo on page 1 & 11.
• Updated tape and reel on page 10.
• Corrected package outline for “option E” on page 9.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
11
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