Maxim MAX1085ACSA 400ksps/300ksps, single-supply, low-power, serial 10-bit adcs with internal reference Datasheet

19-1686; Rev 0; 5/00
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
Features
♦ Single-Supply Operation
+4.5V to +5.5V (MAX1084)
+2.7V to +3.6V (MAX1085)
The 3-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. The devices use an external serial-interface clock to
perform successive-approximation analog-to-digital conversions.
♦ Internal Track/Hold
Low power combined with ease of use and small package size make these converters ideal for remote-sensor
and data-acquisition applications, or for other circuits with
demanding power consumption and space requirements.
The MAX1084/MAX1085 are available in 8-pin SO
packages.
These devices are pin-compatible, higher-speed versions
of the MAX1242/MAX1243; for more information, refer to
the respective data sheets.
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
♦ 10-Bit Resolution
♦ 400ksps Sampling Rate (MAX1084)
♦ Internal +2.5V Reference
♦ Low Power: 2.5mA (400ksps)
♦ SPI/QSPI/MICROWIRE 3-Wire Serial Interface
♦ Pin-Compatible, High-Speed Upgrade to
MAX1242/MAX1243
♦ 8-Pin SO Package
Ordering Information
PART
TEMP.
RANGE
MAX1084ACSA
0°C to +70°C
8 SO
±1/2
MAX1084BCSA
MAX1084AESA
MAX1084BESA
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
8 SO
8 SO
8 SO
±1
±1/2
±1
MAX1085ACSA
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
8 SO
8 SO
8 SO
8 SO
±1/2
±1
±1/2
±1
MAX1085BCSA
MAX1085AESA
MAX1085BESA
Pen Digitizers
Process Control
Pin Configuration
PINPACKAGE
INL
(LSB)
Functional Diagram
VDD
1
TOP VIEW
CS
SCLK
VDD
1
AIN
2
SHDN 3
MAX1084
MAX1085
REF 4
8
SCLK
7
CS
6
DOUT
5
GND
SHDN
AIN
7
8
3
2
MICROWIRE is a trademark of National Semiconductor Corp.
T/H
REF
OUTPUT
SHIFT
REGISTER
6
DOUT
10-BIT
SAR
2.5V
REFERENCE
SO
SPI and QSPI are trademarks of Motorola, Inc.
INT
CLOCK
CONTROL
LOGIC
MAX1084
MAX1085
4
5
GND
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX1084/MAX1085
General Description
The MAX1084/MAX1085 10-bit analog-to-digital converters (ADCs) combine a high-bandwidth track/hold, a serial
interface with high conversion speed, an internal +2.5V
reference, and low power consumption. The MAX1084
operates from a single +4.5V to +5.5V supply; the
MAX1085 operates from a single +2.7V to +3.6V supply.
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................-0.3V to +6V
AIN to GND................................................-0.3V to (VDD + 0.3V)
REF to GND ...............................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND...............................................-0.3V to +6V
DOUT to GND............................................-0.3V to (VDD + 0.3V)
DOUT Current ..................................................................±25mA
Continuous Power Dissipation (TA = +70°C)
8-Pin SO (derate 5.88mW/°C above +70°C) ..............471mW
Operating Temperature Ranges
MAX1084_CSA/MAX1085_CSA.........................0°C to +70°C
MAX1084_ESA/MAX1085_ESA ......................-40°C to +85°C
Storage Temperature Range............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1084
(VDD = +4.5V to +5.5V, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
10
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
MAX1084A
±0.5
MAX1084B
±1.0
No missing codes over temperature
LSB
±1.0
LSB
Offset Error
±4.0
LSB
Gain Error (Note 3)
±3.0
LSB
Gain-Error Temperature
Coefficient
±0.8
ppm/°C
60
dB
-70
dB
70
dB
DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5Vp-p, clock = 6.4MHz)
Signal-to-Noise Plus Distortion
Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Intermodulation Distortion
IMD
Up to the 5th harmonic
fIN1 = 99kHz, fIN2 =102kHz
76
dB
Full-Power Bandwidth
-3dB point
6
MHz
Full-Linear Bandwidth
SINAD > 58dB
350
kHz
CONVERSION RATE
Conversion Time (Note 4)
tCONV
Track/Hold Acquisition Time
tACQ
2.5
µs
468
ns
Aperture Delay
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
fSCLK
Duty Cycle
0.5
6.4
MHz
40
60
%
ANALOG INPUT (AIN)
Input Voltage Range
Input Capacitance
2
VAIN
0
2.5
18
_______________________________________________________________________________________
V
pF
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
(VDD = +4.5V to +5.5V, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2.48
2.50
2.52
UNITS
INTERNAL REFERENCE
REF Output Voltage
VREF
TA = +25°C
REF Short-Circuit Current
REF Output Tempco
TC VREF
Load Regulation (Note 5)
0 to 1.0mA output load
Capacitive Bypass at REF
V
30
mA
±15
ppm/°C
0.1
4.7
2.0
mV/mA
10
µF
DIGITAL INPUTS (SCLK, CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
VINL
Input Hysteresis
3.0
VHYST
Input Leakage
IIN
Input Capacitance
CIN
V
0.8
0.2
VIN = 0 or VDD
V
V
±1
15
µA
pF
DIGITAL OUTPUT (DOUT)
Output Voltage Low
VOL
ISINK = 5mA
Output Voltage High
VOH
ISOURCE = 1mA
Three-State Leakage Current
Three-State Output Capacitance
IL
CS = 5V
COUT
CS = 5V
0.4
V
±10
µA
4
V
15
pF
POWER SUPPLY
Positive Supply Voltage (Note 6)
VDD
Positive Supply Current (Note 7)
IDD
Shutdown Supply Current
Power-Supply Rejection
ISHDN
PSR
4.5
VDD = 5.5V
2.5
SCLK = VDD, SHDN = GND
VDD = 5V ±10%, midscale input
5.5
V
4.0
mA
2
10
µA
±0.5
±2.0
mV
ELECTRICAL CHARACTERISTICS—MAX1085
(VDD = +2.7V to +3.6V, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
10
Resolution
Relative Accuracy (Note 2)
INL
Differential Nonlinearity
DNL
Bits
MAX1085A
±0.5
MAX1085B
±1.0
No missing codes over temperature
LSB
±1.0
LSB
Offset Error
±3.0
LSB
Gain Error (Note 3)
±3.0
LSB
Gain-Error Temperature
Coefficient
±1.6
ppm/°C
_______________________________________________________________________________________
3
MAX1084/MAX1085
ELECTRICAL CHARACTERISTICS—MAX1084 (continued)
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1085 (continued)
(VDD = +2.7V to +3.6V, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS (75kHz sinewave, 2.5Vp-p, fSAMPLE = 300ksps, fSCLK = 4.8MHz)
Signal-to-Noise Plus Distortion
Ratio
SINAD
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
Up to the 5th harmonic
60
dB
-70
dB
70
dB
fIN1 = 99kHz, fIN2 =102kHz
76
dB
Full-Power Bandwidth
-3dB point
3
MHz
Full-Linear Bandwidth
SINAD > 58dB
250
kHz
Intermodulation Distortion
IMD
CONVERSION RATE
Conversion Time (Note 4)
tCONV
Track/Hold Acquisition Time
tACQ
3.3
10
Aperture Delay
fSCLK
Duty Cycle
ns
ns
<50
Aperture Jitter
Serial Clock Frequency
µs
625
ps
0.5
4.8
MHz
40
60
%
ANALOG INPUT
Input Voltage Range
VAIN
Input Capacitance
CIN
0
2.5
18
V
pF
INTERNAL REFERENCE
REF Output Voltage
VREF
TA = +25°C
2.48
REF Output Tempco
2.50
2.52
15
REF Short Circuit Current
±15
TC VREF
Load Regulation (Note 5)
0.1
0 to 0.75mA output load
4.7
Capacitive Bypass at REF
V
mA
ppm/°C
2.0
mV/mA
10
µF
DIGITAL INPUTS (SCLK,CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
VINL
Input Hysteresis
2.0
0.2
VHYST
Input Leakage
IIN
Input Capacitance
CIN
V
0.8
V
±1
VIN = 0 or VDD
V
15
µA
pF
DIGITAL OUTPUTS (DOUT)
Output Voltage Low
VOL
ISINK = 5mA
Output Voltage High
VOH
ISOURCE = 0.5mA
IL
CS = 3V
Three-State Output Capacitance
COUT
CS = 3V
POWER SUPPLY
Positive Supply Voltage (Note 6)
VDD
Three-State Leakage Current
Positive Supply Current (Note 7)
Shutdown Supply Current
Power-Supply Rejection
4
IDD
ISHDN
PSR
SCLK = VDD, SHDN = GND
VDD = 2.7V to 3.6V, midscale input
V
±10
µA
V
15
2.7
VDD = 3.6V
0.4
VDD - 0.5V
pF
3.6
V
2.5
3.5
mA
2
10
µA
±0.5
±2.0
mV
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
(Figures 1, 2, 8, 9; VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Period
tCP
156
ns
SCLK Pulse Width High
tCH
62
ns
SCLK Pulse Width Low
tCL
62
ns
CS Fall to SCLK Rise Setup
tCSS
35
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
SCLK Rise to CS Fall Ignore
tCSO
35
ns
CS Rise to SCLK Rise Ignore
tCS1
35
ns
SCLK Rise to DOUT Hold
tDOH
CLOAD = 20pF
10
ns
SCLK Rise to DOUT Valid
tDOV
CLOAD = 20pF
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
CS Pulse Width High
tCSW
10
80
ns
65
ns
65
ns
100
ns
TIMING CHARACTERISTICS—MAX1085
(Figures 1, 2, 8, 9; VDD = +2.7V to +3.6V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Period
tCP
208
ns
SCLK Pulse Width High
tCH
83
ns
SCLK Pulse Width Low
tCL
83
ns
CS Fall to SCLK Rise Setup
tCSS
45
ns
SCLK Rise to CS Rise Hold
tCSH
0
ns
SCLK Rise to CS Fall Ignore
tCSO
45
ns
45
ns
CS Rise to SCLK Rise Ignore
tCS1
SCLK Rise to DOUT Hold
tDOH
CLOAD = 20pF
SCLK Rise to DOUT Valid
tDOV
CLOAD = 20pF
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
CS Pulse Width High
tCSW
CLOAD = 20pF
13
13
100
ns
100
ns
85
ns
85
ns
ns
Note 1: Tested at VDD = VDD,MIN.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Internal reference, offset, and reference errors nulled.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to
production test limitation.
Note 6: Electrical characteristics are guaranteed from VDD,MIN to VDD,MAX. For operations beyond this range, see Typical Operating
Characteristics.
Note 7: MAX1084 tested with 20pF on DOUT and fSCLK = 6.4MHz, 0 to 5V. MAX1085 tested with same loads, fSCLK = 4.8MHz, 0 to
3V. DOUT = full scale.
_______________________________________________________________________________________
5
MAX1084/MAX1085
TIMING CHARACTERISTICS—MAX1084
Typical Operating Characteristics
(MAX1084: VDD = +5.0V, fSCLK = 6.4MHz; MAX1055: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
0.10
0.05
0.02
DNL (LSB)
INL (LSB)
0.04
OFFSET ERROR (LSB)
0.06
0
-0.02
0
-0.05
-0.04
-0.06
0.50
MAX1084/5toc02
0.08
OFFSET ERROR vs. SUPPLY VOLTAGE
0.15
MAX1084/5toc01
0.10
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1084/5 toc03
INTEGRAL NONLINEARLITY
vs. DIGITAL OUTPUT CODE
0.25
0
-0.10
-0.08
-0.10
-0.25
-0.15
200
400
600
800
1000
1200
0
200
DIGITAL OUTPUT CODE
600
800
1000
2.5
1200
3.0
3.5
0.20
0.15
0.30
0.25
0.20
0.15
0.10
GAIN ERROR (LSB)
GAIN ERROR (LSB)
0.35
5.0
5.5
0.25
MAX1084/5 toc05
0.25
MAX104/5 toc04
0.40
4.5
6.0
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
4.0
VDD (V)
DIGITAL OUTPUT CODE
0.45
0.05
0
-0.05
0
-0.25
-0.10
0.10
-0.15
0.05
-0.20
0
-0.50
-0.25
-40
-20
0
20
40
60
TEMPERATURE (°C)
6
400
MAX1084/5 toc06
0
OFFSET ERROR (LSB)
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
80
100
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
-40
-20
0
20
40
60
TEMPERATURE (°C)
_______________________________________________________________________________________
80
100
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.506
2.508
2.506
2.504
2.502
2.502
VREF (V)
2.504
2.500
2.500
2.498
2.498
2.496
2.496
2.494
2.494
2.492
2.492
2.490
MAX1084/5 toc08
2.508
2.490
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-20
0
SUPPLY VOLTAGE (V)
MAX1084/5 toc09
CONVERTING,
SCLK = 6.4MHz
2.50
2.25
CONVERTING,
SCLK = 4.8MHz
2.00
1.75
60
80
3.0
VDD = 5V, CONVERTING
2.7
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.75
CODE = 1111 1111 1111
RL = ∞
CL = 10pF
40
100
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
3.00
20
TEMPERATURE (°C)
2.4
VDD = 3V, CONVERTING
2.1
1.8
STATIC
MAX1084/5 toc10
VREF (V)
2.510
MAX1084/5 toc07
2.510
VDD = 5V, STATIC
VDD = 3V, STATIC
1.5
1.50
2.5
3.0
3.5
4.0
4.5
5.0
-40
5.5
-20
0
20
40
60
80
100
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Pin Description
PIN
NAME
1
VDD
Positive Supply Voltage
FUNCTION
2
AIN
Sampling Analog Input, 0 to VREF Range
3
SHDN
4
REF
Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with a
4.7µF capacitor.
5
GND
Analog and Digital Ground
6
DOUT
Serial Data Output. DOUT changes state at SCLK’s rising edge. High impedance when CS is high.
7
CS
Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high
impedance.
8
SCLK
Serial Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz
(MAX1084) or 4.8MHz (MAX1085).
Active-Low Shutdown Input. Pulling SHDN low shuts down the device and reduces the supply current
to 2µA (typ).
_______________________________________________________________________________________
7
MAX1084/MAX1085
Typical Operating Characteristics (continued)
(MAX1084: VDD = +5.0V, fSCLK = 6.4MHz; MAX1085: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
VDD
6k
DOUT
DOUT
6k
CLOAD = 20pF
CLOAD = 20pF
DGND
DGND
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time
VDD
6k
DOUT
DOUT
6k
CLOAD = 20pF
CLOAD = 20pF
DGND
a) VOH TO HIGH-Z
DGND
b) VOLTO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
_______________Detailed Description
Converter Operation
The MAX1084/MAX1085 use an input track/hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 10-bit output.
Figure 3 shows the MAX1084/MAX1085 in their simplest
configuration. The internal reference is trimmed to 2.5V.
The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface to
microprocessors (µPs).
The MAX1084/MAX1085 have two modes: normal and
shutdown. Pulling SHDN low shuts the device down and
reduces supply current to 2µA (typ); pulling SHDN high
puts the device into operational mode. Pulling CS low initiates a conversion that is driven by SCLK. The conversion result is available at DOUT in unipolar serial format.
The serial data stream consists of three zeros, followed
by the data bits (MSB first). All transitions on DOUT
occur 20ns after the rising edge of SCLK. Figures 8 and
9 show the interface timing information.
8
Analog Input
Figure 4 shows the sampling architecture of the ADC’s
comparator. The full-scale input voltage is set by the
internal reference (VREF = +2.5V).
Track/Hold
In track mode, the analog signal is acquired and stored
in the internal hold capacitor. In hold mode, the T/H
switch opens and maintains a constant input to the
ADC’s SAR section.
During acquisition, the analog input AIN charges
capacitor CHOLD. Bringing CS low ends the acquisition
interval. At this instant, the T/H switches the input side
of CHOLD to GND. The retained charge on CHOLD represents a sample of the input, unbalancing node ZERO at
the comparator’s input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to 0 within the limits of 10bit resolution. This action is equivalent to transferring a
charge from CHOLD to the binary-weighted capacitive
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
+3V to +5V
0.1µF
10µF
1
ANALOG INPUT
0 TO VREF
2
SHUTDOWN
INPUT
3
4
tACQ = 7(RS + RIN) ✕ 12pF
where R IN = 800Ω, R S = the input signal’s source
impedance, and t ACQ is never less than 468ns
(MAX1284) or 625ns (MAX1085). Source impedance
below 4kΩ does not significantly affect the ADC’s AC
performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the analog input. Note that
the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s input signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1084) or 3MHz (MAX1085) small-signal bandwidth, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using undersampling techniques. To avoid aliasing of unwanted
high-frequency signals into the frequency band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow the input to swing from
GND - 0.3V to VDD + 0.3V without damage.
If the analog input exceeds 50mV beyond the supplies,
limit the input current to 2mA.
Internal Reference
The MAX1084/MAX1085 have an on-chip voltage reference trimmed to 2.5V. The internal reference output is
connected to REF and also drives the internal capacitive
DAC. The output can be used as a reference voltage
source for other components and can source up to
800µA. Bypass REF with a 4.7µF capacitor. Larger
capacitors increase wake-up time when exiting shutdown (see Using SHDN to Reduce Supply Current). The
internal reference is disabled in shutdown (SHDN = 0).
MAX1084/MAX1085
DAC, which in turn forms a digital representation of the
analog input signal. At the conversion’s end, the input
side of C HOLD switches back to AIN, and C HOLD
charges to the input signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal and the minimum time needed for the signal
to be acquired. Acquisition time is calculated by:
VDD
SCLK
AIN
CS
MAX1084
MAX1085
SHDN
DOUT
REF
GND
8
7
SERIAL
INTERFACE
6
5
4.7µF
Figure 3. Typical Operating Circuit
GND
CAPACITIVE DAC
REF
CHOLD
12pF
AIN
ZERO
COMPARATOR
RIN
800Ω
CSWITCH*
6pF
HOLD
TRACK
AUTOZERO
RAIL
*INCLUDES ALL INPUT PARASITICS
Figure 4. Equivalent Input Circuit
Serial Interface
Initialization After Power-Up and
Starting a Conversion
When power is first applied, and if SHDN is not pulled
low, it takes the fully discharged 4.7µF reference
bypass capacitor up to 1.4ms to acquire adequate
charge for specified accuracy. No conversions should
be performed during this time.
_______________________________________________________________________________________
9
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiated. Data can then be shifted out serially with the external clock.
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX1084/MAX1085 between conversions. Figure 6 shows a plot of average supply current
vs. conversion rate. The wake-up time, tWAKE, is the
time from SHDN deasserted to the time when a conversion may be initiated (Figure 5).This time depends on
the time in shutdown (Figure 7) because the external
4.7µF reference bypass capacitor loses charge slowly
during shutdown and can be as long as 1.4ms.
needed to shift out these bits. Extra clock pulses occurring after the conversion result has been clocked out,
and prior to a rising edge of CS, produce trailing zeros
at DOUT and have no effect on converter operation.
Pull CS high after reading the conversion’s LSB. For
maximum throughput, CS can be pulled low again to initiate the next conversion immediately after the specified
minimum time (tCS).
Output Coding and Transfer Function
The data output from the MAX1084/MAX1085 is binary.
Figure 10 depicts the nominal transfer function. Code
transitions occur halfway between successive-integer
LSB values; VREF = 2.5V, and 1LSB = 2.44mV or 2.5V /
1024.
Timing and Control
Conversion-start and data-read operations are controlled by the CS and SCLK digital inputs. The timing
diagrams of Figures 8 and 9 outline serial-interface
operation.
A CS falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of conversion
is determined.
SCLK begins shifting out the data after the rising edge
of the third SCLK pulse. DOUT transitions 20ns after
each SCLK rising edge. The third rising clock edge
produces the MSB of the conversion at DOUT, followed
by the remaining bits. Since there are 12 data bits and
3 leading zeros, at least 15 rising clock edges are
Applications Information
Connection to Standard Interfaces
The MAX1084/MAX1085 serial interface is fully compatible with SPI, QSPI, and MICROWIRE (Figure 11).
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 6.4MHz
(MAX1084) or 4.8MHz (MAX1085).
1) Use a general-purpose I/O line on the CPU to pull CS
low. Keep SCLK low.
2) Activate SCLK for a minimum of 13 clock cycles. The
first two clocks produce zeros at DOUT. DOUT output
data transitions 20ns after SCLK rising edge and is
available in MSB-first format. Observe the SCLK-toDOUT valid timing characteristic. Data can be clocked
into the µP on SCLK’s falling or rising edge.
COMPLETE CONVERSION SEQUENCE
CS
tWAKE
SHDN
DOUT
CONVERSION 0
POWERED UP
CONVERSION 1
POWERED DOWN
POWERED UP
Figure 5. Shutdown Sequence
10
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
MAX1084/MAX1085
SUPPLY CURRENT
vs. CONVERSION RATE
10,000
1.50
DOUT = FS
RL = ∞
1000
SUPPLY CURRENT (µA)
REFERENCE POWER-UP DELAY (ms)
VDD = 3.0V
CL = 10pF
100
10
1
1.25
1.00
0.75
0.50
0.25
0.1
0.1
1
10
100
1k
10k
CREF = 4.7µF
0
0.0001
100k
0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
CONVERSION RATE (SAMPLES)
Figure 6. Supply Current vs. Conversion Rate
Figure 7. Reference Power-Up vs. Time in Shutdown
CS
1
3
4
8
12
15
SCLK
DOUT
HIGH-Z
HIGH-Z
D9
D8
D7
D6
D5
D4
D3 D23 D1
D0
S1
S0
ACQ
HOLD/CONVERT
A/D STATE
ACQUISITION
Figure 8. Interface Timing Sequence
CS
tCSW
ttCSO
CSO
tCL
tCSS
tCH
tCSH
tCSI
SCLK
tCP
tDOH
tDOE
tDOV
tDOD
DOUT
Figure 9. Detailed Serial-Interface Timing
______________________________________________________________________________________
11
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
OUTPUT CODE
11…111
FULL-SCALE
TRANSITION
CS
I/O
SCLK
SCK
11…110
DOUT
MISO
+3V OR +5V
11…101
MAX1084
MAX1085
FS = VREF - 1LSB
1LSB = VREF
1024
SS
a) SPI
CS
00…011
CS
SCK
00…010
SCLK
MISO
00…001
DOUT
+3V OR +5V
00…000
0
1
2
3
INPUT VOLTAGE (LSB)
SS
Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF 1LSB, Zero Scale (ZS) = GND
3) Pull CS high at or after the 13th rising clock edge. If
CS remains low, the two sub-bits and trailing zeros
are clocked out after the LSB.
4) With CS = high, wait the minimum specified time, tCS,
before initiating a new conversion by pulling CS low.
If a conversion is aborted by pulling CS high before
the conversion completes, wait the minimum acquisition time, tACQ, before starting a new conversion. CS
must be held low until all data bits are clocked out.
Data can be output in 2 bytes or continuously, as shown
in Figure 8. The bytes contain the result of the conversion
padded with three leading zeros, 2 sub-bits, and trailing
zeros if SCLK is still active with CS kept low.
SPI and Microwire
When using SPI or QSPI, set CPOL = 0 and CPHA = 0.
Conversion begins with a CS falling edge. DOUT goes
low, indicating a conversion is in progress. Two consecutive 1-byte reads are required to get the full 10+2
bits from the ADC. DOUT output data transitions on
SCLK’s rising edge and is clocked into the µP on the
following rising edge.
The first byte contains 3 leading zeros, and 5 bits of
conversion result. The second byte contains the remaining 5 bits, 2 sub-bits, and 1 trailing zero. See Figure 11
for connections and Figure 12 for timing.
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
12
MAX1084
MAX1085
FS
FS - 3/2LSB
b) QSPI
I/O
CS
SK
SCLK
SI
DOUT
MAX1084
MAX1085
c) MICROWIRE
Figure 11. Common Serial-Interface Connections to the
MAX1084/MAX1085
the 10 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the
data. The MAX1084/MAX1085 require 13 clock cycles
from the µP to clock out the 10 bits of data. Additional
clock cycles clock out the 2 sub-bits followed by trailing
zeros. Figure 13 shows a transfer using CPOL = 0 and
CPHA = 1. The result of conversion contains two zeros
followed by the 10 bits of data in MSB-first format.
Layout and Grounding
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 14 shows the recommended system ground connections. Establish a single-point analog ground (“star”
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
static linearity parameters for the MAX1084/MAX1085
are measured using the endpoints method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB or less guarantees no
missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of CS and the instant when an actual sample is taken.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of fullscale analog input (RMS value) to the RMS quantization
error (residual error). The theoretical minimum analogto-digital noise is caused by quantization error and
results directly from the ADC’s resolution, (N bits):
CS
8
1
SCLK
DOUT HIGH-Z
D9
D8
D7
D6
9
D5
D3
D4
D2
D1
FIRST BYTE READ
D0
S1
HIGH-Z
S0
SECOND BYTE READ
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
CS
DOUT
12
1
SCLK
HIGH-Z
14
HIGH-Z
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)
______________________________________________________________________________________
13
MAX1084/MAX1085
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and GND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1µF and 10µF
bypass capacitors. Minimize capacitor lead lengths for
best supply-noise rejection. To reduce the effect of supply noise, a 10Ω resistor can be connected as a lowpass
filter to attenuate supply noise (Figure 14).
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
MAX1084/MAX1085
Effective Number of Bits
SUPPLIES
VDD
VDD
GND
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
R* = 10Ω
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
4.7µF
0.1µF
VDD
GND
MAX1084
MAX1085
VDD
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 14. Power-Supply Grounding Condition
SNR = (6.02 ✕ N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SINAD (dB) = 20 ✕ log (SignalRMS / NoiseRMS)
14
2
DGND
THD = 20 × LOG
2
2
2
V2 + V3 + V4 + V5
V1
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics, respectively.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component.
___________________Chip Information
TRANSISTOR COUNT: 4286
PROCESS: BiCMOS
______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
SOICN.EPS
______________________________________________________________________________________
15
MAX1084/MAX1085
________________________________________________________________Package Information
MAX1084/MAX1085
400ksps/300ksps, Single-Supply, Low-Power,
Serial 10-Bit ADCs with Internal Reference
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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