Ultra Low Power/High Speed CMOS SRAM 256K X 16 bit BSI Ÿ Ÿ Ÿ Ÿ n FEATURES Ÿ Wide VCC operation voltage : C-grade : 1.8V ~ 3.6V I-grade : 1.9V ~ 3.6V (VCC_min.=1.65V at 25OC) Ÿ Ultra low power consumption : VCC = 2.0V C-grade : 10mA(Max.) operating current I-grade : 12mA(Max.) operating current 0.3uA (Typ.) CMOS standby current VCC = 3.0V C-grade : 13mA(Max.) operating current I-grade : 15mA(Max.) operating current 0.45uA (Typ.) CMOS standby current Ÿ High speed access time : -85 85ns (Max.) -10 100ns (Max.) Ÿ Automatic power down when chip is deselected Ÿ Easy expansion with CE and OE options BS616UV4016 I/O Configuration x8/x16 selectable by LB and UB pin. Three state outputs and TTL compatible Fully static operation Data retention supply voltage as low as 1.2V n DESCRIPTION The BS616UV4016 is a high performance, ultra low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates form a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 0.3uA at 2.0V/25OC and maximum access time of 85ns at 85OC. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state output drivers. The BS616UV4016 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV4016 is available in DICE form, JEDEC standard 44-pin TSOP Type II and 48-ball BGA package. n PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE VCC RANGE POWER DISSIPATION SPEED (ns) C-grade : 1.8~3.6V I-grade : 1.9~3.6V STANDBY Operating (ICCSB1, Max) (ICC, Max) PKG TYPE VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V BS616UV4016DC DICE O O +0 C to +70 C BS616UV4016EC 1.8V ~ 3.6V 85/100 6.0uA 3.0uA 13mA 10mA BS616UV4016AC BGA-48-0608 BS616UV4016DI DICE -40OC to +85OC BS616UV4016EI 1.9V ~ 3.6V 85/100 8.0uA 5.0uA 15mA BS616UV4016AI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 A UB 12mA TSOP2-44 BGA-48-0608 n BLOCK DIAGRAM n PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC GND IO4 IO5 IO6 IO7 WE A17 A16 A15 A14 A13 TSOP2-44 BS616UV4016EC BS616UV4016EI 2 OE 3 A0 4 A1 5 A2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB IO15 IO14 IO13 IO12 GND VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 A12 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 NC IO0 . . . . . . . . . . . . B IO8 LB A3 A4 CE IO0 IO15 C IO9 IO10 A5 A6 IO1 IO2 CE WE OE UB LB VSS IO11 A17 A7 IO3 VCC E VCC IO12 NC A16 IO4 VSS F IO14 IO13 A14 A15 IO5 IO6 G IO15 NC A12 A13 WE IO7 H NC A8 A9 A10 A11 NC 1024 10 Input Row Buffer Decoder Memory Array 1024 x 4096 2048 6 D Address 16 16 16 Data Input Buffer Data Output Buffer Column I/O Write Driver Sense Amp 16 256 Column Decoder 8 Control Address Input Buffer A13 A14 A15 A16 A17 A0 A1 A2 VCC GND 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. R0201-BS616UV4016 1 Revision 1.3 Sep. 2005 BSI BS616UV4016 n PIN DESCRIPTIONS Name Function A0-A17 Address Input These 18 address inputs select one of the 262,144 x 16-bit words in the RAM CE Chip Enable 1 Input CE is active LOW. Chip enable must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The IO pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the IO pins; when WE is LOW, the data present on the IO pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the IO pins and they will be enabled. The IO pins will be in the high impendence state when OE is inactive. LB and UB Data Byte Control Input Lower byte and upper byte data input/output control pins. IO0-IO15 Data Input/Output Ports VCC 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply GND Ground n TRUTH TABLE MODE CE WE OE LB UB IO0~IO7 IO8~IO15 VCC CURRENT Chip De-selected (Power Down) H X X X X High Z High Z ICCSB, ICCSB1 X X X H H High Z High Z ICCSB, ICCSB1 L H H L X High Z High Z ICC L H H X L High Z High Z ICC L L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC L H DIN X ICC Output Disabled Read Write L L H L L X NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state) R0201-BS616UV4016 2 Revision 1.3 Sep. 2005 BSI BS616UV4016 (1) n ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias VTERM TBIAS TSTG n OPERATING RANGE RATING (2) -0.5 Storage Temperature UNITS to 4.6V V -40 to +85 O C -60 to +150 O C PT Power Dissipation 1.0 W IOUT DC Output Current 20 MA AMBIENT TEMPERATURE RANG O Vcc O Commercial 0 C to + 70 C 1.8V ~ 3.6V Industrial -40OC to + 85OC 1.9V ~ 3.6V n CAPACITANCE (1) O (TA = 25 C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V 6 pF VI/O = 0V 8 pF 1. This parameter is guaranteed and not 100% tested. O O n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) PARAMETER NAME PARAMETER VCC Power Supply VIL Input Low Voltage TEST CONDITIONS VCC=2.0V MIN. TYP.(1) MAX. UNITS 1.9 -- 3.6 V -0.3(2) -- VIH Input High Voltage 0.6 V 0.8 VCC=3.0V VCC=2.0V 1.4 VCC=3.0V 2.0 -- VCC+0.3(3) V IIL Input Leakage Current VIN = 0V to VCC, CE = VIH -- -- 1 uA ILO Output Leakage Current VI/O = 0V to V CC CE= VIH, or OE = VIH -- -- 1 uA VOL Output Low Voltage -- -- VOH Output High Voltage Operating Current ICC ICCSB (5) ICCSB1 Power Supply Standby Current – TTL Standby Current – CMOS V CC = Max, IOL = 0.1mA VCC=2.0V V CC = Max, IOL = 2.0mA VCC=3.0V V CC = Min, IOH = -0.1mA VCC=2.0V VCC-0.2 V CC = Min, IOH = -1.0mA VCC=3.0V 2.4 CE = VIL, IIO = 0mA, f = FMAX(4) CE = VIH, IIO = 0mA VCC=2.0V -- -- -- VCC=2.0V VCC=3.0V -12 V mA 15 -- -- 0.5 mA 1.0 VCC=3.0V CE≧VCC-0.2V, VIN≧V CC-0.2V or VIN≦0.2V V 0.4 VCC=3.0V VCC=2.0V 0.2 -- 0.3 5.0 0.45 8.0 uA 1. Typical characteristics are at TA=25OC. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. ICCSB1(MAX) is 3.0/6.0uA at VCC=2.0V/3.0V and TA=70OC. R0201-BS616UV4016 3 Revision 1.3 Sep. 2005 BSI BS616UV4016 O O n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C) MIN. TYP. (1) MAX. UNITS VCC for Data Retention CE≧VCC-0.2V, VIN≧V CC-0.2V or VIN≦0.2V 1.2 -- -- V Data Retention Current CE≧VCC-0.2V, VIN≧V CC-0.2V or VIN≦0.2V -- 0.15 1.7 uA 0 -- -- ns tRC (2) -- -- ns SYMBOL PARAMETER VDR (3) ICCDR TEST CONDITIONS Chip Deselect to Data Retention Time tCDR tR See Retention Waveform Operation Recovery Time O 1. VCC=1.2V, TA=25 C. 2. tRC = Read Cycle Time. 3. ICCRD_Max. is 1.2uA at TA=70OC. n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled) Data Retention Mode VCC VDR≧1.0V VCC tCDR tR CE≧VCC - 0.2V VIH CE VCC n AC TEST CONDITIONS VIH n KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load WAVEFORM tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL Others CL = 30pF+1TTL ALL INPUT PULSES 1 TTL Output CL(1) VCC GND 90% 10% → ← Rise Time: 1V/ns 90% 10% → ← Fall Time: 1V/ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE 1. Including jig and scope capacitance. R0201-BS616UV4016 4 Revision 1.3 Sep. 2005 BSI BS616UV4016 O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 85ns (VCC=1.9~3.6V) MIN. TYP. MAX. DESCRIPTION tAVAX tRC Read Cycle Time tAVQX tAA Address Access Time tELQV tACS Chip Select Access Time tBLQV (1) tBA Data Byte Control Access Time tGLQV tOE Output Enable to Output Valid tELQX tCLZ Chip Select to Output Low Z tBLQX tBE Data Byte Control to Output Low Z tGLQX tOLZ Output Enable to Output Low Z tEHQZ tCHZ Chip Select to Output High Z tBHQZ tBDO Data Byte Control to Output High Z tGHQZ tOHZ tAVQX tOH CYCLE TIME : 100ns (VCC=1.9~3.6V) MIN. TYP. MAX. UNITS 85 -- -- 100 -- -- ns -- -- 85 -- -- 100 ns (CE) -- -- 85 -- -- 100 ns (LB, UB) -- -- 40 -- -- 50 ns -- -- 40 -- -- 50 ns (CE) 15 -- -- 15 -- -- ns (LB, UB) 15 -- -- 15 -- -- ns 15 -- -- 15 -- -- ns (CE) -- -- 35 -- -- 40 ns (LB, UB) -- -- 35 -- -- 40 ns Output Enable to Output High Z -- -- 35 -- -- 40 ns Data Hold from Address Change 15 -- -- 15 -- -- ns NOTE : 1. tBA is 40ns/50ns(@speed=85ns/100ns) with address toggle; tBA is 85ns/100ns(@speed=85ns/100ns) without address toggle n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tOH tAA tOH DOUT READ CYCLE 2 (1,3,4) CE tACS tBA LB, UB tBE DOUT R0201-BS616UV4016 tCLZ (5) 5 tCHZ (5) tBDO Revision 1.3 Sep. 2005 BSI READ CYCLE 3 BS616UV4016 (1, 4) tRC ADDRESS tAA OE tOH tOE tOLZ CE tCLZ (5) LB, UB tACS tOHZ tCHZ (5) (1,5) tBA tBE tBDO DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS616UV4016 6 Revision 1.3 Sep. 2005 BSI BS616UV4016 O O n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 85ns (VCC=1.9~3.6V) MIN. TYP. MAX. DESCRIPTION CYCLE TIME : 100ns (VCC=1.9~3.6V) MIN. TYP. MAX. UNITS tAVAX tWC Write Cycle Time 85 -- -- 100 -- -- ns tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns tAVWH tAW Address Valid to End of Write 85 -- -- 100 -- -- ns tELWH tCW Chip Select to End of Write (CE) 85 -- -- 100 -- -- ns tBLWH (1) tBW (LB, UB) 35 -- -- 40 -- -- ns tWLWH tWP Write Pulse Width 40 -- -- 50 -- -- ns tWHAX tWR Write Recovery Time 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output High Z -- -- 35 -- -- 40 ns tDVWH tDW Data to Write Time Overlap 35 -- -- 40 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 35 -- -- 40 ns tWHQX tOW End of Write to Output Active 10 -- -- 10 -- -- ns Data Byte Control to End of Write (CE, WE) NOTE: 1. tBW is 35ns/40ns (@speed=85ns/100ns) with address toggle; tBW is 85ns/100ns (@speed=85ns/100ns) without address toggle. n SWITCHING WAVEFORMS (WRITE CYCLE) (1) WRITE CYCLE 1 tWC ADDRESS OE tCW (11) (5) CE tBW LB, UB tWR tAW WE tWP tAS tOHZ (3) (2) (4,10) DOUT tDH tDW DIN R0201-BS616UV4016 7 Revision 1.3 Sep. 2005 BSI WRITE CYCLE 2 BS616UV4016 (1,6) tWC ADDRESS tCW (5) CE (11) tBW LB, UB tAW tWP WE tAS tWHZ tWR (2) (3) (4,10) tOW (7) (8) DOUT tDW tDH (8,9) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, IO pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, IO pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE going low to the end of write. R0201-BS616UV4016 8 Revision 1.3 Sep. 2005 BSI BS616UV4016 n ORDERING INFORMATION BS616UV4016 X X Z YY SPEED 85: 85ns 10: 100ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C : +0oC ~ +70oC I : -40oC ~ +85oC PACKAGE D: DICE E: TSOP 2-44 A: BGA-48-0608 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. n PACKAGE DIMENSIONS NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.4 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. BALL PITCH e = 0.75 D E N D1 E1 8.0 6.0 48 5.25 3.75 E1 e D1 VIEW A 48 mini-BGA (6 x 8mm) R0201-BS616UV4016 9 Revision 1.3 Sep. 2005 BSI BS616UV4016 n PACKAGE DIMENSIONS (continued) TSOP2-44 R0201-BS616UV4016 10 Revision 1.3 Sep. 2005