STMicroelectronics M29F800DT70N1T 8 mbit (1mb x8 or 512kb x16, boot block) 5v supply flash memory Datasheet

M29F800DT
M29F800DB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block)
5V Supply Flash Memory
FEATURES SUMMARY
■ SUPPLY VOLTAGE
Figure 1. Packages
– VCC = 5V ±10% for Program, Erase and Read
■
ACCESS TIME: 55, 70, 90ns
■
PROGRAMMING TIME
– 10µs per Byte/Word typical
■
19 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 16 Main Blocks
■
SO44 (M)
PROGRAM/ERASE CONTROLLER
– Embedded Byte/Word Program algorithms
■
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■
UNLOCK BYPASS PROGRAM COMMAND
TSOP48 (N)
12 x 20mm
– Faster Production/Batch Programming
■
TEMPORARY BLOCK UNPROTECTION
MODE
■
COMMON FLASH INTERFACE
– 64 bit Security Code
■
LOW POWER CONSUMPTION
– Standby and Automatic Standby
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29F800DT: 22ECh
– Bottom Device Code M29F800DB: 2258h
February 2003
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M29F800DT, M29F800DB
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Address Inputs (A0-A18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29F800DT, M29F800DB
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 15
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . 25
Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data 25
Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 26
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19. Top Boot Block Addresses, M29F800DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Bottom Boot Block Addresses, M29F800DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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M29F800DT, M29F800DB
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 25. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 27. Programmer Technique Bus Operations, BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 19. In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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M29F800DT, M29F800DB
SUMMARY DESCRIPTION
The M29F800D is a 8 Mbit (1Mb x8 or 512Kb x16)
non-volatile memory that can be read, erased and
reprogrammed. These operations can be performed using a single low voltage (5V) supply. On
power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or
EPROM.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are written to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
The blocks in the memory are asymmetrically arranged, see Figures 5 and 6, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in SO44 and TSOP48 (12
x 20mm) packages. The memory is supplied with
all the bits erased (set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
19
15
A0-A18
DQ0-DQ14
DQ15A–1
W
E
M29F800DT
M29F800DB
G
RB
RP
BYTE
VSS
AI06148B
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
(not available on SO44 package)
BYTE
Byte/Word Organization Select
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
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M29F800DT, M29F800DB
Figure 3. SO Connections
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
1
43
2
3
42
4
41
40
5
39
6
38
7
37
8
36
9
35
10
11 M29F800DT 34
12 M29F800DB 33
32
13
31
14
30
15
29
16
17
28
18
27
19
26
20
25
21
24
22
23
Figure 4. TSOP Connections
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
AI06150
6/39
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
12
13
24
48
M29F800DT
M29F800DB
37
36
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI06149
M29F800DT, M29F800DB
Figure 5. Block Addresses (x8)
M29F800DT
Top Boot Block Addresses (x8)
M29F800DB
Bottom Boot Block Addresses (x8)
FFFFFh
FFFFFh
16 KByte
64 KByte
FC000h
FBFFFh
F0000h
EFFFFh
8 KByte
64 KByte
FA000h
F9FFFh
E0000h
Total of 15
64 KByte Blocks
8 KByte
F8000h
F7FFFh
32 KByte
F0000h
EFFFFh
1FFFFh
64 KByte
64 KByte
E0000h
10000h
0FFFFh
32 KByte
Total of 15
64 KByte Blocks
1FFFFh
08000h
07FFFh
8 KByte
06000h
05FFFh
64 KByte
8 KByte
04000h
03FFFh
10000h
0FFFFh
64 KByte
00000h
16 KByte
00000h
AI06152
Note: Also see Appendix A, Tables 19 and 20 for a full listing of the Block Addresses.
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M29F800DT, M29F800DB
Figure 6. Block Addresses (x16)
M29F800DT
Top Boot Block Addresses (x16)
M29F800DB
Bottom Boot Block Addresses (x16)
7FFFFh
7FFFFh
8 KWord
32 KWord
7E000h
7DFFFh
78000h
77FFFh
4 KWord
32 KWord
7D000h
7CFFFh
70000h
Total of 15
32 KWord Blocks
4 KWord
7C000h
7BFFFh
16 KWord
78000h
77FFFh
0FFFFh
32 KWord
32 KWord
70000h
08000h
07FFFh
16 KWord
Total of 15
32 KWord Blocks
0FFFFh
04000h
03FFFh
4 KWord
03000h
02FFFh
32 KWord
4 KWord
02000h
01FFFh
08000h
07FFFh
32 KWord
00000h
8 KWord
00000h
AI06153
Note: Also see Appendix A, Tables 19 and 20 for a full listing of the Block Addresses.
8/39
M29F800DT, M29F800DB
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A18). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Data Inputs/Outputs (DQ8-DQ14). The Data Inputs/Outputs output the data stored at the selected
address during a Bus Read operation when BYTE
is High, VIH. When BYTE is Low, VIL, these pins
are not used and are high impedance. During Bus
Write operations the Command Register does not
use these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A-1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the Word
on the other addresses, DQ15A–1 High will select
the MSB. Throughout the text consider references
to the Data Input/Output to include this pin when
BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except
when stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V IH, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V IL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, V IH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Ready/Busy
Output section, Table 15 and Figure 14, Reset/
Temporary Unprotect AC Characteristics for more
details.
Holding RP at V ID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
operation. During Program or Erase operations
Ready/Busy is Low, V OL. Ready/Busy is high-impedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 15 and Figure
14, Reset/Temporary Unprotect AC Characteristics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the 8-bit and 16-bit Bus modes of
the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-bit mode, when
it is High, V IH, the memory is in 16-bit mode.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the V CC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the V CC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during program and
erase operations, ICC3.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
9/39
M29F800DT, M29F800DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See
Tables 2 and 3, Bus Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V IL, to Chip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the
value, see Figure 11, Read Mode AC Waveforms,
and Table 12, Read AC Characteristics, for details
of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 13 and 14, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V IH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 11, DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations. Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block
Protection. These bus operations are intended for
use by programming equipment and are not usually used in applications. They require V ID to be
applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2 and 3, Bus Operations.
Block Protection and Blocks Unprotection.
Each block can be separately protected against
accidental Program or Erase. Protected blocks
can be unprotected to allow data to be changed.
There are two methods available for protecting
and unprotecting the blocks, one for use on programming equipment and the other for in-system
use. Block Protect and Chip Unprotect operations
are described in Appendix C.
Table 2. Bus Operations, BYTE = V IL
Operation
E
G
Address Inputs
DQ15A–1, A0-A18
W
Data Inputs/Outputs
DQ14-DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Hi-Z
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Hi-Z
Data Input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
20h
Read Device Code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z
ECh (M29F800DT)
58h (M29F800DB)
Output Disable
Note: X = VIL or VIH.
10/39
M29F800DT, M29F800DB
Table 3. Bus Operations, BYTE = V IH
Operation
Address Inputs
A0-A18
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
E
G
W
Bus Read
VIL
VIL
VIH
Cell Address
Bus Write
VIL
VIH
VIL
Command Address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
0020h
Read Device Code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
22ECh (M29F800DT)
2258h (M29F800DB)
Output Disable
Data Output
Data Input
Note: X = VIL or VIH.
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 4, or 5, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where
it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations
can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. Once the program or erase operation
has started the Read/Reset command is no longer
accepted. The Read/Reset command will not
abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once
the Auto Select command is issued the memory
remains in Auto Select mode until a Read/Reset
command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select
mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation
with A0 = V IL and A1 = VIL. The other address bits
may be set to either V IL or VIH. The Manufacturer
Code for STMicroelectronics is 0020h.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL. The other
address bits may be set to either VIL or VIH.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V IL ,
A1 = V IH, and A12-A18 specifying the address of
the block. The other address bits may be set to either V IL or VIH. If the addressed block is protected
then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal
state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. Typical
program times are given in Table 6. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs the
11/39
M29F800DT, M29F800DB
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass
command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the access time to the device is long (as
with some EPROM programmers) considerable
time saving can be made by using these commands. Three Bus Write operations are required
to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Program command can be used to
program one address in memory at a time. The
command requires two Bus Write operations, the
final write operation latches the address and data
in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A
protected block cannot be programmed; the operation cannot be aborted and the Status Register is
read. Errors must be reset using the Read/Reset
command, which leaves the device in Unlock Bypass Mode. See the Program command for details
on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the erase operation the memory will ignore
all commands. It is not possible to issue any command to abort the operation. Typical chip erase
12/39
times are given in Table 6. All Bus Read operations during the Chip Erase operation will output
the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more
details.
After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous
data is lost.
Block Erase Command. The Block Erase command can be used to erase a list of one or more
blocks. Six Bus Write operations are required to
select the first block in the list. Each additional
block in the list can be selected by repeating the
sixth Bus Write operation using the address of the
additional block. The Block Erase operation starts
the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any
more blocks. Each additional block must therefore
be selected within 50µs of the last block. The 50µs
timer restarts when an additional block is selected.
The Status Register can be read after the sixth
Bus Write operation. See the Status Register for
details on how to identify if the Program/Erase
Controller has started the Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command. Typical block erase times are given in
Table 6. All Bus Read operations during the Block
Erase operation will output the Status Register on
the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in
the unprotected selected blocks to ’1’. All previous
data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
M29F800DT, M29F800DB
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
the Erase Suspend Latency Time (refer to Table 6
for value) of the Erase Suspend Command being
issued. Once the Program/Erase Controller has
stopped the memory will be set to Read mode and
the Erase will be suspended. If the Erase Suspend
command is issued during the period when the
memory is waiting for an additional block (before
the Program/Erase Controller starts) then the
Erase is suspended immediately and will start immediately when the Erase Resume Command is
issued. It is not possible to select any further
blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Reading from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be accepted.
Erase Resume Command. The Erase Resume
command must be used to restart the Program/
Erase Controller from Erase Suspend. An erase
can be suspended and resumed more than once.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This
command is valid when the device is ready to read
the array data or when the device is in autoselected mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is issued subsequent Bus Read operations read from
the Common Flash Interface Memory Area. The
Read/Reset command must be issued to return
the device to Read Array mode. See Appendix B,
Tables 21, 22, 23, 24, 25 and for details on the information contained in the Common Flash Interface (CFI) memory area.
Block Protect and Chip Unprotect Commands.
Each block can be separately protected against
accidental Program or Erase. The whole chip can
be unprotected to allow the data inside the blocks
to be changed.
Block Protect and Chip Unprotect operations are
described in Appendix C.
13/39
M29F800DT, M29F800DB
Command
Length
Table 4. Commands, 16-bit mode, BYTE = VIH
Bus Write Operations
1st
2nd
Addr
Data
1
X
F0
3
555
Auto Select
3
Program
3rd
4th
Addr
Data
Addr
Data
AA
2AA
55
X
F0
555
AA
2AA
55
555
90
4
555
AA
2AA
55
555
A0
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
555
Erase Suspend
1
X
B0
Erase Resume
1
X
30
Read CFI Query
1
55
98
5th
Addr
Data
PA
PD
80
555
80
555
6th
Addr
Data
Addr
Data
AA
2AA
55
555
10
AA
2AA
55
BA
30
Read/Reset
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is V IL or DQ15 when BYTE is VIH.
14/39
M29F800DT, M29F800DB
Length
Table 5. Commands, 8-bit mode, BYTE = VIL
Command
Bus Write Operations
1st
2nd
Addr
Data
1
X
F0
3
AAA
Auto Select
3
Program
3rd
4th
Addr
Data
Addr
Data
AA
555
55
X
F0
AAA
AA
555
55
AAA
90
4
AAA
AA
555
55
AAA
A0
Unlock Bypass
3
AAA
AA
555
55
AAA
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
AAA
AA
555
55
AAA
Block Erase
6+
AAA
AA
555
55
AAA
Erase Suspend
1
X
B0
Erase Resume
1
X
30
Read CFI Query
1
AA
98
5th
Addr
Data
PA
PD
80
AAA
80
AAA
6th
Addr
Data
Addr
Data
AA
555
55
AAA
10
AA
555
55
BA
30
Read/Reset
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
All values in the table are in hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is V IL or DQ15 when BYTE is VIH.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Typ (1, 2)
Max(2)
Unit
Chip Erase
12
60(3)
s
Block Erase (64 Kbytes)
0.8
6(4)
s
Erase Suspend Latency Time
30
Program (Byte or Word)
10
200(3)
µs
Chip Program (Byte by Byte)
12
60(3)
s
Chip Program (Word by Word)
6
30(3)
s
Parameter
Program/Erase Cycles (per Block)
Data Retention
Note: 1.
2.
3.
4.
Min
µs
100,000
cycles
20
years
Typical values measured at room temperature and nominal voltages.
Sampled, but not 100% tested.
Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
Maximum value measured at worst case conditions for both temperature and VCC.
15/39
M29F800DT, M29F800DB
STATUS REGISTER
Bus Read operations from any address always
read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block being erased
is accessed.
The bits in the Status Register are summarized in
Table 7, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being programmed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 7, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After
successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block,
the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block or a
suspended block, the operation is aborted, no er-
16/39
ror is signalled and DQ6 toggles for approximately
1µs.
Figure 8, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to addresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased correctly.
M29F800DT, M29F800DB
Table 7. Status Register Bits
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
DQ7
Toggle
0
–
–
0
Program During Erase
Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Any Address
DQ7
Toggle
1
–
–
0
Chip Erase
Any Address
0
Toggle
0
1
Toggle
0
Block Erase before
timeout
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
No Toggle
0
Erasing Block
0
Toggle
0
1
Toggle
0
Non-Erasing Block
0
Toggle
0
1
No Toggle
0
Erasing Block
1
No Toggle
0
–
Toggle
1
Block Erase
Erase Suspend
Non-Erasing Block
Data read as normal
1
Good Block Address
0
Toggle
1
1
No Toggle
0
Faulty Block Address
0
Toggle
1
1
Toggle
0
Erase Error
Note: Unspecified data bits should be ignored.
Figure 7. Data Polling Flowchart
Figure 8. Data Toggle Flowchart
START
START
READ DQ6
READ DQ5 & DQ7
at VALID ADDRESS
READ
DQ5 & DQ6
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
NO
YES
NO
DQ5
=1
NO
YES
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
READ DQ6
TWICE
DQ7
=
DATA
YES
DQ6
=
TOGGLE
NO
FAIL
PASS
AI03598
NO
YES
FAIL
PASS
AI01370C
17/39
M29F800DT, M29F800DB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature Under Bias
–50
125
°C
TSTG
Storage Temperature
–65
150
°C
VIO
Input or Output Voltage (1,2)
–0.6
VCC +0.6
V
VCC
Supply Voltage
–0.6
6
V
VID
Identification Voltage
–0.6
13.5
V
Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to V CC +2V during transition and for less than 20ns during transitions.
18/39
M29F800DT, M29F800DB
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 9, Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 9. Operating and AC Measurement Conditions
M29F800D
Parameter
55
70/ 90
Unit
Min
Max
Min
Max
VCC Supply Voltage
4.5
5.5
4.5
5.5
V
Ambient Operating Temperature
–40
85
–40
85
°C
Load Capacitance (CL)
30
100
Input Rise and Fall Times
pF
10
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 9. AC Measurement I/O Waveform
10
ns
0 to 3
0.45 to 2.4
V
1.5
0.8 and 2.0
V
Figure 10. AC Measurement Load Circuit
1.3V
High Speed (55ns)
VCC
3V
1N914
1.5V
0V
3.3kΩ
DEVICE
UNDER
TEST
Standard (70, 90ns)
2.4V
OUT
CL
2.0V
0.8V
0.45V
0.1µF
AI05276
CL includes JIG capacitance
AI05277
Table 10. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Note: Sampled only, not 100% tested.
19/39
M29F800DT, M29F800DB
Table 11. DC Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VCC
±1
µA
ICC1
Supply Current (Read)
E = VIL, G = VIH,
f = 6MHz
20
mA
ICC2
Supply Current (Standby) TTL
E = VIH
2
mA
ICC3
Supply Current (Standby) CMOS
E = VCC ±0.2V,
RP = VCC ±0.2V
150
µA
ICC4 (1)
Supply Current (Program/Erase)
Program/Erase
Controller active
20
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2
VCC + 0.5
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage TTL CMOS
VID
Identification Voltage
IID
Identification Current
VLKO
Program/Erase Lockout Supply
Voltage
Note: 1. Sampled only, not 100% tested.
20/39
IOL = 5.8mA
IOH = –2.5mA
2.4
11.5
A9 = VID
3.2
V
12.5
V
100
µA
4.2
V
M29F800DT, M29F800DB
Figure 11. Read Mode AC Waveforms
tAVAV
A0-A18/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGLQV
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI06154
Table 12. Read AC Characteristics
M29F800D
Symbol
Alt
Parameter
Test Condition
Unit
55
70/ 90
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
55
70
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
55
70
ns
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
55
70
ns
tGLQX (1)
tOLZ
Output Enable Low to Output Transition
E = VIL
Min
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
30
30
ns
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
18
20
ns
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
18
20
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or Address
Transition to Output Transition
Min
0
0
ns
tELBL
tELBH
tELFL
tELFH
Chip Enable to BYTE Low or High
Max
5
5
ns
tBLQZ
tFLQZ
BYTE Low to Output Hi-Z
Max
25
30
ns
tBHQV
tFHQV
BYTE High to Output Valid
Max
30
40
ns
Note: 1. Sampled only, not 100% tested.
21/39
M29F800DT, M29F800DB
Figure 12. Write AC Waveforms, Write Enable Controlled
tAVAV
A0-A18/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI06155
Table 13. Write AC Characteristics, Write Enable Controlled
M29F800D
Symbol
Alt
Parameter
Unit
55
70/ 90
tAVAV
tWC
Address Valid to Next Address Valid
Min
55
70
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
45
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
45
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
20
20
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
45
ns
Output Enable High to Write Enable Low
Min
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
ns
tWHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
22/39
M29F800DT, M29F800DB
Figure 13. Write AC Waveforms, Chip Enable Controlled
tAVAV
A0-A18/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI06156
Table 14. Write AC Characteristics, Chip Enable Controlled
M29F800D
Symbol
Alt
Parameter
Unit
55
70/ 90
tAVAV
tWC
Address Valid to Next Address Valid
Min
55
70
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
45
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
45
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
20
20
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
45
ns
Output Enable High Chip Enable Low
Min
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
ns
tEHRL (1)
tBUSY
Program/Erase Valid to RB Low
Max
30
30
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
µs
Note: 1. Sampled only, not 100% tested.
23/39
M29F800DT, M29F800DB
Figure 14. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI06870
Table 15. Reset/Block Temporary Unprotect AC Characteristics
M29F800D
Symbol
tPHWL (1)
tPHEL
Alt
Parameter
Unit
55
70/ 90
tRH
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
50
50
ns
tRB
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
Min
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
ns
tPLYH (1)
tREADY
RP Low to Read Mode
Max
10
10
µs
tPHPHH (1)
tVIDR
RP Rise Time to VID
Min
500
500
ns
tPHGL
(1)
tRHWL (1)
tRHEL (1)
tRHGL
(1)
Note: 1. Sampled only, not 100% tested.
24/39
M29F800DT, M29F800DB
PACKAGE MECHANICAL
Figure 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A
A2
C
b
e
CP
D
N
E
EH
1
A1
α
L
SO-d
Note: Drawing is not to scale.
Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
2.80
A1
Max
0.1102
0.10
0.0039
A2
2.30
2.20
2.40
0.0906
0.0866
0.0945
b
0.40
0.35
0.50
0.0157
0.0138
0.0197
C
0.15
0.10
0.20
0.0059
0.0039
0.0079
CP
0.08
0.0030
D
28.20
28.00
28.40
1.1102
1.1024
1.1181
E
13.30
13.20
13.50
0.5236
0.5197
0.5315
EH
16.00
15.75
16.25
0.6299
0.6201
0.6398
e
1.27
–
–
0.0500
–
–
L
0.80
a
N
0.0315
8
44
8
44
25/39
M29F800DT, M29F800DB
Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
A
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.170
0.270
0.0067
0.0106
C
0.100
0.210
0.0039
0.0083
CP
0.100
0.0039
D
19.800
20.200
0.7795
0.7953
D1
18.300
18.500
0.7205
0.7283
–
–
–
–
E
11.900
12.100
0.4685
0.4764
L
0.500
0.700
0.0197
0.0276
alfa
0
5
0
5
e
N
26/39
0.500
48
0.0197
48
M29F800DT, M29F800DB
PART NUMBERING
Table 18. Ordering Information Scheme
Example:
M29F800DB
55
N
6
T
Device Type
M29
Operating Voltage
F = VCC = 5V ± 10%
Device Function
800D = 8 Mbit (x8/x16), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Package
M = SO44
N = TSOP48: 12 x 20 mm
Temperature Range
6 = –40 to 85 °C
1 = 0 to 70 °C
Option
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
27/39
M29F800DT, M29F800DB
APPENDIX A. BLOCK ADDRESS TABLE
Table 19. Top Boot Block Addresses,
M29F800DT
Table 20. Bottom Boot Block Addresses,
M29F800DB
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
#
Size
(Kbytes)
Address Range
(x8)
Address Range
(x16)
18
16
FC000h-FFFFFh
7E000h-7FFFFh
18
64
F0000h-FFFFFh
78000h-7FFFFh
17
8
FA000h-FBFFFh
7D000h-7DFFFh
17
64
E0000h-EFFFFh
70000h-77FFFh
16
8
F8000h-F9FFFh
7C000h-7CFFFh
16
64
D0000h-DFFFFh
68000h-6FFFFh
15
32
F0000h-F7FFFh
78000h-7BFFFh
15
64
C0000h-CFFFFh
60000h-67FFFh
14
64
E0000h-EFFFFh
70000h-77FFFh
14
64
B0000h-BFFFFh
58000h-5FFFFh
13
64
D0000h-DFFFFh
68000h-6FFFFh
13
64
A0000h-AFFFFh
50000h-57FFFh
12
64
C0000h-CFFFFh
60000h-67FFFh
12
64
90000h-9FFFFh
48000h-4FFFFh
11
64
B0000h-BFFFFh
58000h-5FFFFh
11
64
80000h-8FFFFh
40000h-47FFFh
10
64
A0000h-AFFFFh
50000h-57FFFh
10
64
70000h-7FFFFh
38000h-3FFFFh
9
64
90000h-9FFFFh
48000h-4FFFFh
9
64
60000h-6FFFFh
30000h-37FFFh
8
64
80000h-8FFFFh
40000h-47FFFh
8
64
50000h-5FFFFh
28000h-2FFFFh
7
64
70000h-7FFFFh
38000h-3FFFFh
7
64
40000h-4FFFFh
20000h-27FFFh
6
64
60000h-6FFFFh
30000h-37FFFh
6
64
30000h-3FFFFh
18000h-1FFFFh
5
64
50000h-5FFFFh
28000h-2FFFFh
5
64
20000h-2FFFFh
10000h-17FFFh
4
64
40000h-4FFFFh
20000h-27FFFh
4
64
10000h-1FFFFh
08000h-0FFFFh
3
64
30000h-3FFFFh
18000h-1FFFFh
3
32
08000h-0FFFFh
04000h-07FFFh
2
64
20000h-2FFFFh
10000h-17FFFh
2
8
06000h-07FFFh
03000h-03FFFh
1
64
10000h-1FFFFh
08000h-0FFFFh
1
8
04000h-05FFFh
02000h-02FFFh
0
64
00000h-0FFFFh
00000h-07FFFh
0
16
00000h-03FFFh
00000h-01FFFh
28/39
M29F800DT, M29F800DB
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data structure
is read from the memory. Tables 21, 22, 23, 24, 25
and 25 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 64 bit unique security number is written (see Table , Security Code area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security number after it has been written by ST. Issue a Read
command to return to Read mode.
Table 21. Query Structure Overview
Address
Sub-section Name
Description
x16
x8
10h
20h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
36h
System Interface Information
Device timing & voltage information
27h
4Eh
Device Geometry Definition
Flash device layout
40h
80h
Primary Algorithm-specific Extended
Query table
Additional information specific to the Primary
Algorithm (optional)
61h
C2h
Security Code Area
64 bit unique device number
Note: Query data are always presented on the lowest order data outputs.
Table 22. CFI Query Identification String
Address
Data
Description
x16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported
19h
32h
0000h
Address for Alternate Algorithm extended Query table
1Ah
34h
0000h
Value
"Q"
Query Unique ASCII String "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 24)
AMD
Compatible
P = 40h
NA
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
29/39
M29F800DT, M29F800DB
Table 23. CFI Query System Interface Information
Address
Data
Description
Value
x16
x8
1Bh
36h
0045h
VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
4.5V
1Ch
38h
0055h
VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4
BCD value in volts
bit 3 to 0
BCD value in 100 mV
5.5V
1Dh
3Ah
0000h
VPP [Programming] Supply Minimum Program/Erase voltage
NA
1Eh
3Ch
0000h
VPP [Programming] Supply Maximum Program/Erase voltage
NA
1Fh
3Eh
0004h
Typical timeout per single byte/word program = 2n µs
20h
40h
0000h
Typical timeout for minimum size write buffer program = 2n µs
NA
21h
42h
000Ah
Typical timeout per individual block erase = 2n ms
1s
22h
44h
0000h
Typical timeout for full chip erase = 2n ms
23h
46h
0004h
Maximum timeout for byte/word program = 2n times typical
24h
48h
0000h
Maximum timeout for write buffer program = 2n times typical
NA
25h
4Ah
0003h
Maximum timeout per individual block erase = 2n times typical
8s
26h
4Ch
0000h
Maximum timeout for chip erase = 2n times typical
Note: 1. Not supported in the CFI
30/39
16µs
see note (1)
256µs
see note (1)
M29F800DT, M29F800DB
Table 24. Device Geometry Definition
Address
Data
Description
Value
x16
x8
27h
4Eh
0014h
Device Size = 2n in number of bytes
1 MByte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface Code description
x8, x16
Async.
2Ah
2Bh
54h
56h
0000h
0000h
Maximum number of bytes in multi-byte program or page = 2n
NA
2Ch
58h
0004h
Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size.
4
2Dh
2Eh
5Ah
5Ch
0000h
0000h
Region 1 Information
Number of identical size erase block = 0000h+1
1
2Fh
30h
5Eh
60h
0040h
0000h
Region 1 Information
Block size in Region 1 = 0040h * 256 byte
31h
32h
62h
64h
0001h
0000h
Region 2 Information
Number of identical size erase block = 0001h+1
33h
34h
66h
68h
0020h
0000h
Region 2 Information
Block size in Region 2 = 0020h * 256 byte
35h
36h
6Ah
6Ch
0000h
0000h
Region 3 Information
Number of identical size erase block = 0000h+1
37h
38h
6Eh
70h
0080h
0000h
Region 3 Information
Block size in Region 3 = 0080h * 256 byte
39h
3Ah
72h
74h
000Eh
0000h
Region 4 Information
Number of identical-size erase block = 000Eh+1
3Bh
3Ch
76h
78h
0000h
0001h
Region 4 Information
Block size in Region 4 = 0100h * 256 byte
16 Kbyte
2
8 Kbyte
1
32 Kbyte
15
64 Kbyte
31/39
M29F800DT, M29F800DB
Table 25. Primary Algorithm-Specific Extended Query Table
Address
Data
Description
Value
x16
x8
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
"1"
44h
88h
0030h
Minor version number, ASCII
"0"
45h
8Ah
0000h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h
8Ch
0002h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
47h
8Eh
0001h
Block Protection
00 = not supported, x = number of sectors in per group
1
48h
90h
0001h
Temporary Block Unprotect
00 = not supported, 01 = supported
49h
92h
0004h
Block Protect /Unprotect
04 = M29W400B
4Ah
94h
0000h
Simultaneous Operations, 00 = not supported
No
4Bh
96h
0000h
Burst Mode, 00 = not supported, 01 = supported
No
4Ch
98h
0000h
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
No
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"I"
Yes
4
Table 26. Security Code Area
Address
32/39
"R"
Data
x16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Description
64 bit: unique device number
M29F800DT, M29F800DB
APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any operation from modifying the data stored in the Flash.
Each Block can be protected individually. Once
protected, Program and Erase operations on the
block fail to change the data.
There are three techniques that can be used to
control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section.
Unlike the Command Interface of the Program/
Erase Controller, the techniques for protecting and
unprotecting blocks change between different
Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when
changing drivers for one part to work on another.
Programmer Technique
The Programmer technique uses high (V ID) voltage levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a block follow the flowchart in Figure 17,
Programmer Equipment Block Protect Flowchart.
To unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. To unprotect the chip
follow Figure 18, Programmer Equipment Chip
Unprotect Flowchart. Table 27, Programmer
Technique Bus Operations, gives a summary of
each operation.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP. This can be achieved without violating the
maximum ratings of the components on the microprocessor bus, therefore this technique is suitable
for use after the Flash has been fitted to the system.
To protect a block follow the flowchart in Figure 19,
In-System Block Protect Flowchart. To unprotect
the whole chip it is necessary to protect all of the
blocks first, then all the blocks can be unprotected
at the same time. To unprotect the chip follow Figure 20, In-System Chip Unprotect Flowchart.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Table 27. Programmer Technique Bus Operations, BYTE = V IH or VIL
E
G
W
Address Inputs
A0-A18
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block Protect
VIL
VID
VIL Pulse
A9 = VID, A12-A18 Block Address
Others = X
X
Chip Unprotect
VID
VID
VIL Pulse
A9 = VID, A12 = VIH, A15 = VIH
Others = X
X
Block Protection
Verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
A12-A18 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block Unprotection
Verify
VIL
VIL
VIH
A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,
A12-A18 Block Address
Others = X
Retry = XX01h
Pass = XX00h
Operation
33/39
M29F800DT, M29F800DB
Figure 17. Programmer Equipment Block Protect Flowchart
START
Set-up
ADDRESS = BLOCK ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Protect
Wait 4µs
W = VIL
Wait 100µs
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA
NO
=
01h
YES
A9 = VIH
E, G = VIH
++n
= 25
NO
End
YES
PASS
A9 = VIH
E, G = VIH
FAIL
34/39
AI03469
M29F800DT, M29F800DB
Figure 18. Programmer Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Unprotect
Wait 4µs
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1, A6 = VIH
E = VIL
Wait 4µs
G = VIL
INCREMENT
CURRENT BLOCK
Verify
Wait 60ns
Read DATA
NO
End
NO
++n
= 1000
DATA
=
00h
YES
LAST
BLOCK
YES
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
FAIL
PASS
NO
AI03470
35/39
M29F800DT, M29F800DB
Figure 19. In-System Equipment Block Protect Flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
WRITE 60h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 100µs
Verify
WRITE 40h
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 4µs
READ DATA
ADDRESS = BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
DATA
NO
=
01h
YES
End
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI03471
36/39
M29F800DT, M29F800DB
Figure 20. In-System Equipment Chip Unprotect Flowchart
START
Set-up
PROTECT ALL BLOCKS
n=0
CURRENT BLOCK = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT BLOCK ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
NO
End
NO
++n
= 1000
YES
DATA
=
00h
INCREMENT
CURRENT BLOCK
YES
LAST
BLOCK
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI03472
37/39
M29F800DT, M29F800DB
REVISION HISTORY
Table 28. Document Revision History
Date
Version
13-Dec-2001
-01
First Issue
21-Jan-2002
-02
VIH(max) value corrected
01-Mar-2002
-03
Description of Ready/Busy signal clarified (and Figure 14 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
4.0
Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision
version 03 equals 3.0).
Erase Suspend Latency Time (typical) and Data Retention parameters added to Table 6,
Program, Erase Times and Program, Erase Endurance Cycles, and notes added to the
table. Logic Diagram and Data Toggle Flowchart corrected.
Lead-free package options E and F added to Table 18, Ordering Information Scheme.
Document promoted to full datasheet.
17-Feb-2003
38/39
Revision Details
M29F800DT, M29F800DB
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