TI1 LP8727TME-B/NOPB Micro/mini usb interface with integrated 28v charger Datasheet

LP8727
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SNVS898A – OCTOBER 2012 – REVISED MAY 2013
Micro/Mini USB Interface with Integrated 28V Charger
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FEATURES
APPLICATIONS
•
•
1
2
•
•
•
•
•
•
•
USB Multiplexing Switches
– High-Speed USB on USB and UART Inputs
– Negative Voltage Rail on Audio Inputs
– Internal LDO for ID Detection and MIC Bias
– Compatible with USB Charging
Specification Rev. 1.1
– DSS Input for Default Switch Connection
– Low-Power MIC Standby Mode
Linear Charge with Single Input
– 28 OVP on VBUS Input
– High-Current Mode for Production Test
– Thermal Regulation
Over-Voltage Protected LDO for USB
Transceivers and PMU Wakeup
UVLO (Undervoltage Lock Out)
Interrupt Request to Reduce SW Polling
– USB / ID Detection
– SEND / END Button Detection
– Mic Removal
– OVLO / UVLO on VBUS
– Charger Status
Thermal Shutdown Protection
I2C-compatible Serial Interface
25-Bump 0.4 mm Pitch Thin DSBGA Package
•
GSM, GPRS, EDGE, CDMA & WCDMA
handsets
Portable Media Players / MP3 Players
DESCRIPTION
The LP8727 is designed to provide automatic
multiplexing switches between Micro/Mini USB
connector and USB, UART and Audio paths in
cellular phone applications. It also contains a singleinput Li-Ion battery charger and an overvoltageprotected LDO. Programming is handled via an I2Ccompatible Serial Interface allowing control of
charger, multiplexing switches, and reading status
information of the device.
The multiplexing switches on USB and UART support
high-speed USB, and Audio inputs can be driven to
negative voltage rail. The LP8727 is compatible with
USB charging specifications rev 1.1 from USB IF.
The Li-Ion charger requires few external components
and integrates the power FET. Charging is thermally
regulated to obtain the most efficient charging rate for
a given ambient temperature. It has Overvoltage
Protection (OVP) circuit at the charger input protects
the PMU from input voltages up to +28V, eliminating
the need for any external protection circuitry.
An overvoltage-protected LDO which can supply up
to 50 mA is designed for powering up a low-voltage
USB transceiver or waking up a PMU (Power
Management Unit) when an external power source
(either USB VBUS or wall adapter) is connected to
the USB connector.
The LP8727 PMU is available in 25-bump 0.4 mm
pitch thin DSBGA package (2.015 mm x 2.015 mm).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LP8727
SNVS898A – OCTOBER 2012 – REVISED MAY 2013
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Typical Application Diagram
28V Charger
VBUS
VBAT
+
1 F
OSC
Charge
Pump
UVLO
Voltage
Reference
EPROM
Thermal
Shutdown
10 F
-
VCC Supply
50 mA @
4.85V EXPDET
USB LDO
28V OVP
USB Xcvr or
PMU
1 F
LP8727
USB Detection
DN
3.5V
Micro/Mini USB Connector
D-
USB 2.0 High
Speed
DP
USB Charger
Detection
U1
100 k:
UART
U2
D+
C1COMP
AUD1
ID/Ear Jack Detection
AUD2
1.8V
ID
AUDIO
MIC
VCC
1 F
800 k:
200 k:
620:
-
10 k:
1.5 k:
1.5 k:
200 k:
SDA
BB
INT\
DSS
+
Default
Switch
Status
300 k:
-
100 k:
GND
I/O Supply
SCL
Serial Interface
and
Control
+
RES
100:
100:
ADC
CAP
100 k:
2.2 k:
LDO
(2.3V/2.6V)
GND
2
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Connection Diagram
Top View
5
U1
EXPDET
VBAT
VBAT
VBUS
4
U2
SCL
GND
GND
VBUS
3
DP
SDA
GND
DSS
D-
2
DN
INT\
GND
CAP
D+
1
MIC
AUD1
AUD2
RES
ID
A
B
C
D
E
Figure 1. 25-Bump (0.4mm Pitch) DSBGA Package
LP8727 PIN DESCRIPTIONS (1)
(1)
PIN NAME
PIN #
TYPE
AUD1
B1
AI
Stereo Audio input (Left).
DESCRIPTION
AUD2
C1
AI
Stereo Audio input (Right).
CAP
D2
A
Internal LDO output. Connect a 1.0 µF ceramic capacitor to GND.
D-
E3
DI/O
Common data I/O. Connect to D- on Mini / Micro USB connector.
D+
E2
DI/O
Common data I/O. Connect to D+ on Mini / Micro USB connector.
DN
A2
DI/O
USB differential data I/O (-).
DP
A3
DI/O
USB differential data I/O (+).
DSS
D3
A
Default switch status input. Internally pulled down with a 300 kΩ resistor.
Logic high for UART startup and logic low for USB startup.
EXPDET
B5
P
Overvoltage protected LDO output for low-voltage USB system. Connect a 1.0
µF ceramic capacitor to GND.
GND
C2, C3, C4, D4
G
Ground.
ID
E1
DI
USB ID Input. Connect to ID on Mini / Micro USB connector.
INT\
B2
DO
Open-drain output for interrupt, active low. Typ. 10 kΩ pull-up resistor is
required.
MIC
A1
AO
Microphone output.
RES
D1
A
Bias output for ID detection and Microphone. Connect a 2.2 kΩ resistor to ID
pin.
Serial interface clock input. Connect a 1.5 kΩ pullup resistor.
SCL
B4
DI
SDA
B3
DI/O
Serial interface data input/output. Connect a 1.5 kΩ pullup resistor.
U1
A5
DI/O
UART data Rx / USB differential data I/O (-).
U2
A4
DI/O
UART data Tx / USB differential data I/O (+).
VBAT
C5, D5
P
Main battery connection.
Requires 10 µF ceramic capacitor when a battery is not connected.
VBUS
E4, E5
P
USB VBUS input.
A: Analog Pin, D: Digital Pin, I: Input Pin, DI/O Digital Input/Output Pin, G: Ground, O: Output Pin, I/O: Input/Output Pin, P: Power
Connection
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3) (4)
INPUT VOLTAGE
VBUS to GND
−0.3V to +28V
VBAT, EXPDET, CAP [wrt. GND]
−0.3V to +6.0V
SCL, SDA, INT\, DSS [wrt. GND]
−0.3V to (VVBAT+0.3V)
CP_EN = 1
CP_EN = 0
D+, D−, AUD1, AUD2
−2.1V to (VSWPOS) + 0.3V)
DP, DN, U1, U2, ID, MIC, RES
−0.3V to (VSWPOS) + 0.3V)
D+, D−, DP, DN, AUD1, RES
AUD2, U1, U2, ID, MIC
TEMPERATURE
Junction Temperature (TJ-MAX)
Storage Temperature Range
Maximum Lead
Temperature(Soldering, 10 sec.)
(1)
(2)
(3)
(4)
−0.3V to (VCC + 0.3V)
150°C
−65 to 150°C
260°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and
associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Internal thermal shutdown circuitry protects the device fro permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and
disengages at TJ = 130°C. Also engages at 160°C and disengages 115°C.
Operating Ratings (1) (2)
INPUT VOLTAGE
VBAT
2.5V to 5.5V
VBUS
TEMPERATURE
3.5V to 7V
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
4
−40°C to 125°C
−40°C to 85°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits and
associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package resistance is present, the maximum ambient temperature may have to
be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX), The
maximum power dissipation of the device in the application (PD-MAX) and the junction to ambient thermal resistance of the package
(θJA) in the application, as given by the following equation: TA-MAX = TJ-MAX (θJA x PD-MAX). Due to the pulsed nature of testing the
part, the temp in the Electrical Characteristic table is specified as TA = TJ.
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ESD Rating (1)
VBUS, VBAT, D+ D−, ID
IEC61000-4-2 In-module
±8kV Contact Discharge
Testing @ USB Connector
±15kV Air Discharge
Human Body
±2 kV
Machine Model
(1)
±150V
The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is a 200 pF capacitor discharged directly into each
pin, MIL-STD-883 3015.7.
Thermal Properties
Junction-to-Ambient Thermal Resistance (θJA) (1)
Thin DSBGA-25
(1)
46°C
Junction-to-ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation
exists, special care must be given to thermal dissipation issues in board design.
Electrical Characteristics (1) (2)
Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range
(−40°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to the Typical Application Circuit with VVBAT = 3.7V,
VVBUS = 5V.
Min
Max
VVBAT
Symbol
VBAT Voltage Range
Parameter
Conditions
Typ
2.5
5.5
VVBUS
VBUS Voltage Range
3.5
7
VCC
Internal Supply Voltage
VSWPOS
Positive Switch Regulator
VVBAT > 3.6 or VVBUS > 3.6
3.4
3.3
3.6
VSWNEG
Negative Switch Regulator
VVBAT > 3.6 or VVBUS > 3.6
−1.8
−2.0
−1.7
VVBUS = 5V
4.2
VVBUS = 0V
VVBAT
Units
V
V
UNDERVOLTAGE LOCKOUT
UVLOVBUS
Undervoltage Lockout
Threshold range
VBUS Rising (Default)
3.9
3.7
4.1
VBUS Falling (Default)
3.7
3.5
3.9
UVLOVBAT
Undervoltage Lockout
Threshold range
VBAT Rising (Default)
2.9
2.7
3.1
VBAT Falling (Default)
2.7
2.5
2.9
V
QUIESCENT CURRENTS
IVBAT (STBY)
VBAT Standby Iq
CP_EN = ADC_EN = SEMREM = 0
USB_DET_DIS = 1
3.8
20
IVBAT (SUP1)
VBAT Supply Current1
Register Default @ VVBAT = 3.7V
VVBUS = 0V
42
90
IVBAT (SUP2)
VBAT Supply Current2
Register Default @ VVBAT = 3.7V
ADC_EN = SEMREM = 1, VVBUS =
0V
60
120
IVBUS
(STBY)
VBUS Standby Iq
CP_EN = ADC_EN = SEMREM = 0
USB_DET_DIS = CHG_OFF = 1,
EXPDET_EN = 0
90
200
IVBUS
(SUP)
VBUS Supply Current
Register Default @VVBUS = 5V, No
load on VBAT (No battery)
250
400
µA
LOGIC AND CONTROL INPUTS
VIL
Input Low Level
VIH
Input High Level
ILEAK
Input Current
DSSIN
(1)
(2)
Input Resistance
SDA, SCL
0.4
DSS
0.4
SDA, SCL
1.4
DSS
1.4
All logic inputs
Over pin Voltage range
(2)
DSS Pulldown Resistor to GND
-5
V
V
+5
300
µA
kΩ
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
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Electrical Characteristics(1)(2) (continued)
Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range
(−40°C ≤ TJ ≤ +125°C). Unless otherwise noted, specifications apply to the Typical Application Circuit with VVBAT = 3.7V,
VVBUS = 5V.
Symbol
Parameter
Conditions
Typ
Min
Max
Units
LOGIC AND CONTROL OUTPUTS
VOL
Output Low Level
INT\, IOUT = 2mA
0.4
SDA, ISINK = 3mA
0.4
V
ID DETECTION LDO
VOUT
Output Voltage Accuracy
IOUT
Output Current Rating
IOUT = 500 µA, VOUT = 2.3V
IOUT = 500 µA, VOUT = 2.6V
10 Hz ≤ f ≤ 100 kHz
COUT = 1µF (2)
-3
eN
Output Noise Voltage
PSRR
Power Supply Ripple
Rejection Ratio
f = 10 kHz, COUT = 1µF
COUT
External Output Capacitance
for Stability
See (2)
VOUT
Output Voltage Accuracy
IOUT = 1mA, VOUT = 4.85V @ VVBUS
= 5V
VDO
Dropout Voltage
IOUT = 50 mA @ VVBUS = 5V
IOUT(MAX)
Output Current Rating
ISC
Short Circuit Current Limit
VOUT = 0V
330
COUT
External Output Capacitance
for Stability
See (3)
1.0
IOUT = 20 mA (2)
+3
%
1
mA
15
µVRMS
75
dB
1.0
0.6
20
µF
-5
+3
%
EXPDET LDO
(3)
330
mV
50
mA
mA
0.6
20
µF
Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
Multiplexer Switches Electrical Characteristics
Typical values and limits appearing in normal type apply for TJ=25°C. Unless otherwise noted, VVBAT = 3.7V, VBUS is
disconnected. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = −40°C to
+125°C. (1)
Symbol
Parameter
Conditions
VDP,DN
Analog Signal Range
RSWONUSB
On Resistance
ΔRSWONUSB
On Resistance Match
Between Channels
RFLATUSB
On Resistance Flatness
ILEAKUSB(OFF)
Off Leakage Current (2)
ILEAKUSB(ON)
On Leakage Current
Typ
Min
CP_EN = 0
0
VCC
CP_EN = 1
0
VSWPOS
2.5
(2)
Max
Units
V
6
0V < VD+ or VD-< 1V
0.5
Ω
0.5
−360
360
−360
360
CP_EN = 0
0
VCC
CP_EN = 1
0
VSWPOS
0V < VD+ or VD-< 3.3V, CP_EN = 1
nA
UART ANALOG SWITCHES (U1, U2)
VU1,
Analog Signal Range
U2
RSWONART
On Resistance
ΔRSWONART
On Resistance Match
Between Channels
RFLATURT
On Resistance Flatness
(1)
(2)
6
2.5
0V < VD+ or VD-< 1V
V
6
0.5
Ω
0.5
Junction-to-ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation
exists, special care must be given to thermal dissipation issues in board design.
Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
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Multiplexer Switches Electrical Characteristics (continued)
Typical values and limits appearing in normal type apply for TJ=25°C. Unless otherwise noted, VVBAT = 3.7V, VBUS is
disconnected. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = −40°C to
+125°C.(1)
Symbol
Parameter
Conditions
ILEAKUART(OFF)
Off Leakage Current (2)
ILEAKUART(ON)
On Leakage Current (2)
Typ
0V < VD+ or VD-< 3.3V, CP_EN = 1
Min
Max
−360
360
−360
360
Units
nA
AUDIO ANALOG SWITCHES (AUD1, AUD2)
VAUD1,
AUD2
Analog Signal Range
RSWONAUD
On Resistance
ΔRSWONAUD
On Resistance Match
Between Channels
RFLATAUD
On Resistance Flatness
CP_EN = 0
0
VCC
CP_EN = 1
VSWNEG
VSWPOS
1.6
(2)
V
3.6
−1.8V < VD+ or VD-< 1.8V
0.2
Ω
0.5
ILEAKUAUD(OFF)
Off Leakage Current
ILEAKUAUD(ON)
On Leakage Current (2)
−1.8V < VD+ or VD-< 1.8V,
CP_EN = 1
RSHUNT
Shunt Resistor
ISHUNT = 10 mA
100
−360
360
−360
360
30
180
nA
Ω
MIC ANALOG SWITCHES (MIC)
VMIC
Analog Signal Range
RSWONMIC
On Resistance
RFLATMIC
On Resistance Flatness
ILEAKMIC(OFF)
Off Leakage Current (2)
ILEAKMIC(ON)
On Leakage Current (2)
CP_EN = 0
0
VCC
CP_EN = 1
VSWNEG
VSWPOS
3
0V < VID< 1.6V
10
0.8
−360
360
−360
360
V
Ω
nA
DYNAMIC
TCP_EN
Charge Pump Startup Time
TMICLPDP
MIC Low-Power Detection
Pulse Time
TMICLPD
MIC Low-Power Detection
Period
TDEB
Comparator Debounce Time
TONSW
Analog Switch Turn-on Time
TOFFSW
Analog Switch Turn-off Time
TBBM
Break-Before-Make
VISO
Off-Isolation (5)
VCT
Crosstalk
(3)
(4)
(5)
(6)
ms
µs
117
50
175
100
45
155
60
30
100
MIC_LP = 1, SEMREM = 1
ms
1
RL = 50Ω (3) (4)
10
0
RL = 50Ω, CL = 5pF, f= 20 kHz
VD+ or VD-= 1VRMS (6) (4)
−108
f = 20 Hz to 20 kHz, V VD+ or VD-=
0.25VRMS, RL = 30Ω, DC Bias = 0V,
T = 25°C
0.05
Total Harmonic Distortion
Plus Noise MIC
f = 20 Hz to 20 kHz, V VD+ or VD-=
0.4VRMS, RL = 1kΩ, DC Bias = 0.8V,
T = 25°C
0.05
µs
dB
−107
Total Harmonic Distortion
Plus Noise AUD1, AUD2
THD+NAUD
1
%
All timing is measured using 10% and 90% levels.
Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
Off-isolation = 20log [VD+/D− / (VNO1/2or VNC1/2), VD+/D− = output, VNO1/2 or VNC1/2 = input to off switch.
Crosstalk is measured between any two switches.
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Charger Electrical Characteristics
Typical values and limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the entire junction
temperature range (−40°C to +125°C). (1) (2) (3)
Symbol
Parameter
Conditions
Typ
Min
Max
Units
Charger input is turned off if voltage is
above this threshold
6.9
6.7
7.2
V
170
120
220
mV
4.45
6
V
VOV
Over Voltage Protection
Threshold
VOV_HYS
Over Voltage Protection
Threshold Hysteresis
VVBUS
VBUS Operating Range
VOK_CHG
VBUS OK Trip Point
VTERM
Termination Voltage
RDSON_CHG
Charger pass transistor ON
ICHG = 400 mA
resistance
VVBUS - VVBAT (Rising)
250
VVBUS - VVBAT (Falling)
40
VTERM = 4.2V, ICHG = 50 mA
VTERM is measured at 10% of the
programmed ICHG current
mV
−0.35
+0.35
−1
+1
250
%
400
mΩ
VBUS Programmable FullRate Charging Current
4.45V ≤ VVBUS ≤ 6V
VVBAT < VVBUS - VOK_VBUS
VFULL_RATE < VVBAT < VTERM (4)
90
1100
mA
Full-rate charging current
tolerance
ICHG = 400 mA
−5
+5
%
IPRECHG
Pre-charge current
2.2V < VVBAT < VFULL_RATE
80 mA option selected
60
100
mA
IVBUS(MAX)
Maximum Input Current
VVBUS - VVBAT ≤ 0.8V
2.3
A
VFULL_RATE
Full-rate Qualification
Threshold
VVBAT Rising, Transition from Precharge to Full-rate Charging
2.6
2.7
V
IEOC
End-of-charge Current, %
of Full-rate Current
0.1C option selected
10
%
TREG
Regulated Junction
Temperature
115°C option selected (5)
115
°C
ICHG
80
2.5
DETECTION AND TIMING (5)
VVBUSDET
VBUS Detection Threshold
TPOK
Power OK Debounce Time
VVBUS > VVBAT + VOK_CHG
30
TPRE_FULL
Debounce Time from PreCharge to Full-rate
Transition
Pre-charge to full-rate charging
transition
55
TEOC
Debounce Time from CV to
End-of-Charge Transition
TCHG
Charge Safety Timer
(1)
(2)
(3)
(4)
(5)
8
3.5
Pre-charge Mode
3
4
V
ms
400
ms
45
minutes
Junction-to-ambient thermal resistance is highly application and board layout dependent. In applications where high power dissipation
exists, special care must be given to thermal dissipation issues in board design.
Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
The parameters in the electrical characteristic table are tested under open loop conditions at Vbat = 3.7 unless otherwise specified. For
performance over the input voltage range and closed loop condition, refer to the datasheet curves.
The minimum input voltage equals VOUT (nom) + 0.5V or 2.5V, which ever is greater.
Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
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LP8727 Control Registers
I2C-Compatible Slave Address: 7'h27 (6)
DEVICE ID
CONTROL1
POR
DEFAULT
0011xxxx
x0000001
RESV'D
VENDOR ID
ID_2P2
ID_620
0x02
CONTROL2
0000xx01
INTPOL
INT_EN
0x03
SW
CONTROL
x0000000
RESV'D
MIC_ON
0x04
INT_STAT1
00000000
CHGDET
0x05
0x06
0x07
INT_STAT2
STATUS1
STATUS2
CHARGER
CONTROL1
CHARGER
CONTROL2
00000000
00000000
00000000
ADDR
REGISTER
0x00
0x01
0x08
0x09
(6)
010010xx
BIT7
BIT6
MR_
COMP
CHG
TSHD
DCPORT
CHPORT
TMP_STAT
EXPDET
CHG_EN
_EN
0010x001
BIT5
MIC_LP
BIT4
BIT3
ID_200
VLDO
CP_AUD
RESV'D
BIT2
BIT1
CHIP_REV
SEMREN
ADC_EN
RESV'D
CHG_TYP
DP2
SEND/E
VBUS
ND
TMP
OVLO
CHG_STAT
RESV'D
PTM
CHG_OFF
CHG_SET
BIT0
CP_EN
USB_DET_
DIS
DM1
IDNO
UVLO
RESV'D
RESV'D
RESV'D
RESV'D
RESV'D
IPRECHG
RESV'D
RESV'D
RESV'D
RESV'D
RESV'D
C1COMP
RESV'D
RESV'D
RESV'D
IMIN_SET
(Bolded locations are Read-Only Bits.)
Resv'd = Reserved
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DETAILED REGISTER DESCRIPTIONS (1)
ADDR
REGISTER
NAME
0x00
DEVICE ID
BIT NAME
BIT
POR DEFAULT
DESCRIPTION
CHIP_REV
[3:0]
xxxx
Chip revision.
VENDOR ID
[7:4]
0011
Texas Instruments vendor ID.
Enable charge pump for analog switch operation.
CP_EN
0
1
When CP_EN = 0, input signals to the analog switches
should not go below GND.
0: Disable
1: Enable
Enable ID detection LDO and internal ADC.
ADC_EN
1
0
0: Disable
1: Enable
Enable ID detection LDO and SEND/END & MR
comparators.
SEMREN
2
0
0: Disable
1: Enable
ID detection LDO voltage setting.
VLDO
0x01
3
0
CONTROL1
0: 2.3V
1: 2.6V
Connect ID detection LDO to ID pin through an internal
200 kΩ resistor.
ID_200
4
0
0: Disable
1: Enable
Connect ID detection LDO to ID pin through an internal
620Ω resistor.
ID_620
5
0
0: Disable
1: Enable
ID_2P2
6
0
Connect ID detection LDO to RES output for
microphone biasing. A 2.2 kΩ external resistor is
required between RES and ID pins.
0: Disable
1: Enable
RESERVED
(1)
10
7
x
Not used.
Bolded entries are read-only.
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ADDR
SNVS898A – OCTOBER 2012 – REVISED MAY 2013
REGISTER
NAME
BIT NAME
BIT
POR DEFAULT
DESCRIPTION
Disable USB charger detection.
USB_DET_DIS
0
1
0: Enable
1: Disable
Enable charger type detection. CHG_TYP will be
automatically set to 0 at the end of detection sequence.
CHG_TYP
1
0
0: Disable
1: Enable
RESERVED
[3:2]
xx
Not used.
Enable internal 100Ω pull-down resistors on AUD1 and
AUD2.
CP_AUD
0x02
4
0
CONTROL2
0: Disable
1: Enable
Enable microphone low-power mode.
MIC_LP
5
0
0: Disable
1: Enable
Enable interrupt output. When disabled, INT\ output will
be masked and pending interrupts will not be cleared.
INT_EN
6
0
0: Disable
1: Enable
Interrupt polarity setting.
INTPOL
7
0
0: Active low
1: Active high
Set the switch connection to D- pin.
000: D- pin is connected to DN pin.
001: D- pin is connected to U1 pin.
DM1
[2:0]
000
010: D- pin is connected to AUD1 pin.
011: D- pin is connected to C1COMP.
100: D- pin is connected to DN pin regardless of VBUS
101 to 111: Hi-Z
Set the switch connection to D+ pin.
0x03
000: D+ pin is connected to DP pin.
SW CONTROL
001: D+ pin is connected to U2 pin.
DP2
[5:3]
000
010: D+ pin is connected to AUD2 pin.
011: Hi-Z
100: D+ pin is connected to DP pin regardless of VBUS
101 to 111: Hi-Z
Connect MIC pin to ID pin.
MIC_ON
6
0
RESERVED
7
x
0: Disable
1: Enable
Not used.
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ADDR
REGISTER
NAME
BIT NAME
IDNO
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BIT
[3:0]
POR DEFAULT
DESCRIPTION
0000
ADC output with 200 kΩ / 2.2 kΩ / 620Ω of pullup
resistor (Activated only when ADC_EN = '1'). Change of
IDNO state will trigger assertion of INT\ output.
(Refer to Table 1)
VBUS comparator output. Change of VBUS state will
trigger assertion of INT output.
VBUS
4
0
0: VVBUS < VVBUSDET
1: VVBUS > VVBUSDET
0x04
INT_STAT1
SEND/END
5
0
SE comparator output (Activated only when SEMREN =
'1). Change of SEND/END state will trigger assertion of
INT\ output.
0: VMIC > VSEND/END
1: VMIC < VSEND/END
MR_COMP
6
0
MR comparator output (Activated only when SEMREN =
'1'). Change of MR_COMP state will trigger assertion of
INT\ output.
0: VMIC < VMR_COMP
1: VMIC > VMR_COMP
Charger detection is completed. Change of CHG_DET
state will trigger assertion of INT\ output.
CHG_DET
7
0
0: VBUS is not present or no charger is detected.
1: Charger is detected.
0x05
INT_STAT2
RESERVED
[2:0]
000
UVLO
3
0
OVLO
4
0
TMP
5
0
TSHD
6
0
CHG
7
0
C1COMP
0
0
RESERVED
[3:1]
000
Not used.
0: VVBUS > UVLOUSB
1: VVBUS < UVLOUSB
0: VVBUS < VOV
1: VVBUS > VOV
0: TMP_STAT state is not changed.
1: TMP_STAT state is changed.
0: Thermal shutdown is not triggered.
1: Thermal shutdown is triggered.
0: CHG_STAT state is not changed.
1: CHG_STAT state is changed.
C1COMP output.
0: VD-< VD-DET
1: VD-> VD-DET
Not used.
Charger status.
00: Pre-charge
0x06
STATUS1
CHG_STAT
[5:4]
00
01: CC
10: CV
11: EOC
12
CHPORT
6
0
DCPORT
7
0
0: High-current USB Host/Hub is not detected.
1: High-current USB Host/Hub is detected.
0: Dedicated charger is not detected.
1: Dedicated charger is detected.
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ADDR
SNVS898A – OCTOBER 2012 – REVISED MAY 2013
REGISTER
NAME
BIT NAME
BIT
POR DEFAULT
RESERVED
[4:0]
00000
DESCRIPTION
Not used.
Die temperature.
000: 75°C
001: 95°C
0x07
STATUS2
010: 115°C
TMP_STAT
[7:5]
000
011: 135°C
100: Reserved
101: Reserved
110: Reserved
111: Reserved
RESERVED
[1:0]
xx
Not used.
Pre-charge current setting.
00: 40 mA
IPRECHG
[3:2]
10
01: 60 mA
10: 80 mA
11: 100 mA
Charger block disable.
CHG_OFF
0x08
4
0
0: Enable
1: Disable
CHARGER
CONTROL1
Enable PTM (Production Test Mode).
PTM
5
0
0: Disable
1: Enable
Enable EXPDET LDO.
EXPDET_EN
6
1
0: Disable
1: Enable
Charger stop / start control.
CHG_EN
7
0
0: Stop charging (Force EOC).
1: Start charging (Restart).
EOC level setting.
000: 5%
001: 10%
IMIN_SET
[2:0]
001
010: 16%
011: 20%
100: 25%
101: 33%
110: 50%
RESERVED
0x09
3
x
Not used.
Charging current setting.
CHARGER
CONTROL2
0000: 90 mA
0001: 100 mA
0010: 400 mA
0011: 450 mA
CHG_SET
[7:4]
0010
0100: 500 mA
0101: 600 mA
0110: 700 mA
0111: 800 mA
1000: 900 mA
1001: 1000 mA
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Operation Description
MULTIPLEXING SWITCHES
The LP8727 supports USB High-speed, UART and stereo audio & microphone by providing automatic
multiplexing switches between Micro/Mini USB connector and USB, UART and Audio paths in cellular phone
applications. The LP8727 detects the external devices which can be connected to Micro/Mini USB connector and
informs the processor the detection result by generating an interrupt. But, the LP8727 does not automatically
change the state of switch mux when the external device is detected. The processor is responsible to change the
state of switch mux via I2C.
Micro/Mini USB Connector
VBUS
DL SPK
D+
R SPK
ID
MIC
SEND
/END
12 pF
ZIN = 2.2k:
GND
Figure 2. Stereo Audio & MIC Connection
DEFAULT SWITCH STATUS
The LP8727 can configure default switch connection at startup to either USB or UART by the DSS input. The
DSS input has a 300 kΩ of internal pulldown resistor. When DSS is logic low (connected to GND or left floating),
the default switch connection is set to USB. For UART startup, the DSS should be pulled high to VBAT through
an external 300 kΩ pull-up resistor. The status of DSS input is monitored from the startup of device and will be
latched at the first rising edge of SCL input. The status of DSS input is monitored and latched at the 1st rising
edge of sCL input.
HIGH-IMPEDANCE MODE
If the LP8727 is powered from VBAT (VBUS is not present), the default switch connections for D+, D- and ID
should be Hi-Z regardless of DSS status until USB & ID detection is done. The high-impedance mode should
also be controlled via I2C.
LOW-POWER MODE
The LP8727 is designed to support low-power modes by CP_EN, ADC_EN and SEMREN bits on CONTROL1
register. The ID detection LDO is controlled by either ADC_EN or SEMREN bits.
• CP_EN: When CP_EN bit is set to ‘1’, the charge pump is enabled and this allows the audio signal inputs
(AUD1 and AUD2) to be driven to negative voltage rail.
• ADC_EN: When ADC_EN bit is set to ‘1’, ID detection LDO and the internal ADC are enabled. When
ADC_EN is ‘0’, IDNO bits (ADC output) will be 4’h0000 and INT\ will not be asserted. Any pending interrupts
due to a change in the ADC output will not be cleared and must be cleared manually by reading INT_STATx
registers.
• SEMREN: When SEMREN bit is set to ‘1’, ID detection LDO and the internal comparators for SEND/END and
microphone removal detections are enabled. When SEMREN is ‘0’, the SEND/END and MR_COMP registers
will be set to ‘0’ and INT\ will not be asserted. Any pending interrupts due to a change in the SEND/END or
MR_COMP comparators will not be cleared and must be cleared manually by reading INT_STATx registers.
14
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SEND/END BUTTON AND MICROPHONE REMOVAL DETECTION
The LP8727 supports SEND/END button and microphone removal detection features by monitoring voltage on ID
pin. When the microphone is connected to ID pin, it is biased by RES output through an external 2.2 kΩ resistor.
In the event of removal of the microphone, the voltage on ID pin will go as high as the bias voltage which is
typically 2.3V, and this event will be detected by a comparator. The threshold for microphone removal detection
will be set to 90% of the bias voltage.
Headset accessories have a push button switch (SEND/END) between the ID pin and GND. In case that
SEND/END button is pressed, the voltage on ID pin will drop down to GND potential, and an internal comparator
is used to detect this event. The typical threshold of SEND/END button detection is set to 10% of the bias
voltage.
Both cases will generate interrupts to the host processor.
MICROPHONE LOW-POWER MODE
When the microphone is connected, it is powered from RES output through an external 2.2 kΩ (typ.) resistor. In
case that the microphone is connected but not active, the LP8727 allows reducing the power dissipation at the
microphone, while it is still supporting SEND/END button and microphone removal detection.
During the microphone low-power mode, the internal 200 kΩ resistor will be turned on for immediate microphone
removal detection, and RES output will cycling ON and OFF with a short period of time for SEND/END detection.
The microphone low-power mode is enabled by MIC_LP bit, and interrupts will be generated by SEND/END and
MR_COMP events.
100 k:
LDO
(2.3V/2/6V)
2.2 k:
200 k:
+
800 k:
MR_COMP
PULSE
GENERATOR
MIC
SEND
/END
SEND/END
12 pF
100 k:
+
Figure 3. MIC Low-Power Operation
EXPDET LDO
The EXPDET is overvoltage protected LDO output for low-voltage USB transceiver on the processor, or it can be
used as a startup trigger signal for the PMU.
The EXPDET LDO is directly powered from VBUS and can withstand up to 28V. The typical output voltage is set
to 4.85V and it is designed to supply up to 50 mA. For stable operation, a 1μF ceramic capacitor is required at
the output.
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INTERRUPT STATUS
The LP8727 has 2 interrupt status registers, INT_STAT1 and INT_STAT2. These interrupt conditions are
generated from VBUS comparator, D+/D− & ID detection, changes of SEND/END & MR_COMP states and
charger events. When any of these interrupt conditions occur, then the open drain output (INT\) will be brought
low. This signals to the BB processor that an interrupt has occurred. The BB processor will then read all two
INT_STAT1 and INT_STAT2 registers sequentially through the serial interface to determine which bit caused the
interrupt. Once the status register indicates the actual interrupt condition starts to be read, the INT\ output will be
brought high immediately. However, INT_STAT1 and INT_STAT2 registers will not be cleared after being read by
the BB processor and will always represent the current status.
INT\ OUTPUT
A serial interface read of each of the interrupt status registers immediately pulls up INT\ output. If an interrupt is
captured during a read sequence, the INT\ will not go low until at least 24 serial clocks (SCL) have occurred. Any
pending interrupts will be cleared once the LP8727 goes into SHUTDOWN mode.
DEVICE STATUS
The LP8727 has 2 device status registers, STATUS1 and STATUS2. These registers can be read via the serial
interface in much the same way as the interrupt status registers.
These registers will not be cleared on a read and will always represent the current state.
Device Identification
The LP8727 can recognize various accessories attached to Micro/Mini USB connector by detecting VBUS, D+,
D− and ID pins. The detection comparators have a 60 ms of debounce timer. The device identification flow is
shown in Figure 4.
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START
DEVICE PLUG-IN
ID DETECTION
(200k: PULL-UP)
YES
ADC = 0000?
NO
YES
ADC = 1011?
SWITCH to 2.2k:
PULL-UP
NO
USB DETECTION
PRODUCTION
TEST MODE
(USB)
YES
PRODUCTION
TEST MODE
(UART)
YES
NO
ADC = 0010?
NO
ADC = 0100?
EAR JACK
DETECTED
ADC = 0000?
YES
SWITCH to 620:
PULL-UP
NO
YES
DCPORT = 1?
DEDICATED
CHARGER
DETECTED
REFER TO
DEVICE ID INDEX
YES
ADC = 0000?
USB OTG
DETECTED
NO
NO
YES
CHPORT = 1?
USB HOST/HUB
CHARGER
DETECTED
NO
RETURN
Figure 4. Device Identification Diagram
ID DETECTION
When the external device is connected to Micro/Mini USB connector, the LP8727 reads the voltage of ID pin
using an ADC while the ID pin is pulled up to the output of ID DETECTION LDO (typ. 2.3V) through the internal
200 kΩ resistor. If ADC value code is 4’h0000, the LP8727 will change the pullup resistor from 200 kΩ to 2.2 kΩ
and eventually to 620Ω step-by-step for detecting microphone and USB OTG. In case that the first ADC reading
gives 4’h1011, then the LP8727 will start USB detection according to USB Battery Charging Specification
Revision 1.1.
Table 1. Device Indentification Index
ADC VALUE
ADC VOLTAGE
ID RESISTOR
[kΩ]
D+ CONDITION
D−CONDITION
VBUS [V]
FUNCTION
DETECTION VALUES with 200 kΩ PULL-UP RESISTOR
1011
100%
OPEN
15 kΩ to GND
15 kΩ to GND
5
USB Cable
1011
100%
OPEN
Shorted to D−
Shorted to D+
5.6
TA Charger
1010
81.90%
910
Reserved
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Table 1. Device Indentification Index (continued)
ADC VALUE
ADC VOLTAGE
ID RESISTOR
[kΩ]
1001
75.60%
620
Reserved
1000
68.20%
430
Reserved
0111
62.20%
330
Reserved
0110
54.50%
240
Reserved
5
TA for North
America
D+ CONDITION
D−CONDITION
VBUS [V]
FUNCTION
0101
47.40%
180
0100
39.40%
130
0011
33.30%
100
0010
21.90%
56
0001
12.50%
28.7
0000
0%
MIC
Speaker
Speaker
Microphone
0000
0%
GND
D+
D-
USB OTG
TX
RX
5
UART (Factory)
D+
D-
5
USB (Factory)
Reserved
VZW
DETECTION VALUES with 2.2 kΩ PULL-UP RESISTOR
1011 to 1000
100% to 68.2%
Reserved
0111 to 0100
62.2% to 39.4%
Typical Microphone
001 to 0001
33.3% to 12.5%
0000
0%
Reserved
GND
D+
D-
USB OTG
D+
D−
USB OTG
DETECTION VALUES with 620Ω PULL-UP RESISTOR
1011 to 0001
100% to 12.5%
0000
0%
Reserved
GND
USB DETECTION
The LP8727 can detect dedicated charger, standard downstream port and charging downstream port based on
USB Battery Charging Specification Revision 1.1. In order to avoid false detection before data (D+ and D−)
connection, the LP8727 supports ‘Data Contact Detect’ feature.
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USB Eye Diagram (480 MHz)
UART Eye Diagram (480 MHz)
Figure 5.
Figure 6.
USB Frequency Response (10 MHz - 1GHz)
20
UART Frequency Response (10 MHz - 1GHz)
20
0
0
-20
-20
dB
dB
Operating Characteristics
-40
-40
-60
-60
On Loss
Off Isolation
Crosstalk
-80
-100
10
On Loss
Off Isolation
Crosstalk
-80
-100
100
MHz
Figure 7.
1k
10
Audio Frequency Response (10 MHz - 1GHz)
20
10
0
100
MHz
Figure 8.
1k
AUD1 THD+N (RL = 30Ω)
1
0.1
(%)
dB
-20
-40
0.01
-60
On Loss
Off Isolation
Crosstalk
-80
-100
10
100
MHz
1k
0.001
0.0001
20
50 100 200 500 1k 2k
5k 10k 20k
(Hz)
Figure 9.
Figure 10.
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Operating Characteristics (continued)
AUD2 THD+N (RL = 30Ω)
10
1
(%)
0.1
0.01
0.001
0.0001
20
50 100 200 500 1k 2k
5k 10k 20k
(Hz)
Figure 11.
20
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SINGLE INPUT LINEAR CHARGER
The LP8727 has a built-in Li-Ion/Li-Poly battery management system. Its main features are:
• Single-input linear charger
• Wide array of battery charging current options
• Flexible charging cycle control
• Thermal regulation
• Safety timer in Pre-charge mode
BATTERY CHARGER FUNCTION
A charge management system allowing safe charge and maintenance of a Li-Ion battery is implemented on the
LP8727.
Following the correct detection of a voltage at the charger input, the charger enters pre-charge mode. In this
mode the battery is charged with a small constant current. Pre-charge settings are available in register 0x08, and
these values are remembered as long as the LP8727 is on. IPRECHG bits select the battery current in pre-charge
mode. If battery reaches the level set by VFULLRATE, then the charger will move on to full charging mode.
TPRECHARGE sets the maximum pre-charge time, after which the battery will be isolated, protecting it from further
charging.
In full charging mode full-rate constant current is applied to the battery, to raise the voltage to the termination
level. The charging current is programmable via CHG_SET bits. When termination voltage is reached, the
charger is in constant voltage mode, and a constant voltage is maintained. After reaching the end-of-charge
condition, the charge management isolates the battery and enters the maintenance mode.
Maintenance mode enables the battery voltage to be maintained at the correct level. If restart conditions have
been met, then the charge cycle is re-initiated to re-establish the termination voltage level.
END-OF-CHARGE AND RESTART
When EOC condition is met, the LP8727 will generate an interrupt to the processor and the processor is
responsible to control the charger operation (top-off or maintenance mode) via I2C.
Once the charger goes into maintenance mode (stop charging), the processor is also responsible for monitoring
the battery voltage and restarting the charger when the battery voltage drops to restart voltage.
PRODUCTION TEST MODE (PTM)
When PTM bit is set, then the charger enters special high-load mode. In this mode the charger should be able to
supply up to 2.3A.
OVER-VOLTAGE PROTECTION
A built-in over-voltage protection (OVP) ensures that the charger can withstand high voltages (up to 28V) on
VBUS input. When VBUS voltage exceeds the OVP threshold (typ. 6.9V), the charger operation is disabled in
order to protect the charger from breakdown. When VBUS voltage drops below the OVP threshold, the charger
automatically resumes its charging function.
THERMAL REGULATION
When the die temperature of the charger reaches the thermal regulation threshold (typ. 115°C), the thermal
regulation loop dynamically reduces the charging current to prevent the charger from being overheated. As the
die temperature drops below the thermal regulation threshold, the charging current will be automatically
increased back to the programmed charging current setting.
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Transition to Constant
Voltage-mode
Battery Voltage
Pre-Charge to Full-Rate
Charge Transition
Restart
VTERM
VRESTART
Pre-Charge
Mode
Constant Current
Mode
Constant
Voltage Mode
Maintenance
Mode
CHARGING CURRENT
BATTERY VOLTAGE
Full-Rate
Current
Charging
Current
VFULLRATE
End-of-Charge
IEOC
IPRECHG
TIME
Figure 12. Li-Ion Charging Profile
Charger Input Out-of-Range
CHARGER OFF
(VBUS > VIN_OV) OR (VBUS < VIN_LV)
(IBATT = 0)
Charger Input In-Range (VIN_OV > VBUS > VIN_LV)
AND Wait 40 ms for Charger Services
PRE-CHARGE
[CC MODE]
(Max. IBATT = IPRECHG)
Restart Condition
VBATT > VFULLRATE
Pre-charge Timeout
VBATT < VFULLRATE
FULL-RATE CHARGE
[CC MODE]
MAINTENANCE
(IBATT = 0)
BAD BATTERY
(IBATT = 0)
(Max. IBATT = ICHG)
EOC Condition OR
Fullrate Charge Timeout
VBATT = VTERM
Charger Settings:
- IPRECHG: 80 mA
FULL-RATE CHARGE
[CV MODE]
(VBATT = VTERM)
- VFULLRATE: 2.6V
- VTERM: 4.2V
- ICHG: 400 mA
- IEOC: 10% of ICHG
Safety Timer:
- Pre-charge: 45 min
Figure 13. Charger Operation Diagram
UVLO Operation
UVLO measures system voltages on VBUS and VBAT inputs and compares it to selected voltages. The function
uses 2 comparators. These comparators are combined into UVLO_N state, which can affect startup, cause
shutdown or generate interrupt. UVLO_N state can change on following conditions:
• If system voltage is lower than UVLO and OPVM, then UVLO_N state is set to '0'; and
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If system voltage is higher than UVLO and OPVM, then UVLO_N state is set to '1'.
Using different values for UVLO and OPVM provides a window for voltage drops under high-load working
conditions.
UVLO_N state '0' indicates that the voltage is below normal working range, so the system is not allowed to start
up. This state can also cause the system to shut down.
UVLO_N state '1' indicates that the voltage is in normal working range, so the system is allowed to start up and
operate.
State transition '1' → '0' causes an UVLO interrupt, which can be sent to INT\ output.
Support Functions
REFERENCE
The LP8727 has internal reference block creating all necessary references and biasing for all blocks.
OSCILLATOR
There is internal oscillator giving clock to the logic control.
VVBAT = 3.7V
PARAMETER
Oscillator Frequency
TYP
MIN
MAX
UNIT
31
29
33
kHz
THERMAL SHUTDOWN
The thermal shutdown (TSHD) function monitors the chip temperature to protect the chip from temperature
damage caused by excessive power dissipation. When the chip temperature exceeds 160°C, “1” is written to
TSHD bit on INT_STAT2 register and INT\ is pulled to low and then the LP8727 will initiates SHUTDOWN. The
STARTUP operation after TSHD trigger can be initiated only after the chip has cooled down to the +115°C
threshold.
(1)
PARAMETER
TYP
TSDH (1)
160
TSDH Hysteresis (1)
45
UNIT
°C
specified by design.
CHIP TEMPERATURE MONITOR
The LP8727 supports the chip temperature monitoring feature. When the chip temperature reaches each
temperature threshold, TMP bit on INT_STAT2 will be set to “1”, and it will pull INT\ output low. The chip
temperature can be obtained by reading TMP_STAT bits on STATUS2 register.
TMP_STAT
000
001
010
011
TEMPERATURE
75°C
95°C
115°C
125°C
I2C-Compatible Serial Bus Interface
INTERFACE BUS OVERVIEW
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device.
This protocol uses a two-wire interface for bi-directional communications between the ICs connected to the bus.
The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be
connected to a positive supply, via a pull-up resistor of 1.5 kΩ and remain HIGH even when the bus is idle.
Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on
whether it generates or receives the SCL.
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DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL.
Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the SDA line
during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data
should be sent during the low SCL state. This protocol permits a single data line to transfer both
command/control information and data using the synchronous serial clock.
SDA
SCL
Data Line
Stable:
Data Valid
Change
of Data
Allowed
Figure 14. Bit Transfer
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a
Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following
sections provide further details of this process.
START AND STOP
The Master device on the bus always generates the Start-and-Stop Conditions (control codes). After a Start
Condition is generated, the bus is considered busy, and it retains this status until a certain time after a Stop
Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a
Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 15. Start-and-Stop Conditions
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.
This allows another device to be accessed, or a register read cycle.
ACKNOWLEDGE CYCLE
The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge
clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go
high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the
acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus
signaling the correct reception of the last data byte and its readiness to receive the next byte.
24
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SNVS898A – OCTOBER 2012 – REVISED MAY 2013
Data
Output By
Transmitter
Transmitter Stays Off the
Bus During the
Acknowledgement Clock
Data
Output By
Receiver
Acknowledgement Signal
from Receiver
SCL
1
2
3-6
7
8
9
S
Start Condition
Figure 16. Bus Acknowledge Cycle
”ACKNOWLEDGE AFTER EVERY BYTE” RULE
The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge
signal after every byte received.
There is one exception to the “acknowledge after every byte” rule.
When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging
(“negative acknowledge”) the last byte clocked out of the slave. This “negative acknowledge” still includes the
acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.
ADDRESSING TRANSFER FORMATS
Each device on the bus has a unique slave address. The slave address of the LP8727 is 7’h27 (0100111).
Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device
should send an acknowledge signal on the SDA line, once it recognizes its address.
The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends
on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the
system compares this slave address with its own. If there is a match, the device considers itself addressed and
sends an acknowledge signal. Depending upon the state of the R/W bit (1: Read, 0: Write), the device acts as a
transmitter or a receiver.
CONTROL REGISTER WRITE CYCLE
• Master device generates start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master sends data byte to be written to the addressed register.
• Slave sends acknowledge signal.
• If master will send further data bytes the control register address will be incremented by one after
acknowledge signal.
• Write cycle ends when the master creates stop condition.
CONTROL REGISTER READ CYCLE
• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (r/w = '0').
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (r/w = “1”).
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•
•
•
•
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Slave sends acknowledge signal if the slave address is correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control register address will be incremented by one. Slave
device sends data byte from addressed register.
Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop
condition.
Address Mode
Data Read
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = ‘1’>[Ack]
[Register Data]<Ack or NAck>
… additional reads from subsequent register address possible
<Stop Condition>
Data Write
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent register address possible
<Stop Condition>
< > Data from master
[ ] Data from slave
REGISTER READ AND WRITE DETAIL
S
Slave Address
(7 bits)
'0' A
Control Register Add.
(8 bits)
Register Data
(8 bits)
A
A P
Data transferred, byte +
Ack
R/W
From Slave to Master
A - ACKNOWLEDGE (SDA Low)
S - START CONDITION
From Master to Slave
P - STOP CONDITION
Figure 17. Register Write Format
S
Slave Address
(7 bits)
'0' A
Control Register Add.
(8 bits)
A Sr
Slave Address
(7 bits)
R/W
'1' A
R/W
Register Data
(8 bits)
A/
P
NA
Data transferred, byte +
Ack/NAck
Direction of the transfer
will change at this point
From Slave to Master
A - ACKNOWLEDGE (SDA Low)
NA - ACKNOWLEDGE (SDA High)
From Master to Slave
S - START CONDITION
Sr - REPEATED START CONDITION
P - STOP CONDITION
Figure 18. Register Read Format
26
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SNVS898A – OCTOBER 2012 – REVISED MAY 2013
REVISION HISTORY
Changes from Original (May 2013) to Revision A
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 26
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PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LP8727TME-B/NOPB
ACTIVE
DSBGA
YFQ
25
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
27-B
LP8727TME/NOPB
ACTIVE
DSBGA
YFQ
25
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8727
LP8727TMX-B/NOPB
ACTIVE
DSBGA
YFQ
25
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
27-B
LP8727TMX/NOPB
ACTIVE
DSBGA
YFQ
25
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8727
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LP8727TME-B/NOPB
DSBGA
YFQ
25
250
178.0
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.08
2.08
0.76
4.0
8.0
Q1
LP8727TME/NOPB
DSBGA
YFQ
25
250
178.0
8.4
2.08
2.08
0.76
4.0
8.0
Q1
LP8727TMX-B/NOPB
DSBGA
YFQ
25
3000
178.0
8.4
2.08
2.08
0.76
4.0
8.0
Q1
LP8727TMX/NOPB
DSBGA
YFQ
25
3000
178.0
8.4
2.08
2.08
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP8727TME-B/NOPB
DSBGA
YFQ
25
250
210.0
185.0
35.0
LP8727TME/NOPB
DSBGA
YFQ
25
250
210.0
185.0
35.0
LP8727TMX-B/NOPB
DSBGA
YFQ
25
3000
210.0
185.0
35.0
LP8727TMX/NOPB
DSBGA
YFQ
25
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YFQ0025xxx
D
0.600
±0.075
E
TMD25XXX (Rev C)
D: Max = 2.04 mm, Min = 1.98 mm
E: Max = 2.04 mm, Min = 1.98 mm
4215084/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
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12/12
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