MX66C1024 5V Low Power CMOS SRAM 128 x 8 Bit n FEATURES n DESCRIPTION • Vcc operation voltage : 5V • Low power consumption : 45mA (Max.) write current 2mA (Max.) read current 0.6uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) -10 100ns (Max.) • Input levels are CMOS-compatible • Automatic power down when chip is deselected • Three state outputs • Fully static operation • Data retention supply voltage as low as 1.2V • Easy expansion with CE2, CE1, and OE options The MX66C1024 is a high performance, extremely low power CMOS Static Random Access Memory organized as 131,072 words by 8 bits and operates at 5.0V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.005uA and maximum access time of 70ns and 100ns Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The MX66C1024 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The MX66C1024 is available in the JEDEC standard 32 pin SOP, STSOP and TSOP. n PIN CONFIGURATIONS P/N DS00040 1 2 3 4 5 6 7 8 MX66C1024MC 9 MX66C1024MI 10 11 12 13 14 15 16 • A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 • NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MX66C1024TC MX66C1024SC MX66C1024TI MX66C1024SI n BLOCK DIAGRAM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A6 A7 A12 A14 A16 A15 A13 A8 A9 A11 Address 20 Row 1024 Memory Array Input Buffer 1024 x 1024 Decoder 1024 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 CE2 CE1 WE OE Vdd Gnd 1 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com 8 8 Data Input Buffer Data Output Buffer Column I/O 8 Write Driver Sense Amp 8 128 Column Decoder 14 Control Address Input Buffer A5 A4 A3 A2 A1 A0 A10 Rev. 1.0, November 1999 MX66C1024 n PIN DESCRIPTIONS Name Function A0-A16 Address Input These 17 address input select one of the 131,072 x 8-bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0 – DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground n TRUTH TABLE MODE WE CE1 CE2 OE Not selected (Power Down) X H X X I/O OPERATION Vcc CURRENT X X L X High Z ICCSB, ICCSB1 Output Disabled H L H Read H L H H High Z ICC L D OUT ICC Write L L H X DIN ICC n ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER with n OPERATING RANGE RATING UNITS -0.5 to +7.0 V RANGE AMBIENT TEMPERATURE C Commercial 0 C to +70 C C Industrial -40 C to +70 C VTERM Terminal Voltage Respect to GND TBIAS Temperature Under Bias -40 to +125 O TSTG Storage Temperature -60 to +150 O PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA P/N DS00040 2 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com O O O n CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. O CIN CDQ PARAMETER Input Capacitance Input/Output Capacitance CONDITIONS MAX. UNIT VIN=0V 6 pF VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. Rev. 1.0, November 1999 MX66C1024 n DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC ) PARAMETER NAME VIL VIH IIL PARAMETER MIN. TYP. (1) MAX. TEST CONDITIONS Guaranteed Input Low (2) Voltage Guaranteed Input High (2) Voltage Input Leakage Current IOL Output Leakage Current Vcc = Max, CE1= V , CE2= V or OE = VIH, VI/O = 0V to Vcc -- 0.8 V 2.2 -- Vcc+0.5 V -- -- 1 uA -- -- 1 uA IL, VOL Output Low Voltage Vcc = Max, IOL = 1mA VOH Output High Voltage Vcc = Min, IOH = -0.5mA ICC Operating Power Supply Current ICCSB Standby Power Supply Current ICCSB1 Power Down Current CE1 = V , or CE2 = V , Vcc = 5.0 V (3) IDQ = 0mA, F = Fmax CE1 = VIH, or CE2 = VIL, Vcc = 5.0 V (3) IDQ = 0mA, F = Fmax > Vcc-0.2V, CE2 <= 0.2V, CE1 = < VIN > = Vcc-0.2V or VIN = 0.2V Supply -0.5 Vcc = Max, VIN = 0V to Vcc IH IL UNITS -- -- 0.4 V 2.4 -- -- V -- -- 45 mA -- -- 2 mA -- 0.6 3 uA IH 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC . n DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC ) SYMBOL PARAMETER VDR Vcc for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR TEST CONDITIONS < CE1 > = Vcc - 0.2V, CE2 = 0.2V, VIN > Vcc - 0.2V or VIN<= 0.2V = < CE1 > = Vcc - 0.2V, CE2 = 0.2V, VIN > = Vcc - 0.2V or VIN <= 0.2V MIN. TYP. (1) MAX. UNITS 1.2 -- -- V -- 0.005 0.2 uA 0 -- -- ns -- -- ns See Retention Waveform Operation Recovery Time TRC (2) 25OC 1. Vcc = 1.5V, TA = + 2. tRC = Read Cycle Time n LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) Data Retention Mode Vcc VDR ≥ 1.2V Vcc Vcc tR t CDR CE ≥ Vcc - 0.2V VIH VIH CE n LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) Data Retention Mode Vcc VDR ≥ 1.2V Vcc Vcc tR t CDR CE2 ≤ 0.2V VIH VIH CE2 P/N DS00040 3 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 MX66C1024 n KEY TO SWITCHING WAVEFORMS n AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Vcc/0V 5ns WAVEFORM 0.5Vcc n AC TEST LOADS AND WAVEFORMS 1000 Ω 1000 Ω 5.0V 5.0V OUTPUT OUTPUT INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H , 100PF INCLUDING JIG AND SCOPE 5PF INCLUDING JIG AND SCOPE 1500 Ω 1500 Ω FIGURE 1A FIGURE 1B DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE THEVENIN EQUIVALENT 600 Ω OUTPUT 0.9V ALL INPUT PULSES Vcc 10% 90% 90% 10% GND → ← → ← 5ns FIGURE 2 n AC ELECTRICAL CHARACTERISTICS (over the operating range) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION MX66C1024-70 MIN. TYP. MAX. MX66C1024-10 MIN. TYP. MAX. 70 -- -- 100 -- -- ns UNIT tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time -- -- 70 -- -- 100 ns tE1LQV tACS1 Chip Select Access Time (CE1) -- -- 70 -- -- 100 ns tE2HOV tACS2 Chip Select Access Time (CE2) -- -- 70 -- -- 100 ns tGLQV tOE Output Enable to Output Valid -- -- 50 -- -- 50 ns tE1LQX tCLZ1 Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns tE2HOX tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 10 -- -- ns tE1HQZ tCHZ1 Chip Deselect to Output in High Z (CE1) 0 -- 40 0 -- 40 ns Chip Deselect to Output in High Z (CE2) 0 40 0 40 ns tE2HQZ tCHZ1 tGHQZ tOHZ Output Disable to Output in High Z tAXOX tOH Output Disable to Output Address Change 0 -- 35 0 -- 35 ns 10 -- -- 10 -- -- ns 1. Typical characteristics are at Vcc = 5V, TA = 25oC. P/N DS00040 4 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 MX66C1024 n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT READ CYCLE2 (1,3,4) CE1 CE2 t ACS1 t ACS2 t (5) t (5) CHZ CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t t CE1 (5) t t t OLZ ACS1 CLZ1 CE2 t (5) t OHZ(1,5) t CHZ ACS2 (5) t OH OE t (2,5) CHZ CLZ2 D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. P/N DS00040 5 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 MX66C1024 n AC ELECTRICAL CHARACTERISTICS (over the operating range) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION MX66C1024-70 MIN. TYP. MAX. MX66C1024-10 MIN. TYP. MAX. 70 -- -- 100 -- -- ns 70 -- -- 100 -- -- ns 0 -- -- 0 -- -- ns t UNIT tE1LWH tCW Chip Select to End of Write tAVWL tAS Address Set up Time tAVWH tAW Address Valid to End of Write 70 -- -- 10 -- -- ns tWLWH tWP Write Pulse Width 50 -- -- 50 -- -- ns tWHAX tWR1 Write Recovery Time 0 -- -- -- -- -- ns tE2LAX tWR2 Write Recovery Time 0 -- -- -- -- -- ns tWLOZ tWHZ Write to Output in High Z -- -- 30 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 30 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHOZ tOHZ Output Disable to Output in High Z 0 -- 30 0 -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns (CE1, WE) (CE2) 1. Typical characteristics are at Vcc = 5V, TA = 25oC. n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 t (1) WC ADDRESS (3) t WR1 t WR2 OE (5) (11) t CW t CW CE1 (5) CE2 (11) t WE AW t t AS (3) WP (2) (4,10) t OHZ D OUT t t DH DW D IN P/N DS00040 6 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 MX66C1024 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t (5) CW CE1 (5) CE2 (11) t CW t AW t WR2 t WP (3) (2) WE t t AS DH (4,10) t (7) WHZ D OUT (8) t DW t DH (8) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write. P/N DS00040 7 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 MX66C1024 n SPEED (ns) ORDERING PART NUMBER 70 MX66C1024MC - 70 100 MX66C1024MC - 10 70 MX66C1024MI - 70 100 MX66C1024MI - 10 70 MX66C1024TC - 70 100 MX66C1024TC - 10 70 MX66C1024TI- 70 100 MX66C1024TI- 10 70 MX66C1024SC- 70 100 MX66C1024SC- 10 70 MX66C1024SI- 70 100 MX66C1024SI- 10 PACKAGE SOP - 32 PIN SOP - 32 PIN SOP - 32 PIN SOP - 32 PIN TSOP - 32 PIN TSOP - 32 PIN TSOP - 32 PIN TSOP - 32 PIN STSOP - 32 PIN STSOP - 32 PIN STSOP - 32 PIN STSOP - 32 PIN TEMPERATURE RANGE 0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C 0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C 0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C n PACKAGE DIMENSIONS P/N DS00040 8 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www. .com Rev. 1.0, November 1999 MX66C1024 n PACKAGE DIMENSIONS (continued) P/N DS00040 9 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www.macronix.com Rev. 1.0, November 1999 This page is left blank intentionally. P/N DS00040 Macronix America Inc., USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 http: www. .com Rev. 1.0, November 1999