TI1 LSF0102 Channel bidirectional multi-voltage level translator Datasheet

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LSF0101, LSF0102, LSF0108
SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
LSF010x 1/2/8 Channel Bidirectional Multi-Voltage Level Translator for Open-Drain and
Push-Pull Application
1 Features
2 Applications
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Provides Bidirectional Voltage Translation With No
Direction Pin
Supports Up to 100 MHz Up Translation and
Greater Than 100 MHz Down Translation at
≤ 30pF Cap Load and Up To 40 MHz Up/Down
Translation at 50 pF Cap Load
Supports Hot Insertion
Allow Bidirectional Voltage Level Translation
Between
– 0.95 V ↔ 1.8/2.5/3.3/5 V
– 1.2 V ↔ 1.8/2.5/3.3/5 V
– 1.8 V ↔ 2.5/3.3/5 V
– 2.5 V ↔ 3.3/5 V
– 3.3 V ↔ 5 V
Low Standby Current
5 V Tolerance I/O Port to Support TTL
Low Ron Provides Less Signal Distortion
High-Impedance I/O pins For EN = Low
Flow-Through Pinout for Ease PCB Trace Routing
Latch-Up Performance Exceeds 100 mA Per
JESD 17
–40°C to 125°C Operating Temperature Range
ESD Performance Tested Per JESD 22
– 2000 V Human-Body Model (A114-B, Class II)
– 200 V Machine Model (A115-A)
– 1000 V Charged-Device Model (C101)
GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C,
and Other Interfaces in Telecom Infrastructure
Industrial
Automotive
Personal Computing
•
•
•
3 Description
LSF family supports up to 100 MHz up translation
and greater than 100 MHz down translation at ≤ 30pF
cap load and up to 40 MHz up/down translation at 50
pF cap load which allows the LSF family to support
more consumer or telecom interfaces (MDIO or
SDIO). The LSF family has bidirectional voltage
translation without the need for DIR pin which
minimizes system effort (for PMBus, I2C, or SMbus).
LSF family supports 5 V tolerance on IO port which
makes it compatible with TTL levels in industrial and
telecom applications. The LSF family is able to set up
different voltage translation levels on each channel
which makes it very flexible.
Device Information(1)
PART NUMBER
LSF0101
LSF0102
LSF0108
PACKAGE(PINS)
BODY SIZE (NOM)
SON (6)
1.45 mm × 1.00 mm
X2SON (8)
1.40 mm × 1.00 mm
DSBGA (8)
1.90 mm × 1.00 mm
SM8 (8)
2.80 mm × 2.95 mm
VSSOP (8)
2.30 mm × 2.00 mm
VQFN (20)
4.50 mm × 2.50 mm
TSSOP (20)
4.40 mm × 6.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
LSF0102
LSF0101
A2
7
Vref_B
A1
3
6
B1
A2
4
5
B2
2
B2
8
8
3
7
1
1
2
A1
2
A1
EN
GND
Vref_A
Vref_A
B1
B2
B1
Vref_B
EN
4
C2
5
D2
6
A2
GND
5
3
A3
B1
4
C1
6
4
D1
7
3
A1
A2
A1
Vref_A
A4
Vref_B
A5
EN
8
6
5
9
1
2
RKS Package
20-Pin VQFN
(Top View)
DQE Package
8-Pin X2SON
(Top View)
A6
GND
Vref_A
LSF0108
YZT Package
8-Pin DSBGA
(Bottom View)
A7
DRY Package
6-Pin SON
(Top View)
A8
10
1
B8
11
20
GND
EN
18
B1
Vref_B
B3
B2
19
16
B5
B4
17
14
B7
B6
15
12
13
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LSF0101, LSF0102, LSF0108
SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information: LSF0101, LSF0108.................
Thermal Information: LSF0102 .................................
Electrical Characteristics...........................................
LSF0101/02 AC Performance (Translating Down)
Switching Characteristics , VGATE = 3.3 V .................
6.8 LSF0108 AC Performance (Translating Down)
Switching Characteristics, VGATE = 3.3 V ..................
6.9 LSF0101/02 AC Performance (Translating Down)
Switching Characteristics, VGATE = 2.5 V ..................
6.10 LSF0108 AC Performance (Translating Down)
Switching Characteristics, VGATE = 2.5 V ..................
6.11 LSF0101/02 AC Performance (Translating Up)
Switching Characteristics, VGATE = 3.3 V ..................
6.12 LSF0108 AC Performance (Translating Up)
Switching Characteristics, VGATE = 3.3 V ..................
6.13 LSF0101/02 AC Performance (Translating Up)
Switching Characteristics, VGATE = 2.5 V ..................
6.14 LSF0108 AC Performance (Translating Up)
Switching Characteristics, VGATE = 2.5 V .................. 8
6.15 Typical Characteristics ............................................ 8
7
8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application .................................................. 12
7
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 19
7
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
7
7
7
7
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
8
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2015) to Revision G
•
Page
Added all available package dimensions in Device Information and changed the pin diagram description. ......................... 1
Changes from Revision E (July 2015) to Revision F
Page
•
Changed Features from "Supports High Speed Translation, Greater Than 100 MHz" to "Supports Up to 100 MHz
Up Translation and Greater Than 100 MHz Down Translation at ≤ 30pF Cap Load and Up To 40 MHz Up/Down
Translation at 50 pF Cap Load." ........................................................................................................................................... 1
•
Updated all propagation delay tables changed from generic to specific LSF devices. ......................................................... 7
Changes from Revision D (October 2014) to Revision E
Page
•
Deleted "Less Than 1.5 ns Max Propagation Delay" from Features. .................................................................................... 1
•
Updated ESD Ratings table. .................................................................................................................................................. 5
•
Increased MAX value for TA, Operating free-air temperature, from 85°C to 125°C. .............................................................. 5
Changes from Revision C (May 2014) to Revision D
Page
•
Changed bidirectional voltage level translation from 1.0 to 0.95 ........................................................................................... 1
•
Changed YZT package to fix view error. ............................................................................................................................... 1
•
Changed YZT package to fix view error. ............................................................................................................................... 3
•
Added pin numbers to Pin Functions table............................................................................................................................. 4
2
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LSF0101, LSF0102, LSF0108
www.ti.com
•
SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
Added Vref_A footnote. ........................................................................................................................................................ 13
Changes from Revision B (May 2014) to Revision C
Page
•
Changed LSF0108 status from preview to production. .......................................................................................................... 1
•
Updated document title. ......................................................................................................................................................... 1
•
Updated Handling Ratings table. ........................................................................................................................................... 5
Changes from Revision A (January 2014) to Revision B
•
Page
Added LSF0108 to data sheet. .............................................................................................................................................. 1
Changes from Original (December 2013) to Revision A
Page
•
Updated part number.............................................................................................................................................................. 1
•
Updated Electrical Characteristics table................................................................................................................................. 6
5 Pin Configuration and Functions
LSF0102 DCT or DCU Package
8-Pin SM8 or VSSOP
Top View
GND
Vref_A
A1
A2
LSF0102 DQE Package
8-Pin X2SON
Top View
EN
GND
1
8
Vref_A
2
7
Vref_B
B1
A1
3
6
B1
B2
A2
4
5
B2
EN
Vref_B
LSF0102 YZT Package
8-Pin DSBGA
Bottom View
A2
A1
Vref_A
GND
D1
4
5
D2
C1
3
6
C2
B1
2
7
B2
A1
1
8
A2
B2
B1
Vref_B
EN
LSF0101 DRY Package
6-Pin SON
Top View
GND
Vref_A
A1
1
6
EN
2
5
Vref_B
3
4
B1
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LSF0101, LSF0102, LSF0108
SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
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LSF0108 PW Package
20-Pin TSSOP
Top View
20 EN
19 Vref_B
GND 1
Vref_A 2
A1 3
18 B1
A2 4
A3 5
17 B2
16 B3
A4 6
A5 7
A6 8
A7 9
15 B4
14 B5
13 B6
12 B7
11 B8
A8 10
LSF0108 RKS Package
20-Pin VQFN
Top View
1
20
GND EN
19
Vref_B
A1
3
18
B1
A2
4
17
B2
A3
5
16
B3
A4
6
15
B4
A5
7
14
B5
A6
8
13
B6
A7
9
12
B7
11
2
10
Vref_A
A8 B8
Pin Functions
PIN
DESCRIPTION
DCT, DCU,
DQE, YZT NO.
DRY
NO.
An
3, 4
3
3 to 10
Bn
6, 5
4
18 to 11
EN
8
6
20
Switch enable input; connect to Vref_B and pull-up through a high resistor (200 kΩ).
GND
1
1
1
Ground
Vref_A
2
2
2
Reference supply voltage; see Application and Implementation.
Vref_B
7
5
19
Reference supply voltage; see Application and Implementation.
NAME
4
PW or RKS
NO.
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Data port
Copyright © 2013–2016, Texas Instruments Incorporated
Product Folder Links: LSF0101 LSF0102 LSF0108
LSF0101, LSF0102, LSF0108
www.ti.com
SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature (unless otherwise noted)
Input voltage (2)
VI
VI/O
Input/output voltage
(2)
MIN
MAX
UNIT
–0.5
7
V
–0.5
7
V
128
mA
VI < 0
–50
mA
DCT package
220
DCU package
227
Continuous channel current
IIK
Input clamp current
RθJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
–65
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VI/O
Input/output voltage
0
5
V
Vref_A/B/EN
Reference voltage
0
5
V
IPASS
Pass transistor current
64
mA
TA
Operating free-air temperature
–40
125
°C
Copyright © 2013–2016, Texas Instruments Incorporated
Product Folder Links: LSF0101 LSF0102 LSF0108
UNIT
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LSF0101, LSF0102, LSF0108
SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
www.ti.com
6.4 Thermal Information: LSF0101, LSF0108
THERMAL METRIC (1)
LSF0101
LSF0108
LSF0108
DRY (SON)
RKS (VQFN)
PW (TSSOP)
6 PINS
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
407.0
49.3
106.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
285.2
45.9
41.0
°C/W
RθJB
Junction-to-board thermal resistance
271.6
20.6
57.6
°C/W
ψJT
Junction-to-top characterization parameter
113.5
2.5
4.2
°C/W
ψJB
Junction-to-board characterization parameter
271.0
20.6
47.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
3.4
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information: LSF0102
THERMAL METRIC (1)
LSF0102
LSF0102
LSF0102
LSF0102
DCU (US8)
DCT (SM8)
DQE (X2SON)
YZT (DSBGA)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
210.1
189.6
246.5
125.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
89.1
119.6
149.1
1.0
°C/W
RθJB
Junction-to-board thermal resistance
88.8
102.1
100.0
62.7
°C/W
ψJT
Junction-to-top characterization parameter
8.3
44.5
17.1
3.4
°C/W
ψJB
Junction-to-board characterization parameter
88.4
101.0
99.8
62.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
MAX
UNIT
VIK
II = –18 mA,
VEN = 0
–1.2
V
IIH
VI = 5 V
VEN = 0
5.0
µA
ICC
Vref_B = VEN = 5.5 V, Vref_A = 4.5 V or 1 V, IO = 0, VI = VCC or GND
CI(ref_A/B/EN)
VI = 3 V or 0
Cio(off)
VO = 3 V or 0,
VEN = 0
Cio(on)
VO = 3 V or 0,
VEN = 3 V
VI = 0,
ron (2)
(1)
(2)
6
1
µA
11
IO = 64 mA
pF
4.0
6.0
pF
10.5
12.5
pF
Vref_A = 3.3 V; Vref_B = VEN = 5 V
8.0
Vref_A = 1.8 V; Vref_B = VEN = 5 V
9.0
Vref_A = 1.0 V; Vref_B = VEN = 5 V
10
Vref_A = 1.8 V; Vref_B = VEN = 5 V
10
Vref_A = 2.5 V; Vref_B = VEN = 5 V
15
Ω
Ω
VI = 0,
IO = 32 mA
VI = 1.8 V,
IO = 15 mA
Vref_A = 3.3 V; Vref_B = VEN = 5 V
9.0
Ω
VI = 1.0 V,
IO = 10 mA
Vref_A = 1.8 V; Vref_B = VEN = 3.3 V
18
Ω
VI = 0 V,
IO = 10 mA
Vref_A = 1.0 V; Vref_B = VEN = 3.3 V
20
Ω
VI = 0 V,
IO = 10 mA
Vref_A = 1.0 V; Vref_B = VEN = 1.8 V
30
Ω
All typical values are at TA = 25°C.
Measured by the voltage drop between the A and B pins at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) pins.
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SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
6.7 LSF0101/02 AC Performance (Translating Down) Switching Characteristics , VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.1
0.7
0.3
1.2
0.8
0.4
MAX
UNIT
ns
6.8 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.9
1.4
0.75
2
1.5
0.85
MAX
UNIT
ns
6.9 LSF0101/02 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.2
0.8
0.35
1.3
1
0.5
MAX
UNIT
ns
6.10 LSF0108 AC Performance (Translating Down) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V (unless
otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
2
1.45
0.8
2.1
1.55
0.9
MAX
UNIT
ns
6.11 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1
0.8
0.4
1
0.9
0.4
MAX
UNIT
ns
6.12 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 3.3 V
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
2.1
1.55
0.9
2.2
1.65
1
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MAX
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UNIT
ns
7
LSF0101, LSF0102, LSF0108
SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
www.ti.com
6.13 LSF0101/02 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.1
0.9
0.45
1.3
1.1
0.6
MAX
UNIT
ns
6.14 LSF0108 AC Performance (Translating Up) Switching Characteristics, VGATE = 2.5 V
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V and RL
= 300 (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
FROM (INPUT)
TO (OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
TYP
TYP
TYP
MAX
MAX
1.8
1.35
0.8
1.9
1.45
0.9
MAX
UNIT
ns
6.15 Typical Characteristics
4
Input
Output
3.5
3
Voltage - V
2.5
2
1.5
1
0.5
0
0
5
-0.5
10
15
20
Time - ns
Figure 1. Signal Integrity (1.8 to 3.3 V Translation Up at 50 MHz)
8
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SDLS966G – DECEMBER 2013 – REVISED FEBRUAURY 2016
7 Parameter Measurement Information
VT
RL
USAGE
SWITCH
Translating up
Translating down
S1
S2
S1
Open
From Output
Under Test
S2
3.3 V
Input
VM
VM
VIL
CL
(see Note A)
5V
Output
VM
VM
LOAD CIRCUIT
VOL
TRANSLATING UP
5V
Input
VM
VM
VIL
2V
Output
VM
VM
VOL
TRANSLATING DOWN
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit for Outputs
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8 Detailed Description
8.1 Overview
The LSF family can be used in level translation applications for interfacing devices or systems operating at
different interface voltages with one another. The LSF family is ideal for use in applications where an open-drain
driver is connected to the data I/Os. With appropriate pull-up resistors and layout, LSF can achieve 100 MHz.
The LSF family can also be used in applications where a push-pull driver is connected to the data I/Os.
8.2 Functional Block Diagrams
Vref_A
2
A1 3
Vref_B
LSF0101
5
6 EN
4 B1
SW
1
GND
Figure 3. LSF0101 Functional Block Diagram
Vref_A
2
A1 3
A2 4
Vref_B
LSF0102
7
SW
SW
8 EN
6 B1
5 B2
1
GND
Figure 4. LSF0102 Functional Block Diagram
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Functional Block Diagrams (continued)
Vref_B
Vref_A
19
2
LSF0108
B1
SW
4
A2
17
B2
SW
5
A3
16
B3
SW
6
A4
15
B4
SW
14
7
A5
B5
SW
8
A6
13
B6
SW
9
A7
12
B7
SW
10
A8
EN
18
3
A1
20
11
SW
B8
1
GND
Figure 5. LSF0108 Functional Block Diagram
8.3 Feature Description
The LSF family are bidirectional voltage level translators operational from 0.95 to 4.5 V (Vref_A) and 1.8 to 5.5 V
(Vref_B). This allows bidirectional voltage translations between 1 V and 5 V without the need for a direction pin in
open-drain or push-pull applications. LSF family supports level translation applications with transmission speeds
greater than 100 Mbps for open-drain systems using a 30-pF capacitance and 250-Ω pullup resistor.
When the An or Bn port is LOW, the switch is in the ON-state and a low resistance connection exists between
the An and Bn ports. The low Ron of the switch allows connections to be made with minimal propagation delay
and signal distortion. Assuming the higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the
An port is limited to the voltage set by Vref_A. When the An port is HIGH, the Bn port is pulled to the drain pullup supply voltage (Vpu#) by the pull-up resistors. This functionality allows a seamless translation between higher
and lower voltages selected by the user without the need for directional control.
The supply voltage (Vpu#) for each channel can be individually set up with a pull-up resistor. For example, CH1
can be used in up-translation mode (1.2 V ↔ 3.3 V) and CH2 in down-translation mode (2.5 V ↔ 1.8 V).
When EN is HIGH, the translator switch is on, and the An I/O is connected to the Bn I/O, respectively, allowing
bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state
exists between ports. The EN input circuit is designed to be supplied by Vref_B. To ensure the high-impedance
state during power-up or power-down, EN must be LOW.
8.4 Device Functional Modes
Table 1 expresses the functional modes of the LSF devices.
Table 1. Function Table
INPUT EN
(1)
(1)
PIN
FUNCTION
H
An = Bn
L
H-Z
EN is controlled by Vref_B logic levels and should be at least 1 V
higher than Vref_A for best translator.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LSF devices are able to perform voltage translation for open-drain or push-pull interface. Table 2 provides
some consumer/telecom interfaces as reference in regards to the different channel numbers that are supported
by the LSF family.
Table 2. Voltage Translator for Consumer/Telecom Interface
Part Name
Channel Number
LSF0101
1
GPIO
Interface
LSF0102
2
GPIO, MDIO, SMBus, PMBus, I2C
LSF0108
8
GPIO, MDIO, SDIO, SVID, UART, SMBus, PMBus, I2C, SPI
9.2 Typical Application
9.2.1 I2C PMBus, SMBus, GPIO
3.3V enable signal
ON
Off
Vref(A) = 1.2V
Vpu1 = 3.3V
200KΩ
Vref_A
2
Rpu
Vpu3 = 2.5V
Vcc
Rpu
A1 3
GPIO3
Vcc
A2 4
GPIO4
GND
Vref_B
LSF0102
7
8 EN
Rpu Rpu
6 B1
SW
5 B2
SW
Vcc
GPIO1
GPIO2
GND
1
GND
Figure 6. Bidirectional Translation to Multiple Voltage Levels
9.2.1.1 Design Requirements
9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF family has an EN input that is used to disable the device by setting EN LOW, which places all I/Os in
the high-impedance state. Since LSF family is switch-type voltage translator, the power consumption is very low.
It is recommended to always enable LSF family for bidirectional application (I2C, SMBus, PMBus, or MDIO).
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Typical Application (continued)
Table 3. Application Operating Condition
PARAMETER
MIN
TYP
MAX
UNIT
Vref_A (1)
reference voltage (A)
0.95
4.5
V
Vref_B
reference voltage (B)
Vref_A + 0.8
5.5
V
VI(EN)
input voltage on EN pin
Vref_A + 0.8
5.5
V
Vpu
pull-up supply voltage
0
Vref_B
V
(1)
Vref_A have to be the lowest voltage level across all of inputs and outputs.
The 200 kΩ, pull-up resistor is required to allow Vref_B to regulate the EN input. A filter capacitor on
Vref_B is recommended. Also Vref_B and VI(EN) are recommended to be at 1.0 V higher than Vref_A for best
signal integrity.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the EN input must be connected to Vref_B and both pins pulled to HIGH side Vpu through a pull-up resistor
(typically 200 kΩ). This allows Vref_B to regulate the EN input. A filter capacitor on Vref_B is recommended. The
master output driver can be push-pull or open-drain (pull-up resistors may be required) and the slave device
output can be push-pull or open-drain (pull-up resistors are required to pull the Bn outputs to Vpu).
If either output is push-pull, data must be unidirectional or the outputs must be tri-state and be
controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either direction.
If both outputs are open-drain, no direction control is needed.
In Figure 6, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage.
When Vref_B is connected through a 200 kΩ resistor to a 3.3 V Vpu power supply, and Vref_A is set 1.0 V. The
output of A3 and B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2,
MDIO) has a maximum output voltage equal to Vpu.
9.2.1.2.2 Pull-up Resistor Sizing
The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15
mA, to calculate the pull-up resistor value use the following equation:
Rpu = (Vpu – 0.35 V) / 0.015 A
(1)
Table 4 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor
value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the
transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both
sides of the LSF family device at 0.175 V, although the 15 mA applies only to current flowing through the LSF
family device.
Table 4. Pull-up Resistor Values (1) (2)
VDPU
(1)
(2)
(3)
15 mA
NOMINAL (Ω)
10 mA
+10%
(3)
(Ω)
NOMINAL (Ω)
3 mA
+10%
(3)
(Ω)
NOMINAL (Ω)
+10% (3) (Ω)
5V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
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9.2.1.2.3 LSF Family Bandwidth
The maximum frequency of the LSF family is dependent on the application. The device can operate at speeds of
>100 MHz gave the correct conditions. The maximum frequency is dependent upon the loading of the
application. The LSF family behaves like a standard switch where the bandwidth of the device is dictated by the
on resistance and on capacitance of the device.
Figure 7 shows a bandwidth measurement of the LSF family using a two-port network analyzer.
0
–1
–2
Gain (dB)
–3
–4
–5
–6
–7
–8
–9
0.1
1
10
100
Frequency (MHz)
1000
Figure 7. 3-dB Bandwidth
The 3-dB point of the LSF family is ≈ 600 MHz; however, this measurement is an analog type of measurement.
For digital applications the signal should not degrade up to the fifth harmonic of the digital signal. The frequency
bandwidth should be at least five times the maximum digital clock rate. This component of the signal is very
important in determining the overall shape of the digital signal. In the case of the LSF family, a digital clock
frequency of greater than 100 MHz can be achieved.
The LSF family does not provide any drive capability. Therefore higher frequency applications will require higher
drive strength from the host side. No pull-up resistor is needed on the host side (3.3 V) if the LSF family is being
driven by standard CMOS totem pole output driver. Ideally, it is best to minimize the trace length from the LSF
family on the sink side (1.8 V) to minimize signal degradation.
All fast edges have an infinite spectrum of frequency components; however, there is an inflection (or knee) in the
frequency spectrum of fast edges where frequency components higher than ƒknee are insignificant in determining
the shape of the signal.
To calculate the maximum practical frequency component, or the knee frequency (fknee), use the following
equations:
ƒknee = 0.5 / RT (10 – 80%)
ƒknee = 0.4 / RT (20 – 80%)
(2)
(3)
For signals with rise time characteristics based on 10% to 90% thresholds, fknee is equal to 0.5 divided by the rise
time of the signal. For signals with rise time characteristics based on 20% to 80% thresholds, which is very
common in many of today's device specifications, ƒknee is equal to 0.4 divided by the rise time of the signal.
Some guidelines to follow that will help maximize the performance of the device:
• Keep trace length to a minimum by placing the LSF family close to the I2C output of the processor.
• The trace length should be less than half the time of flight to reduce ringing and line reflections or nonmonotonic behavior in the switching region.
• To reduce overshoots, a pull-up resistor can be added on the 1.8 V side; be aware that a slower fall time is to
be expected.
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9.2.1.3 Application Curve
4
Input
Output
3
Voltage - V
2
1
0
±1
0
50
100
150
200
250
300
350
400
450
500
Time - ns
C002
Figure 8. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz)
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9.2.2 MDIO
3.3V enable signal
ON
Vref(A) = 1.8V
Off
Vref_A
2
Rpu
Rpu
Vcc
A1 3
MDIO
A2 4
MDC
Vpu = 3.3V
200KΩ
Vref_B
LSF0102
7
SW
SW
8 EN
Rpu
Rpu
Vcc
6 B1
MDIO
5 B2
MDC
1
GND
GND
GND
Figure 9. Typical Application Circuit (MDIO/Bidirectional Interface)
9.2.2.1 Design Requirements
Refer to Design Requirements.
9.2.2.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
9.2.2.3 Application Curve
Input (3.3V)
Output (1.0V)
Figure 10. Captured Waveform From Above MDIO Setup
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9.2.3 Multiple Voltage Translation in Single Device
Vpu= 5.0V
Vref(A) = 1.8V
Vref_B
Vref_A
LSF0108
1.8V
Vcc
GPIO
GPIO
A1
A2
A3
GPIO
A4
GPIO
A5
SCL
A6
SDA
SW
SW
SW
SW
SW
SW
200KΩ
EN
Rpu
Vcc
B1
GPIO
B2
GPIO
Vcc
B3
GPIO
B4
B5
Vpu= 3.3V
GPIO
Rpu
Rpu
SCL
B6
SDA
Rpu
Rpu
MDIO
SW
MDIO
MDC
SW
MDC
9.2.3.1 Design Requirements
Refer to Design Requirements.
9.2.3.2 Detailed Design Procedure
Refer to Detailed Design Procedure.
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9.2.3.3 Application Curve
3.5
Input
Output
3
2.5
Voltage - V
2
1.5
1
0.5
0
-0.5
0
2.4E+0
4.8E+0
7.2E+0
9.6E+0
1.2E+1
Time - ns
1.44E+1
1.68E+1
1.92E+1
2.16E+1
D001
Figure 11. Translation Down (3.3 to 1.8 V) at 150 MHz
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10 Power Supply Recommendations
There are no power sequence requirements for the LSF family. For enable and reference voltage guidelines,
please refer to the Enable, Disable, and Reference Voltage Guidelines.
11 Layout
11.1 Layout Guidelines
Because the LSF family is a switch-type level translator, the signal integrity is highly related with a pull-up
resistor and PCB capacitance condition.
• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.
• Place LSF close to high voltage side.
• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.
11.2 Layout Example
LSF0102
GND
Vref_A
A1
A2
1
2
3
4
8
7
6
5
EN
Short Signal Trace as possible
Vref_B
B1
B2
Minimize Stub as possible
Figure 12. Short Trace Layout
TP1
SD Controller
(1.8V IO)
LSF0108
SDIO level translator
SDIO Connector
(3.3V IO)
Device PCB
TP2
Figure 13. Device Placement
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Layout Example (continued)
3.5
3.5E+0
Output
Input
3E+0
3
2.5E+0
2.5
2E+0
2
Voltage - V
Voltage - V
Input
Output
1.5E+0
1E+0
1
5E-1
0.5
0
0
-0.5
-5E-1
0
2.5E+0
5E+0
7.5E+0
1E+1
1.25E+1
Time - ns
1.5E+1
1.75E+1
2E+1
2.25E+1
2.5E+1
Figure 14. Waveform From TP1 (Pull-up Resistor: 160-Ω
and 50-pF Capacitance 3.3 V to 1.8 V at 100 MHz)
20
1.5
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0
3E+0
6E+0
9E+0
1.2E+1
1.5E+1
Time - ns
1.8E+1
2.1E+1
2.4E+1
2.7E+1
3E+1
Figure 15. Waveform From TP2 (Pull-up Resistor: 160-Ω
and 50-pF Capacitance 1.8 V to 3.3 V at 100 MHz)
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LSF0101
Click here
Click here
Click here
Click here
Click here
LSF0102
Click here
Click here
Click here
Click here
Click here
LSF0108
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LSF0101DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
VD
LSF0102DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
NG2
Y
LSF0102DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(G2 ~ NG2P ~ NG2S)
NY
LSF0102DQER
ACTIVE
X2SON
DQE
8
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
RV
LSF0102YZTR
ACTIVE
DSBGA
YZT
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
RV
LSF0108PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LSF0108
LSF0108RKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LSF0108
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LSF0101DRYR
Package Package Pins
Type Drawing
SON
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DRY
6
5000
180.0
9.5
1.15
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.6
0.75
4.0
8.0
Q1
LSF0102DCTR
SM8
DCT
8
3000
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
LSF0102DCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
LSF0102DCUR
VSSOP
DCU
8
3000
178.0
9.5
2.25
3.35
1.05
4.0
8.0
Q3
LSF0102DCUR
VSSOP
DCU
8
3000
180.0
9.0
2.05
3.3
1.0
4.0
8.0
Q3
LSF0102DQER
X2SON
DQE
8
5000
180.0
9.5
1.15
1.6
0.5
4.0
8.0
Q1
LSF0102YZTR
DSBGA
YZT
8
3000
180.0
8.4
1.02
2.02
0.75
4.0
8.0
Q1
LSF0108PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
LSF0108RKSR
VQFN
RKS
20
3000
177.8
12.4
2.73
4.85
1.03
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LSF0101DRYR
SON
DRY
6
5000
184.0
184.0
19.0
LSF0102DCTR
SM8
DCT
8
3000
182.0
182.0
20.0
LSF0102DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
LSF0102DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
LSF0102DCUR
VSSOP
DCU
8
3000
182.0
182.0
20.0
LSF0102DQER
X2SON
DQE
8
5000
184.0
184.0
19.0
LSF0102YZTR
DSBGA
YZT
8
3000
182.0
182.0
20.0
LSF0108PWR
TSSOP
PW
20
2000
364.0
364.0
27.0
LSF0108RKSR
VQFN
RKS
20
3000
202.0
201.0
28.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D: Max = 1.918 mm, Min =1.858 mm
E: Max = 0.918 mm, Min =0.858 mm
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