IDT IDT5V2528APGG 2.5v / 3.3v phase-lock loop clock driver zero delay buffer Datasheet

IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
2.5V / 3.3V PHASE-LOCK
LOOP CLOCK DRIVER
ZERO DELAY BUFFER
FEATURES:
•
•
•
•
The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buffers operate from
the 3.3V VDD and AVDD power supply pins.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Of
the ten outputs, up to seven may be configured for 2.5V or 3.3V LVTTL
outputs. The number of 2.5V outputs is controlled by 3-level input signals
G_Ctrl and T_Ctrl, and by connecting the appropriate VDDQ pins to 2.5V or
3.3V. The 3-level input signals may be hard-wired to high-mid-low levels.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the G_Ctrl input.
When the G_Ctrl input is mid or high, the outputs switch in phase and
frequency with CLK; when the G_Ctrl is low, all outputs (except FBOUT) are
disabled to the logic-low state.
Unlike many products containing PLLs, the IDT5V2528 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the IDT5V2528 requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for test purposes by strapping AVDD to ground.
Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
1:10 fanout
3-level inputs for output control
External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
No external RC network required for PLL loop stability
Configurable 2.5V or 3.3V LVTTL outputs
tPD Phase Error at 100MHz to 166MHz: ±150ps
Jitter (peak-to-peak) at 133MHz and 166MHz: ±75ps
Spread spectrum compatible
Operating Frequency:
− Std: 25MHz to 140MHz
− A: 25MHz to 167MHz
Available in TSSOP package
•
•
•
•
•
•
•
IDT5V2528/A
DESCRIPTION:
The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
FUNCTIONAL BLOCK DIAGRAM
28
G_Ctrl
T_Ctrl
3
1
TY0, VDDQ pin 4
26
TY1, VDDQ pin 25
24
TY2, VDDQ pin 25
MODE
SELECT
17
TY3, VDDQ pin 15
16
TY4, VDDQ pin 15
13
TY5, VDDQ pin 11
12
CLK
10
6
TY7, VDDQ pin 11
PLL
FBIN
TY6, VDDQ pin 11
20
7
Y0, VDD pin 21
19
AVDD
Y1, VDD pin 21
5
22
FBOUT, VDD pin 21
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2003
1
c
2002
Integrated Device Technology, Inc.
DSC 5971/11
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Rating
Max.
Unit
VDD, VDDQ, AVDD
Supply Voltage Range
–0.5 to +4.6
V
T_Ctrl
1
28
G_Ctrl
VI (2)
Input Voltage Range
–0.5 to +5.5
V
GND
2
27
GND
VO(2)
Voltage Range applied to any
–0.5 to
V
TY0
3
26
TY1
Input Clamp Current
–50
mA
Output Clamp Current
±50
mA
Continuous Output Current
±50
mA
±200
mA
output in the HIGH or LOW state
VDDQ
4
25
VDDQ
IIK (VI < 0)
AVDD
5
24
TY2
IOK
VDD+0.5
(VO < 0 or VO > VDD)
CLK
6
23
GND
FBIN
7
22
FBOUT
AGND
8
21
VDD
VDD or GND
Continuous Current
GND
9
20
Y0
TSTG
Storage Temperature Range
TY7
10
19
Y1
TJ
Junction Temperature
VDDQ
11
18
GND
TY6
12
17
TY3
TY5
13
16
TY4
GND
14
15
VDDQ
IO
(VO = 0 to VDD)
–65 to +150
°C
+150
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
TSSOP
TOP VIEW
of 150°C and a board trace length of 750 mils.
CAPACITANCE(1)
Symbol
CIN
Description
Min
Typ.
Max.
Unit
Input Capacitance
—
5
—
pF
—
6
—
pF
—
—
20
—
—
pF
VI = VDD or GND
CO
Output Capacitance
VI = VDD or GND
CL
Load Capacitance 2.5V outputs
3.3V outputs
30
NOTE:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
RECOMMENDED OPERATING RANGE
Symbol
Description
VDD, AVDD (1)
Power Supply Voltage
VDDQ (1)
Power Supply Voltage
TA
2.5V Outputs
3.3V Outputs
Ambient Operating Temperature
Min.
Typ.
Max.
Unit
3
3.3
3.6
V
2.3
3
2.5
3.3
2.7
3.6
V
–40
+25
+85
°C
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
2
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Terminal
Name
No.
Type
Description
CLK(1)
6
I
Clock input
FBIN
7
I
Feedback input
G_Ctrl(2)
28
3-level
3-level input for 2.5V / 3.3V Output Select/ Output bank enable. When G_Ctrl is LOW, all outputs except FBOUT are disabled
to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see
OUTPUT SELECTION table).
T_Ctrl(2)
1
3-level
FBOUT
22
O
Feedback output
3, 10, 12, 13,
O
2.5V or 3.3V Clock outputs. 1, 2, 3, 5, or 7 of these outputs may be selected as 2.5V outputs (see OUTPUT SELECTION table).
O
3.3V Clock Outputs
TY (7:0)
3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table)
16, 17, 24, 26
Y (1:0)
19, 20
AVDD(3)
5
Power
3.3V Analog power supply. AVDD provides the power reference for the analog circuitry.
AGND
8
Ground
Analog ground. AGND provides the ground reference for the analog circuitry.
VDD
21
Power
3.3V Power supply
VDDQ
4, 11, 15, 25
Power
2.5V or 3.3V Power supply for TY outputs
GND
2, 9, 14, 18
Ground
Ground
23, 27
NOTES:
1. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms
is required for the PLL to phase lock the feedback signal to the reference signal.
2. 3-level inputs will float to MID logic level if left unconnected.
3. AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.
STATIC FUNCTION TABLE (AVDD = 0V)(1)
G_Ctrl
L
L
Inputs
T_Ctrl
X
X
see
OUTPUT SELECTION
table
CLK
L
H
H
L
running
TY(7:0)
L
L
H
L
running
Outputs
Y(1:0)
L
L
H
L
running
OUTPUT SELECTION
FBOUT
L
H
H
L
running
NOTE:
1. AVDD should be powered up along with VDD, before setting AVDD to ground, to put the
control pins in a valid state.
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)
Inputs
G_Ctrl
T_Ctrl
L
X
L
X
see OUTPUT
SELECTION table
CLK
L
H
L
H
TY(7:0)
L
L
L
H
Outputs
Y(1:0)
L
L
L
H
FBOUT
L
H
L
H
3
G_Ctrl
M
T_Ctrl
L
M
M
M
H
H
L
H
M
H
H
TY(7:0)
TY0 (2.5V)
TY1 - TY7 (3.3V)
TY1, TY2 (2.5V)
TY0, TY3 - TY7 (3.3V)
TY0 - TY2 (2.5V)
TY3 - TY7 (3.3V)
TY0 - TY4 (2.5V)
TY5 - TY7 (3.3V)
TY1 - TY7 (2.5V)
TY0 (3.3V)
TYo - TY7 (3.3V)
VDDQ
Configuration
Pin 4 (2.5V)
Pins 11, 15, 25 (3.3V)
Pin 25 (2.5V)
Pins 4, 11, 15 (3.3V)
Pins 4, 25 (2.5V)
Pins 11, 15 (3.3V)
Pins 4, 15, 25 (2.5V)
Pin 11 (3.3V)
Pins 11, 15, 25 (2.5V)
Pin 4 (3.3V)
Pins 4, 11, 15, 25 (3.3V)
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
VIK
VIH
VIL
VIHH
VIMM
VILL
VOH
VOH
VOL
VOL
I3
II
Parameter
Input Clamp Voltage
Input HIGH Level
Input LOW Level
Input HIGH Voltage Level(2)
Input MID Voltage Level(2)
Input LOW Voltage Level(2)
Output HIGH Voltage Level
(3.3V Outputs)
Output HIGH Voltage Level
(2.5V Outputs)
Output LOW Voltage Level
(3.3V Outputs)
Output LOW Voltage Level
(2.5V Outputs)
3-Level Input DC Current
(G_Ctrl, T_Ctrl)
Input Current
Test Conditions
II = -18mA
CLK, FBIN
CLK, FBIN
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
IOH = -100µA
IOH = -12mA
IOH = -100µA
IOH = -12mA
IOL = 100µA
IOL = 12mA
IOL = 100µA
IOL = 12mA
VIN = VDD
VIN = VDD/2
VIN = GND
VI = VDD or GND
Min.
Typ.(1)
2
VDD - 0.6
VDD/2 - 0.3
VDD - 0.2
2.4
VDD - 0.1
2
HIGH Level
MID Level
LOW Level
–50
–200
Max
- 1.2
Unit
V
V
0.8
V
V
VDD/2 + 0.3 V
0.6
V
V
V
V
0.2
0.4
0.1
0.4
+200
+50
µA
±5
µA
V
NOTES:
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
2. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias floating inputs to VDD/2. If these inputs are switched, the function and timing of
the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
POWER SUPPLY CHARACTERISTICS
Symbol
IDDPD
IDDA
IDD
IDDD
Parameter
Power Down Supply Current
AVDD Supply Current
Dynamic Power Supply Current
Dynamic Power Supply
Current per Output
Test Conditions
VDD = 3.6, VDDQ = 2.7V / 3.3V, AVDD = 0V
VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CLK = 0 or VDD
VDD = AVDD = 3.6V, VDDQ = 2.7V / 3.3V, CL = 0pF
VDD = AVDD = VDDQ = 3.6V
CL = 30pF, CLK = 100MHz
VDD = AVDD = 3.6V, VDDQ = 2.7V
CL = 20pF, CLK = 100MHz
NOTE:
1. For nominal voltage and temperature.
4
Typ.(1)
8
3.5
500
15
Max
40
10
—
—
12
—
Unit
µA
mA
µA/MHz
mA
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS OVER OPERATING RANGE
5V2528
Min
Clock frequency
fCLOCK
Input clock duty cycle
Min
Max
Units
MHz
25
140
25
167
40%
60%
40%
60%
Stabilization time(1)
tLOCK
5V2528A
Max
1
1
ms
NOTE:
1.Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference
signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are
not applicable.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528(1)
Symbol
tPHASE error
tPHASE error - jitter(3)
tSK1(0)(4)
tSK2(0)(4)
tSK3(0)(4,5)
tJ
tR
tF
tR
tF
Parameter(2)
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-133MHz)
Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (133MHz)
Output Skew between 3.3V Outputs
Output Skew between 2.5V Outputs
Output Skew between 2.5V and 3.3V Outputs
Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 133MHz
Duty Cycle
Output Rise Time for 3.3V Outputs (20% to 80%)
Output Fall Time for 3.3V Outputs (20% to 80%)
Output Rise Time for 2.5V Outputs (20% to 80%)
Output Fall Time for 2.5V Outputs (20% to 80%)
Min.
–150
–50
—
—
—
–75
45
0.8
0.8
0.5
0.5
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
150
50
150
150
200
75
55
2.1
2.1
1.5
1.5
Unit
ps
ps
ps
ps
ps
ps
%
ns
ns
ns
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - 5V2528A(1)
Symbol
tPHASE error
tPHASE error - jitter(3)
tSK1(0)(4)
tSK2(0)(4)
tSK3(0)(4,5)
tJ
tR
tF
tR
tF
Parameter(2)
Phase Error from Rising Edge CLK to Rising Edge FBIN (100MHz-166MHz)
Phase Error minus Jitter from Rising Edge CLK to Rising Edge FBIN (166MHz)
Output Skew between 3.3V Outputs
Output Skew between 2.5V Outputs
Output Skew between 2.5V and 3.3V Outputs 25MHz to 133MHz
133MHz to 166MHz
Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 166MHz
Duty Cycle
Output Rise Time for 3.3V Outputs (20% to 80%)
Output Fall Time for 3.3V Outputs (20% to 80%)
Output Rise Time for 2.5V Outputs (20% to 80%)
Output Fall Time for 2.5V Outputs (20% to 80%)
Min.
–150
–50
—
—
—
—
–75
45
0.8
0.8
0.5
0.5
NOTES:
1. All parameters are measured with the following load conditions: 30pF || 500Ω for 3.3V outputs and 20pF || 500Ω for 2.5V outputs.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. All skew parameters are only valid for equal loading of all outputs.
5. Measured for VDDQ = 2.3V and 3V, 2.5V and 3.3V, or 2.7V and 3.6V.
5
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
150
50
150
150
200
250
75
55
2.1
2.1
1.5
1.5
Unit
ps
ps
ps
ps
ps
ps
%
ns
ns
ns
ns
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUIT AND VOLTAGE WAVEFORMS
From Output
Under Test
From Output
Under Test
500Ω
CL=30pF(2)
500Ω
CL=20pF(2)
Test Circuit for 3.3V Outputs
Test Circuit for 2.5V Outputs
VDD/2
CLK
FBIN
VDD/2
tPHASE ERROR
CLK
Y, TY
IDT5V2528/A
CL (2)
CF (4)
FBIN
FBOUT
500Ω
on each Y,
TY output
FBOUT
or
Any Y, TY (3.3V)
Any Y, TY (3.3V)
80%
20%
VDDQ/2
tR
tF
VDDQ/2
VDDQ/2
tSK1(o)
tSK3(o)
500Ω
PCBTRACE
80%
20%
VDDQ/2
Any TY (2.5V)
Any TY (2.5V)
tR
VDDQ/2
tSK2(o)
PHASE ERROR AND SKEW CALCULATIONS(3,4)
NOTES:
1. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF ≤ 1.2 ns.
2. CL includes probe and jig capacitance.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y, TY, and FBOUT. CF = CL – CFBIN – CPCBtrace; CFBIN ≅ 5pF.
6
tF
VDDQ/2
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
XXXXX
Device Type
XX
Package
X
Process
I
-40°C to +85°C (Industrial)
PG
PGG
Thin Shrink Small Outline Package
TSSOP - Green
5V2528
5V2528A
2.5V / 3.3V Phase-Lock Loop Clock Driver
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
7
for Tech Support:
[email protected]
(408) 654-6459
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