MOTOROLA Order this document by MCM101524/D SEMICONDUCTOR TECHNICAL DATA MCM101524 Product Preview 1M x 4 Bit Fast Static Random Access Memory with ECL I/O TB PACKAGE 400 MIL TAB CASE 984A–01 The MCM101524 is a 4,194,304 bit static random access memory organized as 1,048,576 words of 4 bits. This circuit is fabricated using high performance silicon–gate BiCMOS technology. Asynchronous design eliminates the need for external clocks or timing strobes. The MCM101524 is available in a 400 mil, 36 lead TAB. PIN ASSIGNMENT • Fast Access Times: 12, 15 ns • Equal Address and Chip Select Access Times • Power Operation: – 195 mA Maximum, Active AC A10 1 36 A1 A11 2 35 A2 A12 3 34 A3 VEE A13 4 33 A8 VCC A14 5 32 A19 S 6 31 NC D0 7 30 D3 BLOCK DIAGRAM A17 A16 A15 A14 A13 ROW DECODER MEMORY MATRIX 1024 ROWS x 4096 COLUMNS Q0 8 29 Q3 VCC 9 28 VEE A11 VEE 10 27 VCC A10 Q1 11 26 Q2 A9 D1 12 25 D2 A8 W 13 24 NC D0 • • D3 Q0 • • Q3 A0 14 23 A9 A15 15 22 A4 A16 16 21 A5 A17 17 20 A6 A18 18 19 A7 A12 COLUMN I/O COLUMN DECODER INPUT DATA CONTROL A19 A18 A7 A6 A5 A4 A3 A2 A1 A0 Q0 S W Q3 PIN NAMES A0 – A19 . . . . . . . . . . . . . Address Inputs S . . . . . . . . . . . . . . . . . . . . . . . Chip Select Q0 – Q3 . . . . . . . . . . . . . . . . Data Output VEE . . . . . . . . . . . . . . . . . . Power Supply W . . . . . . . . . . . . . . . . . . . . . Write Enable D0 – D3 . . . . . . . . . . . . . . . . . . Data Input NC . . . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . . . . . . . . . . . . Ground This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. REV 2 9/94 Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM101524 1 TRUTH TABLE (X = Don’t Care) W Operation Data H X Not Enabled X L — L H Read X Q IEE L L Write X L IEE S Output Current ABSOLUTE MAXIMUM RATINGS (See Note) Rating VEE Pin Potential (to Ground) Voltage Relative to VCC for Any Pin Except VEE Output Current (per I/O) Power Dissipation Symbol Value Unit VEE – 7.0 to + 0.5 V Vin, Vout VEE – 0.5 to + 0.5 V Iout – 50 mA PD 2.0 W Temperature Under Bias Tbias – 30 to + 85 °C Operating Temperature TJ 0 to + 60 °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. Storage Temperature — Plastic Tstg – 55 to + 125 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 0 V, VEE = – 5.2 V ± 5%, TJ = 0 to + 60°C, Unless Otherwise Noted) DC OPERATING CONDITIONS AND SUPPLY CURRENTS Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) Parameter VEE – 5.46 – 5.2 – 4.94 V Input High Voltage VIH – 1165 — – 880 mV Input Low Voltage VIL – 1810 — – 1475 mV Output High Voltage VOH – 1025 — – 880 mV Output Low Voltage VOL – 1810 — – 1620 mV Input Low Current IIL – 50 — — µA Input High Current IIH — — 220 µA IIL(CS) 0.5 — 170 µA IEE — — – 195 mA IEEQ — — – 150 mA Chip Select Input Low Current Operating Power Supply Current: tAVAV = 20 ns (All Outputs Open)* Quiescent Power Supply Current: fo = 0 MHz (Outputs Open) Voltage Compensation (VOH) ∆VOH/∆VEE ± 35 mV/V @ – 4.94 to – 5.46 V Voltage Compensation (VOL) ∆VOL/∆VEE ± 60 mV/V @ – 4.94 to – 5.46 V * Address Increment RISE/FALL TIME CHARACTERISTICS Parameter Symbol Test Condition Min Typ Max Unit Output Rise Time tr 20% to 80% 0.5 1.0 1.5 ns Output Fall Time tf 20% to 80% 0.5 1.0 1.5 ns CAPACITANCE (f = 1.0 MHz, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Output Capacitance MCM101524 2 Symbol Typ Max Unit Address and Data S, W Cin Cck 3.5 4 7 7 pF Q Cout 4 8 pF MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (VEE = – 5.2 V ± 5%, VCC = 0 V, TJ = 0 to +60°C, Unless Otherwise Noted) Input Pulse Levels . . . . . . . . . . . . . – 1.7 V to – 0.9 V (See Figure 1) Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . . 50% Output Timing Measurement Reference Level . . VOH = – 1165 mV VOL = – 1475 mV Output Load (AC Test Circuit) . . . . . . . . . . . . . . . . . . . . . See Figure 2 READ CYCLE TIMING (See Notes 1 and 2) MCM101524–12 Parameter MCM101524–15 Symbol Min Max Min Max Unit Notes Read Cycle Time tAVAV 12 — 15 — ns 2, 3 Address Access Time tAVQV — 12 — 15 ns Chip Select Access Time tSLQV — 12 — 15 ns Select High to Output Low tSHQL 0 8 0 9 ns Output Hold from Address Change tAXQX 4 — 4 — ns tSLIEEH 0 — 0 — ns 4 ns 4 Power Up Time Power Down Time tSHIEEL — 12 — 15 NOTES: 1. W is high for read cycle. 2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. This parameter is sampled and not 100% tested. 5. Device is continuously selected (S ≤ VIL). 6. Addresses valid prior to or coincident with S going low. 6 AC TEST CONDITIONS VCC – 0.9 V 80% 50% 20% 80% 50% 20% tr Q CL – 1.7 V – 2.0 V tf tr = Rise Time tf = Fall Time 50% = Timing Reference Levels Figure 1. Input Levels MOTOROLA FAST SRAM RL 0.1 µF 0.01 µF VEE RL = 50 Ω CL = 30 pF Figure 2. AC Test Circuit MCM101524 3 READ CYCLE 1 (See Notes 1, 2, and 5) tAVAV A (ADDRESS) tAXQX PREVIOUS DATA VALID DATA VALID Q (DATA OUT) tAVQV READ CYCLE 2 (See Note 6) tAVAV A (ADDRESS) tSLQV S (CHIP SELECT) tSHQL DATA VALID Q (DATA OUT) IEE tSLIEEH tSHIEEL SUPPLY CURRENT MCM101524 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) MCM101524–12 Parameter MCM101524–15 Symbol Min Max Min Max Unit Notes tAVAV 12 — 15 — ns 3 Address Setup Time tAVWL 1 — 1 — ns Address Valid to End of Write tAVWH 9 — 10 — ns Write Pulse Width tWLWH, tWLSH 8 — 9 — ns Data Valid to End of Write tDVWH 8 — 9 — ns Data Hold Time tWHDX 1 — 1 — ns Write High to Output Active tWHQX 4 — 4 — ns Write High to Output Valid tWHQV — 13 — 16 ns Write Recovery Time tWHAX 1 — 1 — ns Write Cycle Time Write Low to Output Low tWLQL 0 8 0 9 NOTES: 1. A write occurs during the overlap of S low and W low. 2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. This parameter is sampled and not 100% tested. 4 ns WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) tAVAV ADDRESS VALID A (ADDRESS) tAVWH tWHAX tAVWL S (CHIP SELECT) tWLSH DATA VALID D (DATA IN) tDVWH tWHDX tWLWH W (WRITE ENABLE) tWHQV tWLQL tWHQX Q (DATA OUT) Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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MOTOROLA FAST SRAM MCM101524 5 WRITE CYCLE 2 (S Controlled, See Notes 1 and 2) MCM101524–12 Parameter MCM101524–15 Symbol Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — ns 3 Address Setup Time tAVSL 1 — 1 — ns Address Valid to End of Write tAVSH 9 — 10 — ns tSLSH tSLWH 8 — 9 — ns Data Valid to End of Write tDVSH 8 — 9 — ns Chip Select Set–Up Time tSLWL 0 — 0 — ns Data Hold Time tSHDX 1 — 1 — ns Write Pulse Width (S) (W) Write Recovery Time tSHAX 1 — 1 — NOTES: 1. A write occurs during the overlap of S low and W low. 2. Product sensitivites to noise require proper grounding and decoupling of power supplies during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. ns WRITE CYCLE 2 (S Controlled, See Notes 1 and 2) tAVAV tAVSH A (ADDRESS) tSHAX tAVSL tSLSH S (CHIP SELECT) tSHDX tDVSH DATA VALID D (DATA IN) tSLWL tSLWH W (WRITE ENABLE) Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 101524 XX XX XX Motorola Memory Prefix Shipping Method (Blank = Rails) Part Number Speed (12 = 12 ns, 15 = 15 ns) Package (TB = TAB) Full Part Numbers — MCM101524TB12 MCM101524TB15 MCM101524 6 MOTOROLA FAST SRAM PACKAGE DIMENSIONS TB PACKAGE 400 MIL TAB CASE 984A–01 S P Z U CARRIER U1 36 1 S1 V W AD TAB TAPE J K 18 19 TAB TAPE REF 3X CARRIER VIEW AM R RETAINER -T- Y SECTION AN–AN 0.05 (0.002) T M-N S S H S B -N- AN C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 1.40 (0.055) 4X A -H- C1 VIEW AM TAPE CARRIER RETAINER ELIMINATED FROM VIEW FOR CLARITY MOTOROLA FAST SRAM -M- AN DIM A B C C1 J K P R S S1 U U1 V W Y Z AA AB AC AD AE AF AG AH AJ AK AL AR AS AT AU AV AV1 MILLIMETERS MIN MAX 18.14 REF 8.03 REF 26.95 BSC 26.95 BSC ––– 0.25 ––– 0.71 3.00 REF 2.39 REF 50.00 REF 50.00 REF 6.00 REF 6.00 REF 39.40 REF 45.68 REF 38.00 REF 1.15 1.25 16.21 16.31 11.20 11.30 8.99 9.09 0.15 0.21 0.762 BSC 0.18 0.28 21.31 21.24 35.00 REF 25.40 REF 26.95 BSC 34.98 REF 0.65 0.75 0.50 BSC 0.60 0.70 26.95 REF 25.35 25.45 25.35 25.45 INCHES MIN MAX 0.714 REF 0.316 REF 1.061 BSC 1.061 BSC ––– 0.010 ––– 0.028 0.118 REF 0.094 REF 1.969 REF 1.969 REF 0.236 REF 0.236 REF 1.551 REF 1.798 REF 1.496 REF 0.045 0.049 0.638 0.642 0.441 0.445 0.354 0.358 0.006 0.008 0.030 BSC 0.007 0.011 0.832 0.836 1.378 REF 1.000 REF 1.061 BSC 1.377 REF 0.026 0.030 0.020 BSC 0.024 0.028 1.061 REF 0.998 1.002 0.998 1.002 MCM101524 7 TB PACKAGE 400 MIL TAB CASE 984A–01 (cont.) 0.25 (0.010) T M-N S AK H AA AB AC S AE/2 4X AL S AJ 34X AE VIEW AP AH AG 0.05 (0.0020) 36X AF 0.25 (0.010) S T M-N S H S T M-N S H S S 196X AU AV REF 4X 0.10 (0.004) 2.00 (0.78) L T M-N H S 194X AR S AS AT 0.10 (0.004) L T M-N S H S REF AS VIEW AP AV1 BOTTOM VIEW Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM101524 8 ◊ CODELINE TO BE PLACED HERE *MCM101524/D* MCM101524/D MOTOROLA FAST SRAM