LINER LTC3605A 20v, 5a synchronous step-down regulator Datasheet

LTC3605A
20V, 5A Synchronous
Step-Down Regulator
Features
Description
High Efficiency: Up to 96%
nn 5A Output Current
nn 4V to 20V V Range
IN
nn Integrated Power N-Channel MOSFETs
(70mΩ Top and 35mΩ Bottom)
nn Adjustable Frequency 800kHz to 4MHz
nn PolyPhase® Operation (Up to 12 Phases)
nn Output Tracking
nn 0.6V ±1% Reference Accuracy
nn Current Mode Operation for Excellent Line and Load
Transient Response
nn Shutdown Mode Draws Less Than 15µA Supply Current
nn LTC3605: 15V Absolute Maximum V
IN
nn LTC3605A: 22V Absolute Maximum V
IN
nn The LTC3605A Is Pin Compatible with the LTC3605
nn Available in 24-Pin (4mm × 4mm) QFN Package
The LTC®3605A is a high efficiency, monolithic synchronous buck regulator using a phase lockable controlled
on-time constant frequency, current mode architecture.
PolyPhase operation allows multiple LTC3605A regulators to run out of phase while using minimal input and
output capacitance. The operating supply voltage range
is from 20V down to 4V, making it suitable for dual, triple
or quadruple lithium-ion battery inputs as well as point
of load power supply applications from a 12V or 5V rail.
nn
Applications
Point of Load Power Supply
Portable Instruments
nn Distributed Power Systems
nn Battery-Powered Equipment
nn
nn
The operating frequency is programmable from 800kHz to
4MHz with an external resistor. The high frequency capability allows the use of small surface mount inductors. For
switching noise sensitive applications, it can be externally
synchronized from 800kHz to 4MHz. The PHMODE pin
allows user control of the phase of the outgoing clock
signal. The unique constant frequency/controlled on-time
architecture is ideal for high step-down ratio applications
that are operating at high frequency while demanding
fast transient response. Two internal phase-lock loops
synchronize the internal oscillator to the external clock
and also servos the regulator on-time to lock on to either
the internal clock or the external clock if it’s present.
L, LT, LTC, LTM, PolyPhase, OPTI-LOOP, Linear Technology and the Linear logo are registered
trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents, including 5481178,
5847554, 6580258, 6304066, 6476589, 6774611.
Typical Application
Efficiency and Power Loss
High Efficiency 1MHz, 5A Step-Down Regulator
90
80
PVIN
CLKOUT
SVIN
INTVCC
2.2µF
CLKIN
BOOST
PGOOD
LTC3605A
SW
VON
VIN
10
VOUT = 3.3V
RUN
0.1µF 1µH
11.5k
FB
RT
ITH
47µF
×2
2.55k
16k
162k
VOUT
3.3V
PGND
70
1
60
50
40
0.1
30
20
VIN = 8V
VIN = 12V
VIN = 20V
10
0
0.01
220pF
0.1
1
LOAD CURRENT (A)
10
POWER LOSS (W)
22µF
×2
EFFICIENCY (%)
VIN
4V TO 20V
100
0.01
3605A TA01b
3605A TA01a
3605afc
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1
LTC3605A
Absolute Maximum Ratings
Pin Configuration
(Note 1)
SVIN
BOOST
INTVCC
SGND
CLKOUT
CLKIN
TOP VIEW
24 23 22 21 20 19
RT 1
18 PVIN
PHMODE 2
17 PVIN
MODE 3
16 SW
25
PGND
FB 4
15 SW
14 SW
ITH 6
13 SW
SW
SW
9 10 11 12
PGND
8
VON
7
RUN
TRACK/SS 5
PGOOD
PVIN, SVIN, SW Voltage.............................. –0.3V to 22V
SW Transient Voltage...................................–2V to 24.5V
BOOST Voltage...........................–0.3V to PVIN + INTVCC
RUN Voltage.............................................. –0.3V to SVIN
VON Voltage................................................ –0.3V to SVIN
INTVCC Voltage.......................................... –0.3V to 3.6V
ITH, RT, CLKOUT, PGOOD Voltage......... –0.3V to INTVCC
CLKIN, PHMODE, MODE Voltage........... –0.3V to INTVCC
TRACK/SS, FB Voltage........................... –0.3V to INTVCC
Operating Junction Temperature Range
(Note 2)................................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3605AEUF#PBF
LTC3605AEUF#TRPBF
3605A
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
LTC3605AIUF#PBF
LTC3605AIUF#TRPBF
3605A
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ ≈ TA = 25°C (Note 2). VIN = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
SVIN
SVIN Supply Range
PVIN
VIN Power Supply Range
IQ
Input DC Supply Current
Active
Shutdown
(Note 3)
Mode = 0, RT = 162k
VIN =12V, RUN = 0
VFB
Feedback Reference Voltage
ITH =1.2V (Note 4)
l
VIN = 4V to 20V, ITH = 1.2V
l
l
TYP
MAX
UNITS
4
20
V
1.2
20
V
1.5
11
5
40
mA
µA
0.600
0.606
V
0.001
0.03
%/V
0.1
0.3
%
0.594
DVFB(LINE)
Feedback Voltage Line Regulation
DVFB(LOAD)
Feedback Voltage Load Regulation
IFB
Feedback Pin Input Current
gm (EA)
Error Amplifier Transconductance
tON(MIN)
Minimum On-Time
40
ns
tOFF(MIN)
Minimum Off-Time
70
ns
2
ITH = 1.2V
1.15
1.35
±30
nA
1.6
mS
3605afc
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LTC3605A
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ ≈ TA = 25°C (Note 2). VIN = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
ILIM
Positive Inductor Valley Current Limit
Negative Inductor Valley Current Limit
RTOP
Top Power NMOS On-Resistance
5
6
–5
7.5
A
A
70
150
mΩ
RBOTTOM
Bottom Power NMOS On-Resistance
INTVCC = 3.3V
VUVLO
INTVCC Undervoltage Lockout
Threshold
INTVCC Falling
INTVCC Hysteresis (Rising)
2.4
35
60
mΩ
2.6
0.25
2.8
V
V
VRUN
Run Threshold 2 (IQ ≥ 1mA)
Run Threshold 1 (IQ ≥ 100µA)
RUN Rising
RUN Rising
1.1
0.45
1.2
0.6
1.3
0.75
V
V
VINTVCC
Internal VCC Voltage
4V < VIN < 20V
3.2
3.3
3.4
V
INTVCC = 3.3V
0.5
UNITS
DVINTVCC
INTVCC Load Regulation
ILOAD = 0mA to 20mA
OV
Output Overvoltage
PGOOD Upper Threshold
VFB Rising
7
10
13
%
UV
Output Undervoltage
PGOOD Lower Threshold
VFB Falling
–13
–10
–7
%
DVFB(HYS)
PGOOD Hysteresis
VFB Returning
RPGOOD
PGOOD Pull-Down Resistance
IPGOOD
PGOOD Leakage
ITRACK/SS
TRACK Pull-Up Current
fOSC
Oscillator Frequency
RT = 162k
CLKIN
CLKIN Threshold
CLKIN VIL
CLKIN VIH
1
VVIN_OV
VIN Overvoltage Lockout Threshold
VIN Rising
VIN Falling
22.8
20.8
1.5
12
0.54V < VFB < 0.66V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Absolute Maximum Ratings are those values
beyond which the life of a device may be impaired.
Note 2: The LTC3605A is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3605AE (E-grade) is guaranteed to meet specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3605AI (I-grade) is guaranteed over the full –40°C to 125°C operating
temperature range.
The junction temperature (TJ) is calculated from the ambient temperature
(TA) and power dissipation (PD) according to the formula:
TJ = TA + (PD • θJA°C/W)
where θJA is the package thermal impedance. Note that the maximum
ambient temperature is determined by specific operating conditions
in conjunction with board layout, the rated thermal package thermal
resistance and other environmental factors.
%
l
0.85
%
25
Ω
2
µA
2.5
4
1
1.2
MHz
0.3
V
V
24.2
22.1
V
V
23.5
21.5
µA
Note 3: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 4: The LTC3605A is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH).
Note 5: TJ is calculated from the ambient temperature TA and
power dissipation as follows: TJ = TA + PD • (37°C/W). See Thermal
Considerations section.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
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3
LTC3605A
Typical Performance Characteristics TA = 25°C unless otherwise specified.
2.0
70
60
50
40
30
20
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
10
0
0.01
0.1
1
LOAD CURRENT (A)
1.5
1.0
0.5
0
10
0
4
12
8
INPUT VOLTAGE (V)
3605A G01
10
5
4
0
MODE = 3.3V
NO LOAD
INTERNAL ITH
COMPENSATION
(ITH = 3.3V)
1.0
TOP FET
10
5
80
60
BOTTOM FET
40
0.5
1
1.5 2 2.5 3 3.5
FREQUENCY (MHz)
4
4.5
20
0.5
VIN = 12V
VOUT = 1.2V
f = 1MHz
MODE = INTVCC
0
EXTERNAL ITH
COMPENSATION
–0.5
–1.0
20
0
16
Load Regulation
1.5
100
15
12
8
INPUT VOLTAGE (V)
3605A G03
RDS(ON) vs Temperature
RDS(ON) (mΩ)
IINTVCC (mA)
15
0
20
120
20
0
16
Shutdown Current vs VIN
3605A G02
IINTVCC Current vs Frequency
25
20
NORMALIZED (%)
EFFICIENCY (%)
80
QUIESCENT CURRENT (mA)
VIN = 12V
90 fSW = 1MHz
Quiescent Current vs VIN
SHUTDOWN CURRENT (µA)
Efficiency vs Load Current
100
0
–45 –20
5
–1.5
30 55 80 105 130
TEMPERATURE (°C)
0
1
2
4
3
IOUT (A)
3605A G05
3605A G04
Load Step
(External ITH Compensation)
VOUT
100mV/DIV
AC-COUPLED
IL
5A/DIV
IL
5A/DIV
ILOAD
5A/DIV
ILOAD
5A/DIV
6
7
3605A G06
Load Step
(Internal ITH Compensation)
VOUT
100mV/DIV
AC-COUPLED
5
Output Tracking
VTRACK
VFB
VIN = 12V
VOUT = 1.2V
ILOAD = 0.4A
4
20µs/DIV
3605A G07
VIN = 12V
VOUT = 1.2V
ILOAD = 0.4A
ITH = 3.3V
20µs/DIV
3605A G08
VIN = 12V
VOUT = 1.2V
500µs/DIV
3605A G09
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LTC3605A
Typical Performance Characteristics TA = 25°C unless otherwise specified.
Switching Frequency vs RT
350
4.0
SWITCH LEAKAGE (nA)
FREQUENCY (MHz)
3.5
3.0
2.5
2.0
1.5
1.0
Efficiency vs VIN
96
300
94
250
92
200
150
100
0
50 100 150 200 250 300 350 400 450 500
RT (kΩ)
0
0
2
4
6
8 10 12
VIN (V)
1.5
1.0
0.5
0
2
4
6
8 10
VON (V)
12
80
14 16 18 20
14
16
18
ILOAD = 5A
0
5
10
15
VIN (V)
20
25
3505A G12
101
120
INTVCC Load Regulation
TA = 25°C
100
100
99
NORMALIZED INTVCC (%)
2.0
0
86
Current Limit Foldback
NORMALIZED MAXIMUM OUTPUT CURRENT (%)
FREQUENCY (MHz)
2.5
88
3605A G11
Frequency vs VON Voltage
VIN = 20V
RT = 162k
ILOAD = 1A
90
82
3605A G10
3.0
VOUT = 3.3V
84
50
0.5
0
Switch Leakage vs VIN
EFFICIENCY (%)
4.5
80
60
40
98
97
96
95
94
93
92
20
91
0
0
0.1
0.2
0.3 0.4
VFB (V)
0.5
0.6
0.7
90
0
80 100 120
40
60
20
INTVCC OUTPUT CURRENT (mA)
3605A G15
3605A G14
3605A G13
DCM Operation
RUN Pin Threshold vs Temperature
140
CCM Operation
1.30
RUN THRESHOLD (V)
1.25
1.20
CLKOUT
2V/DIV
CLKOUT
2V/DIV
VSW
5V/DIV
VSW
5V/DIV
IL
2A/DIV
IL
2A/DIV
1.15
1.10
1.05
1.00
–40
–15
60
35
85
10
TEMPERATURE (°C)
110
VIN = 20V
VOUT = 2.5V
MODE = 0V
IOUT = 0A
L1 = 0.5µH
400ns/DIV
3605A G17
VIN = 20V
VOUT = 2.5V
MODE = 3.3V
IOUT = 0A
L1 = 0.5µH
400ns/DIV
3605A G18
3605A G16
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5
LTC3605A
Pin Functions
RT (Pin 1): Oscillator Frequency Programming Pin. Connect an external resistor (between 200k to 40k) from RT
to SGND to program the frequency from 800kHz to 4MHz.
Since the synchronization range is ±30% of set frequency,
be sure that the set frequency is within this percentage
range of the external clock to ensure frequency lock.
VON (Pin 9): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT and keeps the
switching frequency constant at different VOUT. However,
when VON is <0.6V or >6V, then switching frequency will
no longer remain constant.
PHMODE (Pin 2): Control Input to Phase Selector. Determines the phase relationship between internal oscillator
and CLKOUT. Tie it to INTVCC for 2-phase operation, tie it
to SGND for 3-phase operation, and tie it to INTVCC/2 for
4-phase operation.
PGND (Pin 10, Exposed Pad Pin 25): Power Ground.
Return path of internal power MOSFETs. Connect this
pin to the negative terminals of the input capacitor and
output capacitor. The exposed pad must be soldered to
the PCB ground for electrical contact and rated thermal
performance.
MODE (Pin 3): Operation Mode Select. Tie this pin to
INTVCC to force continuous synchronous operation at
all output loads. Tying it to SGND enables discontinuous
mode operation at light loads. Tying this pin to INTVCC /2
shuts off the internal clock during discontinuous intervals.
FB (Pin 4): Output Feedback Voltage. Input to the error
amplifier that compares the feedback voltage to the internal
0.6V reference voltage. This pin is normally connected to
a resistive divider from the output voltage.
TRACK/SS (Pin 5): Output Tracking and Soft-Start Pin.
Allows the user to control the rise time of the output voltage. Putting a voltage below 0.6V on this pin bypasses
the internal reference input to the error amplifier, instead
it servos the FB pin to the TRACK voltage. Above 0.6V,
the tracking function stops and the internal reference
resumes control of the error amplifier. There’s an internal
2.5µA pull-up current from INTVCC on this pin, so putting
a capacitor here provides soft-start function.
ITH (Pin 6): Error Amplifier Output and Switching Regulator Compensation Point. The current comparator’s trip
threshold is linearly proportional to this voltage, whose
normal range is from 0.3V to 1.8V. Tying this pin to INTVCC activates internal compensation and output voltage
positioning, raising VOUT to 1.5% higher than the nominal
value at IOUT = 0 and 1.5% lower at IOUT = 5A.
RUN (Pin 7): Run Control Input. Enables chip operation
by tying RUN above 1.2V. Tying it below 1.1V shuts down
the part.
PGOOD (Pin 8): Output Power Good with Open-Drain
Logic. PGOOD is pulled to ground when the voltage on the
FB pin is not within ±10% of the internal 0.6V reference.
6
SW (Pins 11 to 16): Switch Node Connection to External
Inductor. Voltage swing of SW is from a diode voltage
drop below ground to PVIN.
PVIN (Pins 17, 18): Power VIN. Input voltage to the onchip power MOSFETs.
SVIN (Pin 19): Signal VIN. Filtered input voltage to the
on-chip 3.3V regulator. Connect a (1Ω to 10Ω) resistor
between SVIN and PVIN and bypass to GND with a 0.1µF
capacitor.
BOOST (Pin 20): Boosted Floating Driver Supply for Internal Top Power MOSFET. The (+) terminal of the bootstrap
capacitor connects here. This pin swings from a diode
voltage drop below INTVCC up to PVIN + INTVCC.
INTVCC (Pin 21): Internal 3.3V Regulator Output. The
internal power drivers and control circuits are powered
from this voltage. Decouple this pin to power ground with
a minimum of 1µF low ESR ceramic capacitor.
SGND (Pin 22): Signal Ground Connection.
CLKOUT (Pin 23): Output Clock Signal for PolyPhase
Operation. The phase of CLKOUT with respect to CLKIN
is determined by the state of the PHMODE pin. CLKOUT’s
peak-to-peak amplitude is INTVCC to GND.
CLKIN (Pin 24): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with 20k.
The phase-locked loop will force the top power NMOS’s
turn on signal to be synchronized with the rising edge of
the CLKIN signal.
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LTC3605A
Block Diagram
VOUT
VON
100K
0.6V
3pF
9
3 MODE
6V
35pF
SVIN
3.3V
REG
ION
PLL-SYNC
(±30%)
CIN2
CIN
17-18
ION
INTVCC
OST
21
V
tON = VON (0.64pF)
IION
VIN
INTVCC
R
S
BOOST
Q
20
CB
TG
12 x OSC
RT
1
+
PHMODE
2
RT
CLKIN
24
+
IREV
ICMP
–
OSC
PLL-SYNC
(±30%)
–
RUN
CLKOUT
11–16
SENSE–
BG
CVCC
10, 25
FOLDBACK
DISABLED
AT START-UP
3.3µA
+
0µA TO 10µA
M2
PGND
3pF
35pF
COUT
DB
SENSE+
–3.3µA TO 6.7µA
100k
L1
VOUT
SWITCH
LOGIC
AND
ANTISHOOT
THROUGH
OV
23
M1
SW
ON
20k
8
PGOOD
0.3V
FOLDBACK
x 4 + 0.6
–
1
180k
–
Q2 Q4
ITHB
R2
0.66V
OV
FB
+
Q6
Q1
4
R1
–
SGND
UV
22
+
–
EA
– + +
x=
PVIN
1Ω
19
SS
+
0.6V
0.6V
REF
ITH
6
RC
–
RUN
+
0.54V
INTVCC
2.5µA
1.2V
CC1
TRACK/SS
RUN
7
5
CSS
3605A BD
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7
LTC3605A
Operation
Main Control Loop
The LTC3605A is a current mode monolithic step-down
regulator. In normal operation, the internal top power
MOSFET is turned on for a fixed interval determined by
a one-shot timer, OST. When the top power MOSFET
turns off, the bottom power MOSFET turns on until the
current comparator, ICMP , trips, restarting the one-shot
timer and initiating the next cycle. Inductor current is determined by sensing the voltage drop across the bottom
power MOSFET ’s VDS. The voltage on the ITH pin sets
the comparator threshold corresponding to the inductor
valley current. The error amplifier, EA, adjusts this ITH
voltage by comparing the feedback signal, VFB, from the
output voltage with that of an internal 0.6V reference. If
the load current increases, it causes a drop in the feedback
voltage relative to the internal reference. The ITH voltage
then rises until the average inductor current matches that
of the load current.
At low load current, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator, IREV , which then shuts off the bottom power
MOSFET, resulting in discontinuous operation. Both power
MOSFETs will remain off with the output capacitor supplying
the load current until the ITH voltage rises above the zero
current level (0.6V) to initiate another cycle. Discontinuous mode operation is disabled by tying the MODE pin to
INTVCC, which forces continuous synchronous operation
regardless of output load.
The operating frequency is determined by the value of the
RT resistor, which programs the current for the internal
oscillator. An internal phase-lock loop servos the oscillator
frequency to an external clock signal if one is present on
the CLKIN pin. Another internal phase-lock loop servos the
switching regulator on-time to track the internal oscillator
to force constant switching frequency.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage, VFB, exits a ±10% window around the regulation
point. Continuous operation is forced during OV and UV
8
condition except during start-up when the TRACK pin is
ramping up to 0.6V.
Foldback current limiting is provided if the output is
shorted to ground. As VFB drops to zero, the maximum
sense voltage allowed across the bottom power MOSFET
is lowered to approximately 40% of the original value to
reduce the inductor valley current.
RUN Threshold
Pulling the RUN pin to ground forces the LTC3605A into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.6V turns on the internal reference only, while still
keeping the power MOSFETs off. Further increasing the
RUN voltage above 1.2V turns on the entire chip.
INTVCC Regulator
An internal low dropout (LDO) regulator produces the
3.3V supply that powers the drivers and the internal bias
circuitry. The INTVCC can supply up to 100mA RMS and
must be bypassed to ground with a minimum of 1µF
ceramic capacitor. Good bypassing is necessary to supply
the high transient currents required by the power MOSFET
gate drivers. Applications with high input voltage and high
switching frequency will increase die temperature because
of the higher power dissipation across the LDO. Connecting a load to the INTVCC pin is not recommended since
it will further push the LDO into its RMS current rating
while increasing power dissipation and die temperature.
VIN Overvoltage Protection
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC3605A constantly
monitors the VIN pin for an overvoltage condition. When
VIN rises above 23.5V, the regulator suspends operation
by shutting off both power MOSFETs. Once VIN drops
below 21.5V, the regulator immediately resumes normal
operation. The regulator does not execute its soft-start
function when exiting an overvoltage condition.
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LTC3605A
Operation
Output Voltage Programming
Output Power Good
The output voltage is set by an external resistive divider
according to the following equation:
When the LTC3605A’s output voltage is within the ±10%
window of the regulation point, which is reflected back as
a VFB voltage in the range of 0.54V to 0.66V, the output
voltage is good and the PGOOD pin is pulled high with
an external resistor. Otherwise, an internal open-drain
pull-down device (12Ω) will pull the PGOOD pin low.
To prevent unwanted PGOOD glitches during transients
or dynamic VOUT changes, the LTC3605A’s PGOOD falling edge includes a blanking delay of approximately 52
switching cycles.
VOUT = 0.6V • (1 + R2/R1)
The resistive divider allows the VFB pin to sense a fraction
of the output voltage as shown in Figure 1.
VOUT
R2
CFF
FB
LTC3605A
R1
Multiphase Operation
SGND
The internal PLL has a synchronization range of ±30%
around its programmed frequency. Therefore, during
external clock synchronization be sure that the external
clock frequency is within this ±30% range of the RT programmed frequency.
For output loads that demand more than 5A of current,
multiple LTC3605As can be cascaded to run out of phase
to provide more output current. The CLKIN pin allows the
LTC3605A to synchronize to an external clock (±30% of
frequency programmed by RT) and the internal phaselocked-loop allows the LTC3605A to lock onto CLKIN’s
phase as well. The CLKOUT signal can be connected to the
CLKIN pin of the following LTC3605A stage to line up both
the frequency and the phase of the entire system. Tying
the PHMODE pin to INTVCC, SGND or INTVCC/2 generates
a phase difference (between CLKIN and CLKOUT) of 180
degrees, 120 degrees, or 90 degrees respectively, which
corresponds to 2-phase, 3-phase or 4-phase operation. A
total of 12 phases can be cascaded to run simultaneously
out of phase with respect to each other by programming
the PHMODE pin of each LTC3605A to different levels.
Output Voltage Tracking and Soft-Start
Internal/External ITH Compensation
The LTC3605A allows the user to program its output voltage
ramp rate by means of the TRACK/SS pin. An internal 2µA
pulls up the TRACK/SS pin to INTVCC. Putting an external
capacitor on TRACK/SS enables soft starting the output
to prevent current surge on the input supply. For output
tracking applications, TRACK/SS can be externally driven
by another voltage source. From 0V to 0.6V, the TRACK/SS
voltage will override the internal 0.6V reference input to the
error amplifier, thus regulating the feedback voltage to that
of TRACK/SS pins. During this start-up time, the LTC3605A
will operate in discontinuous mode. When TRACK/SS is
above 0.6V, tracking is disabled and the feedback voltage
will regulate to the internal reference voltage.
During single phase operation, the user can simplify the
loop compensation by tying the ITH pin to INTVCC to enable internal compensation. This connects an internal 30k
resistor in series with a 40pF capacitor to the output of
the error amplifier (internal ITH compensation point) while
also activating output voltage positioning such that the
output voltage will be 1.5% above regulation at no load and
1.5% below regulation at full load. This is a trade-off for
simplicity instead of OPTI-LOOP® optimization, where ITH
components are external and are selected to optimize the
loop transient response with minimum output capacitance.
3605A F01
Figure 1. Setting the Output Voltage
Programming Switching Frequency
Connecting a resistor from the RT pin to SGND programs
the switching frequency from 800kHz to 4MHz according
to the following formula:
Frequency (Hz) =
1.6e11
RT (W)
For more information www.linear.com/LTC3605A
3605afc
9
LTC3605A
Operation
Minimum Off-Time and Minimum On-Time
Considerations
The minimum off-time, tOFF(MIN), is the smallest amount of
time that the LTC3605A is capable of turning on the bottom power MOSFET, tripping the current comparator and
turning the power MOSFET back off. This time is generally
about 70ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum
duty cycle is reached, due to a dropping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
VIN(MIN) = VOUT •
tON + tOFF(MIN)
tON
Conversely, the minimum on-time is the smallest duration of time in which the top power MOSFET can be in
its “on” state. This time is typically 40ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
DCMIN = f • tON(MIN)
where tON(MIN) is the minimum on-time. As the equation
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In the rare cases where the minimum duty cycle is
surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its
programmed value. This is an acceptable result in many
applications, so this constraint may not be of critical
importance in most cases. High switching frequencies
may be used in the design without any fear of severe
consequences. As the sections on inductor and capacitor
selection show, high switching frequencies allow the use
of smaller board components, thus reducing the size of
the application circuit.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
10
IRMS ≅ IOUT(MAX)
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS ≅ IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response. The output ripple, DVOUT, is
determined by:
⎛
⎞
1
DVOUT < DIL ⎜
+ESR⎟
⎠
⎝ 8 • f • COUT
The output ripple is highest at maximum input voltage
since DIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR
and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic, and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors are very low ESR but have
lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteristics
and small footprints. Their relatively low value of bulk
capacitance may require multiples in parallel.
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LTC3605A
Operation
Using Ceramic Input and Output Capacitors
Inductor Selection
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
VIN input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause
a voltage spike at VIN large enough to damage the part.
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple current:
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
A reasonable starting point is to choose a ripple current
that is about 50% of IOUT(MAX). This is especially important at low VOUT operation where VOUT is 1.8V or below.
Care must be given to choose an inductance value that
will generate a big enough current ripple (40% to 50%)
so that the chip’s valley current comparator has enough
signal-to-noise ratio to force constant switching frequency.
Meanwhile, also note that the largest ripple current occurs
at the highest VIN. To guarantee that ripple current does
not exceed a specified maximum, the inductance should
be chosen according to:
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and the
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does
the output drop linearly. The output droop, VDROOP , is
usually about 2 to 3 times the linear drop of the first cycle.
Thus, a good place to start with the output capacitor value
is approximately:
COUT ≈ 2.5
DIOUT
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance to
the supply is very low. A 22µF ceramic capacitor is usually
enough for these conditions. Place this input capacitor as
close to the PVIN pins as possible.
DIL =
⎞
VOUT ⎛
V
⎜⎜1– OUT ⎟⎟
f • L ⎝ VIN(MAX) ⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
L=
⎞
⎛
VOUT
V
• ⎜⎜1– OUT ⎟⎟
f • DIL(MAX) ⎝ VIN(MAX) ⎠
However, the inductor ripple must not be so large that its
valley current level can exceed the negative current limit,
which can be as low as –3.5A. If the negative current limit
is exceeded in forced continuous mode of operation, VOUT
can get charged to above the regulation level until the
inductor current no longer exceeds the negative current
limit. In such instances, choose a larger inductor value
to reduce the inductor ripple current. The alternative is
to reduce the RT resistor value to increase the switching
frequency in order to reduce the inductor ripple current.
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
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11
LTC3605A
Operation
inductance selected. As the inductance or frequency increases, core losses decrease. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Table 1. Inductor Selection Table
INDUCTANCE
DCR
MAX CURRENT
DIMENSIONS
HEIGHT
6.7mm × 7mm
3mm
4.3mm × 4.7mm
2.0mm
7mm × 7.7mm
2.0mm
Vishay IHLP-2525CZ-01 Series
0.33µH
4.1mW
18A
0.47µH
6.5mW
13.5A
0.68µH
9.4mW
11A
0.82µH
11.8mW
10A
1.0µH
14.2mW
9A
Vishay IHLP-1616BZ-11 Series
0.22µH
4.1mW
12A
0.47µH
15mW
7A
Toko FDV0620 Series
0.20µH
4.5mW
12.4A
0.47µH
8.3mW
9A
1µH
18.3mW
5.7A
4.5mW
16.6A
0.75µH
7.5mW
12.2A
1µH
9mW
10.6A
6.9mm × 7.7mm
3.0mm
7mm × 7.3mm
3.0mm
Cooper HCP0703 Series
0.22µH
2.8mW
23A
0.47µH
4.2mW
17A
0.68µH
5.5mW
15A
0.82µH
8mW
13A
1µH
10mW
11A
1.5µH
14mW
9A
TDK RLF7030 Series
1µH
8.8mW
6.4A
1.5µH
9.6mW
6.1A
2.2µH
12mW
5.4A
6.9mm × 7.3mm
3.2mm
7mm × 7.7mm
3.8mm
Würth Elektronik WE-HC 744312 Series
0.25µH
2.5mW
18A
0.47µH
3.4mW
16A
0.72µH
7.5mW
12A
1µH
9.5mW
11A
1.5µH
10.5mW
9A
12
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK and Würth Elektronik. Refer to
Table 1 for more details.
Checking Transient Response
NEC/Tokin MLC0730L Series
0.47µH
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The OPTI-LOOP compensation allows the transient response to be optimized for a wide range of loads and
output capacitors. The availability of the ITH pin not
only allows optimization of the control loop behavior but
also provides a DC-coupled and AC-filtered closed-loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed-loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
The ITH external components shown in the circuit on the
first page of this data sheet provides an adequate starting
point for most applications. The series R-C filter sets the
dominant pole zero loop compensation. The values can
be modified slightly (from 0.5 to 2 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type
and value have been determined. The output capacitors
need to be selected because their various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
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LTC3605A
Operation
having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the
overall loop stability without breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to DILOAD • ESR, where
ESR is the effective series resistance of COUT. DILOAD also
begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with the R and the
bandwidth of the loop increases with decreasing C. If R
is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor, CFF ,
can be added to improve the high frequency response, as
shown in Figure 1. Capacitor CFF provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>10µF) input capacitors.
The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates
current limiting, short-circuit protection and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100%–(L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC3605A circuits: 1) I2R losses, 2) switching
and biasing losses, 3) other losses.
1. I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
of both top and bottom MOSFET RDS(ON) and the duty
cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1-DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
2. The INTVCC current is the sum of the power MOSFET
driver and control currents. The power MOSFET driver
current results from switching the gate capacitance of
the power MOSFETs. Each time a power MOSFET gate is
switched from low to high to low again, a packet of charge
dQ moves from INTVCC to ground. The resulting dQ/dt
is a current out of INTVCC that is typically much larger
than the DC control bias current. In continuous mode,
IGATECHG = f(QT + QB), where QT and QB are the gate
charges of the internal top and bottom power MOSFETs
and f is the switching frequency. Since INTVCC is a low
dropout regulator output powered by VIN, its power
loss equals:
PLDO = VIN • IINTVCC
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13
LTC3605A
Operation
Refer to the IINTVCC vs Frequency curve in the Typical
Performance Characteristics for typical INTVCC current
at various frequencies.
3. Other “hidden” losses such as transition loss and copper trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
node transitions. The LTC3605A internal power devices
switch quickly enough that these losses are not significant compared to other sources. Other losses including
diode conduction losses during dead-time and inductor
core losses which generally account for less than 2%
total additional loss.
Thermal Considerations
In a majority of applications, the LTC3605A does not dissipate much heat due to its high efficiency and low thermal
resistance of its exposed-back QFN package. However, in
applications where the LTC3605A is running at high ambient temperature, high VIN, high switching frequency and
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 160°C,
both power switches will be turned off until the temperature
drops about 15°C cooler.
6
LOAD CURRENT (A)
5
3
2
VIN = 12V
VOUT = 3.3V
fSW = 1MHz
DC1215 DEMO BOARD
1
20
60
80
100
120
40
AMBIENT TEMPERATURE (°C)
140
3605A F02
Figure 2. Load Current vs Ambient Temperature
14
TRISE = PD • θJA
As an example, consider the case when the LTC3605A is
used in applications where VIN = 12V, IOUT = 5A, f = 1MHz,
VOUT = 1.8V. The equivalent power MOSFET resistance
RSW is:
RSW = RDS(ON)Top •
⎛ V ⎞
VOUT
+RDS(ON)Bot ⎜1– OUT ⎟
VIN
VIN ⎠
⎝
10.2
1.8
+ 35mW •
12
12
= 40.25mW
= 70mW •
The VIN current during 1MHz force continuous operation
with no load is about 11mA, which includes switching
and internal biasing current loss, transition loss, inductor
core loss and other losses in the application. Therefore,
the total power dissipated by the part is:
PD = IOUT2 • RSW + VIN • IVIN (No Load)
= 25A2 • 40.25mΩ + 12V • 11mA = 1.14W
The QFN 4mm × 4mm package junction-to-ambient thermal
resistance, θJA, is around 37°C/W. Therefore, the junction
temperature of the regulator operating in a 25°C ambient
temperature is approximately:
TJ = 1.14W • 37°C/W + 25°C = 67°C
4
0
To avoid the LTC3605A from exceeding the maximum junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. Redoing the calculation
assuming that RSW increased 15% at 67°C yields a new
junction temperature of 72°C. If the application calls for
a higher ambient temperature and/or higher switching
frequency, care should be taken to reduce the temperature
rise of the part by using a heat sink or air flow. Figure 2
is a temperature derating curve based on the DC1215
demo board.
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LTC3605A
Operation
Junction Temperature Measurement
The junction-to-ambient thermal resistance will vary depending on the size and amount of heat sinking copper
on the PCB board where the part is mounted, as well as
the amount of air flow on the device. One of the ways to
measure the junction temperature directly is to use the
internal junction diode on one of the pins (PGOOD) to
measure its diode voltage change based on ambient
temperature change. First remove any external passive
component on the PGOOD pin, then pull out 100µA from
the PGOOD pin to turn on its internal junction diode and
bias the PGOOD pin to a negative voltage. With no output
current load, measure the PGOOD voltage at an ambient
temperature of 25°C, 75°C and 125°C to establish a slope
relationship between the delta voltage on PGOOD and
delta ambient temperature. Once this slope is established,
then the junction temperature rise can be measured as a
function of power loss in the package with corresponding
output load current. Keep in mind that doing so will violate
absolute maximum voltage ratings on the PGOOD pin,
however, with the limited current, no damage will result.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3605A (refer to Figure 3). Check the following in
your layout:
CIN
1. Do the capacitors CIN connect to the power PVIN and
power PGND as close as possible? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers.
2. Are COUT and L1 closely connected? The (–) plate of
COUT returns current to PGND and the (–) plate of CIN.
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground line terminated near SGND. The feedback signal VFB should be
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized. Keep
R1 and R2 close to the IC.
4. Solder the Exposed Pad (Pin 25) on the bottom of the
package to the PGND plane. Connect this PGND plane
to other layers with thermal vias to help dissipate heat
from the LTC3605A.
5. Keep sensitive components away from the SW pin. The
RT resistor, the compensation capacitor CC and CITH
and all the resistors R1, R3 and RC, and the INTVCC
bypass capacitor, should be placed away from the SW
trace and the inductor L1. Also, the SW pin pad should
be kept as small as possible.
6. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with smallsignal components returning to the SGND pin which is
then connected to the PGND pin at the negative terminal
of the output capacitor, COUT.
L1
VIN
GND
VOUT
VIN
VOUT
COUT
GND
3605A F03b
3605A F03a
Figure 3a. Sample PCB Layout—Topside
Figure 3b. Sample PCB Layout—Bottom Side
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15
LTC3605A
Operation
Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components. These
copper areas should be connected to PGND.
The nearest standard value inductor would be 0.33µH.
Design Example
As a design example, consider using the LTC3605A in an
application with the following specifications:
VIN = 10.8V to 13.2V, VOUT = 1.8V, IOUT(MAX) = 5A,
IOUT(MIN) = 500mA, f = 2MHz
Because efficiency is important at both high and low load
current, discontinuous mode operation will be utilized.
First select from the characteristic curves the correct RT
resistor value for 2MHz switching frequency. Based on that
RT should be 80.6k. Then calculate the inductor value for
about 50% ripple current at maximum VIN:
16
⎛
⎞⎛
1.8V
1.8V ⎞
L =⎜
⎟⎜1–
⎟ = 0.31µH
⎝ 2MHz • 2.5A ⎠⎝ 13.2V ⎠
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
47µF ceramic capacitors will be used.
CIN should be sized for a maximum current rating of:
⎛ 1.8V ⎞⎛ 13.2V ⎞1/2
IRMS = 5A ⎜
– 1⎟ = 1.7A
⎟⎜
⎝ 13.2V ⎠⎝ 1.8V
⎠
Decoupling the PVIN pins with two 22µF ceramic capacitors is adequate for most applications.
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LTC3605A
Typical Applications
12V to 1.2V 1MHz Buck Regulator
C1
2.2µF
0.1µF
D1
10Ω
23
24
1
162k
2
3
4
5
12k
330pF
6
10pF
0.1µF
22
21
20
CLKIN CLKOUT SGND INTVCC BOOST SVIN
RT
PVIN
PHMODE
PVIN
MODE
SW
LTC3605A
FB
SW
TRACK/SS
SW
ITH
SW
RUN
PGOOD
7
SVIN
VON
PGND
9
10
8
SW
11
CIN
22µF
×2
19
18
VIN
4V TO 20V
0.1µF
17
16
L1 0.68µH
15
47pF
14
COUT
47µF
×2
13
SW
4.99k
VOUT
1.2V
5A
4.99k
12
100k
PGND
SGND
3605A TA02
C1: AVX 0805ZD225MAT2A
CIN: TDK C4532X5RIC226M
COUT: TDK C3216X5ROJ476M
D1: CENTRAL SEMI CMDSH-3
L1: VISHAY IHLP-2525CZERR68-M01
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17
LTC3605A
Typical Applications
12V, 10A 2-Phase Single Output Regulator
0.1µF
C1
2.2µF
D1
10Ω
24
1
162k
2
3
4
5
6
5.4k
470pF
0.1µF
23
22
21
20
CLKIN CLKOUT SGND INTVCC BOOST SVIN
RT
PVIN
PHMODE
PVIN
MODE
18
SW
TRACK/SS
SW
10pF
PGOOD
7
VON
PGND
9
10
8
SVIN
SW
11
L1 1.5µH
15
14
10k
COUT1
47µF
×2
13
SW
RUN
0.1µF
16
SW
FB
VIN
4V TO 20V
17
LTC3605A
ITH
CIN1
22µF
×2
19
SW
100pF
VOUT
3.3V
10A
2.21k
12
100k
PGND
SGND
0.1µF
C2
2.2µF
D2
10Ω
24
1
162k
2
3
4
5
6
5.4k
470pF
21
20
PVIN
PHMODE
PVIN
SW
MODE
LTC3605A
FB
SW
TRACK/SS
SW
ITH
SW
PGOOD
8
VON
PGND
9
10
SW
11
CIN2
22µF
×2
19
RT
7
C1, C2: AVX 0805ZD225MAT2A
CIN1, CIN2: TDK C4532X5RIC226M
COUT1, COUT2: TDK C3216X5ROJ476M
D1, D2: CENTRAL SEMI CMDSH-3
L1, L2: VISHAY IHLP-2525CZER1R5-M01
22
CLKIN CLKOUT SGND INTVCC BOOST SVIN
RUN
10pF
23
0.1µF
18
17
16
15
L2 1.5µH
14
COUT2
47µF
13
SW
12
SVIN
PGND
3605A TA03
12V, 10A, 2-Phase Efficiency
100
90
EFFICIENCY (%)
80
70
12V, 10A, 2-Phase Load Step
VOUT
100mV/DIV
AC-COUPLED
DCM
CCM
60
IL1
2A/DIV
50
40
IL2
2A/DIV
30
20
20µs/DIV
10
0
0.1
SGND
1
LOAD CURRENT (A)
3605A TA03c
10
3605A TA03b
18
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For more information www.linear.com/LTC3605A
LTC3605A
Typical Applications
Dual Output Tracking Application
C1
2.2µF
0.1µF
D1
10Ω
23
24
1
162k
2
3
4
5
16.2k
100pF
6
10pF
0.1µF
22
21
20
CLKIN CLKOUT SGND INTVCC BOOST SVIN
RT
PVIN
PHMODE
PVIN
MODE
18
SW
TRACK/SS
SW
ITH
SW
PGOOD
7
VON
PGND
9
10
8
SVIN1
SW
L1 0.33µH
15
14
7.5k
COUT1
47µF
13
11
4.99k
PGND
SGND
0.1µF
D2
1
162k
2
3
4
5
16.2k
100pF
6
10pF
23
22
21
20
RT
PVIN
PHMODE
PVIN
MODE
SW
LTC3605A
FB
SW
TRACK/SS
SW
ITH
SW
7
SVIN2
PGOOD
VON
PGND
9
10
8
SW
CIN2
22µF
×2
19
CLKIN CLKOUT SGND INTVCC BOOST SVIN
RUN
2.49k
12
10Ω
24
VOUT1
1.8V
5A
SW
100k
C2
2.2µF
0.1µF
16
SW
FB
VIN1
4V TO 20V
17
LTC3605A
RUN
CIN1
22µF
×2
19
18
VIN2
4V TO 20V
0.1µF
17
16
L2 0.33µH
15
VOUT2
1.2V
5A
4.99k
14
13
COUT2
47µF
4.99k
SW
11
12
100k
PGND
SGND
3605A TA04
C1, C2: AVX 0805ZD225MAT2A
CIN1, CIN2: TDK C4532X5RIC226M
COUT1, COUT2: TDK C3216X5ROJ476M
D1, D2: CENTRAL SEMI CMDSH-3
L1, L2: VISHAY IHLP-2525CZERR33-M01
Dual Output Tracking Waveform
VOUT1
500mV/DIV
VOUT2
500mV/DIV
500µs/DIV
VIN = 12V
VOUT1 = 1.8V, VOUT2 = 1.2V
IOUT1 = 80mA, IOUT2 = 80mA
3605A TA04b
3605afc
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19
LTC3605A
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697 Rev B)
0.70 ±0.05
4.50 ±0.05
2.45 ±0.05
3.10 ±0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
0.75 ±0.05
PIN 1 NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
23 24
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
2.45 ±0.10
(4-SIDES)
(UF24) QFN 0105 REV B
0.200 REF
0.00 – 0.05
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
20
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LTC3605A
Revision History
REV
DATE
DESCRIPTION
A
12/12
Updated VVIN_OV specification.
PAGE NUMBER
B
09/13
Clarified conditions for electrical specifications.
Clarified specifications in the Electrical Characteristics section.
Clarified TRACK/SS pin description.
Clarified schematics.
C
04/15
3
2, 3
3
6
7, 17
Clarified the Main Control Loop description and added RUN Threshold section header.
8
Clarified negative valley current limit parameter.
3
Added negative valley current limit explanation.
11
3605afc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC3605A
21
LTC3605A
Typical Application
–3.6V Negative Converter
C1
2.2µF
CIN
22µF
×2
0.1µF
D1
10Ω
24
1
2
162k
3
4
5
16.2k
470pF
6
47pF
0.1µF
23
22
21
20
CLKIN CLKOUT SGND INTVCC BOOST SVIN
RT
PVIN
PHMODE
PVIN
MODE
SW
LTC3605A
FB
SW
TRACK/SS
SW
ITH
SW
RUN
7
SVIN
PGOOD
VON
PGND
9
10
8
SW
11
VIN
3V TO 16V
19
0.1µF
18
17
16
L1 1µH
15
14
24.9k
13
COUT
47µF
×2
SW
4.99k
12
100k
3605A TA05
–3.6V Negative Converter Efficiency
VOUT
–3.6V
2A
–3.6V Negative Converter
100
90
EFFICIENCY (%)
80
DCM
70
60
50
SW
CCM
IL
2A/DIV
40
30
20
VIN = 12V
VOUT = –3.6V
ILOAD = 2A
10
0
0.01
0.1
1
LOAD CURRENT (A)
10
400ns/DIV
3605A TA05c
3605A TA05b
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PART NUMBER DESCRIPTION
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LTC3608
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LTC3610
24V, 12A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter
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LTC3611
32V, 10A (IOUT), 1MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 4V to 32V, VOUT(MIN) = 0.6V, IQ = 900µA,
ISD < 15µA, 9mm × 9mm QFN-64
22 Linear Technology Corporation
95% Efficiency, VIN: 4V to 15V, VOUT(MIN) = 0.6V, IQ = 2mA,
ISD < 1µA, 4mm × 4mm QFN-24
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC3605A
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC3605A
3605afc
LT 0415 REV C • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2012