FDB3682 / FDP3682
N-Channel PowerTrench® MOSFET
100V, 32A, 36mΩ
Features
Applications
• r DS(ON) = 32mΩ (Typ.), VGS = 10V, ID = 32A
• DC/DC converters and Off-Line UPS
• Qg(tot) = 18.5nC (Typ.), VGS = 10V
• Distributed Power Architectures and VRMs
• Low Miller Charge
• Primary Switch for 24V and 48V Systems
• Low QRR Body Diode
• UIS Capability (Single Pulse and Repetitive Pulse)
• High Voltage Synchronous Rectifier
• Qualified to AEC Q101
• Direct Injection / Diesel Injection System
Formerly developmental type 82755
• 42V Automotive Load Control
• Electronic Valve Train System
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
G
SOURCE
TO-263AB
FDB SERIES
D
TO-220AB
DRAIN
(FLANGE)
S
FDP SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
100
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC = 25oC, VGS = 10V)
32
A
Continuous (TC = 100oC, VGS = 10V)
23
A
6
A
Drain Current
ID
Continuous (Tamb = 25oC, VGS = 10V, R θJA = 43oC/W)
Pulsed
E AS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 1)
Power dissipation
Derate above 25oC
Operating and Storage Temperature
Figure 4
A
55
mJ
95
W
0.63
W/oC
-55 to 175
oC
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-220, TO-263
RθJA
Thermal Resistance Junction to Ambient TO-220, TO-263 (Note 2)
RθJA
2
Thermal Resistance Junction to Ambient TO-263, 1in copper pad area
1.58
o
C/W
62
o
C/W
43
o
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2002 Fairchild Semiconductor Corporation
FDB3682 / FDP3682 Rev. B
FDB3682 / FDP3682
September 2002
Device Marking
FDB3682
Device
FDB3682
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
FDP3682
FDP3682
TO-220AB
Tube
N/A
50 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
100
-
-
V
-
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
V GS = VDS, ID = 250µA
2
-
4
V
ID=32A, VGS=10V
-
0.032
0.036
VDS = 80V
VGS = 0V
TC = 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
Ω
ID = 16A, VGS = 6V,
-
0.040
0.060
ID=32A, VGS=10V, TC=175oC
-
0.080
0.090
-
1250
-
-
190
-
pF
-
45
-
pF
nC
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 25V, VGS = 0V,
f = 1MHz
pF
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
-
18.5
28
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
-
2.4
3.6
nC
Qgs
Gate to Source Gate Charge
-
6.5
-
nC
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDD = 50V
ID = 32A
Ig = 1.0mA
-
4.1
-
nC
-
4.6
-
nC
ns
Resistive Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
83
td(ON)
Turn-On Delay Time
-
9
-
ns
tr
Rise Time
-
46
-
ns
td(OFF)
Turn-Off Delay Time
-
26
-
ns
tf
Fall Time
-
32
-
ns
tOFF
Turn-Off Time
-
-
87
ns
V
VDD = 50V, ID = 32A
VGS = 10V, RGS = 16Ω
Drain-Source Diode Characteristics
ISD = 32A
-
-
1.25
ISD = 16A
-
-
1.0
V
Reverse Recovery Time
ISD = 32A, dISD/dt = 100A/µs
-
-
55
ns
Reverse Recovery Charge
ISD = 32A, dISD/dt = 100A/µs
-
-
90
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 0.27mH, IAS = 20A.
2: Pulse Width = 100s
©2002 Fairchild Semiconductor Corporation
FDB3682 / FDP3682 Rev. B
FDB3682 / FDP3682
Package Marking and Ordering Information
FDB3682 / FDP3682
1.2
35
1.0
30
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Characteristics TC = 25°C unless otherwise noted
0.8
0.6
0.4
VGS = 10V
25
20
15
10
0.2
5
0
0
25
50
75
100
150
125
0
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x R θJC + TC
SINGLE PULSE
0.01
10-4
10 -5
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
400
TC = 25oC
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
VGS = 10V
150
100
30
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
FDB3682 / FDP3682 Rev. B
FDB3682 / FDP3682
Typical Characteristics TC = 25°C unless otherwise noted
100
200
10µs
IAS, AVALANCHE CURRENT (A)
100
ID, DRAIN CURRENT (A)
100µs
1ms
10
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
SINGLE PULSE
TJ = MAX RATED
DC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
10
STARTING TJ = 150oC
TC = 25 oC
1
0.1
1
10
100
200
0.001
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 20V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
80
60
40
TJ = 175o C
TJ = 25o C
20
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
60
TC = 25oC
VGS = 6V
40
20
TJ = -55oC
VGS = 5V
0
0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0
7.5
1
VGS , GATE TO SOURCE VOLTAGE (V)
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
3.0
60
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE (mΩ)
10
VGS = 6V
50
40
VGS = 10V
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
2.0
1.5
1.0
VGS = 10V, ID =32A
0.5
20
0
5
10
15
20
25
30
35
Id, DRAIN CURRENT (A)
Figure 9. Drain to Source On Resistance vs Drain
Current
©2002 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDB3682 / FDP3682 Rev. B
FDB3682 / FDP3682
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
0.4
ID = 250µA
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
-80
-40
TJ, JUNCTION TEMPERATURE (o C)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
40
80
120
160
200
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
2000
VGS, GATE TO SOURCE VOLTAGE (V)
10
1000
C, CAPACITANCE (pF)
0
TJ , JUNCTION TEMPERATURE (o C)
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
20
0.1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2002 Fairchild Semiconductor Corporation
100
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 32A
ID = 16A
2
0
0
5
10
15
20
Qg, GATE CHARGE (nC)
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
FDB3682 / FDP3682 Rev. B
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS = 10V
VGS
+
VDD
VGS
-
VGS = 2V
DUT
Qgs2
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDB3682 / FDP3682 Rev. B
FDB3682 / FDP3682
Test Circuits and Waveforms
FDB3682 / FDP3682
Thermal Resistance vs. Mounting Pad Area
(T
–T )
JM
A
P D M = ----------------------------R θ JA
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P DM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
80
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (o C/W)
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
40
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2)
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeter
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
(EQ. 2)
Area in Inches Squared
R
θ JA
128
( 1.69 + Area )
= 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeters Squared
©2002 Fairchild Semiconductor Corporation
FDB3682 / FDP3682 Rev. B
rev May 2002
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
RSLC2
5
51
Ebreak 11 7 17 18 108
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
-
It 8 17 1
DRAIN
2
5
EVTHRES
+ 19 8
+
LGATE
GATE
1
Lgate 1 9 5.96e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 3.19e-9
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
.SUBCKT FDB3682 2 1 3 ;
CA 12 8 4e-10
Cb 15 14 5.5e-10
Cin 6 8 1.22e-9
EVTEMP
RGATE +
18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
7
RSOURCE
RLgate 1 9 59.6
RLdrain 2 5 10
RLsource 3 7 31.9
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
14
13
S1B
CA
15
17
18
RVTEMP
CB
6
8
5
8
EDS
-
19
VBAT
+
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 10.5e-3
Rgate 9 20 1.86
RSLC1 5 51 RSLCMOD 1.0e-6
RSLC2 5 50 1.0e3
Rsource 8 7 RsourceMOD 11.9e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RLSOURCE
RBREAK
S2B
13
SOURCE
3
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*70),2.5))}
.MODEL DbodyMOD D (IS=2.4E-12 RS=4.4e-3 TRS1=2.0e-3 TRS2=4.5e-7
+ CJO=9e-10 M=0.57 TT=2.9e-8 XTI=4.0)
.MODEL DbreakMOD D (RS=0.6 TRS1=1.4e-3 TRS2=-5.0e-5)
.MODEL DplcapMOD D (CJO=2.7e-10 IS=1.0e-30 N=10 M=0.56)
.MODEL MstroMOD NMOS (VTO=4.16 KP=32 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=3.48 KP=2.7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.86)
.MODEL MweakMOD NMOS (VTO=2.97 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=18.6 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=-1.1e-8)
.MODEL RdrainMOD RES (TC1=1.6e-2 TC2=4e-5)
.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.9e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.1e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-3.5e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-5.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
FDB3682 / FDP3682 Rev. B
FDB3682 / FDP3682
PSPICE Electrical Model
FDB3682 / FDP3682
SABER Electrical Model
REV May 2002
template FDB3682 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-12,rs=4.4e-3,trs1=2.0e-3,trs2=4.5e-7,cjo=9e-10,m=0.57,tt=2.9e-8,xti=4.0)
dp..model dbreakmod = (rs=0.6,trs1=1.4e-3,trs2=-5e-5)
dp..model dplcapmod = (cjo=2.7e-10,isl=10e-30,nl=10,m=0.56)
m..model mstrongmod = (type=_n,vto=4.16,kp=32,is=1e-30, tox=1)
m..model mmedmod = (type=_n,vto=3.48,kp=2.7,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.97,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5)
DPLCAP 5
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3)
10
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4)
RSLC1
c.ca n12 n8 = 4e-10
51
c.cb n15 n14 = 5.5e-10
RSLC2
c.cin n6 n8 = 1.22e-9
LDRAIN
DRAIN
2
RLDRAIN
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
spe.ebreak n11 n7 n17 n18 = 108
spe.eds n14 n8 n5 n8 = 1
GATE
spe.egs n13 n8 n6 n8 = 1
1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
LGATE
EVTEMP
RGATE +
18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
7
RSOURCE
i.it n8 n17 = 1
S1A
l.lgate n1 n9 = 5.96e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 3.19e-9
res.rlgate n1 n9 = 59.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 31.9
DBREAK
50
-
12
S2A
13
8
S1B
CA
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RLSOURCE
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
-
19
IT
14
+
+
EGS
SOURCE
3
VBAT
5
8
EDS
-
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=-1.1e-8
res.rdrain n50 n16 = 10.5e-3, tc1=1.6e-2,tc2=4e-5
res.rgate n9 n20 = 1.86
res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=2.9e-6
res.rslc2 n5 n50 = 1.0e3
res.rsource n8 n7 = 11.9e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.1e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-3.5e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/70))** 2.5))
}
}
©2002 Fairchild Semiconductor Corporation
FDB3682 / FDP3682 Rev. B
th
JUNCTION
REV 20 May 2002
FDB3682_JC TH TL
CTHERM1 TH 6 1.6e-3
CTHERM2 6 5 4.5e-3
CTHERM3 5 4 5.0e-3
CTHERM4 4 3 8.0e-3
CTHERM5 3 2 8.2e-3
CTHERM6 2 TL 4.7e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 3.3e-2
RTHERM2 6 5 7.9e-2
RTHERM3 5 4 9.5e-2
RTHERM4 4 3 1.4e-1
RTHERM5 3 2 2.9e-1
RTHERM6 2 TL 6.7e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDB3682
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.6e-3
ctherm.ctherm2 6 5 =4.5e-3
ctherm.ctherm3 5 4 =5.0e-3
ctherm.ctherm4 4 3 =8.0e-3
ctherm.ctherm5 3 2 =8.2e-3
ctherm.ctherm6 2 tl =4.7e-2
rtherm.rtherm1 th 6 =3.3e-2
rtherm.rtherm2 6 5 =7.9e-2
rtherm.rtherm3 5 4 =9.5e-2
rtherm.rtherm4 4 3 =1.4e-1
rtherm.rtherm5 3 2 =2.9e-1
rtherm.rtherm6 2 tl =6.7e-1
}
CTHERM3
RTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2002 Fairchild Semiconductor Corporation
CASE
FDB3682 / FDP3682 Rev. B
FDB3682 / FDP3682
SPICE Thermal Model
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