HEF4093B Quad 2-input NAND Schmitt trigger Rev. 8 — 21 November 2011 Product data sheet 1. General description The HEF4093B is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The difference between the positive voltage (VT+) and the negative voltage (VT) is defined as hysteresis voltage (VH). It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits Schmitt trigger input discrimination Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Wave and pulse shapers Astable multivibrators Monostable multivibrators 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C Type number Package Name Description Version HEF4093BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 HEF4093BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 5. Functional diagram 1A 1 3 1B 2A 2 5 4 2B 3A 4A nA nY 8 nB 3Y 001aag105 9 12 11 4B 2Y 6 10 3B 1Y 4Y 13 001aag104 Fig 1. Functional diagram Fig 2. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 1A 1 14 VDD 1B 2 13 4B 1Y 3 12 4A 2Y 4 HEF4093B 11 4Y 2A 5 10 3Y 2B 6 9 3B VSS 7 8 3A 001aag106 Fig 3. Pin configuration HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 6.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 5, 8, 12 input 1B to 4B 2, 6, 9, 13 input 1Y to 4Y 3, 4, 10, 11 output VDD 14 supply voltage VSS 7 ground (0 V) 7. Functional description Table 3. Function table[1] Input Output nA nB nY L L H L H H H L H H H L [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg storage temperature Tamb ambient temperature Ptot total power dissipation P power dissipation Conditions VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V Unit +18 V - 10 mA 0.5 VDD + 0.5 V - 10 mA - 10 mA - 50 mA 65 +150 C 40 +125 C DIP14 [1] - 750 mW SO14 [2] - 500 mW - 100 mW per output [1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. Product data sheet Max Tamb = 40 C to +125 C [2] HEF4093B Min 0.5 All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD Conditions Min Max Unit supply voltage 3 15 V VI input voltage 0 VDD V Tamb ambient temperature 40 +125 C in free air 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VOH VOL IOH IOL HIGH-level output voltage IO < 1 A VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min Max Min Max Min Max Min Max 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 5V LOW-level output voltage IO < 1 A 15 V - 0.05 - 0.05 - 0.05 - 0.05 V HIGH-level output current VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4093B Product data sheet VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A 5V all valid input combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 A - 0.5 - 0.5 - 15.0 - 15.0 A - 1.0 - 1.0 - 30.0 - 30.0 A - - - 7.5 - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; CL = 50 pF; tr = tf 20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specified. Symbol Parameter HIGH to LOW propagation delay tPHL tPLH tTHL [1] nA or nB to nY nA or nB to nY HIGH to LOW output transition time nY to LOW nA or nB to HIGH Extrapolation formula[1] Min Typ Max Unit 5V 63 ns + (0.55 ns/pF)CL - 90 185 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 58 ns + (0.55 ns/pF)CL - 85 170 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns VDD LOW to HIGH propagation delay LOW to HIGH output transition time tTLH Conditions 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula where: 5V PD = 1300 fi + (fo CL) VDD (W) fi = input frequency in MHz; 10 V PD = 6400 fi + (fo CL) VDD2 (W) fo = output frequency in MHz; 15 V PD = 18700 fi + (fo CL) CL = output load capacitance in pF; 2 VDD2 (W) (fo CL) = sum of the outputs; VDD = supply voltage in V. HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 12. Waveforms tr VI tf 90 % input VM 0V 10 % tPHL VOH tPLH 90 % output VM 10 % VOL tTHL tTLH 001aag197 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. tr, tf = input rise and fall times. Fig 4. Propagation delay and output transition time Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD VDD VI VO G DUT CL RT 001aag182 Test data given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 5. Test circuit Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF HEF4093B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 13. Transfer characteristics Table 11. Transfer characteristics VSS = 0 V; Tamb = 25 C; see Figure 6 and Figure 7. Symbol Parameter VT+ VT VH Conditions VDD Min Typ Max 5V 1.9 2.9 3.5 10 V 3.6 5.2 7 V 15 V 4.7 7.3 11 V 5V 1.5 2.2 3.1 V 10 V 3 4.2 6.4 V 15 V 4 6.0 10.3 V 5V 0.4 0.7 - V 10 V 0.6 1.0 - V 15 V 0.7 1.3 - V positive-going threshold voltage negative-going threshold voltage hysteresis voltage Unit V VO VI VT+ VT− VI VH VT− Fig 6. VT+ Transfer characteristic HEF4093B Product data sheet VH VO 001aag107 001aag108 Fig 7. Waveforms showing definition of VT+ and VT (between limits at 30 % and 70 %) and VH All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 001aag109 200 001aag110 1000 IDD (μA) IDD (μA) 100 500 0 0 0 2.5 5 0 5 VI (V) 10 VI (V) a. VDD = 5 V; Tamb = 25 C b. VDD = 10 V; Tamb = 25 C 001aag111 2000 IDD (μA) 1000 0 0 10 20 VI (V) c. Fig 8. VDD = 15 V; Tamb = 25 C Typical drain current as a function of input HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 001aag112 10 VI (V) VT+ VT− 5 0 2.5 5 7.5 10 12.5 15 17.5 VDD (V) Tamb = 25 C. Fig 9. Typical switching levels as a function of supply voltage 14. Application information Some examples of applications for the HEF4093B are: • Wave and pulse shapers • Astable multivibrators • Monostable multivibrators Cp VDD 14 VDD 14 R 1 1 3 3 VDD 2 VDD 2 C 7 7 001aag113 001aag114 Fig 10. Astable multivibrator Fig 11. Schmitt trigger driven via a high-impedance input If a Schmitt trigger is driven via a high-impedance (R > 1 k), then it is necessary to V DD – V SS C > ------------------------ ; otherwise oscillation can occur incorporate a capacitor C with a value of -----CP VH on the edges of a pulse. Cp is the external parasitic capacitance between inputs and output; the value depends on the circuit board layout. Remark: The two inputs may be connected together, but this will result in a larger through-current at the moment of switching. HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 15. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 12. Package outline SOT27-1 (DIP14) HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 10 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT108-1 (SO14) HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4093B v.8 20111121 Product data sheet - HEF4093B v.7 Modifications: • Table 6: IOH minimum values changed to maximum HEF4093B v.7 20100901 Product data sheet - HEF4093B v.6 HEF4093B v.6 20091202 Product data sheet - HEF4093B v.5 HEF4093B v.5 20090728 Product data sheet - HEF4093B v.4 HEF4093B v.4 20080612 Product data sheet - HEF4093B_CNV v.3 HEF4093B_CNV v.3 19950101 Product specification - HEF4093B_CNV v.2 HEF4093B_CNV v.2 19950101 Product specification - - HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 12 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 13 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 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Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4093B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 14 of 15 HEF4093B NXP Semiconductors Quad 2-input NAND Schmitt trigger 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transfer characteristics . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 21 November 2011 Document identifier: HEF4093B