Low Voltage 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translator ADG3300 FUNCTIONAL BLOCK DIAGRAM Bidirectional level translation Operates from 1.15 V to 5.5 V Low quiescent current <1 µA No direction pin VCCA APPLICATIONS Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces VCCY A1 Y1 A2 Y2 A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 Y8 EN GND 05061-001 FEATURES Figure 1. GENERAL DESCRIPTION The ADG3300 is a bidirectional logic level translator that contains eight bidirectional channels. It can be used in multivoltage digital system applications such as data transfer between a low voltage DSP/controller and a higher voltage device. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction of the translation. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA-compatible logic signals applied to the A side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCAcompatible logic levels on the A side. The enable pin provides three-state operation of the Y side pins. When the enable pin (EN) is pulled low, the A1 to A8 pins are internally pulled down by 6 kΩ resistors, while the Y terminals are in the high impedance state. The EN pin is referred to VCCA supply voltage and driven high for normal operation. The ADG3300 is available in a compact 20-lead TSSOP package, and it is guaranteed to operate over the 1.15 V to 5.5 V supply voltage range and extended −40°C to +85°C temperature range. PRODUCT HIGHLIGHTS 1. Bidirectional level translation. 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. 3. No direction pin. 4. 20-lead TSSOP package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADG3300 TABLE OF CONTENTS Specifications..................................................................................... 3 Input Driving Requirements..................................................... 15 Absolute Maximum Ratings............................................................ 6 Output Load Requirements ...................................................... 15 ESD Caution.................................................................................. 6 Enable Operation ....................................................................... 15 Pin Configuration and Function Descriptions............................. 7 Power Supplies............................................................................ 15 Typical Performance Characteristics ............................................. 8 Data Rate ..................................................................................... 16 Test Circuits..................................................................................... 12 Applications..................................................................................... 17 Terminology .................................................................................... 14 Layout Guidelines....................................................................... 17 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 18 Level Translator Architecture.................................................... 15 Ordering Guide .......................................................................... 18 REVISION HISTORY 4/05—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG3300 SPECIFICATIONS1 VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter LOGIC INPUTS/OUTPUTS A Side Input High Voltage3 Input Low Voltage3 Output High Voltage Output Low Voltage Three-State Pull-Down Resistance Y Side Input Low Voltage3 Input High Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Enable (EN) Input High Voltage3 Input Low Voltage3 Leakage Current Capacitance3 Enable Time3 SWITCHING CHARACTERISTICS3 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Conditions Min VIHA VIHA VILA VOHA VOLA RA,HiZ VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 VCCA − 0.4 VY = VCCY, IOH = 20 µA, Figure 27 VY = 0 V, IOL = 20 µA, Figure 27 EN = 0 VCCA − 0.4 VIHY VILY VOHY VOLY CY ILY, HiZ VIHEN VIHEN VILEN ILEN CEN tEN Typ2 Max 0.4 4.2 6 0.4 8.4 VCCY − 0.4 0.4 VA = VCCA, IOH = 20 µA, Figure 28 VA = 0 V, IOL = 20 µA, Figure 28 f = 1 MHz, EN = 0, Figure 31 VY = 0 V/VCCY, EN = 0, Figure 29 VCCY − 0.4 VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 VCCA − 0.4 0.4 6 ±1 0.4 ±1 VEN = 0 V/VCCA, VA = 0 V, Figure 30 RS = RT = 50 Ω, VA = 0 V/VCCA (A Y), Figure 32 Unit V V V V V kΩ V V V V pF µA V V V µA pF µs 3 1 1.8 6 2 2 10 3.5 3.5 2 4 3 ns ns ns Mbps ns ns 4 1 7 3 ns ns 3 7 2 3.5 2 ns Mbps ns ns 8 2 2 11 5 5 2 4 4 RS = RT = 50 Ω, CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y 50 RS = RT = 50 Ω, CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A 50 RS = RT = 50 Ω, CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y 50 Rev. 0 | Page 3 of 20 ns ns ns Mbps ns ns ADG3300 Parameter Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Conditions RS = RT = 50 Ω, CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A Min Typ2 Max Unit 5 2 2 8 3.5 3.5 2 3 3 ns ns ns Mbps ns ns 9 3 2 18 5 5 2 5 10 5 2 2 9 4 4 2 4 4 12 7 3 25 12 5 2 5 15 14 5 2.5 35 16 6.5 3 6.5 23.5 7 2.5 2 10 4 5 1.5 2 4 5 1 3 8 4 5 2 3 3 50 RS = RT = 50 Ω, CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y 40 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A 40 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y 25 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A 25 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, Figure 33 tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y 60 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 15 pF, Figure 34 tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A 60 Rev. 0 | Page 4 of 20 ns ns ns Mbps ns ns ADG3300 Parameter POWER REQUIREMENTS Power Supply Voltages Quiescent Power Supply Current Symbol Conditions Min VCCA VCCY ICCA VCCA ≤ VCCY 1.15 1.65 ICCY Three-State Mode Power Supply Current IHiZA IHiZY VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VCCA = VCCY = 5.5 V, EN = 0 VCCA = VCCY = 5.5 V, EN = 0 1 Temperature range is a follows: B version: −40°C to +85°C. All typical values are at TA = 25°C, unless otherwise noted. 3 Guaranteed by design; not subject to production test. 2 Rev. 0 | Page 5 of 20 Typ2 Max Unit 0.17 5.5 5.5 5 V V µA 0.27 5 µA 0.1 0.1 5 5 µA µA ADG3300 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCCA to GND VCCY to GND Digtal Inputs (A) Digtal Inputs (Y) EN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance (4-Layer Board) 20-Lead TSSOP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Rating −0.3 V to +7 V VCCA to +7 V −0.3 V to (VCCA + 0.3 V) −0.3 V to (VCCY + 0.3 V) −0.3 V to +7 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. −40°C to +85°C −65°C to +150°C 150°C 78°C/W 300°C 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 ADG3300 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A1 1 20 Y1 VCCA 2 19 VCCY A2 3 A3 4 A4 5 A5 6 15 Y5 A6 TOP VIEW (Not to Scale) 18 Y2 17 Y3 16 Y4 7 14 Y6 A7 8 13 Y7 9 12 Y8 A8 EN 10 11 GND 05061-002 ADG3300 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic A1 VCCA A2 A3 A4 A5 A6 A7 A8 EN GND Y8 Y7 Y6 Y5 Y4 Y3 Y2 VCCY Y1 Description Input/Output A1. Referenced to VCCA. Power Supply Voltage Input for the A1 to A8 I/O pins (1.15 V ≤ VCCA < VCCY). Input/Output A2. Referenced to VCCA. Input/Output A3. Referenced to VCCA. Input/Output A4. Referenced to VCCA. Input/Output A5. Referenced to VCCA. Input/Output A6. Referenced to VCCA. Input/Output A7. Referenced to VCCA. Input/Output A8. Referenced to VCCA. Active High Enable Input. Ground. Input/Output Y8. Referenced to VCCY. Input/Output Y7. Referenced to VCCY. Input/Output Y6. Referenced to VCCY. Input/Output Y5. Referenced to VCCY. Input/Output Y4. Referenced to VCCY. Input/Output Y3. Referenced to VCCY. Input/Output Y2. Referenced to VCCY. Power Supply Voltage Input for the Y1 to Y8 I/O pins (1.65 V ≤ VCCY ≤ 5.5 V). Input/Output Y1. Referenced to VCCY. Rev. 0 | Page 7 of 20 ADG3300 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 1.0 TA = 25°C 1 CHANNEL 0.9 CL = 50pF TA = 25°C 1 CHANNEL CL = 15pF 2.5 0.8 VCCA = 3.3V, VCCY = 5V 2.0 ICCY (mA) 0.6 0.5 VCCA = 3.3V, VCCY = 5V 1.5 0.4 1.0 VCCA = 1.8V, VCCY = 3.3V 0.3 VCCA = 1.8V, VCCY = 3.3V 0.2 0.5 0.1 VCCA = 1.2V, VCCY = 1.8V VCCA = 1.2V, VCCY = 1.8V 0 5 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 50 0 05061-003 0 0 5 10 15 20 25 30 35 40 45 50 DATA RATE (Mbps) 05061-006 ICCA (mA) 0.7 Figure 6. ICCY vs. Data Rate (Y A Level Translation) Figure 3. ICCA vs. Data Rate (A Y Level Translation) 1.6 10 TA = 25°C 1 CHANNEL 9 CL = 50pF TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY = 1.8V 1.4 8 20Mbps 1.2 7 ICCY (mA) ICCY (mA) VCCA = 3.3V, VCCY = 5V 6 5 4 1.0 0.8 10Mbps 0.6 VCCA = 1.8V, VCCY = 3.3V 3 0.4 5Mbps 2 VCCA = 1.2V, VCCY = 1.8V 1 0 5 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 50 53 63 73 TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY =1.8V 0.9 0.8 0.7 ICCA (mA) 2.0 1.5 1.0 0.6 20Mbps 0.5 0.4 0.3 VCCA = 1.8V, VCCY = 3.3V 10Mbps 5Mbps 0.2 VCCA = 1.2V, VCCY = 1.8V 5 10 15 20 25 30 35 40 45 DATA RATE (Mbps) 50 1Mbps 0 05061-005 0 0.1 13 23 33 43 CAPACITIVE LOAD (pF) 53 Figure 8. ICCA vs. Capacitive Load at Pin A for Y A (1.8 V 1.2 V) Level Translation Figure 5. ICCA vs. Data Rate (Y A Level Translation) Rev. 0 | Page 8 of 20 05061-008 0.5 0 43 1.0 VCCA = 3.3V, VCCY = 5V ICCA (mA) 33 Figure 7. ICCY vs. Capacitive Load at Pin Y for A Y (1.2 V 1.8 V) Level Translation TA = 25°C 1 CHANNEL CL = 15pF 2.5 23 CAPACITIVE LOAD (pF) Figure 4. ICCY vs. Data Rate (A Y Level Translation) 3.0 13 05061-007 1Mbps 0 05061-004 0 0.2 ADG3300 9 7 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 8 7 TA = 25°C 1 CHANNEL 6 VCCA = 3.3V VCCY = 5V 50Mbps 50Mbps 5 ICCA (mA) ICCY (mA) 6 5 30Mbps 4 4 30Mbps 3 20Mbps 3 20Mbps 2 2 10Mbps 10Mbps 1 1 33 43 53 CAPACITIVE LOAD (pF) 63 0 13 05061-009 23 73 53 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 3.5 VCCA = 1.2V, VCCY = 1.8V 7 50Mbps 3.0 RISE TIME (ns) ICCA (mA) 43 Figure 12. ICCA vs. Capacitive Load at Pin A for Y A (5 V 3.3 V) Level Translation 5.0 4.0 33 CAPACITIVE LOAD (pF) Figure 9. ICCY vs. Capacitive Load at Pin Y for A Y (1.8 V 3.3 V) Level Translation 4.5 23 05061-012 5Mbps 5Mbps 0 13 2.5 2.0 30Mbps 1.5 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 20Mbps 1.0 2 VCCA = 3.3V, VCCY = 5V 10Mbps 0.5 5Mbps 23 33 43 CAPACITIVE LOAD (pF) 53 0 13 05061-010 0 13 Figure 10. ICCA vs. Capacitive Load at Pin A for Y A (3.3 V 1.8 V) Level Translation 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 05061-013 1 Figure 13. Rise Time vs. Capacitive Load at Pin Y (A Y Level Translation) 12 4.0 TA = 25°C 1 CHANNEL VCCA = 3.3V 10 V CCY = 5V TA = 25°C 1 CHANNEL 3.5 DATA RATE = 50kbps 50Mbps VCCA = 1.2V, VCCY = 1.8V 3.0 FALL TIME (ns) 30Mbps 6 20Mbps 4 2.5 VCCA = 1.8V, VCCY = 3.3V 2.0 1.5 VCCA = 3.3V, VCCY = 5V 1.0 10Mbps 2 0.5 0 13 23 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 11. ICCY vs. Capacitive Load at Pin Y for A Y (3.3 V 5 V) Level Translation 0 13 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 05061-014 5Mbps 05061-011 ICCY (mA) 8 Figure 14. Fall Time vs. Capacitive Load at Pin Y (A Y Level Translation) Rev. 0 | Page 9 of 20 ADG3300 12 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 VCCA = 1.2V, VCCY = 1.8V 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 2 8 6 VCCA = 1.8V, VCCY = 3.3V 4 2 1 VCCA = 3.3V, VCCY = 5V 23 28 33 38 43 48 53 CAPACITIVE LOAD (pF) 0 13 05061-015 18 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 18. Propagation Delay (tPHL) vs. Capacitive Load at Pin Y (A Y Level Translation) Figure 15. Rise Time vs. Capacitive Load at Pin A (Y A Level Translation) 9 TA = 25°C 1 CHANNEL DATA RATE = 50kbps 8 PROPAGATION DELAY (ns) 3.0 2.5 VCCA = 1.2V, VCCY = 1.8V 2.0 VCCA = 1.8V, VCCY = 3.3V 1.5 VCCA = 3.3V, VCCY = 5V 1.0 0.5 TA = 25°C 1 CHANNEL DATA RATE = 50kbps 7 VCCA = 1.2V, VCCY = 1.8V 6 5 4 3 VCCA = 1.8V, VCCY = 3.3V 2 VCCA = 3.3V, VCCY = 5V 1 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53 0 13 05061-016 0 23 28 33 38 43 48 53 CAPACITIVE LOAD (pF) Figure 19. Propagation Delay (tPLH) vs. Capacitive Load at Pin A (Y A Level Translation) Figure 16. Fall Time vs. Capacitive Load at Pin A (Y A Level Translation) 9 14 TA = 25°C 1 CHANNEL 8 DATA RATE = 50kbps TA = 25°C 1 CHANNEL 12 DATA RATE = 50kbps PROPAGATION DELAY (ns) VCCA = 1.2V, VCCY = 1.8V 10 8 6 VCCA = 1.8V, VCCY = 3.3V 4 VCCA = 3.3V, VCCY = 5V 2 VCCA = 1.2V, VCCY = 1.8V 7 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 VCCA = 3.3V, VCCY = 5V 2 1 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 0 05061-017 0 13 18 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 Figure 20. Propagation Delay(tPHL) vs. Capacitive Load at Pin A (Y A Level Translation) Figure 17. Propagation Delay (tPLH) vs. Capacitive Load at Pin Y (A Y Level Translation) Rev. 0 | Page 10 of 20 53 05061-020 3.5 05061-019 4.0 FALL TIME (ns) 23 05061-018 VCCA = 3.3V, VCCY = 5V 0 13 PROPAGATION DELAY (ns) VCCA = 1.2V, VCCY = 1.8V 10 PROPAGATION DELAY (ns) RISE TIME (ns) 7 DATA RATE = 50kbps TA = 25°C 1 CHANNEL ADG3300 Figure 21. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps) Figure 24. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps) TA = 25°C DATA RATE = 25Mbps CL = 50pF 1 CHANNEL TA = 25°C DATA RATE = 50Mbps CL = 50pF 1 CHANNEL 05061-022 400mV/DIV 5ns/DIV 1V/DIV Figure 22. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps) 500mV/DIV 3ns/DIV 3ns/DIV Figure 25. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps) TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL CL = 50pF 1 CHANNEL 05061-023 TA = 25°C DATA RATE = 50Mbps 3ns/DIV 05061-024 400mV/DIV 05061-025 5ns/DIV TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL 800mV/DIV Figure 23. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps) 3ns/DIV 05061-026 200mV/DIV CL = 50pF 1 CHANNEL 05061-021 TA = 25°C DATA RATE = 25Mbps Figure 26. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps) Rev. 0 | Page 11 of 20 ADG3300 TEST CIRCUITS EN VCCA ADG3300 VCCY 0.1µF 0.1µF ADG3300 VCCA A VCCY 0.1µF Y 0.1µF K2 K1 A GND Figure 27. VOH/VOL Voltages at Pin A EN VCCA ADG3300 K2 Figure 30. EN Pin Leakage Current EN VCCA VCCY 0.1µF EN K 05061-031 05061-027 IOL ADG3300 VCCY 0.1µF Y A A Y K1 GND GND IOH 05061-028 IOL Figure 28. VOH/VOL Voltages at Pin Y EN VCCA ADG3300 VCCY 0.1µF 0.1µF Y K A GND 05061-030 A Figure 29. Three-State Leakage Current at Pin Y Rev. 0 | Page 12 of 20 Figure 31.Capacitance at Pin Y CAPACITANCE METER 05061-033 IOH Y A GND ADG3300 VCCA 0.1µF VCCY ADG3300 + 10µF + 10µF 0.1µF 1MΩ A VA K1 Y VY K2 50pF 1MΩ SIGNAL SOURCE EN Z0 = 50Ω RS GND VEN 50Ω RT 50Ω VCCA tEN1 VEN 0V VCCA VA 0V VCCY 90% VY 0V VCCA tEN2 VEN 0V VA VCCA 0V VCCY VY 10% 05061-034 0V NOTES 1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2. Figure 32. Enable Time EN VCCY ADG3300 VCCA SIGNAL SOURCE 0.1µF Z0 = 50Ω V A RS 50Ω EN + 10µF 0.1µF + 10µF A Y VY VA 50pF VCCY + 10µF 0.1µF + 10µF 0.1µF RT 50Ω ADG3300 VCCA SIGNAL SOURCE A Y Z0 = 50Ω RS 50Ω RT 50Ω 15pF GND VY GND VA VY 50% 50% VA tP,Y-A tP,Y-A 90% 50% 10% tR,A-Y 05061-035 tF,A-Y tF,Y-A tR,Y-A Figure 34. Switching Characteristics (Y A Level Translation) Figure 33. Switching Characteristics (A Y Level Translation) Rev. 0 | Page 13 of 20 05061-036 tP,A-Y tP,A-Y VY 90% 50% 10% ADG3300 TERMINOLOGY Table 4. Symbol VIHA VILA VOHA VOLA RA,HiZ VIHY VILY VOHY VOLY CY ILY, HiZ VIHEN VILEN CEN ILEN tEN tP, A-Y tR, A-Y tF, A-Y DMAX, A-Y tSKEW, A-Y tPPSKEW, A-Y tP, Y-A tR, Y-A tF, Y-A DMAX, Y-A tSKEW, Y-A tPPSKEW, Y-A VCCA VCCY ICCA ICCY IHiZA IHiZY Description Logic input high voltage at Pins A1 to A8. Logic input low voltage at Pins A1 to A8. Logic output high voltage at Pins A1 to A8. Logic output low voltage at Pins A1 to A8. Pull-down resistance measured at Pins A1 to A8 when EN = 0. Logic input high voltage at Pins Y1 to Y8. Logic input low voltage at Pins Y1 to Y8. Logic output high voltage at Pins Y1 to Y8. Logic output low voltage at Pins Y1 to Y8. Capacitance measured at Pins Y1 to Y8 (EN = 0). Leakage current at Pins Y1 to Y8 when EN = 0 (high impedance state at Pins Y1 to Y8). Logic input high voltage at the EN pin. Logic input low voltage at the EN pin. Capacitance measured at EN pin. Enable (EN) pin leakage curent. Three-state enable time for Pins Y1 to Y8. Propagation delay when translating logic levels in the A Y direction. Rise time when translating logic levels in the A Y direction. Fall time when translating logic levels in the A Y direction. Guaranteed data rate when translating logic levels in the A Y direction under the driving and loading conditions specified in Table 1. Difference between propagation delays on any two channels when translating logic levels in the A Y direction. Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions) when translating logic levels in the A Y direction. Propagation delay when translating logic levels in the Y A direction. Rise time when translating logic levels in the Y A direction. Fall time when translating logic levels in the Y A direction. Guaranteed data rate when translating logic levels in the Y A direction under the driving and loading conditions specified in Table 1. Difference between propagation delays on any two channels when translating logic levels in the Y A direction. Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/loading conditions) when translating in the Y A direction. VCCA supply voltage. VCCY supply voltage. VCCA supply current. VCCY supply current. VCCA supply current during three-state mode (EN = 0). VCCY supply current during three-state mode (EN = 0). Rev. 0 | Page 14 of 20 ADG3300 THEORY OF OPERATION The ADG3300 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each side of the device. When driving the A pins, the device translates the VCCAcompatible logic levels to VCCY-compatible logic levels available at the Y pins. Similarly, since the device is capable of bidirectional translation, when driving the Y pins, the VCCY-compatible logic levels are translated to VCCA-compatible logic levels available at the A pins. When EN = 0, the A1 to A8 are internally pulled down with 6 kΩ resistors while Y1 to Y8 pins are three-stated. When EN is driven high, the ADG3300 goes into normal operation mode and performs level translation. INPUT DRIVING REQUIREMENTS To ensure correct operation of the ADG3300, the circuit that drives the input of an ADG3300 channels should have an output impedance of less than or equal to 150 Ω and a minimum current driving capability of 36 mA. OUTPUT LOAD REQUIREMENTS The ADG3300 level translator is designed to drive CMOScompatible loads. If current driving capability is required, it is recommended to use buffers between the ADG3300 outputs and the load. ENABLE OPERATION The ADG3300 provides three-state operation at the Y I/O pins by using the enable (EN) pin as shown in Table 5. LEVEL TRANSLATOR ARCHITECTURE The ADG3300 consists of eight bidirectional channels. Each channel can translate logic levels in either the A Y or the Y A direction. It uses a one-shot accelerator architecture, which ensures excellent switching characteristics. Figure 35 shows a simplified block diagram of a bidirectional channel. Table 5. Truth Table EN 0 1 1 VCCA VCCY T1 2 T2 P A U2 ONE-SHOT GENERATOR Y N A I/O Pins 6 kΩ pull-down to GND Normal operation2 High impedance state. In normal operation, the ADG3300 performs level translation. When EN = 0, the ADG3300 enters into three-state mode. In this mode the current consumption from both the VCCA and VCCY supplies is reduced, allowing the user to save power, which is critical, especially for battery-operated systems. The EN input pin can be driven with either VCCA- or VCCY-compatible logic levels. 6kΩ U1 Y I/O Pins Hi-Z1 Normal operation2 POWER SUPPLIES T4 U4 U3 T3 05061-037 6kΩ Figure 35. Simplified Block Diagram of an ADG3300 Channel The logic level translation in the A Y direction is performed using a level translator (U1) and an inverter (U2), and the translation in the Y A direction is performed using the inverters U3 and U4. The one-shot generator detects a rising or falling edge present on either the A side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T1–T2) for a rising edge, or the NMOS transistors (T3–T4) for a falling edge. This charges/discharges the capacitive load faster, which results in fast rise and fall times. For proper operation of the ADG3300, the voltage applied to the VCCA must always be less than or equal to the voltage applied to VCCY. To meet this condition, the recommended power-up sequence is VCCY first and then VCCA. The ADG3300 operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where VCCA might be greater than VCCY during power-up due to a significant increase in the current taken from the VCCA supply. For optimum performance, the VCCA and VCCY pins should be decoupled to GND as close as possible to the device. The inputs of the unused channels (A or Y) should be tied to their corresponding VCC rail (VCCA or VCCY) or to GND. Rev. 0 | Page 15 of 20 ADG3300 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the VCCA and VCCY supply voltage combination and the load capacitance. It is given by the maximum frequency of a square wave that can be applied to the device, which meets the VOH and VOL levels at the output and does not exceed the maximum junction temperature (see Table 2). Table 6 shows the guaranteed data rates at which the ADG3300 can operate in both directions (A Y and Y A level translation) for various VCCA and VCCY supply combinations. Table 6. Guaranteed Data Rate (Mbps)1 VCCY VCCA 1.2 V (1.15 V to 1.3 V) 1.8 V (1.65 V to 1.95 V) 2.5 V (2.3 V to 2.7 V) 3.3 V (3.0 V to 3.6 V) 5 V (4.5 V to 5.5 V) 1 1.8 V (1.65 V to 1.95 V) 25 - 2.5 V (2.3 V to 2.7 V) 30 45 - 3.3 V (3.0 V to 3.6 V) 40 50 60 - The load capacitance used is 50 pF when translating in the A Y direction and 15 pF when translating in the Y A direction. Rev. 0 | Page 16 of 20 5V (4.5 V to 5.5 V) 40 50 50 50 - ADG3300 APPLICATIONS other devices without causing contention issues. Figure 37 shows an application where a 3.3 V microprocessor is connected to 1.8 V peripheral devices using the three-state feature. 100nF I/OH1 3.3V 1.8V I/OL1 VCCY I/OH2 Y2 I/OH3 Y3 MICROPROCESSOR/ I/OH4 MICROCONTROLLER/ I/OH5 DSP I/OH6 Y4 I/OH7 I/OH8 GND CS Y1 VCCA I/OH1 A2 Y2 I/OH2 I/OL3 A3 Y3 I/OH3 MICROPROCESSOR/ I/OL4 MICROCONTROLLER/ DSP I/OL5 A4 I/OH4 A5 Y5 I/OH5 I/OL6 A6 Y6 I/OH6 I/OL7 A7 Y7 I/OH7 I/OL8 A8 Y8 I/OH8 EN GND GND 1.8V I/OL 2 A3 I/OL 3 A4 I/OL 4 A5 I/OL 5 Y6 A6 I/OL 6 Y7 A7 I/OL 7 Y8 A8 I/OL 8 GND EN GND PERIPHERAL DEVICE 1 100nF A1 I/OL 1 A2 I/OL 2 A3 I/OL 3 A4 I/OL 4 Y5 A5 I/OL 5 Y6 A6 I/OL 6 Y7 A7 I/OL 7 Y8 A8 I/OL 8 GND EN GND Y2 Y3 Y4 1.8V VCCA ADG3300 PERIPHERAL DEVICE 2 Figure 37. 1.8 V to 3.3 V Level Translation Circuit Using the Three-State Feature LAYOUT GUIDELINES PERIPHERAL DEVICE 05061-038 GND Y4 ADG3300 A2 Y5 Y1 VCCY I/OL2 ADG3300 VCCY 3.3V I/OL1 VCCA 100nF 100nF A1 A1 Y1 Figure 36 shows an application where a 1.8 V microprocessor can read or write data to or from a 3.3 V peripheral device using an 8-bit bus. 100nF 100nF 05061-039 The ADG3300 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the A pins, and the higher voltage logic signals are connected to the Y pins. The ADG3300 can provide level translation in both directions from A Y and Y A on all eight channels, eliminating the need for a level translator IC for each direction. The internal architecture allows the ADG3300 to perform bidirectional level translation without an additional signal to set the direction of the translation. It also allows simultaneous data flow in both directions on the same part, for example, four channels translate in the A Y direction while the other four translate in the Y A direction. This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation. Figure 36. 1.8 V to 3.3 V 8-Bit Level Translation Circuit When the application requires level translation between a microprocessor and multiple peripheral devices, the ADG3300 Y I/O pins (Y1 to Y8) can be three-stated by setting EN = 0. This feature allows the ADG3300 to share the data buses with As with any high speed digital IC, the printed circuit board layout is important in the overall circuit performance. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCCA and VCCY) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCCA and VCCY pins. The parasitic inductance of the high speed signal track might cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. A solid copper plane for the return path (GND) is also recommended. Rev. 0 | Page 17 of 20 ADG3300 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AC Figure 38 . 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters ORDERING GUIDE Model ADG3300BRUZ1 ADG3300BRUZ-REEL1 ADG3300BRUZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description TSSOP TSSOP TSSOP Z = Pb-free part. Rev. 0 | Page 18 of 20 Package Option RU-20 RU-20 RU-20 ADG3300 NOTES Rev. 0 | Page 19 of 20 ADG3300 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05061–0–4/05(0) Rev. 0 | Page 20 of 20