LTC6602 Dual Matched, High Frequency Bandpass/Lowpass Filters DESCRIPTION FEATURES n n n n n n n n n n n n n Matched Dual Filter/Driver, Ideal for RFID Readers Guaranteed Phase Matching to Within 2 Degrees Guaranteed Gain Matching to Within 0.2dB Configurable as Lowpass or Bandpass Programmable 5th Order Lowpass: 42kHz to 900kHz Programmable 4th Order Highpass: 4.2kHz to 90kHz Programmable Gain: 1×, 4×, 16×, 32× Simple Pin Programming or SPI Interface Low Noise: –145dBm/Hz (Input Referred) Low Distortion: –75dBc at 200kHz Differential, Rail-to-Rail Inputs and Outputs Input Range Extends from 0V to 5V Low Voltage Operation: 2.7V to 3.6V Shutdown Mode 4mm × 4mm QFN Package APPLICATIONS n n n n n Multiprotocol RFID Readers: EPC-GEN2, ISD and IPX IDEN, PHS, GSM Basestations Repeaters, Radio Links, and Modems Wireless Telemetry JTRS The LTC®6602 is a dual, matched, programmable bandpass or lowpass filter and differential driver. The selectivity of the LTC6602, combined with its phase matching and dynamic range, make it ideal for filtering in RFID systems. With two degree phase matching between channels, the LTC6602 can be used in applications requiring highly matched filters, such as transceiver I and Q channels. Gain programmability, and the fully differential inputs and outputs, simplify implementation in most systems. Both channels of the LTC6602 consist of a programmable lowpass and highpass filter. For bandpass functionality, the lowpass filters are programmed for the upper cutoff frequency. For lowpass functionality, the highpass filters can be bypassed. The filter cutoff frequencies can be set with a guaranteed accuracy of 3% with the use of a single resistor. Alternatively, the filter cutoff frequencies can be controlled with an external clock. The LTC6602 operates on a single 2.7V to 3.6V supply and features a low power shutdown mode. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.. TYPICAL APPLICATION UHF RFID Reader Dual Baseband Filter and Dual ADC Gain vs Frequency 3V 20 0.1μF 100Ω I INPUT Q INPUT 38.3k 0.1μF MUTE INPUT FROM TRANSMITTER V+A V+D +INA –OUTA –INA +OUTA +INB –OUTB –INB +OUTB RBIAS LTC6602 100pF SER MUTE CLKCNTL AIN– I OUTPUT VCM 2.2μF Q OUTPUT LTC2297 BIN+ 100Ω CLKIO VOCM 14-BIT ADC 100pF 100Ω 100pF 100pF BIN– 14-BIT ADC GAIN0(D0) HPF0(SDO) GAIN1 LPF0(SCLK) GND LPF1(CS) –20 –30 –40 –60 1k 10k 100k 1M FREQUENCY (Hz) 10M 6602 TA01b HPF1(SDI) GND –10 –50 45kHz-300kHz BPF 100pF 100Ω 15kHz-150kHz BPF 90kHz-900kHz BPF 0 100pF V+IN EXTERNAL CLOCK = 90MHz 10 AIN+ GAIN (dB) 0.1μF CLK IN 6602 TA01 CS SCLK SDI SPI CONTROL INPUT ÷4 CLOCK INPUT 24MHz TO 128MHz (COVERS THE TAG BACKSCATTER LINK FREQUENCY RANGE OF 40kHz to 640kHz OF THE CLASS 1 GENERATION 2 UHF RFID COMMUNICATION PROTOCOL) 6602fa 1 LTC6602 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) +OUTA MUTE GAIN0(D0) GAIN1 +INA –INA TOP VIEW V+IN to GND ................................................................6V V+A, V+D to GND .........................................................4V Filter Inputs to GND ....................... –0.3V to V+IN + 0.3V All Other Pins to GND.............. –0.3V to V+A, V+D + 0.3V Maximum Input Current .......................................±10mA Output Short Circuit Duration........................... Indefinite Operating Temperature Range (Note 2) LTC6602CUF ........................................ –40°C to 85°C LTC6602IUF ......................................... –40°C to 85°C Specified Temperature Range (Note 3) LTC6602CUF ............................................ 0°C to 70°C LTC6602IUF ......................................... –40°C to 85°C Storage Temperature Range................... –65°C to 150°C 24 23 22 21 20 19 V+IN 1 18 –OUTA V+A 2 17 SER VOCM 3 16 V+D 25 RBIAS 4 15 CLKIO –OUTB 9 10 11 12 HPFO(SDO) 8 HPF1(SDI) 7 LPFO(SCLK) 13 +OUTB –INB 14 GND LPF1(CS) 6 +INB CLKCNTL 5 UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO THE PCB. ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6602CUF#PBF LTC6602CUF#TRPBF 6602 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C LTC6602IUF#PBF LTC6602IUF#TRPBF 6602 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which app ly over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. PARAMETER CONDITIONS Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 45kHz, Gain = 0dB Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P fIN = 22.5kHz fIN = 45kHz fIN = 150kHz fIN = 300kHz fIN = 900kHz Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz, VIN = 3.6VP-P fIN = 45kHz fIN = 150kHz fIN = 300kHz l l l l l l l l MIN TYP MAX UNITS –1.8 0.1 –2.7 –32 –1.2 0.5 –2 –44 –30 –0.8 0.8 –1.2 –43 dB dB dB dB dB ±0.2 ±0.2 ±0.2 dB dB dB 6602fa 2 LTC6602 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. PARAMETER CONDITIONS Filter Phase Either Channel External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz fIN = 50kHz fIN = 250kHz l l External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 45kHz, Lowpass Filter Cutoff = 300kHz fIN = 50kHz fIN = 250kHz l l Matching of Filter Phase Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 15kHz, Gain = 0dB Lowpass Filter Cutoff = 150kHz, VIN = 3.6VP-P fIN = 7.5kHz fIN = 15kHz fIN = 50kHz fIN = 150kHz fIN = 450kHz Matching of Filter Gain Filter Phase Either Channel Matching of Filter Phase External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 15kHz fIN = 50kHz fIN = 150kHz l l l External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 16.5kHz fIN = 125kHz l l External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 15kHz, Lowpass Filter Cutoff = 150kHz fIN = 16.5kHz fIN = 125kHz l l Filter Gain Either Channel External Clock = 90MHz, Highpass Filter Cutoff = 90kHz, Gain = 0dB Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P fIN = 45kHz fIN = 90kHz fIN = 300kHz fIN = 900kHz fIN = 2700kHz Matching of Filter Gain External Clock = 90MHz, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz, VIN = 3.6VP-P fIN = 90kHz fIN = 300kHz fIN = 900kHz Filter Phase Either Chanel External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz fIN = 100kHz fIN = 750kHz Matching of Filter Phase Filter Cutoff Accuracy when Self Clocked l l l l l l l l l l MIN TYP MAX UNITS 125 –134 130 –130 134 –126 deg deg ±2 ±1.5 deg deg –30 –0.8 0.9 –1.3 –43 dB dB dB dB dB ±0.2 ±0.2 ±0.2 dB dB dB 146 –134 deg deg ±2 ±1 deg deg –27 –0.7 1.2 –0.5 –44 dB dB dB dB dB ±0.3 ±0.6 ±0.4 dB dB dB 145 –127 deg deg –1.6 0.4 –2.3 137 –142 –1.8 –0.1 –2.1 –32 –1.2 0.7 –1.9 –44 142 –138 –29 –1.2 0.6 –1.1 –45 l l l l l 136 –136 141 –131 External Clock = 90MHz, VIN = 3.6VP-P, Highpass Filter Cutoff = 90kHz, Lowpass Filter Cutoff = 900kHz fIN = 100kHz fIN = 750kHz l l ±2 ±1.5 deg deg CLKCNTL = 3V (Note 4) RBIAS = 200k, Output Clock = 24.705MHz RBIAS = 54.9k, Output Clock = 90MHz l l ±3 ±3 % % 6602fa 3 LTC6602 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. PARAMETER CONDITIONS PGA Gain Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC, 0.6V to 2.4V Each Output Gain Setting = 0dB Gain Setting = 12dB Gain Setting = 24dB Gain Setting = 30dB l l l l Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC, 0.6V to 2.4V Each Output Gain Setting = 0dB Gain Setting = 12dB Gain Setting = 24dB Gain Setting = 30dB l l l l PGA Gain Matching Noise At 200kHz MIN TYP MAX UNITS 0.4 11.6 23.5 29.1 0.8 12 23.8 29.6 1.2 12.4 24.1 30.1 dB dB dB dB ±0.2 ±0.2 ±0.3 ±0.3 dB dB dB dB Voltage Noise Referred to the Input Gain = 0dB Gain = 12dB Gain = 24dB Gain = 30dB –119 –131 –142 –146 dBm/Hz dBm/Hz dBm/Hz dBm/Hz Noise Bandwidth = 1.57MHz (Note 5), Referred to the Input Gain = 0dB Gain = 12dB Gain = 24dB Gain = 30dB –62 –74 –85 –89 dBm dBm dBm dBm THD VIN = 1.5VP-P, fIN = 100kHz –75 dB Input Impedance Differential Common Mode 16 20 kΩ kΩ VOS Differential Differential Offset Voltage at Either Output Differential Offset Voltage at Either Output HPF Bypassed, Lowest LPF Cutoff Differential Offset Voltage at Either Output HPF Bypassed, Highest LPF Cutoff l l l VOSCM Common Mode Offset Voltage VOCM = 1.5V, Supplies = 3V VOSCM = VOUT-CM – VOCM l l Integrated Noise CMR Differential ΔVINCM /ΔVOUTDIFF Common Mode Input from 0 to 3V V+IN = 3V Common Mode Input from 0 to 5V V+IN = 5V l ±7 ±10 ±10 ±15 ±30 ±30 mV mV mV –40 ±20 70 mV 75 95 dB 75 95 VOCM Pin Voltage V+A = V+D = 3V, Pin 3 Open l 1.2 1.4 1.6 V VOCM Pin Input Impedance V+A = V+D = 3V, Pin 3 Open l 300 400 700 Ω Output Swing Lowpass Cutoff = 150kHz, Highpass Filter Bypassed, Measured at DC Source 1mA, VOUT High, Relative to V+A Sink 1mA, VOUT Low, Relative to GND l l 200 200 500 500 mV mV Lowpass Cutoff = 150kHz, Highpass Filter Bypassed Sourcing Sinking l l 15 25 25 50 mA mA Internal Clock (RBIAS = 54.9k); Sum of the Currents into V+D, V+A, and V+IN All Supplies Set to 3V HPF = 15k, LPF = 150k HPF = 45k, LPF = 300k HPF = 90k, LPF = 900k l l l 65 100 105 80 125 130 mA mA mA Short-Circuit Current Supply Current 4 10 dB 6602fa 4 LTC6602 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 300kHz, highpass cutoff = 45kHz, internal clocking with RBIAS = 54.9k unless otherwise noted. PARAMETER CONDITIONS Supply Current, Shutdown Mode Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V Shutdown Via Serial Interface, Control Bit D1 = 1. MIN TYP MAX UNITS l Supply Voltage V+D, V+A Relative to GND V+IN Relative to GND l l 170 235 μA 2.7 2.7 3.6 5.5 V V PSR V+D = V+A = V+IN, All from 2.7V to 3.6V V+D = V+A = 3.0V, V+IN from 4.5V to 5.5V l l 50 80 RBIAS Resistor Range Clock Frequency Error ≤ ±3%, CLKCNTL = 3V l 54.9 RBIAS Pin Voltage 54.9k < RBIAS < 200k Clock Frequency Drift Over Temperature RBIAS = 54.9k, CLKCNTL Pin Open Clock Frequency Change Over Supply V+A, V+D from 2.7V to 3.6V, RBIAS = 54.9k, CLKCNTL Pin Open l –0.6 0.1 0.6 %/V Output Clock Duty Cycle RBIAS = 54.9k l 25 50 75 % CLKIO Pin High Level Input Voltage CLKCNTL = 0V (Note 6) CLKIO Pin Low Level Input Voltage CLKCNTL = 0V (Note 6) CLKIO Pin Input Current CLKCNTL = 0V CLKIO = 0V (Note 7) CLKIO = V+D 60 95 dB dB 200 1.17 V 40 ppm/ºC V+D – 0.3 l l kΩ V 0.3 V 10 μA μA –1 CLKIO Pin High Level Output Voltage V+A = V+D = 3V, CLKCNTL = 3V IOH = –1mA IOH = –4mA 2.95 2.9 V V CLKIO Pin Low Level Output Voltage V+A = V+D = 3V, CLKCNTL = 3V IOL = 1mA IOL = 4mA 0.05 0.1 V V CLKIO Rise Time V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF 0.3 ns CLKIO Fall Time V+A = V+D = CLKCNTL = 3V, 20%/80%, CLOAD = 5pF 0.3 ns SER, MUTE High Level Input Voltage Pins 17, 20 l SER, MUTE Low Level Input Voltage Pins 17, 20 l SER, MUTE Input Current Pin 17 or Pin 20 = 0V (Note 7) Pin 17 or Pin 20 = V+D l l –10 CLKCNTL High Level Input Voltage Pin 5 l V+D – 0.5 CLKCNTL Low Level Input Voltage Pin 5 CLKCNTL Input Current CLKCNTL = 0V (Note 7) CLKCNTL = V+D l l V+D – 0.3 –25 V 0.3 V 2 μA μA V –15 15 0.5 V 25 μA μA 6602fa 5 LTC6602 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Specifications apply to pins 6, 9-11, 21 and 22. Pin Programmable Control Mode Specifications SYMBOL PARAMETER CONDITIONS MIN VIH Digital Input High Voltage Pins 6, 9-11, 21, 22 l VIL Digital Input Low Voltage Pins 6, 9-11, 21, 22 l IIN Digital Input Current Pins 6, 9-11, 21, 22 (Note 7) l TYP MAX UNITS V+D = 2.7V to 3.6V 2 V –1 0.8 V 1 μA Serial Port DC and Timing Specifications SYMBOL PARAMETER CONDITIONS MIN VIH Digital Input High Voltage Pins 6, 9, 10 l VIL Digital Input Low Voltage Pins 6, 9, 10 l IIN Digital Input Current Pins 6, 9, 10 (Note 7) l –1 VOH Digital Output High Voltage Pins 11, 21 Sourcing 500μA l VSUPPLY -0.3 TYP MAX UNITS V+D = 2.7V to 3.6V 2 V 0.8 V 1 μA V VOL Digital Output Low Voltage Pins 11, 21 Sinking 500μA l t1 SDI Valid to SCLK Setup (Note 6) l 60 ns t2 SDI Valid to SCLK Hold (Note 6) l 0 ns t3 SCLK Low l 100 ns t4 SCLK High l 100 ns t5 CS Pulse Width l 60 ns t6 LSB SCLK to CS (Note 6) l 60 ns t7 CS Low to SCLK (Note 6) l 30 ns t8 SDO Output Delay CL = 15pF l t9 SCLK Low to CS Low (Note 6) l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: LTC6602C and LTC6602I are guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: LTC6602C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6602C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LTC6602I is guaranteed to meet the specified performance limits from –40°C to 85°C. 0.3 125 0 V ns ns Note 4: This test measures the internal oscillator accuracy (deviation from the fCLK equation). Variations in the internal oscillator frequency cause variations in the filter cutoff frequency. See the “Applications Information” section. Note 5: 1.57MHz is the equivalent noise bandwidth of a 1MHz 1st order RC lowpass filter. Note 6: Guaranteed by design, not subject to test. Note 7: To conform to the Logic IC standard, current out of a pin is arbitrarily given a negative value. 6602fa 6 LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS Distortion vs Input Frequency –10 –20 –30 TA = 25°C, VS = 3V, DIFFERENTIAL INPUT, VIN = 1.5VP-P, 12.4-82.4kHz BPF, RBIAS = 200k 45kHz-300kHz BPF, RBIAS = 54.9k, GAIN = 0dB –75 HD3 12kHz-82kHz BPF HD2 45kHz-300kHz BPF –80 HD2 12kHz-82kHz BPF –50 45kHz-300kHz BPF 10k 100k 1M FREQUENCY (Hz) –90 10M 0 50 100 150 200 250 INPUT FREQUENCY (kHz) –70 DISTORTION (dBc) DISTORTION (dBc) HD3 –80 6 12 18 GAIN (dB) 24 HD2 –90 30 15 30 45 60 75 HIGHPASS CUTOFF FREQUENCY (kHz) 0.05 –40°C 25°C HD3 HD2 –90 90 85°C –0.05 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 6602 G07 TA = 25°C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P RBIAS = 54.9k fHP = 45kHz GAIN = 0dB 0 150 300 450 600 750 LOWPASS CUTOFF FREQUENCY (kHz) Common Mode Rejection 120 VS = 3V 0.3 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 0.2 110 0.1 5 TYPICAL UNITS –0.1 –0.2 –0.3 –0.4 –40 –20 0 20 40 60 TEMPERATURE (°C) 900 6602 G06 0.4 0.0 6 –80 Filter Cutoff Accuracy vs Temperature FILTER CUTOFF FREQUENCY DEVIATION (%) FILTER CUTOFF FREQUENCY DEVIATION (%) Filter Cutoff Accuracy vs Supply Voltage 5 –75 6602 G05 6602 G04 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 2 3 4 OUTPUT VOLTAGE (VP-P) –70 –85 0 1 66062 G03 –85 –85 0 0 Distortion vs Lowpass Cutoff Frequency TA = 25°C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P RBIAS = 54.9k fLP = 300kHz GAIN = 0dB HD3 –75 HD2 0.00 –100 300 66062 G02 –70 –80 HD3 –90 Distortion vs Highpass Cutoff Frequency TA = 25°C VS = 3V fIN = 100kHz DIFFERENTIAL INPUT, VOUT = 1.5VP-P –75 R BIAS = 54.9k 45kHz-300kHz BPF HD2 –80 DISTORTION (dBc) 1k Distortion vs Gain 0.10 –70 HD3 45kHz-300kHz BPF 6602 G01 –90 TA = 25°C V = 3V –40 f S = 100kHz IN DIFFERENTIAL INPUT –50 RBIAS = 54.9k RBIAS = 45kHz-300kHz BPF –60 GAIN = 0dB –85 –40 –60 Distortion vs Output Voltage –30 80 6602 G08 COMMON MODE REJECTION (dB) GAIN (dB) 15kHz-150kHz BPF 90kHz-900kHz BPF DISTORTION (dBc) TA = 25°C VS = 3V EXTERNAL CLOCK RBIAS = 54.9k 0 GAIN = 0dB 10 –70 DISTORTION (dBc) Gain vs Frequency 20 CMR = ΔVIN-CM /ΔVOUT-DIFF 100 90 80 70 GAIN = 0dB 60 GAIN = 12dB TA = 25°C 50 V = 3V S GAIN = 24dB 40 VIN-CM = 0V GAIN = 30dB ΔVIN-CM = 1.25VP-P 30 RBIAS = 54.9k 45kHz-300kHz BPF 20 1k 10k 100k 1M 10M FREQUENCY (Hz) 6602 G09 6602fa 7 LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS Common Mode Rejection 100 GAIN = 12dB GAIN = 0dB 90 80 70 GAIN = 24dB GAIN = 30dB 60 TA = 25°C 50 V = 3V S 40 VIN-CM = 0V ΔVIN-CM = 1.25VP-P 30 RBIAS = 54.9k 15kHz-150kHz BPF 20 1k 10k 100k FREQUENCY (Hz) 120 TA = 25°C, VS = 3V, 110 VIN-CM = 0V, ΔVIN-CM = 1.25VP-P, RBIAS = 54.9k, 90kHz-900kHz BPF 100 110 100 90 80 70 GAIN = 0dB 60 50 GAIN = 24dB GAIN = 12dB 30 CMR = ΔVIN-CM /ΔVOUT-DIFF 20 10k 100k 1M FREQUENCY (Hz) 10M GAIN = 24dB CMRR (dB) CMRR (dB) 90 GAIN = 0dB 60 GAIN = 12dB 50 40 40 TA = 25°C, VS = 3V, 30 VIN-CM = 0V, ΔVIN-CM = 1.25VP-P, RBIAS = 54.9k, 15kHz-150kHz BPF 20 1k 10k 100k FREQUENCY (Hz) 48 GAIN = 24dB 60 50 GAIN = 0dB GAIN = 0dB 40 20 10k 1M 100k 1M FREQUENCY (Hz) GAIN = 0dB TA = 25°C VS = 3V f1 = fC –5kHz f2 = fC +5kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST RBIAS = 54.9k 15kHz-150kHz BPF 42 40 0 20 40 60 80 100 120 140 160 CENTER SIGNAL FREQUENCY, fC (kHz) 6602 G16 OIP3 (dBm) OIP3 (dBm) GAIN = 24dB 50 100 150 200 250 300 350 CENTER SIGNAL FREQUENCY, fC (kHz) OIP3 vs Temperature 50 48 TA = 25°C, VS = 3V f1 = fC –10kHz, f2 = fC +10kHz VOUT = 6dBm PER TONE 46 FOR 2-TONE TEST RBIAS = 54.9k 90kHz-900kHz BPF 44 0 6602 G15 OIP3 vs Average Signal Frequency, fC GAIN = 12dB 44 38 10M 6602 G14 GAIN = 30dB 46 GAIN = 30dB GAIN = 12dB 42 30 OIP3 vs Average Signal Frequency, fC 48 TA = 25°C VS = 3V f1 = fC –5kHz, f2 = fC +5kHz 46 V OUT = 6dBm PER TONE FOR 2-TONE TEST RBIAS = 54.9k 45kHz-300kHz BPF 44 GAIN = 24dB GAIN = 30dB 6602 G13 38 OIP3 vs Average Signal Frequency, fC OIP3 (dBm) GAIN = 30dB TA = 25°C 110 VS = 3V VIN-CM = 0V 100 ΔV IN-CM = 1.25VP-P 90 RBIAS = 54.9k 90kHz-900kHz BPF 80 GAIN = 12dB 70 10M 6602 G12 120 120 70 GAIN = 0dB TA = 25°C, VS = 3V, 30 VIN-CM = 0V, ΔVIN-CM = 1.25VP-P, RBIAS = 54.9k, 45kHz-300kHz BPF 20 1k 10k 100k 1M FREQUENCY (Hz) GAIN = 30dB Common Mode Rejection Ratio 80 GAIN = 12dB 60 6602 G11 Common Mode Rejection Ratio 100 70 40 6602 G10 110 GAIN = 24dB 80 50 40 1M GAIN = 30dB 90 GAIN = 12dB OIP3 (dBm) COMMON MODE REJECTION (dB) COMMON MODE REJECTION (dB) CMR = ΔVIN-CM /ΔVOUT-DIFF 110 Common Mode Rejection Ratio Common Mode Rejection 120 CMRR (dB) 120 42 VS = 3V VOUT = 6dBm PER TONE FOR 2-TONE TEST 48 RBIAS = 54.9k GAIN = 30dB fIN = 95kHz, 105kHz 15kHz-150kHz BPF 46 44 fIN = 145kHz, 155kHz 45kHz-300kHz BPF GAIN = 24dB 40 42 GAIN = 30dB GAIN = 0dB 38 0 100 200 300 400 500 600 700 800 900 1000 CENTER SIGNAL FREQUENCY, fC (kHz) 6602 G17 fIN = 590kHz, 610kHz 90kHz-900kHz BPF 40 –40–30–20–10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 6602 G18 6602fa 8 LTC6602 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C VS = 3V RBIAS = 54.9k 105 SUPPLY CURRENT (mA) OUTPUT IMPEDANCE (Ω) Supply Current vs Supply Voltage 110 10 15kHz-150kHz BPF 90kHz-900kHz BPF 1 900kHz LPF Supply Current vs Temperature 120 CLKCNTL PIN FLOATING RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB 90kHz-900kHz BPF 100 SUPPLY CURRENT (mA) Output Impedance vs Frequency 100 85°C 100 25°C –40°C 95 1k 10k 100k 1M FREQUENCY (Hz) 10M 80 15kHz-150kHz BPF 60 40 90 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) VS = 3V 20 CLKCNTL PIN FLOATING RBIAS = 54.9k GAIN = 0dB 0 –40–30–20–10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 6602 G20 6602 G21 45kHz-300kHz BPF 0.1 45kHz-300kHz BPF 6602 G19 RBIAS Pin Voltage vs IRBIAS Clock Output Operating at 90MHz RBIAS PIN VOLTAGE (V) 1.25 1V/DIV 0V 1.20 1.15 1.10 6602 G22 2.5ns/DIV TA = 25°C VS = 3V 0 5 10 15 IRBIAS (μA) 20 25 6602 G23 Input Referred Noise Density GAIN = 0dB INTEGRATED NOISE = 186.5μVRMS VOLTAGE NOISE DENSITY (nV/√Hz) VOLTAGE NOISE DENSITY (nV/√Hz) 1000 GAIN = 12dB INTEGRATED NOISE = 47.1μVRMS 100 10 1 GAIN = 30dB INTEGRATED NOISE = 7.5μVRMS 1k GAIN = 24dB INTEGRATED NOISE = 12.6μVRMS 10k 100k FREQUENCY (Hz) TA = 25°C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 45kHz-300kHz BPF INTEGRATED NOISE BW = 1.57MHz 1M Input Referred Noise Density GAIN = 0dB INTEGRATED NOISE = 189μVRMS 100 GAIN = 12dB INTEGRATED NOISE= 47.8μVRMS 10 GAIN = 24dB INTEGRATED NOISE = 12.5μVRMS 1 GAIN = 30dB INTEGRATED NOISE = 7.2μVRMS 1k 10k 100k FREQUENCY (Hz) 6602 G24 TA = 25°C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 15kHz-150kHz BPF INTERNAL NOISE BW = 400kHz 1000 VOLTAGE NOISE DENSITY (nV/√Hz) Input Referred Noise Density 1000 1M 6602 G25 GAIN = 0dB INTEGRATED NOISE = 304.2μVRMS GAIN = 12dB INTEGRATED NOISE = 77.6μVRMS 100 10 GAIN = 24dB INTEGRATED NOISE = 20.7μVRMS GAIN = 30dB INTEGRATED NOISE = 17.5μVRMS 1 10k 100k 1M FREQUENCY (Hz) TA = 25°C, VS = 3V, EXTERNAL CLOCK RBIAS = 54.9k, 90kHz-900kHz BPF INTERNAL NOISE BW = 2.5MHz 10M 6602 G26 6602fa 9 LTC6602 PIN FUNCTIONS V+IN (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor unless it is tied to V+A (Pin 2). The bypass should be as close as possible to the IC, but is not as critical as the bypassing of V+A and V+D (Pin16). V+A (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC. VOCM (Pin 3): Output common mode voltage reference. If floated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5V), maximizing the dynamic range of the filter. If this pin is floated, it must be bypassed with a quality 0.1μF capacitor to ground. This pin has a typical input impedance of 400Ω and may be overdriven. Driving this pin to a voltage other than the default value will reduce the signal range the filter can handle before clipping. RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input. The value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the filter networks. The voltage on this pin is held by the LTC6602 to approximately 1.17V. For best performance, use a precision metal film resistor with a value between 54.9k and 200k and limit the capacitance on this pin to less than 10pF. This resistor is necessary even if an external clock is used. CLKCNTL (Pin 5): Clock Control Input. This three-state input selects the function of CLKIO (Pin 15). Tying the CLKCNTL pin to ground allows the CLKIO pin to be driven by an external clock (CLKIO is the master clock input). If the CLKCNTL pin is floated, the internal oscillator is enabled, but the master clock is not present at the CLKIO pin (CLKIO is a no-connect). If the CLKCNTL pin is tied to V+D (Pin 16), the internal oscillator is enabled and the master clock is present at the CLKIO pin (CLKIO is the master clock output). To detect a floating CLKCNTL pin, the LTC6602 attempts to pull the pin toward mid-supply. This is realized with two internal current sources, one tied to V+D and CLKCNTL and the other one tied to ground and CLKCNTL. Therefore, driving the CLKCNTL pin high requires sourcing approximately 15μA. Likewise, driving the CLKCNTL pin low requires sinking 15μA. When the CLKCNTL pin is floated, preferably it should be bypassed by a 1nF capacitor to ground or it should be surrounded by a ground shield to prevent excessive coupling from other PCB traces. LPF1(CS) (Pin 6): Logic Input. When in pin programmable control mode, this pin is the MSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low). +INB, –INB (Pins 7, 8): Channel B differential inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. LPF0(SCLK) (Pin 9): Logic Input. When in pin programmable control mode, this pin is the LSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface. HPF1(SDI) (Pin 10): Logic Input. When in pin programmable control mode, this pin is the MSB of the highpass cutoff frequency control code; in serial control mode, this pin is the serial data input. HPF0(SDO) (Pin 11): Logic Input. When in pin programmable control mode, this pin is the LSB of the highpass cutoff frequency control code; in serial control mode, this pin is the serial data output. –OUTB, +OUTB (Pins 12, 13): Channel B differential filter outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). GND (Pin 14): Ground. Connect to a ground plane for best performance. 6602fa 10 LTC6602 PIN FUNCTIONS CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground, CLKIO is the master clock input. When CLKCNTL is floated, CLKIO is pulled to ground by a weak, 5μA pulldown. When CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock output. When configured as a clock output, this pin can drive 1k and/or 5pF loads. Heavier loads may cause inaccuracies due to supply bounce at high frequencies. V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC. larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). MUTE (Pin 20): MUTEX input. Drive to ground to disconnect and mute the inputs. Float or drive to V+D (Pin 16) for normal operation. GAIN0(D0) (Pin 21): Logic Input. When in pin programmable control mode, this pin is the LSB of the gain control code; in serial control mode, this pin is the LSB of the serial control register, an output. SER (Pin 17): Interface Selection Input. When tied to V+D (Pin 16), the interface is in pin programmable control mode, i.e. the filter gain and cutoff frequencies are programmed by the GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0 pin connections. When SER is tied to ground, the filter gain, the filter cutoff frequencies and shutdown mode are programmed by the serial interface. GAIN1 (Pin 22): Logic Input. When in pin programmable control mode, this pin is the MSB of the gain control code; in serial control mode, this pin is a no-connect. –OUTA, +OUTA (Pins 18, 19): Channel A differential filter outputs. These pins can drive 1k and/or 50pF loads. For Exposed Pad (Pin 25): Ground. The Exposed Pad must be soldered to PCB. –INA, +INA (Pins 23, 24): Channel A differential inputs. The input range and input resistance are described in the Applications Information section. Input voltage levels can range from GND to the V+IN supply rail. 6602fa 11 LTC6602 BLOCK DIAGRAM +INA –INA GAIN1 GAIN0(D0) MUTE +OUTA 24 23 22 21 20 19 V+IN 1 18 –OUTA CHANNEL A PGA LPF HPF 17 SER V+A 2 CONTROL BIAS CLK VDDA 1.6k VOCM 3 16 V+D 1.6k GND CONTROL LOGIC BIAS/OSC CLOCK GENERATOR RBIAS 4 15 CLKIO BIAS CLKCNTL 5 PGA CONTROL CLK LPF HPF 14 GND CHANNEL B LPF1(CS) 6 13 +OUTB 7 8 9 10 11 12 +INB –INB LPF0(SCLK) HPF1(SDI) HPF0(SDO) –OUTB 6602 BD 6602fa 12 LTC6602 TIMING DIAGRAM Timing Diagram of the Serial Interface t4 t1 t2 t6 t3 t7 SCLK t9 D3 SDI D2 D1 D0 D7 • • • • D4 D3 t5 CS t8 SDO D4 PREVIOUS BYTE D3 D2 D1 D0 D7 • • • • D4 CURRENT BYTE D3 6602 TD 6602fa 13 LTC6602 APPLICATIONS INFORMATION Theory of Operation (Refer to Block Diagram) Pin Programmable Interface The LTC6602 features two matched filter channels, each containing gain control, lowpass, and highpass networks that are controlled by a single control block and clocked by a single clock generator. The gain, lowpass and highpass sections can be independently programmed. The two channels are not independent, i.e. if the gain is set to 24dB, then both channels have a gain of 24dB. The filter can also be programmed to bypass the highpass filter networks, giving a lowpass response. The filter can be clocked with an external clock source, or using the internal oscillator. A resistor connected to the RBIAS pin sets the bias currents for the filter networks and the internal oscillator frequency (unless driven by an external clock). Altering the clock frequency changes the filter bandwidths. This allows the filters to be “tuned” to many different bandwidths. As shown in Figure 1, connecting SER to V+D allows the filter to be directly controlled through the pin programmable control lines GAIN1, GAIN0, HPF1, HPF0, LPF1 and LPF0. The HPF0(SDO) and GAIN0(D0) pins are bidirectional (inputs in pin programmable control mode, outputs in serial mode). In pin programmable control mode, the voltages at HPF0(SDO) and GAIN0(D0) cannot exceed V+D; otherwise, large currents can be injected to V+D through the internal diodes (see Figure 2). Connecting a 10k resistor at the HPF0(SDO) and GAIN0(D0) pins (see Figure 1) is recommended for current limiting, to less than 10mA. SER has an internal pull-up to V+D. None of the logic inputs have an internal pull-up or pull-down. 3.3V 3.3V LTC6602 0.1μF + V+IN V+A V+A V+D V+D +INA +OUTA VIN – LTC6602 0.1μF V+IN –INA –OUTA + + VOUT VIN +INA + VOUT – – +OUTA –INA SER –OUTA – SER LPF1 LPF1(CS) LPF1(CS) LPF0 LPF0(SCLK) LPF0(SCLK) HPF1 HPF1(SDI) μP HPF0(SDO) HPF0 10k HPF0(SDO) GAIN1 GAIN1 GAIN1 GAIN0 GAIN0(D0) 10k GND LOWPASS CUTOFF = 900kHz (fCLK = 90MHz) HIGHPASS CUTOFF = 90kHz (fCLK = 90MHz) GAIN = 16 HPF1(SDI) GAIN0(D0) GND GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR. 10k RESISTORS ON HPF0(SDO) AND GAIN0(D0) PROTECT THE DEVICE IF VHPF0 > V+D OR VGAIN0 > V+D 6602 F01 Figure 1. Filter in Pin Programmable Control Mode 6602fa 14 LTC6602 APPLICATIONS INFORMATION V+D SHUTDOWN 6-BIT GAIN, BW CONTROL CODE OUT CS 8-BIT LATCH HPF0(SDO) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER DIN (INTERNAL NODE) 6602 F02 SDO SCLK 6602 F03 Figure 2. Bidirectional Design of HPFO(SDO) and GAIN0(D0) Pins Figure 3. Diagram of Serial Interface (MSB First Out) 3.3V 3.3V 0.1μF V+IN + LTC6602 #1 0.1μF V+A V+A V+D V+D + + +OUTA +INA VIN1 +OUTA + –INA –OUTA – VOUT2 – – –OUTA –INA +INA VIN2 VOUT1 – LTC6602 #2 V+IN SER SER LPF1(CS) LPF1(CS) LPF1(CS) SCLK μP SDI LPF0(SCLK) GAIN0(D0) HPF1(SDI) HPF0(SDO) OUT1 GND LPF0(SCLK) GAIN0(D0) OUT2 HPF1(SDI) HPF0(SDO) SDO GND SCLK SDI D15 D11 D10 D9 D8 GAIN, BW CONTROL WORD FOR #2 SHUTDOWN FOR #2 D7 D3 D2 D1 D0 GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1 CS 6602 F04 Figure 4. Two Filters in a Daisy Chain Serial Control Register Definition D7 D6 D5 D4 D3 D2 D1 D0 GAIN0 GAIN1 LPF0 LPF1 HPF0 HPF1 SHDN OUT 6602fa 15 LTC6602 APPLICATIONS INFORMATION Serial Interface Self-Clocking Operation Connecting SER to ground allows the filter to be controlled through the SPI serial interface. When CS is low, the serial data on SDI is shifted into an 8-bit shift-register on the rising edge of the clock (SCLK), with the MSB transferred first (see Figure 3). Serial data on SDO is shifted out on the clock’s falling edge. A high CS will load the 8 bits of the shift-register into an 8-bit D-latch, which is the serial control register. The clock is disabled internally when CS is pulled high. Note: SCLK must be low before CS is pulled low to avoid an extra internal clock pulse. SDO is always active in serial mode (never tri-stated) and cannot be “wire-or’ed” to other SPI outputs. In addition, SDO is not forced to zero when CS is pulled high. The LTC6602 features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor connected to the RBIAS pin. The clock frequency is determined by the following simple formula (see Figure 5): GAIN1 and GAIN0 are the gain control bits (register bits D6 and D7 when in serial mode). Their function is shown in Table 1. In serial mode, register bit D1 can be set to ‘1’ to put the device into a low power shutdown mode. Register bit D0 is a general purpose output (Pin 21) when in serial mode. Table 1. Gain Control GAIN 1 GAIN 0 PASSBAND GAIN (dB) 0 0 0 0 1 12 1 0 24 1 1 30 Note: RBIAS ≤ 200k. 200 175 150 RBIAS (kΩ) An LTC6602 may be daisy chained with other LTC6602s or other devices having serial interfaces. Daisy chaining is accomplished by connecting the SDO of the lead chip to the SDI of the next chip, while SCLK and CS remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6602s in a daisy chained SPI configuration. fCLK = 494.1MHz • 10k/RBIAS 125 100 75 50 20 30 40 50 60 70 80 DESIRED CLOCK FREQUENCY (MHz) 90 6602 F05 Figure 5. RBIAS vs Desired Clock Frequency The design is optimized for V+A, V+D = 3V, fCLK = 90MHz, where the filter cutoff frequency error is typically <3% when a 0.1% external 54.9k resistor is used. With different resistor values and cutoff frequency control settings (HPF1, HPF0, LPF1 and LPF0), the highpass and lowpass cutoff frequencies can be accurately varied from 4.1175kHz to 90kHz and from 41.175kHz to 900kHz, respectively. Table 2 summarizes the cutoff frequencies that can be obtained with an external resistor (RBIAS) value of 54.9k. Note that the cutoff frequencies scale with the clock frequency. For example, if HPF1, HPF0, LPF1 and LPF0 are all equal to zero, and RBIAS is increased from 54.9k to 200k, fCLK will decrease from 90MHz to 24.705MHz, the lowpass cutoff frequency will be reduced from 150kHz to 41.175kHz, and the highpass cutoff frequency will be reduced from 15kHz to 4.1175Hz. The cutoff frequencies that can be obtained with an external resistor value of 200k 6602fa 16 LTC6602 APPLICATIONS INFORMATION are shown in Table 3. When the LTC6602 is programmed for the lowest lowpass cutoff frequency (LPF1, LPF0 = ‘0’), the power is automatically reduced by about 35%. Table 2. Cutoff Frequency Control, RBIAS = 54.9k, fCLK = 90MHz LPF1 LPF0 Lowpass BW (kHz) HPF1 HPF0 Highpass BW (kHz) 0 0 150 0 0 15 0 1 300 0 1 45 1 0 900 1 0 90 1 1 900 1 1 Bypass HPF LPF1 LPF0 Lowpass BW (kHz) HPF1 HPF0 Highpass BW (kHz) 0 0 41.175 0 0 4.1175 0 1 82.35 0 1 12.3525 1 0 247.05 1 0 24.705 1 1 247.05 1 1 Bypass HPF The following graphs show a few of the possible combinations of highpass and lowpass filters. Gain and Group Delay vs Frequency (45kHz to 300kHz Bandpass Response) Gain and Group Delay vs Frequency (15kHz to 150kHz Bandpass Response) 40 40 20 GAIN = 30dB GAIN = 24dB 18 GAIN = 0dB 12 0 –10 10 –20 8 –30 6 –40 4 –40 2 –50 0 10M –60 GROUP DELAY –50 –60 1k 10k 100k 1M FREQUENCY (Hz) 60 GAIN = 30dB 48 GAIN = 12dB 42 30 –20 24 –30 18 12 GROUP DELAY 1k 10k 100k FREQUENCY (Hz) 20 GAIN (dB) GAIN = 12dB GAIN = 0dB 6 –10 5 –20 4 –30 3 –40 –50 –60 10k 2 GROUP DELAY 100k 1M FREQUENCY (Hz) 1 0 10M 6602 G30 1.0 30 GAIN = 30dB 0.9 20 GAIN = 24dB 0.8 10 GAIN = 12dB 0.7 0 –10 GAIN = 0dB GROUP DELAY 0.6 0.5 –20 0.4 –30 0.3 TA = 25°C VS = 3V –50 EXTERNAL CLOCK RBIAS = 54.9k –60 1k 10k 100k 1M FREQUENCY (Hz) –40 GROUP DELAY (μs) 0 GAIN = 24dB 40 GROUP DELAY (μs) 10 0 1M Gain and Group Delay vs Frequency (900kHz Lowpass Response) GAIN (dB) 30 10 TA = 25°C VS = 3V 9 EXTERNAL CLOCK 8 RBIAS = 54.9k 7 6 6602 G29 Gain and Group Delay vs Frequency (90kHz to 900kHz Bandpass Response) GAIN = 30dB 36 GAIN = 0dB –10 6602 G28 40 54 GAIN = 24dB GROUP DELAY (μs) 14 GAIN (dB) GAIN = 12dB 0 TA = 25°C 30 VS = 3V EXTERNAL 20 CLOCK 10 RBIAS = 54.9k 16 GROUP DELAY (μs) TA = 25°C 30 VS = 3V EXTERNAL 20 CLOCK 10 RBIAS = 54.9k GAIN (dB) Table 3. Cutoff Frequency Control, RBIAS = 200k, fCLK = 24.705MHz 0.2 0.1 0.0 10M 6602 G28 6602fa 17 LTC6602 APPLICATIONS INFORMATION Preserving Oscillator Accuracy The oscillator is sensitive to transients on the positive supply. The IC should be soldered to the PC board and the PCB layout should include a 0.1μF ceramic capacitor between V+A (Pin 2) and ground, as close as possible to the IC to minimize inductance. The PCB layout should also include an additional 0.1μF ceramic capacitor between V+D (Pin 16) and ground. Avoid parasitic capacitance on RBIAS (Pin 4) and avoid routing noisy signals near RBIAS. Use a ground plane connected to Pin 14 and the Exposed Pad (Pin 25). Alternative Methods of Setting the Clock Frequency of the LTC6602 The oscillator may be programmed by any method that sinks a current out of the RBIAS pin. The circuit in Figure 6 sets the clock frequency by using a programmable current source and in the expression for fCLK, the resistor RBIAS is replaced by the ratio of 1.17V/ICONTROL. Because the voltage of the RBIAS pin is approximately 1.17V ±5%, the Figure 6 circuit is less accurate than if a resistor controls the clock frequency. Figure 7 shows the LTC6602’s oscillator configured as a VCO. A voltage source is connected in series with the RBIAS resistor. The clock frequency, fCLK, will vary with VCONTROL. Again, this circuit decouples the relationship between the current out of the RBIAS pin and the voltage of the RBIAS pin; the frequency accuracy will be degraded. The clock frequency, however, will increase monotonically with decreasing VCONTROL. Operation Using an External Clock The LTC6602 may be clocked by an external oscillator for tighter bandwidth control by pulling CLKCNTL (Pin 5) to ground and driving a clock into CLKIO (Pin 15). If an external clock is used, the RBIAS resistor is still necessary. The value of RBIAS must be no larger than the value that would be required for using the internal oscillator. For example, a 100k resistor would program the internal oscillator for 49.41MHz, so an external oscillator frequency of 49.41MHz would require an RBIAS resistance of no more than 100k. If the value of RBIAS is too large, the filters will not receive a large enough bias current, possibly causing errors due to insufficient settling. RBIAS RBIAS RBIAS ICONTROL VCONTROL fCLK = 10k • (494.1MHz/1.17V) • ICONTROL(A) 6602 F06 Figure 6. Current Controlled Clock Frequency + – fCLK = 494.1MHz • (10k/RBIAS) • (1 – VCONTROL/1.17V) 6602 F07 Figure 7. Voltage Controlled Clock Frequency 6602fa 18 LTC6602 APPLICATIONS INFORMATION –70 TA = 25°C fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P –75 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB DISTORTION (dBc) DISTORTION (dBc) –70 HD3 –80 HD2 –85 –90 TA = 25°C fIN = 100kHz DIFFERENTIAL INPUT, VIN = 1.5VP-P –75 RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB HD3 –80 HD2 –85 0 0.5 1.0 1.5 2.0 2.5 COMMON MODE INPUT VOLTAGE (V) –90 3.0 0 1 2 3 4 COMMON MODE INPUT VOLTAGE (V) 6602 F08 Figure 8. Distortion vs Common Mode Input Voltage (3V) Input Common Mode and Differential Voltage Range The input signal range extends from zero to the V+IN supply voltage. This input supply can be tied to V+A and V+D, or driven up to 5.5V for increased input common mode voltage range. Figures 8 and 9 show the distortion of the filter versus common mode input voltage with a 1.5VP-P differential input signal. For best performance, the inputs should be driven differentially. For single ended signals, connect the unused input to VOCM (Pin 3) or to a quiet DC reference voltage. To achieve the best distortion performance, the input signal should be centered around the DC voltage of the unused input. Refer to the Typical Performance Characteristics section to estimate the distortion for a given input level. Dynamic Input Impedance The unique input sampling structure of the LTC6602 has a dynamic input impedance which depends on the configuration and the clock frequency. This dynamic input impedance has both a differential component and a common mode component. The common mode input impedance is a function of the clock frequency and the control bit LPF1. The differential input impedance is a function of the clock frequency and the control bits LPF1, GAIN1 and GAIN0. Table 4 shows the typical input impedances for a clock frequency of 90MHz. These input impedances are all proportional to 1/fCLK, so if the clock frequency were reduced 5 6602 F09 Figure 9. Distortion vs Common Mode Input Voltage (5V) by half to 45MHz, the impedances would be doubled. The typical part to part variation in dynamic input impedance for a given clock frequency is –20% to +35%. Table 4. Differential, Common Mode Input Impedances, fCLK = 90MHz GAIN1 GAIN0 LPF1 Differential Input Impedance (kΩ) Common Mode Input Impedance (kΩ) 0 0 0 16 20 0 0 1 6 6.7 0 1 0 8 20 0 1 1 2.8 6.7 1 0 0 2.6 20 1 0 1 1.8 6.7 1 1 0 2.4 20 1 1 1 1.3 6.7 Output Common Mode and Differential Voltage Range The output voltage is a fully differential signal with a common mode level equal to the voltage at VOCM. Any of the filter outputs may be used as single-ended outputs, although this will degrade the performance. The output voltage range is typically 0.5V to V+A – 0.5V (V+A = 2.7V to 3.6V). The common mode output voltage can be adjusted by overdriving the voltage present on VOCM. To maximize the undistorted peak-to-peak signal swing of the filter, the VOCM voltage should be set to V+A /2. Note that the 6602fa 19 LTC6602 APPLICATIONS INFORMATION VSUPPLY –20 DISTORTION (dBc) –30 0.1μF –40 LTC6602 V+IN V+A –50 V+D –60 HD3 –70 –80 HD2 –90 0.5 TA = 25°C fIN = 100kHz VIN = 1.5VP-P RBIAS = 54.9k 45kHz-300kHz BPF GAIN = 0dB VIN+ + – VIN– 1.0 1.5 2.0 2.5 COMMON MODE OUTPUT VOLTAGE (V) + – +INA +OUTA VOUT+ –INA –OUTA VOUT– VOCM 1μF GND DC COUPLED INPUT VIN (COMMON MODE) = (VIN+ + VIN–)/2 VOUT (COMMON MODE) = (VOUT+ + VOUT–)/2 = VSUPPLY/2 6602 F10 6602 F11 Figure 10. Distortion vs Common Mode Output Voltage VSUPPLY VSUPPLY 0.1μF RPULL-UP RPULL-UP + – VIN– LTC6602 0.1μF V+IN 1.87k V+D + – 0.1μF 1μF VSUPPLY VSUPPLY V+A 0.1μF VIN+ Figure 11. DC Coupled Inputs 1.87k V+A V+D 0.1μF +INA –OUTA –INA –OUTB VOCM VIN+ 1.87k VIN– + – LTC6602 V+IN + – 0.1μF 1.87k 1μF +INA –OUTA –INA –OUTB VOCM GND GND 6602 F12b 6602 F12a AC COUPLED INPUT VIN (COMMON MODE) = VSUPPLY/2 AC COUPLED INPUT = RCM • VSUPPLY = COMMON MODE AT +INA AND –INA 2 • RCM + 1.87k (b) Variable Lowpass Cutoff Frequency (a) Fixed Lowpass Cutoff Frequency Figure 12. AC Coupled Inputs output common mode voltages of the two channels are not independent as they are both set by the VOCM pin. Figure 10 illustrates the distortion versus output common mode voltage for a 1.5VP-P differential input voltage and a common mode input voltage that is equal to mid-supply. Interfacing to the LTC6602 The input and output common mode voltages of the LTC6602 are independent. The input common mode voltage is set by the signal source if DC coupled, as shown in Figure 11. If the inputs are AC coupled, the input common mode voltage will pulled to ground by an equivalent resistance of RCM, shown in Table 4. This does not affect the filter’s performance as long as the input amplitude is less than 0.5VP-P. At low filter gain settings, a larger input voltage swing may be desired. Figure 12 shows two circuits with AC coupled inputs. In a fixed lowpass cutoff frequency, connecting resistors between each input and V+IN will pull the input common mode voltage up, increasing the input signal swing (Figure 12a). The resistance, RPULL-UP, necessary to set the input common mode voltage, VICM, to any desired level can be calculated by V RPULLUP = RCM SUPPLY 1 VICM where RCM = 20k • 90MHz/fCLK for LPFI = 0 RCM = 6.7k • 90MHz/fCLK for LPFI = 1 For example, if the lowpass cutoff frequency is set to 300kHz, 20k resistors connected between each input and V+IN will set the input common mode voltage to mid-supply. 6602fa 20 LTC6602 APPLICATIONS INFORMATION 3.3V 3.3V LTC6602 MASTER 0.1μF V+IN RBIAS V+A V+IN +INA RBIAS –INA RBIAS V+D +OUTA VIN1 – RBIAS V+A V+D + LTC6602 SLAVE 0.1μF –OUTA + + VOUT1 VIN2 – – +INA +OUTA + VOUT2 –INA CLKCNTL CLKCNTL CLKIO CLKIO GND GND –OUTA – 6602 F13 Figure 13. Two Filters in a Master/Slave Configuration If the lowpass cutoff frequency varies then the Figure 12b circuit must be used. The output common mode voltage is equal to the voltage of the VOCM pin. The VOCM pin is biased to one half of the supply voltage by an internal resistive divider (see Block Diagram). To alter the common mode output voltage, VOCM can be driven with an external voltage source or resistor network. If external resistors are used, it is important to note that the internal 1.6k resistors can vary ±30% (their ratio varies only ±1%). The filter outputs can also be AC coupled. The LTC6602 can be interfaced to an A/D converter by pulling CLKCNTL (Pin 5) to V+D. This configures CLKIO (Pin 15) as a clock output, which can be used to drive the clock input of the A/D converter. This allows the A/D converter to be synchronized with the filter sampling clock, avoiding “beat frequencies” and simplifying the board layout. Any routing attached to the CLKIO pin should be as short as possible, in order to minimize ringing. Similarly, two LTC6602s can be connected in a master/ slave configuration as shown in Figure 13. This results in four matched filter channels, all synchronized to the same clock. The master has its CLKCNTL pin pulled to V+D, configuring its CLKIO pin as an output, while the slave has its CLKCNTL pin pulled to ground, configuring its CLKIO pin as an input. Output Drive The filter outputs can drive 1k and/or 50pF loads connected to AC ground with a 0.5V to 2.5V signal (corresponding to a 4VP-P differential signal). For differential loads (loads connected between +OUTA and –OUTA or +OUTB and –OUTB) the outputs can produce a 4VP-P signal across 2k and/or 25pF. For smaller signal amplitudes, the outputs can drive correspondingly heavier loads. For larger capacitive loads, an external 50Ω series resistor is recommended for each output. 6602fa 21 LTC6602 APPLICATIONS INFORMATION Mute Function The LTC6602 features a mute function which is asserted by pulling MUTE (Pin 20) to ground. This breaks the signal path that leads from the input pins to the filter networks, attenuating the input signal by at least 20dB. The mute function can be used to protect the filter inputs from large transients. The filter clock continues to run when the filter is muted, allowing for a fast recovery time when MUTE is de-asserted. Typically, the recovery time is less than 5μs, as shown in Figure 14. When the mute function is asserted, the differential input impedance becomes very high, but the common mode input impedance to ground remains the same. This keeps the input common mode voltage stable when muted, even when the inputs are AC coupled. Connecting GAIN0(D0) to MUTE allows for serial control of the mute function. MUTE has an internal pull-up to V+D. MUTE (2V/DIV) VOUT (1V/DIV) 4μs/DIV 6602 F14 Figure 14. Mute Function Recovery Time Clock Feedthrough Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter’s output. The clock feedthrough is measured with +INA and –INA (or +INB, –INB) tied to VOCM and depends on the PC board layout and the power supply decoupling. The clock feedthrough can be reduced with a simple RC post filter. DC Offset The output DC offset of the LTC6602 is less than ±15mV. To obtain optimum DC offset performance, appropriate PC board layout techniques should be used. The filter IC should be soldered to the PC board. The power supplies should be well decoupled including 0.1μF ceramic capacitors from V+D (Pin 16) and V+A (Pin 2) to ground. A ground plane should be used. Noisy signals should be isolated from the filter input pins. The output DC offset typically changes less than ±2mV when the clock frequency varies from 24.705MHz to 90MHz. The offset is measured by connecting the inputs to VOCM and measuring the differential voltage at the filter’s output. Aliasing Aliasing is an inherent phenomenon of sampled data filters. Significant aliasing only occurs when the frequency of the input signal approaches the sampling frequency or multiples of the sampling frequency. The ratio of the LTC6602 input sampling frequency to the clock frequency, fCLK, is determined by the state of control bit LPF1. If LPF1 is set to ‘0’, the input sampling frequency is equal to fCLK/3. If LPF1 is set to ‘1’, the input sampling frequency is equal to fCLK. Input signals with frequencies near the input sampling frequency will be aliased to the passband of the filter and appear at the output unattenuated. A simple LC anti-aliasing filter is recommended at the filter inputs to attenuate frequencies near the input sampling frequency that will be aliased to the passband. For example, if the clock frequency is set to 90MHz and the lowpass cutoff frequency of the filter is set to it’s maximum (LPF1 = ‘1’), the lowest frequency that would be aliased to the passband would be fCLK – fCUTOFF, i.e. 90MHz – 900kHz = 89.1MHz. In order to attenuate this frequency by 40dB, an LC filter with a cutoff frequency of 8.91MHz or lower would be required at the filter inputs. The capacitor connected between the LTC6602 filter inputs should be at least 150pF to provide sufficient charge to the input sampler. If there is no anti-aliasing filter, the LTC6602 filter inputs should be driven by a low impedance source (<100Ω). Wideband Noise The wideband noise of the filter is the RMS value of the device’s output noise spectral density. The wideband noise voltage is used to determine the operating signal-to-noise ratio at a given distortion level. The wideband noise is nearly independent of the value of the clock frequency and excludes the clock feedthrough. Most of the wideband noise is concentrated in the filter passband and cannot be removed with post filtering. 6602fa 22 LTC6602 APPLICATIONS INFORMATION 120 fCLK (MHz) SUPPLY CURRENT (mA) 100 HPF1 = 0 HPF1 = 0 HPF0 = 0 HPF0 = 1 10 LPF1 = 1 LPF1 = 0 LPF0 = 1 10k 100k FILTER CUTOFF FREQUENCY (Hz) 60 40 20 HPF1 = 1 LPF1 = 0 HPF0 = 0 LPF0 = 0 1k TA = 25°C VS = 3V 100 CLKCNTL PIN FLOATING HPF1 = 0 HPF0 = 1 80 GAIN = 0dB 0 10k 1M LPF1 = 0 LPF0 = 0 LPF1 = 0 LPF0 = 1 LPF1 = 1 100k LOWPASS CUTOFF FREQUENCY (Hz) 6602 F15 1M 6602 F16 Figure 15. fCLK vs Filter Cutoff Frequencies Figure 16. Supply Current vs Lowpass Cutoff Frequency Table 5. Total Input Referred Integrated Noise Voltage (Passband Gain = 30dB) LPF1 LPF0 HPF1 HPF0 Noise Voltage 0 0 0 0 –90dBm 0 1 0 1 –89dBm 1 X 1 0 –82dBm Power Supply Current The power supply current depends on the state of the lowpass cutoff frequency controls (LPF1, LPF0) and the value of RBIAS. When the LTC6602 is programmed for the lowest lowpass cutoff frequency (LPF1 = LPF0 = ‘0’), the supply current is reduced by about 35% relative to the supply current for the higher bandwidth settings. Power supply current vs. cutoff frequency for various bandwidth settings is shown in the “Typical Performance Characteristics” section. The LTC6602 can be programmed through the serial interface to enter into a low power shutdown mode as described in the Serial Interface section. The power supply current during shutdown is less than 235μA. Supply Current versus Noise Tradeoff The passband of the LTC6602 is determined by the master clock frequency (which is set by RBIAS when the internal oscillator is used), HPF1, HPF0, LPF1 and LPF0. The LTC6602 is optimized for use with RBIAS having a value between 200k and 54.9k to set the internal oscillation frequency from 24.705MHz to 90MHz. Both lowpass and highpass corner frequencies are proportional to the clock frequency (internal or external). To extend the filter’s operational frequency range, the master clock is divided down before reaching the filter. LPF1 and LPF0 set the division ratio of the lowpass clock while HPF1 and HPF0 set the division ratio of the highpass clock. Figure 15 shows the possible cutoff frequencies versus fCLK, HPF1, HPF0, LPF1 and LPF0. Overlapping frequency ranges allow more than one possible choice of bandwidth settings for some cutoff frequencies. Figure 16 shows supply current as a function of the lowpass cutoff frequency, LPF1 and LPF0. Note that the higher bandwidth setting always gives the minimum supply current for a given cutoff frequency. The total integrated noise voltage for a passband gain of 30dB is shown in Table 5. Note that the noise is higher for the higher bandwidth settings. This creates a tradeoff between supply current and noise. For a given cutoff frequency, using the highest possible bandwidth setting gives the minimum supply current at the expense of higher noise. 6602fa 23 LTC6602 APPLICATIONS INFORMATION The LTC6602, an Adaptable Baseband Filter for an RFID Reader A radio-frequency identification (RFID) system is an auto-id technology that identifies any object that contains a coded tag. An RFID system consists of a reader (or interrogator) and a tag. An RFID system capable of identifying multiple tags at a maximum operating distance operates in the UHF frequency range. A UHF reader transmits information to a tag by modulating an RF signal in the 860MHz to 960MHz frequency range. Typically a tag is passive, meaning that it receives all of its operating energy from a reader that transmits a continuous wave (CW) RF signal to power a tag. A tag responds by modulating the reflection coefficient of its antenna, thereby backscattering an information signal to the reader. Reliable detection of a tag signal requires communication protocols that define the physical and operating interaction between readers and tags. The latest UHF RFID protocol, the Electronic Product Code™ (EPC) global class-1 generation 2 standard (C1G2), have been accepted worldwide and is also known as ISO 18000-6C. The C1G2 standard defines a reader to tag and a tag to reader communication using a flexible set of signal modulation, data encoding, data rates and command procedures. C1G2 specifies reader and tag data symbols using pulse-interval encoding. Tag signal detection requires measuring the time interval between signal transitions (a data “1” symbol has a longer interval than a data “0” symbol). The reader initiates a tag inventory by sending a signal that instructs a tag to set its backscatter data rate and encoding. C1G2 certified RFID readers can operate in an RF environment where many readers are in close proximity. The three operating modes of C1G2, single interrogator, multiple interrogator and dense interrogator, define the spectral limits of reader and tag signals for an optimum balance of reliable multitag detection and high data throughput (for more information on C1G2, consult the references at the end of this design note). The advantages of C1G2 complex protocols can be realized by using a reader whose receiver contains a high linearity direct conversion I and Q demodulator, a low noise amplifier, a dual baseband filter with variable gain and bandwidth and a dual analog to digital converter (ADC). Certified C1G2 UHF RFID readers can adapt to a great variety of operating conditions. To achieve operating flexibility a reader’s baseband circuits must include an adaptable bandwidth filter. Figure 17 shows an LTC6602 based filter circuit that uses SPI control to vary the filter’s bandwidth to adjust for the C1G2 complex set of data rates, encoding and modulation. The filter’s clock frequency is set by the SPI control of 8-bit LTC2630 DAC (digital to analog converter). The DAC voltage through a resistive divider sets the current into the LTC6602 RBIAS pin. The resistive divider sets the clock frequency range for a DAC voltage range 0V to 3V. For the resistor values in Figure 17 (191k and 61.9k) the clock frequency range is 40MHz to 100MHz (234.4kHz per bit). The lowpass and highpass division ratio is set by the SPI control of the LTC6602. The cutoff range for the highpass filter is 6.7kHz to 100kHz and for the lowpass filter is 66.7kHz to 1MHz. The optimum filter bandwidth setting can be adjusted by a software algorithm and is a function of the reader’s data clock, data rate, encoding and modulation. The filter bandwidth must be sufficiently narrow to maximize the dynamic range to the ADC input and wide enough to preserve signal transitions and pulse width. If the filter setting is optimum then a DSP algorithm can reliably detect tag data. Figure 18a shows the filter’s time response to a typical tag symbol sequence (a “short” pulse interval followed by a “long” pulse interval). The lowpass cutoff frequency is set equal to the reciprocal of the shortest interval (fCUTOFF = 1/10μs = 100kHz). If the lowpass cutoff frequency is lower the signal transition and time interval will be distorted beyond recognition by any tag signal detection algorithm. The setting of the highpass cutoff frequency is more qualitative than specific. The highpass cutoff frequency must be lower than the reciprocal of the longest interval (for Figure 18 example, highpass fCUTOFF < 1/20μs < 50kHz) and as high as possible to decrease the receiver’s low frequency noise (baseband amplifier and down-converted phase and amplitude noise). Figures 18a and 18b show the filter’s total response (lowpass plus highpass filter). The filter’s output is shown with 30kHz and a 10kHz highpass cutoff frequency setting. Comparing the filter outputs with a 10kHz and a 30kHz highpass setting, the signal transitions and time intervals of the 10kHz output are adequate for 6602fa 24 LTC6602 APPLICATIONS INFORMATION detecting the symbol sequence (in an RFID environment, noise will be superimposed on the output signal). In general, increasing the lowpass fCUTOFF and/or decreasing the highpass fCUTOFF “enhances” signal transitions and intervals and increases filter output noise. 5V 3V 0.1μF 1 2 V+IN V+A 24 +INA SPI CONTROL OF DAC SETS THE LTC6602 CLOCK FREQUENCY 40MHz TO 100MHz 1 2 3 CS SDI 16 V+D –OUTA 18 I CHANNEL INPUT 23 –INA 7 +INB Q CHANNEL INPUT 8 VOUT SCLK 0.1μF GND 6 5 174k 0.1μF 4 0.1μF 68.1k 4 V+ 3 20 21 3V LTC2630 8-BIT DAC TRANSMITTER MUTE INPUT DAC VOUT RANGE 0V TO 2.5V (USING THE LTC2630 INTERNAL REFERENCE) 22 14 25 +OUTA 19 I CHANNEL OUTPUT –OUTB 12 Q CHANNEL OUTPUT LTC6602 +OUTB 13 –INB 15 CLKIO RBIAS 17 SER VOCM 5 3V CLKCNTL MUTE 11 GAIN0(D0) HPFO(SDO) 10 HPFI(SDI) GAIN1 SPI CONTROL OF LTC6602 9 SETS THE FILTER GAIN AND THE LPFO(SCLK) GND LOWPASS AND HIGHPASS 6 LPF1(CS) GND DIVISION RATIO ADC VCOM INPUT CS1 SCK SDI CS2 6602 F17 Figure 17. An Adaptable RFID Baseband Filter with SPI Control LOWPASS ONLY FILTER 100kHz LOWPASS + 30kHz HIGHPASS FILTER 100kHz LOWPASS + 10kHz HIGHPASS FILTER 0 10 20 30 40 50 60 70 80 90 100110120 (μs) 0 10 20 30 40 50 60 70 80 90 100110120 (μs) 100kHZ LOWPASS TYPICAL TAG SYMBOL SEQUENCE 0 10 20 30 40 50 60 70 80 90 100110120 (μs) 6602 F19c 6602 F19b 6602 F19a (a) (b) (c) Figure 18. Filter Transient Response to a Tag Symbol Sequence 6602fa 25 LTC6602 TYPICAL APPLICATIONS Switching the RBIAS Resistor 3V PARALLEL CONTROL 1 2 V+IN V+A 16 24 +INA –OUTA 18 +OUTA 19 23 –INA 7 +INB 8 4 R3 R2 0.1μF R1 3 20 SOT-363 21 22 14 25 DIODES INC DMN2004DMK CLK1 CLK0 0 0 RBIAS1 0 1 RBIAS2 1 0 RBIAS3 1 1 RBIAS4 RBIAS1 > RBIAS2 OR RBIAS3 fCLK1 fCLK2 fCLK3 fCLK4 CLK1 0.1μF V+D –OUTB 12 LTC6602 +OUTB 13 –INB RBIAS CLKIO VOCM SER MUTE CLKCNTL GAIN0(D0) HPF0(SDO) HPF1(SDI) GAIN1 GND LPF0(SCLK) GND LPF1(CS) 15 17 5 3V 11 10 9 6 VOCM MUTE CLK0 GAIN1 GAIN0 LPF1 LPF0 HPF1 HPF0 DESIGN PROCEDURE 1. CHOOSE fCLK1, fCLK2 AND fCLK3 2. CALCULALTE RBIAS1, RBIAS2 AND RBIAS3 3. CALCULATE R2, R3 AND RBIAS4 RBIAS = 4941 fCLK RBIAS1 IN k fCLK IN MHz R1 = RBIAS1 R2 = RBIAS1 • RBIAS2 RBIAS1 – RBIAS2 R3 = RBIAS1 • RBIAS3 RBIAS1 – RBIAS3 RBIAS4 = R1 • R2 • R3 R1 • (R2 + R3) + R2 • R3 3V SERIAL CONTROL 1 2 24 +INA 1 2 3 CS SCLK VOUT GND V+ SDI LTC2630 8-BIT DAC DAC VOUT 0V 2.5V R1 = 8 R2 6 5 0.1μF 4 R1 4 0.1μF 3 20 21 22 3V 14 LTC6602 fCLK fCLKHI fCLKLO 1.056 • 1013 1.137 • fCLKHI + fCLKLO R2 = 1.056 • 1013 fCLKHI – fCLKLO 25 0.1μF V+D –OUTA 18 +OUTA 19 23 –INA 7 +INB DAC VOUT RANGE, 0V TO 2.5V (USING LTC2630 INTERNAL REFERENCE) 16 V+A V+IN –OUTB 12 LTC6602 +OUTB 13 –INB RBIAS CLKIO VOCM SER MUTE CLKCNTL GAIN0(D0) HPF0(SDO) GAIN1 HPF1(SDI) GND LPF0(SCLK) GND LPF1(CS) 15 17 5 3V 11 10 9 6 VOCM MUTE CS1 SCLK SDI CS2 SDO 6602 TA02 6602fa 26 LTC6602 PACKAGE DESCRIPTION UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 p0.05 4.50 p 0.05 2.45 p 0.05 3.10 p 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 p0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 p 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD R = 0.115 TYP 0.75 p 0.05 PIN 1 NOTCH R = 0.20 TYP OR 0.35 s 45o CHAMFER 23 24 PIN 1 TOP MARK (NOTE 6) 0.40 p 0.10 1 2 2.45 p 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 0.25 p 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6602fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC6602 TYPICAL APPLICATION Direct Conversion Demodulator and Programmable Baseband Filter RF IN 5V 4.7pF 3V 0.1μF 270nH* 0.1μF 10pF 270pF 4 3 2 1 GND GND RF GND 16 5 6 EN VCC 7 V CC 8 VCC 5V 1μF 0.1μF 15 LT5575 270nH* 1 V+IN 10pF 10pF 24 +INA 10pF I INPUT 23 –INA 14 Q INPUT 10pF 1000pF 13 10pF 7 +INB 8 –INB 4 38.3k 270nH* GND LO GND VCC 17 9 10 11 12 10pF 20 270pF 270nH* 0.1μF 10pF 21 22 1000pF 14 MUTE INPUT FROM TRANSMITTER LO IN 3 4.7pF 25 2 16 V+A V+D –OUTA 18 +OUTA 19 I OUTPUT –OUTB 12 LTC6602 +OUTB 13 CLKIO RBIAS VOCM SER MUTE CLKCNTL GAIN0(D0) HPF0(SDO) GAIN1 HPF1(SDI) GND LPF0(SCLK) GND LPF1(CS) Q OUTPUT 15 17 CLOCK INPUT 5 11 10 9 6 VOCM INPUT FROM ADC CS SCLK SDI SPI CONTROL INPUT *COILCRAFT 0603HP-R27X 6602 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1563 4th Order Filter Building Block Lowpass or Bandpass Filter, 256Hz to 256kHz LTC1565-31 7th Order, Fully Differential 650kHz Lowpass Filter No External Components, Low Offset, SO8 Pkg LTC1566-1 7th Order, Fully Differential 2.3MHz Lowpass No External Components, Low Noise, SO8 Pkg LT®1567 Low Noise, Filter Building Block Up to 5MHz Differential Rail-to-Rail Output, MSOP Pkg LT1568 4th Order Filter Building Block, Configurable as 2 Matched Lowpass, Bandpass or 4-Pole Lowpass 200kHz ≤ fc ≤ 5MHz, Low Noise, Rail-to-Rail Input/Output, Programmable Gain, Shutdown Mode LTC2291 Dual 12-Bit, 25 Msps A/D Converter Low Power (150mW), Single 3V Supply; 71.4dB SNR, 90dB SFDR LTC2296 Dual 14-Bit, 25 Msps A/D Converter Low Power (150mW), Single 3V Supply; 74.5dB SNR, 90dB SFDR LT5516 800MHz to 1.5GHz Direct Conversion I/Q Demodulator 21.5dBm IIP3; 12.8dB NF LT5575 800MHz to 2.7GHz Direct Conversoin I/Q Demodulator 28dBm IIP3 at 900MHz; 13.2dBm P1dB; Integrated RF Input Balance Transformer LT66002.5/5/10/15/20 Fully Differential Amplifier and Lowpass Filter Cutoff Frequencies: 2.5MHz/5MHz/10MHz/20MHz Programmable Gain, Adjustable Output CM Voltage, Specified for 3V, 5V, ±5V 6602fa 28 Linear Technology Corporation LT 0908 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008