PHILIPS HEF4046B Phase-locked loop Datasheet

INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4046B
MSI
Phase-locked loop
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
DESCRIPTION
The HEF4046B is a phase-locked loop circuit that consists
of a linear voltage controlled oscillator (VCO) and two
different phase comparators with a common signal input
amplifier and a common comparator input. A 7 V regulator
(zener) diode is provided for supply voltage regulation if
necessary. For functional description see further on in this
data.
Fig.1 Functional diagram.
FAMILY DATA
HEF4046BP(N):
16-lead DIL; plastic
HEF4046BD(F):
16-lead DIL; ceramic (cerdip)
See Family Specifications
(SOT38-1)
IDD LIMITS category MSI
(SOT74)
HEF4046BT(D):
See further on in this data.
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
January 1995
2
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
PINNING
1. Phase comparator pulse output
2. Phase comparator 1 output
3. Comparator input
4. VCO output
5. Inhibit input
6. Capacitor C1 connection A
7. Capacitor C1 connection B
8. VSS
9. VCO input
10. Source-follower output
11. Resistor R1 connection
12. Resistor R2 connection
13. Phase comparator 2 output
14. Signal input
15. Zener diode input for regulated supply.
Fig.2 Pinning diagram.
factor to obtain the maximum lock range. The average
output voltage of the phase comparator is equal to 1⁄2 VDD
when there is no signal or noise at the signal input. The
average voltage to the VCO input is supplied by the
low-pass filter connected to the output of phase
comparator 1. This also causes the VCO to oscillate at the
centre frequency (fo). The frequency capture range (2 fc) is
defined as the frequency range of input signals on which
the PLL will lock if it was initially out of lock. The frequency
lock range (2 fL) is defined as the frequency range of input
signals on which the loop will stay locked if it was initially
in lock. The capture range is smaller or equal to the lock
range.
FUNCTIONAL DESCRIPTION
VCO part
The VCO requires one external capacitor (C1) and one or
two external resistors (R1 or R1 and R2). Resistor R1 and
capacitor C1 determine the frequency range of the VCO.
Resistor R2 enables the VCO to have a frequency off-set
if required. The high input impedance of the VCO simplifies
the design of low-pass filters; it permits the designer a wide
choice of resistor/capacitor ranges. In order not to load the
low-pass filter, a source-follower output of the VCO input
voltage is provided at pin 10. If this pin (SFOUT) is used, a
load resistor (RSF) should be connected from this pin to
VSS; if unused, this pin should be left open. The VCO
output (pin 4) can either be connected directly to the
comparator input (pin 3) or via a frequency divider. A LOW
level at the inhibit input (pin 5) enables the VCO and the
source follower, while a HIGH level turns off both to
minimize stand-by power consumption.
With phase comparator 1, the range of frequencies over
which the PLL can acquire lock (capture range) depends
on the low-pass filter characteristics and this range can be
made as large as the lock range. Phase comparator 1
enables the PLL system to remain in lock in spite of high
amounts of noise in the input signal. A typical behaviour of
this type of phase comparator is that it may lock onto input
frequencies that are close to harmonics of the VCO centre
frequency. Another typical behaviour is, that the phase
angle between the signal and comparator input varies
between 0° and 180° and is 90° at the centre frequency.
Figure 3 shows the typical phase-to-output response
characteristic.
Phase comparators
The phase-comparator signal input (pin 14) can be
direct-coupled, provided the signal swing is between the
standard HE4000B family input logic levels. The signal
must be capacitively coupled to the self-biasing amplifier
at the signal input in case of smaller swings. Phase
comparator 1 is an EXCLUSIVE-OR network. The signal
and comparator input frequencies must have a 50% duty
January 1995
3
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
(1) Average output voltage.
Fig.3
Signal-to-comparator inputs phase
difference for comparator 1.
Figure 4 shows the typical waveforms for a PLL employing
phase comparator 1 in locked condition of fo.
Fig.4 Typical waveforms for phase-locked loop employing phase comparator 1 in locked condition of fo.
January 1995
4
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
comparator inputs are equal in both phase and frequency.
At this stable point, both p and n-type drivers remain OFF
and thus the phase comparator output becomes an open
circuit and keeps the voltage at the capacitor of the
low-pass filter constant.
Phase comparator 2 is an edge-controlled digital memory
network. It consists of four flip-flops, control gating and a
3-state output circuit comprising p and n-type drivers
having a common output node. When the p-type or n-type
drivers are ON, they pull the output up to VDD or down to
VSS respectively. This type of phase comparator only acts
on the positive-going edges of the signals at SIGNIN and
COMPIN. Therefore, the duty factors of these signals are
not of importance.
Moreover, the signal at the phase comparator pulse output
(PCPOUT) is a HIGH level which can be used for indicating
a locked condition. Thus, for phase comparator 2 no phase
difference exists between the signal and comparator
inputs over the full VCO frequency range. Moreover, the
power dissipation due to the low-pass filter is reduced
when this type of phase comparator is used because both
p and n-type output drivers are OFF for most of the signal
input cycle. It should be noted that the PLL lock range for
this type of phase comparator is equal to the capture
range, independent of the low-pass filter. With no signal
present at the signal input, the VCO is adjusted to its
lowest frequency for phase comparator 2 . Figure 5 shows
typical waveforms for a PLL employing this type of phase
comparator in locked condition.
If the signal input frequency is higher than the comparator
input frequency, the p-type output driver is maintained ON
most of the time, and both the n and p-type drivers are
OFF (3-state) the remainder of the time. If the signal input
frequency is lower than the comparator input frequency,
the n-type output driver is maintained ON most of the time,
and both the n and p-type drivers are OFF the remainder
of the time. If the signal input and comparator input
frequencies are equal, but the signal input lags the
comparator input in phase, the n-type output driver is
maintained ON for a time corresponding to the phase
difference. If the comparator input lags the signal input in
phase, the p-type output driver is maintained ON for a time
corresponding to the phase difference. Subsequently, the
voltage at the capacitor of the low-pass filter connected to
this phase comparator is adjusted until the signal and
Fig.5 Typical waveforms for phase-locked loop employing phase comparator 2 in locked condition.
January 1995
5
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Figure 6 shows the state diagram for phase comparator 2.
Each circle represents a state of the comparator. The
number at the top, inside each circle, represents the state
of the comparator, while the logic state of the signal and
comparator inputs are represented by a ‘0’ for a logic LOW
or a ‘1’ for a logic HIGH, and they are shown in the left and
right bottom of each circle.
The state diagram assumes, that only one transition on
either the signal input or comparator input occurs at any
instant. States 3, 5, 9 and 11 represent the condition at the
output when the p-type driver is ON, while states 2, 4, 10
and 12 determine the condition when the n-type driver is
ON. States 1, 6, 7 and 8 represent the condition when the
output is in its high impedance OFF state; i.e. both p and
n-type drivers are OFF, and the PCPOUT output is HIGH.
The condition at output PCPOUT for all other states is LOW.
The transitions from one to another result from either a
logic change at the signal input (S) or the comparator input
(C). A positive-going and a negative-going transition are
shown by an arrow pointing up or down respectively.
S ↑: 0 to 1 transition at the signal input.
C ↓ : 1 to 0 transition at the comparator input.
Fig.6 State diagram for comparator 2.
January 1995
6
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
DC CHARACTERISTICS
VSS = 0 V
Tamb (°C)
VDD
V
Supply current
−40
SYMBOL
5
+ 25
+ 85
TYP.
MAX.
TYP.
MAX.
−
−
20
−
TYP.
−
MAX.
−
µA
−
−
300
−
−
−
µA
15
−
−
750
−
−
−
µA
Quiescent device
5
−
20
−
20
−
150
µA
current (note 2)
10
(note 1)
10
ID
IDD
15
−
40
−
40
−
300
µA
−
80
−
80
−
600
µA
Notes
1. Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 open.
2. Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 at VDD; input current pin 14 not included.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL MIN.
TYP.
MAX.
Phase comparators
Operating supply voltage
Input resistance
at SIGNIN
A.C. coupled input
VDD
3
15
5
V
750
kΩ
10 RIN
220
kΩ
15
140
kΩ
5
150
mV
sensitivity
10 VIN
150
mV
at SIGNIN
15
200
mV
at self-bias
operating point
peak-to-peak values;
R1 = 10 kΩ; R2 = ∞;
C1 = 100 pF; independent
of the lock range
D.C. coupled input sensitivity
at SIGNIN; COMPIN
LOW level
5
10 VIL
15
5
HIGH level
10 VIH
15
Input current
at SIGNIN
V
3,0
V
4,0
V
3,5
V
7,0
V
11,0
full temperature range
V
7
µA
10 + IIN
30
µA
15
70
µA
5
3
µA
10 −IIN
18
µA
15
45
µA
5
January 1995
1,5
7
SIGNIN at VDD
SIGNIN at VSS
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
VDD
V
SYMBOL MIN.
TYP.
MAX.
VCO
Operating supply
VDD
voltage
Power dissipation
Maximum operating
frequency
3
15
V
as fixed oscillator only
5
15
V
phase-locked loop operation
150
µW
10 P
2500
µW
15
9000
µW
5
5
0,5
1,0
MHz
10 fmax
1,0
2,0
MHz
15
1,3
2,7
MHz
Temperature/
5
0,220,30
%/°C
frequency
10
0,040,05
%/°C
stability
15
0,010,05
%/°C
5
00,22
%/°C
10
00,04
%/°C
15
Linearity
Duty factor at
VCOOUT
no frequency offset
(fmin = 0);
see also note 1
00,01
%/°C
5
0,50
%
R1 > 10 kΩ
see Fig.13
10
0,25
%
R1 > 400 kΩ
and Figs 14
15
0,25
%
R1 = 1 MΩ
15 and 16
5
50
%
50
%
10 δ
50
5
106
MΩ
10 RIN
106
MΩ
15
106
MΩ
5
1,7
V
VCOIN minus
10
2,0
V
SFOUT
15
2,1
V
5
1,5
V
10
1,7
V
VCOIN
VCOIN at VDD;
R1 = 10 kΩ; R2 = ∞;
C1 = 50 pF
with frequency offset
(fmin > 0);
see also note 1
15
Input resistance at
fo = 10 kHz; R1 = 1 MΩ;
R2 = ∞; VCOIN at 1⁄2 VDD;
see also Figs 10 and 11
%
Source follower
Offset voltage
Linearity
15
1,8
V
5
0,3
%
10
1,0
%
15
1,3
%
RSF = 10 kΩ;
VCOIN at 1⁄2 VDD
RSF = 50 kΩ;
VCOIN at 1⁄2 VDD
RSF > 50 kΩ;
see Fig.13
Zener diode
Zener voltage
VZ
7,3
V
IZ = 50 µA
Dynamic resistance
RZ
25
Ω
IZ = 1 mA
Notes
1. Over the recommended component range.
January 1995
8
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
DESIGN INFORMATION
CHARACTERISTIC
USING PHASE COMPARATOR 1
USING PHASE COMPARATOR 2
No signal on SIGNIN
VCO in PLL system adjusts
to centre frequency (fo)
VCO in PLL system adjusts to min.
frequency (fmin)
Phase angle between
SIGNIN and COMPIN
90° at centre frequency (fo),
approaching 0° and 180° at
ends of lock range (2 fL)
always 0° in lock
(positive-going edges)
Locks on harmonics of
centre frequency
yes
no
Signal input noise
rejection
high
low
Lock frequency
range (2 fL)
the frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2 fL = full VCO frequency range = fmax − fmin
Capture frequency
range (2 fC)
the frequency range of the input signal on which the loop will lock if it was initially
out of lock
depends on low-pass
filter characteristics; fC < fL
Centre frequency (fo)
fC = fL
the frequency of the VCO when VCOIN at 1⁄2VDD
VCO component selection
Recommended range for R1 and R2: 10 kΩ to 1 MΩ; for C1: 50 pF to any practical value.
1. VCO without frequency offset (R2 = ∞).
a) Given fo: use fo with Fig.7 to determine R1 and C1.
b) Given fmax: calculate fo from fo = 1⁄2 fmax; use fo with Fig.7 to determine R1 and C1.
2. VCO with frequency offset.
a) Given fo and fL : calculate fmin from the equation fmin = fo − fL; use fmin with Fig.8 to determine R2 and C1; calculate
f max
f max
fo + fL
f max
----------- from the equation ---------- = -------------- with Fig. 9 to determine the ratio R2/R1 to obtain R1.
- ; use ---------f min
f min
f min
fo – fL
b) Given fmin and fmax: use fmin with Fig.8 to determine R2 and C1; calculate
f max
f max
----------- ; use ---------f min
f min
with Fig.9 to determine R2/R1 to obtain R1.
January 1995
9
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.7
Typical centre frequency as a function of capacitor C1; Tamb = 25 °C; VCOIN at 1⁄2 VDD; INH at VSS; R2 = ∞.
January 1995
10
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.8 Typical frequency offset as a function of capacitor C1; Tamb = 25 °C; VCOIN at VSS; INH at VSS; R1 = ∞.
January 1995
11
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.9 Typical ratio of R2/R1 as a function of the ratio fmax/fmin.
January 1995
12
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.10 Power dissipation as a function of R1;
R2 = ∞; VCOIN at 1⁄2 VDD; CL = 50 pF.
Fig.11 Power dissipation as a function of R2;
R1 = ∞; VCOIN at VSS (0 V);
CL = 50 pF.
January 1995
13
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.12 Power dissipation of source follower as a
function of RSF; VCOIN at 1⁄2 VDD; R1 = ∞ ;
R2 = ∞ .
For VCO linearity:
f1 + f2
′
f o = -------------2
′
f o – fo
- × 100%
lin. = --------------′
fo
Figure 13 and the above
formula also apply to
source follower linearity:
substitute VSF OUT for f.
∆V = 0,3 V at VDD = 5 V
∆V = 2,5 V at VDD = 10 V
∆V = 5 V at VDD = 15 V
Fig.13 Definition of linearity (see AC characteristics).
January 1995
14
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.14 VCO frequency linearity as a function of R1;
R2 = ∞; VDD = 5 V.
Fig.15 VCO frequency linearity as a function of R1;
R2 = ∞; VDD = 10 V.
Fig.16 VCO frequency linearity as a function of R1;
R2 = ∞; VDD = 15 V.
January 1995
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