HD74LS165A Parallel-Load 8-bit Shift Register REJ03D0449–0300 Rev.3.00 Jul.15.2005 The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift / load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is accomplished through a 2-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking and holding either clock input low with the shift / load input high enables the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. Parallel loading is inhibited as long as the shift / load input is high. Data at the parallel inputs are loaded directly into the register on a high-to-low transition of the shift / load input independently of the levels of the clock, clock inhibit, or serial inputs. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS165AP DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74LS165AFPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Pin Arrangement Shift/ Load 1 16 VCC 15 Clock Inhibit Clock 2 Shift/Load Clock CK Inhibit E 3 E D 14 D F 4 F C 13 C G 5 G B 12 B H 6 H A 11 A Output QH 7 QH 10 Serial Input GND 8 9 Output QH Parallel Inputs Serial QH Input (Top view) Rev.3.00, Jul.15.2005, page 1 of 7 Parallel Inputs HD74LS165A Function Table Inputs Shift / Load Clock Inhibit Clock Serial L H H H H X L L L H X ↑ ↑ ↑ X X X H L X Internal outputs Parallel A…H a…h X X X X QA a QA0 H L QA0 Output QH QB b QB0 QAn QAn QB0 h QH0 QGn QGn QH0 Notes: 1. H; high level, L; low level, X; irrelevant 2. ↑; transition from low to high level 3. a to h; the level of steady-state input at inputs A to H respectively 4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were established. 5. QAn to QGn; the level of QA to QG, respectively, before the most recent ↓ transition of the clock. Block Diagram Serial Input A B C D E F G H PR PR PR PR PR PR PR PR S QA S QB S QC S QD S QE S QF S QG S QH CK CK CK CK CK CK CK CK R QA R QB R QC R QD R QE R QF R QG R QH Clear Clear Clear Clear Clear Clear Clear Clear QH QH Shift / Load Clock Clock Inhibit Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Item VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.3.00, Jul.15.2005, page 2 of 7 HD74LS165A Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Operating temperature Topr –20 25 75 °C Clock frequency ƒclock 0 — 25 MHz Clock pulse width tw (clock) 25 — — ns Load pulse width tw (load) 15 — — ns Clock enable setup time tsu 30 — — ns Parallel input setup time tsu 10 — — ns Serial input setup time tsu 20 — — ns Shift setup time tsu 45 — — ns Hold time th 0 — — ns Supply voltage Output current Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V — — — — — — — — –20 — — — — — — — — — — — 21 — 0.4 0.5 0.3 0.1 60 20 –1.2 –0.4 –100 36 –1.5 Output voltage VOL Shift / Load Other inputs Shift / Load High level input current Other inputs Low level input Shift / Load current Other inputs Short-circuit output current Supply current** Input clamp voltage Input current II IIH IIL IOS ICC VIK Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, IOL = 8 mA VIL = 0.8 V V mA mA µA µA mA mA mA mA V VCC = 5.25 V, VI = 7 V VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Note: * VCC = 5 V, Ta = 25°C **. With the outputs open, clock inhibit and clock at 4.5 V, and a clock pulse applied to the shift / load, ICC is measured with the parallel inputs at 4.5 V, than with the parallel inputs grounded. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Rev.3.00, Jul.15.2005, page 3 of 7 Inputs Outputs Load Any Clock Any H QH H QH min. 25 — typ. 35 21 max. — 35 Unit MHz ns — — — — 26 14 16 13 35 25 25 25 ns ns ns ns — — 24 19 30 30 ns ns — 17 25 ns Condition CL = 15 pF, RL = 2 kΩ HD74LS165A Testing Method Test Circuit 4.5V VCC Serial Input A See Testing Table P.G. Zout = 50Ω Load circuit 1 Output Shift/Load Input B C RL QH CL D E F G H QH Same as Load Circuit 1. Clock Clock Inhibit Notes: 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveforms 1 3V Shift/ Load 1.3V 0V tsu Serial Input 3V 1.3V 1.3V tsu Clock Inhibit Notes: 0V tsu 1.3V 3V 1.3V 0V A. The eight data inputs and the clock-inhibit input are low. Results are monitored at output QH at Tn + 7. B. The input pulse generators have the following characteristics: PRR < 1 MHz, duty cycle < 50%, Zout ≈ 50 Ω, tTLH ≤ 15 ns, tTHL ≤ 6 ns. Rev.3.00, Jul.15.2005, page 4 of 7 HD74LS165A Waveforms 2 3V Clock Inhibit Input (Disable while clock is high) 1.3V 0V tsu 3V Clock Input 1.3V tsu 1.3V 1.3V 0V tw (clock) 3V F and H 1.3V Inputs (See Notes A and B) 1.3V 1.3V 1.3V 0V tsu tw (load) tw (load) 3V Shift/ Load 1.3V 1.3V 1.3V 1.3V 0V tPHL tPLH tPHL tPLH tPHL tPLH VOH Output QH 1.3V 1.3V 1.3V 1.3V 1.3V VOL tPLH tPHL tPLH tPHL tPLH tPHL VOH Output QH 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V VOL Notes: A. The remaining six data inputs and the serial input are low. B. Prior to test, high-level data is loaded into H input. C. The input pulse Generators have the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, Zout ≈ 50 Ω, tTLH ≤ 15 ns, tTHL ≤ 6 ns. Rev.3.00, Jul.15.2005, page 5 of 7 HD74LS165A Typical Shift, Load and Inhibit Sequences Clock Clock Inhibit Serial Input Shift / Load H L A B H L C D Data H L E F G H H H Output QH H H L H L H L H Output QH L L H L H L H L Inhibit Load Rev.3.00, Jul.15.2005, page 6 of 7 Serial Shift HD74LS165A Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jul.15.2005, page 7 of 7 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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