TI1 INA827 Wide supply range, rail-to-rail output instrumentation amplifier with a minimum gain of 5 Datasheet

INA827
www.ti.com
SBOS631 – JUNE 2012
Wide Supply Range, Rail-to-Rail Output
Instrumentation Amplifier with a Minimum Gain of 5
Check for Samples: INA827
FEATURES
DESCRIPTION
•
The INA827 is a low-cost instrumentation amplifier
(INA) that offers extremely low power consumption
and operates over a very wide single- or dual-supply
range. The device is optimized for the lowest possible
gain drift of only 1 ppm per degree Celsius in G = 5,
which requires no external resistor. However, a single
external resistor sets any gain from 5 to 1000.
1
23
•
•
•
•
•
•
•
•
•
Eliminates Errors from External Resistors at
Gain of 5
Common-Mode Range Goes Below
Negative Supply
Input Protection: Up to ±40 V
Rail-to-Rail Output
Outstanding Precision:
– Common-Mode Rejection: 88 dB, min
– Low Offset Voltage: 150 µV, max
– Low Drift: 2.5 µV/°C, max
– Low Gain Drift: 1 ppm/°C, max (G = 5 V/V)
– Power-Supply Rejection:
100 dB, min (G = 5)
– Noise: 17 nV/√Hz, G = 1000 V/V
High Bandwidth:
– G = 5: 600 kHz
– G = 100: 150 kHz
Supply Current: 200 µA, typ
Supply Range:
– Single Supply: +2.7 V to +36 V
– Dual Supply: ±1.35 V to ±18 V
Specified Temperature Range:
–40°C to +125°C
Package: MSOP-8
The INA827 is optimized to provide excellent
common-mode rejection ratio (CMRR) of over 88 dB
(G = 5) over frequencies up to 5 kHz. In G = 5,
CMRR exceeds 88 dB across the full input commonmode range from the negative supply all the way up
to 1 V of the positive supply. Using a rail-to-rail
output, the INA827 is well-suited for low-voltage
operation from a 2.7 V single-supply as well as dual
supplies up to ±18 V. Additional circuitry protects the
inputs against overvoltage of up to ±40 V beyond the
power supplies by limiting the input currents to a save
level.
The INA827 is available in a small MSOP-8 package
and is specified for the –40°C to +125°C temperature
range. For a similar instrumentation amplifier with a
gain range of 1 V/V to 1000 V/V, see the INA826.
V+
0.1 mF
8
(1)
RS
-IN
1
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-)
APPLICATIONS
•
•
•
•
•
•
Industrial Process Controls
Multichannel Systems
Power Automation
Weigh Scales
Medical Instrumentation
Data Acquisition
2
8 kW
RG
G=5+
7
A3
8 kW
+
3
+IN
Load VO
50 kW
(1)
RS
4
80 kW
RG
50 kW
A2
6
REF
Device
5
0.1 mF
V-
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PhotoMOS is a registered trademark of Panasonic Electric Works Europe AG.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
INA827
SBOS631 – JUNE 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
INA827
MSOP-8
DGK
IPSI
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
INA827AIDGK
Tape and Reel, 250
INA827AIDGKR
Tape and Reel, 3000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Voltage
VALUE
UNIT
Supply
±20
V
Input
±40
V
REF input
±20
Output short-circuit (2)
Temperature range
Electrostatic discharge (ESD) rating
(1)
(2)
2
V
Continuous
Operating, TA
–55 to +150
°C
Storage, Tstg
–65 to +150
°C
Junction, TJ
+175
°C
Human body model (HBM)
2000
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Short-circuit to VS / 2.
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ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
INA827
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RTI, VOS = VOSI + (VOSO / G)
40
150
µV
TA = –40°C to +125°C
0.5
2.5
µV/°C
RTI, VOS = VOSI + (VOSO / G)
500
2000
5
30
INPUT
VOSI
Input stage
Offset voltage (1)
VOSO
PSRR
ZIN
Output stage
Power-supply rejection ratio
Impedance
TA = –40°C to +125°C
G = 5, VS = ±1.35 V to ±18 V
100
120
dB
G = 10, VS = ±1.35 V to ±18 V
106
126
dB
G > 100, VS = ±1.35 V to ±18 V
120
140
dB
2 || 1
GΩ || pF
10 || 5
GΩ || pF
Differential
Common-mode
RFI filter, –3-dB frequency
25
VS = ±1.35 V to ±18 V, VO = 0 V
Operating input range (2)
VCM
Input overvoltage range
MHz
(V–) – 0.2
(V+) – 0.9
V
VS = ±1.35 V to ±18 V, VO = 0 V, TA = +125°C
(V–) – 0.05
(V+) – 0.8
V
VS = ±1.35 V to ±18 V, VO = 0 V, TA = –40°C
(V–) – 0.3
(V+) – 0.95
V
TA = –40°C to +125°C
(V+) – 40
(V–) + 40
G = 5, VCM = V– to (V+) – 1 V
DC to 60 Hz
CMRR
µV
µV/°C
Common-mode rejection ratio
At 5 kHz
V
88
100
dB
G = 10, VCM = V– to (V+) – 1 V
94
106
dB
G > 100, VCM = V– to (V+) – 1 V
110
126
dB
G = 5, VCM = V– to (V+) – 1 V
88
dB
G = 10, VCM = V– to (V+) – 1 V
94
dB
G > 100, VCM = V– to (V+) – 1 V
104
dB
BIAS CURRENT
IB
IOS
35
Input bias current
TA = –40°C to +125°C
–5
Input offset current
0.7
TA = –40°C to +125°C
50
nA
95
nA
5
nA
10
nA
NOISE VOLTAGE (3)
eNI
eNO
RTI
iN
(1)
(2)
Voltage noise
Input
f = 1 kHz, G = 1000, RS = 0 Ω
17
18
nV/√Hz
Output
f = 1 kHz, G = 5, RS = 0 Ω
250
285
nV/√Hz
G = 5, fB = 0.1 Hz to 10 Hz, RS = 0 Ω
1.4
G = 1000, fB = 0.1 Hz to 10 Hz, RS = 0 Ω
0.5
µVPP
f = 1 kHz
120
fA/√Hz
Referred-to-input
Noise current
fB = 0.1 Hz to 10 Hz
µVPP
5
pAPP
Total offset, referred-to-input (RTI): VOS = VOSI + (VOSO / G).
Input voltage range of the INA827 input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage. See the Typical Characteristics for more information.
(3)
(eNI)2 +
eNO
Total RTI voltage noise =
G
2
.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
INA827
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GAIN
80 kW
G
Gain equation
G
Range of gain
GE
5+
V/V
RG
5
G = 5, VO = ±10 V
Gain error
Gain versus temperature
(4)
Gain nonlinearity
1000
V/V
±0.005
±0.035
G = 10 to 1000, VO = ±10 V
±0.1
±0.4
G = 5, TA = –40°C to +125°C
±0.1
±1
ppm/°C
G > 5, TA = –40°C to +125°C
8
25
ppm/°C
G = 5 to 100, VO = –10 V to +10 V, RL = 10 kΩ
2
5
ppm
20
50
ppm
G = 1000, VO = –10 V to +10 V, RL = 10 kΩ
%
%
OUTPUT
Voltage swing
RL = 10 kΩ
(V–) + 0.1
Load capacitance stability
Short-circuit current
(V+) – 0.15
V
1000
pF
Continuous to common
±16
mA
G=5
600
kHz
G = 10
530
kHz
G = 100
150
kHz
G = 1000
15
kHz
G = 5, VO = ±14.5 V
1.5
V/µs
G = 100, VO = ±14.5 V
1.5
V/µs
G = 5, VSTEP = 10 V
10
µs
G = 100, VSTEP = 10 V
12
µs
G = 1000, VSTEP = 10 V
95
µs
G = 1, VSTEP = 10 V
11
µs
G = 100, VSTEP = 10 V
18
µs
G = 1000, VSTEP = 10 V
118
µs
FREQUENCY RESPONSE
BW
SR
Bandwidth, –3 dB
Slew rate
To 0.01%
tS
Settling time
To 0.001%
REFERENCE INPUT
RIN
Input impedance
60
Voltage range
V–
Gain to output
kΩ
V+
1
Reference gain error
V
V/V
0.01
%
POWER SUPPLY
VS
IQ
Power-supply voltage
Quiescent current
Single
Dual
+2.7
+36
±1.35
±18
V
V
VIN = 0 V
200
250
µA
TA = –40°C to +125°C
250
320
µA
°C
TEMPERATURE RANGE
θJA
(4)
4
Specified
–40
+125
Operating
–50
+150
Thermal resistance
215
°C
°C/W
The values specified for G > 5 do not include the effects of the external gain-setting resistor, RG.
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THERMAL INFORMATION
INA827
THERMAL METRIC (1)
DGK (MSOP)
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
215.4
θJCtop
Junction-to-case (top) thermal resistance
66.3
θJB
Junction-to-board thermal resistance
97.8
ψJT
Junction-to-top characterization parameter
10.5
ψJB
Junction-to-board characterization parameter
96.1
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
PIN CONFIGURATION
DGK PACKAGE
MSOP-8
(TOP VIEW)
-IN
1
8
+VS
RG
2
7
VOUT
RG
3
6
REF
+IN
4
5
-VS
PIN DESCRIPTIONS
NAME
NO.
–IN
1
Negative input
DESCRIPTION
+IN
4
Positive input
REF
6
Reference input. This pin must be driven by low impedance.
RG
2, 3
VOUT
7
Output
–VS
5
Negative supply
+VS
8
Positive supply
Gain setting pin. Place a gain resistor between pin 2 and pin 3.
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TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
TYPICAL DISTRIBUTION OF
INPUT OFFSET VOLTAGE
250
TYPICAL DISTRIBUTION OF
INPUT OFFSET VOLTAGE DRIFT
30
SD: 40.1 µV
MEAN: −7.6 µV
25
200
SD: 0.51 µV/°C
MEAN: 0.08 µV/°C
20
Units
Units
150
15
100
10
50
5
VOSI (µV)
3
2
1
0
−1
−2
−3
150
130
90
110
70
50
30
10
−10
−30
−50
−70
−90
−110
−130
0
−150
0
VOSI Drift (µV/°C )
G001
G002
Figure 1.
Figure 2.
TYPICAL DISTRIBUTION OF
OUTPUT OFFSET VOLTAGE
TYPICAL DISTRIBUTION OF
OUTPUT OFFSET VOLTAGE DRIFT
200
16
160
SD: 5.3 µV/°C
MEAN: −7.7 µV/°C
12
Units
Units
120
8
80
4
40
VOSO (µV)
Figure 3.
6
VOSO Drift (µV/°C )
25
20
15
10
5
0
−5
−10
−15
−25
G002
−20
0
−2000
−1800
−1600
−1400
−1200
−1000
−800
−600
−400
−200
0
200
400
600
800
1000
1200
1400
1600
1800
2000
0
G004
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
TYPICAL DISTRIBUTION OF
INPUT BIAS CURRENT
TYPICAL DISTRIBUTION OF
INPUT OFFSET CURRENT
700
500
SD: 0.59 nA
MEAN: 0.01 nA
600
400
300
400
Units
Units
500
300
200
200
100
100
IB (nA)
IOS (nA)
G005
4
3
3.5
2
2.5
1
1.5
0
0.5
−1
−0.5
−2
−1.5
−3
−2.5
−4
−3.5
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
0
20
0
G006
Figure 5.
Figure 6.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Single Supply, VS = +2.7 V, G = 5)
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Single Supply, VS = +2.7 V, G = 100)
2
Common−Mode Voltage (V)
Common−Mode Voltage (V)
2
1.5
1
Vref = 0V
Vref = 1.35V
0.5
0
−0.5
−0.5
0
0.5
1
1.5
Output Voltage (V)
2
2.5
1.5
1
0.5
0
−0.5
−0.5
3
Vref = 0V
Vref = 1.35V
0
G007
0.5
1
1.5
Output Voltage (V)
2
2.5
3
G008
Figure 7.
Figure 8.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Single Supply, VS = +5 V, G = 5)
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Single Supply, VS = +5 V, G = 100)
4.5
Common−Mode Voltage (V)
Common−Mode Voltage (V)
4.5
3.5
2.5
Vref = 0V
Vref = 2.5V
1.5
0.5
−0.5
−0.5
0.5
1.5
2.5
3.5
Output Voltage (V)
4.5
5.5
3.5
2.5
Vref = 0V
Vref = 2.5V
1.5
0.5
−0.5
−0.5
G009
Figure 9.
0.5
1.5
2.5
3.5
Output Voltage (V)
4.5
5.5
G009
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Dual Supply, VS = ±5 V)
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Dual Supply, VS = ±15 V, ±12 V, G = 5)
16
4
2
Gain = 5
Gain = 100
0
−2
−4
8
Vs = +/− 12V
Vs = +/− 15V
4
0
−4
−8
−12
−6
−4
−2
0
2
Output Voltage (V)
4
−16
−16
6
−12
−8
G011
−4
0
4
Output Voltage (V)
8
12
16
G012
Figure 12.
INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE
(Dual Supply, VS = ±15 V, ±12 V, G = 100)
INPUT OVERVOLTAGE vs INPUT CURRENT
(G = 1, VS = ±15 V)
16
8
16
12
6
12
4
8
2
4
0
0
8
Input Current (mA)
Common−Mode Voltage (V)
Figure 11.
Vs = +/− 12V
Vs = +/− 15V
4
0
−4
−4
−2
IIN
VOUT
−4
−8
Output Voltage (V)
−6
12
Common−Mode Voltage (V)
Common−Mode Voltage (V)
6
−8
−12
−6
−12
−8
−30
−12
−8
−4
0
4
Output Voltage (V)
8
12
16
CMRR vs FREQUENCY
(RTI, 1-kΩ Source Imbalance)
70
120
60
100
50
80
60
G=5
G = 10
G = 100
G = 1000
10
100
30
G=5
G = 10
G = 100
G = 1000
10
10k
100k
0
10
G016
Figure 15.
8
−16
40
20
1k
Frequency (Hz)
30
G014
CMRR vs FREQUENCY
(RTI)
140
0
20
Figure 14.
80
20
−10
0
10
Input Voltage (V)
Figure 13.
160
40
−20
G013
CMRR (dB)
CMRR (dB)
−16
−16
100
1k
Frequency (Hz)
10k
100k
G017
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
NEGATIVE PSRR vs FREQUENCY (RTI)
180
160
160
140
140
120
120
PSRR (dB)
PSRR (dB)
POSITIVE PSRR vs FREQUENCY (RTI)
180
100
80
60
20
10
100
G=5
G = 10
G = 100
G = 1000
40
20
1k
Frequency (Hz)
10k
0
100k
10
100
1k
Frequency (Hz)
G018
10k
100k
G019
Figure 17.
Figure 18.
GAIN vs FREQUENCY
VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY (RTI)
70
10k
50
40
Noise Density (nV/ Hz)
G=5
G = 10
G = 100
G = 1000
60
Gain (dB)
80
60
G=5
G = 10
G = 100
G = 1000
40
0
100
30
20
10
0
−10
G=5
G = 10
G = 100
G = 1000
1k
100
10
−20
−30
100
1k
10k
100k
Frequency (Hz)
1M
1
100m
10M
G022
1
10
100
1k
Frequency (Hz)
10k
100k
G023
Figure 19.
Figure 20.
CURRENT NOISE SPECTRAL DENSITY
vs FREQUENCY (RTI)
0.1-Hz TO 10-Hz RTI VOLTAGE NOISE (G = 5)
400
Noise (1 mV/div)
Current Noise Density (fA/ Hz)
500
300
200
100
0
1
10
100
Frequency (Hz)
1k
10k
Time (1 s/div)
G025
G024
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
0.1-Hz TO 10-Hz RTI CURRENT NOISE
Noise (2 pA/div)
Noise (500 nV/div)
0.1-Hz TO 10-Hz RTI VOLTAGE NOISE (G = 1000)
Time (1 s/div)
Time (1 s/div)
G026
G027
Figure 23.
Figure 24.
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
(VS = +2.7 V)
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
(VS = ±15 V)
100
−45°C
25°C
85°C
125°C
120
100
80
60
40
20
0
−45°C
25°C
85°C
125°C
90
Input Bias Current (nA)
Input Bias Current (nA)
140
80
70
60
50
40
30
20
10
−0.5
0.0
0.5
1.0
1.5
Common−Mode Voltage (V)
2.0
0
−18
2.5
−14
−10
G028
Figure 25.
INPUT BIAS CURRENT vs TEMPERATURE
18
G029
INPUT OFFSET CURRENT vs TEMPERATURE
2.5
Unit 1
Unit 2
Unit 3
2
Input Offset Current (nA)
Input Bias Current (nA)
14
Figure 26.
100
80
−6
−2
2
6
10
Common−Mode Voltage (V)
60
40
20
Unit 1
Unit 2
1.5
1
0.5
0
−0.5
0
−50
−25
0
25
50
75
Temperature (°C)
100
125
150
−1
−50
G030
Figure 27.
10
−25
0
25
50
75
Temperature (°C)
100
125
150
G031
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
GAIN ERROR vs TEMPERATURE
(G = 5)
SUPPLY CURRENT vs TEMPERATURE
50
300
Gain Error (ppm)
30
Quiescent Current (µA)
Unit 1
Unit 2
Unit 3
40
20
10
0
−10
−20
−30
Unit 1
Unit 2
Unit 3
250
200
150
−40
−50
−50
−25
0
25
50
75
Temperature (°C)
100
125
100
−50
150
−25
0
25
50
75
Temperature (°C)
G032
Figure 29.
8
8
6
6
4
2
0
−2
−4
−6
G034
4
2
0
−2
−4
−6
−8
−8
−8
−6
−4
−2
0
2
4
Output Voltage (V)
6
8
−10
−10
10
−8
−6
−4
G035
Figure 31.
8
40
6
30
Non−Linearity (ppm)
50
4
2
0
−2
−4
G036
0
−10
−20
−30
−40
−2
0
2
4
Output Voltage (V)
10
10
−8
−4
8
20
−6
−6
6
GAIN NONLINEARITY (G = 1000)
10
−8
−2
0
2
4
Output Voltage (V)
Figure 32.
GAIN NONLINEARITY (G = 100)
Non−Linearity (ppm)
150
GAIN NONLINEARITY (G = 10)
10
Non−Linearity (ppm)
Non−Linearity (ppm)
GAIN NONLINEARITY (G = 5)
−10
−10
125
Figure 30.
10
−10
−10
100
6
8
10
−50
−10
G037
Figure 33.
−8
−6
−4
−2
0
2
4
Output Voltage (V)
6
8
10
G038
Figure 34.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
OFFSET VOLTAGE vs
NEGATIVE COMMON-MODE VOLTAGE
(VS = ±15 V)
OFFSET VOLTAGE vs
POSITIVE COMMON-MODE VOLTAGE
(VS = ±15 V)
80
100
VS = ±15 V
−45°C
25°C
85°C
125°C
40
0
−20
−40
0
−20
−40
−15
Common−Mode Voltage (V)
−100
13.5
−14.5
14
Common−Mode Voltage (V)
G057
14.5
G058
Figure 35.
Figure 36.
OFFSET VOLTAGE vs
NEGATIVE COMMON-MODE VOLTAGE
(VS = +2.7 V)
OFFSET VOLTAGE vs
POSITIVE COMMON-MODE VOLTAGE
(VS = +2.7 V)
500
500
VS = +2.7 V
−45°C
25°C
85°C
125°C
300
200
0
−100
−200
200
100
0
−100
−200
−300
−300
−400
−400
1
1.5
Common−Mode Voltage (V)
−45°C
25°C
85°C
125°C
300
100
−500
0.5
VS = +2.7 V
400
Offset Voltage (µV)
400
Offset Voltage (µV)
20
−80
−80
−15.5
−500
−0.5
2
−0.4
−0.3 −0.2 −0.1
0
0.1
Common−Mode Voltage (V)
G059
0.2
Figure 38.
POSITIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (VS = ±15 V)
NEGATIVE OUTPUT VOLTAGE SWING
vs OUTPUT CURRENT (VS = ±15 V)
15
0.3
G060
Figure 37.
−14
−45°C
25°C
85°C
125°C
14.8
14.7
−14.2
14.6
14.5
14.4
14.3
−14.3
−14.4
−14.5
−14.6
−14.7
14.2
−14.8
14.1
−14.9
0
1
2
3
4
5
6
7
Output Current (mA)
8
9
−45°C
25°C
85°C
125°C
−14.1
Output Voltage (V)
14.9
Output Voltage (V)
40
−60
−60
10
−15
0
G039
Figure 39.
12
−45°C
25°C
85°C
125°C
60
20
14
VS = ±15 V
80
Offset Voltage (µV)
Offset Voltage (µV)
60
1
2
3
4
5
6
7
Output Current (mA)
8
9
10
G040
Figure 40.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
SETTLING TIME vs STEP SIZE
(VS = ±15-V)
LARGE-SIGNAL FREQUENCY RESPONSE
35
20
Vs = ±15V
Vs = ±2.5V
30
Settle to 0.01%
Settle to 0.001%
18
Settling Time (µs)
Output Voltage (Vpp)
16
25
20
15
10
14
12
10
8
6
4
5
0
2
1k
10k
100k
Frequency (Hz)
0
1M
2
G043
4
6
8
10
12
14
Step Size (V)
16
Figure 41.
Figure 42.
SMALL-SIGNAL RESPONSE OVER
CAPACITIVE LOADS (G = 5)
SMALL-SIGNAL RESPONSE
(G = 5, RL = 1 kΩ, CL = 100 pF)
18
20
G044
Output Voltage (10 mV/div)
Output Voltage (V)
0.2
0.1
CL = 0 pF
CL = 100 pF
CL = 220 pF
CL = 500 pF
CL = 1 nF
CL = 220 nF
0
−0.1
−0.2
Time (5 ms/div)
Time (5 ms/div)
G045
Figure 44.
SMALL-SIGNAL RESPONSE
(G = 10, RL = 10 kΩ, CL = 100 pF)
SMALL-SIGNAL RESPONSE
(G = 100, RL = 10 kΩ, CL = 100 pF)
Output Voltage (10 mV/div)
Output Voltage (10 mV/div)
Figure 43.
G046
Time (5 ms/div)
G052
Figure 45.
Time (20 ms/div)
G053
Figure 46.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
SMALL-SIGNAL RESPONSE
(G = 1000, RL = 10 kΩ, CL = 100 pF)
LARGE-SIGNAL RESPONSE AND SETTLING TIME
(G = 5, RL = 10 kΩ, CL = 100 pF)
Output Settling (0.002%/div)
Output Voltage (5 V/div)
Output Voltage (10 mV/div)
Output Voltage
Output Settling
Time (100 ms/div)
Time (50 ms/div)
G054
G061
Figure 47.
Figure 48.
LARGE-SIGNAL RESPONSE AND SETTLING TIME
(G = 10, RL = 10 kΩ, CL = 100 pF)
LARGE-SIGNAL RESPONSE AND SETTLING TIME
(G = 100, RL = 10 kΩ, CL = 100 pF)
Time (50 ms/div)
Output Settling (0.002%/div)
Output Voltage
Output Settling
Output Voltage (5 V/div)
Output Voltage (5 V/div)
Output Settling (0.002%/div)
Output Voltage
Output Settling
Time (50 ms/div)
G062
Figure 49.
G063
Figure 50.
LARGE-SIGNAL RESPONSE AND SETTLING TIME
(G = 1000, RL = 10 kΩ, CL = 100 pF)
OPEN-LOOP OUTPUT IMPEDANCE
10M
Time (100 ms/div)
1M
Impedance (Ω)
Output Voltage (5 V/div)
Output Settling (0.002 %/div)
Output Voltage
Output Settling
100k
10k
1k
100
1m 10m 100m
G064
Figure 51.
14
1
10 100 1k
Frequency (Hz)
10k 100k 1M 10M
G055
Figure 52.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 5, unless otherwise noted.
CHANGE IN INPUT OFFSET VOLTAGE vs WARM-UP TIME
5
4
Offset Voltage (µV)
3
2
1
0
−1
−2
−3
−4
−5
0
40
80
120
Time (s)
160
200
G056
Figure 53.
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APPLICATION INFORMATION
Figure 54 shows the basic connections required for device operation. Good layout practice mandates that bypass
capacitors are placed as close to the device pins as possible.
The INA827 output is referred to the output reference (REF) terminal, which is normally grounded. This
connection must be low-impedance to assure good common-mode rejection. Although 5 Ω or less of stray
resistance can be tolerated while maintaining specified CMRR, small stray resistances of tens of ohms in series
with the REF pin can cause noticeable degradation in CMRR.
V+
0.1 mF
8
(1)
RS
-IN
1
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-)
2
8 kW
RG
G=5+
7
A3
8 kW
+
3
+IN
Load VO
50 kW
(1)
RS
4
80 kW
RG
50 kW
A2
6
REF
Device
5
0.1 mF
V-
(1) This resistor is optional if the input voltage remains above [(V–) – 2 V] or if the signal source current drive capability is limited to less than
3.5 mA. See the Input Protection section for more details.
Figure 54. Basic Connections
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SETTING THE GAIN
Device gain is set by a single external resistor (RG), connected between pins 2 and 3. The value of RG is
selected according to Equation 1:
80 kW
5+
RG
(1)
Table 1 lists several commonly-used gains and resistor values. The on-chip resistors are laser-trimmed to
accurate absolute values. The accuracy and temperature coefficients of these resistors are included in the gain
accuracy and drift specifications of the INA827.
Table 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN (V/V)
RG (Ω)
NEAREST 1% RG (Ω)
5
—
—
10
16.00k
15.8k
20
5.333k
5.36k
50
1.778k
1.78k
100
842.1
845
200
410.3
412
500
161.6
162
1000
80.40
80.6
Gain Drift
The stability and temperature drift of the external gain setting resistor (RG) also affects gain. The RG contribution
to gain accuracy and drift can be directly inferred from the gain of Equation 1.
The best gain drift of 1 ppm per degree Celsius can be achieved when the INA827 uses G = 5 without RG
connected. In this case, the gain drift is limited only by the slight temperature coefficient mismatch of the
integrated 50-kΩ resistors in the differential amplifier (A3). At gains greater than 5, the gain drift increases as a
result of the individual drift of the resistors in the feedback of A1 and A2, relative to the drift of the external gain
resistor RG. Process improvements to the temperature coefficient of the feedback resistors now enable a
maximum gain drift of the feedback resistors to be specified at 35 ppm per degree Celsius, thus significantly
improving the overall temperature stability of applications using gains greater than 5.
Low resistor values required for high gains can make wiring resistance important. Sockets add to wiring
resistance and contribute additional gain error (such as possible unstable gain errors) at gains of approximately
100 or greater. To ensure stability, avoid parasitic capacitances greater than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see the Typical
Characteristics.
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OFFSET TRIMMING
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF terminal. Figure 55 shows an optional circuit for trimming the output offset voltage.
The voltage applied to the REF terminal is summed at the output. The op amp buffer provides low impedance at
the REF terminal to preserve good common-mode rejection.
VIN-
V+
RG
VIN+
INA827
VO
100 mA
1/2 REF200
REF
OPA333
±10 mV
Adjustment Range
100 W
10 kW
100 W
100 mA
1/2 REF200
V-
Figure 55. Optional Trimming of Output Offset Voltage
INPUT COMMON-MODE RANGE
The linear input voltage range of the INA827 input circuitry extends from the negative supply voltage to 1 V
below the positive supply, while maintaining 88-dB (minimum) common-mode rejection throughout this range.
The common-mode range for most common operating conditions is described in Figure 14 and Figure 35 through
Figure 38. The INA827 can operate over a wide range of power supplies and VREF configurations, thus making a
comprehensive guide to common-mode range limits for all possible conditions impractical to provide.
The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,
which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1
and A2 (see Figure 56) provides a check for the most common overload conditions. The A1 and A2 designs are
identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when
the A2 output is saturated, A1 may continue to be in linear operation and responding to changes in the
noninverting input voltage. This difference may give the appearance of linear operation but the output voltage is
invalid.
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range
that extends to single-supply ground, the INA827 employs a current-feedback topology with PNP input
transistors; see Figure 56. The matched PNP transistors (Q1 and Q2) shift the input voltages of both inputs up by
a diode drop and (through the feedback network) shift the output of A1 and A2 by approximately +0.8 V. With
both inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the
linear range, allowing differential measurements to be made at the GND level. As a result of this input levelshifting, the voltages at pins 2 and 3 are not equal to the respective input terminal voltages (pins 1 and 4). For
most applications, this inequality is not important because only the gain-setting resistor connects to these pins.
18
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INSIDE THE INA827
Refer to Figure 54 for a simplified representation of the INA827. A more detailed diagram (shown in Figure 56)
provides additional insight into the INA827 operation.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions and preserve excellent noise performance. When excessive voltage is applied, these transistors
limit input current to approximately 8 mA.
The differential input voltage is buffered by Q1 and Q2 and is applied across RG, causing a signal current to flow
through RG, R1, and R2. The output difference amplifier (A3) removes the common-mode component of the input
signal and refers the output signal to the REF terminal.
The equations shown in Figure 56 describe the output voltages of A1 and A2. The VBE and voltage drop across
R1 and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages.
V+
V+
RG
(External)
50 kW
R1
8 kW
A1 Out = VCM + VBE + 0.125 V - VD/2 ´ G
A2 Out = VCM + VBE + 0.125 V + VD/2 ´ G
Output Swing Range A1, A2, (V+) - 0.1 V to (V-) + 0.1 V
V-
R2
8 kW
V-
V+
10 kW
VOUT
A3
10 kW
V+
VO = G ´ (VIN+ - VIN-) + VREF
Linear Input Range A3 = (V+) - 0.9 V to (V-) + 0.1 V
V-
50 kW
REF
VV+
V+
-IN
Q1
VD/2
Overvoltage
Protection
Q2
C1
V-
A1
A2
RB
VCM
C2
V-
VB
Overvoltage
Protection
RB
VD/2
V+IN
Figure 56. INA827 Simplified Circuit Diagram
INPUT PROTECTION
The INA827 inputs are individually protected for voltages up to ±40 V. For example, a condition of –40 V on one
input and +40 V on the other input does not cause damage. However, if the input voltage exceeds [(V–) – 2 V]
and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite
polarity; see Figure 14. This polarity reversal can easily be avoided by adding a 10-kΩ resistance in series with
both inputs.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. Figure 14
illustrates this input current limit behavior. The inputs are protected even if the power supplies are disconnected
or turned off.
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INPUT BIAS CURRENT RETURN PATH
The INA827 input impedance is extremely high—approximately 20 GΩ. However, a path must be provided for
the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means that
this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 57 shows various
provisions for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds
the INA827 common-mode range, and the input amplifiers saturate. If the differential source resistance is low,
the bias current return path can be connected to one input (as shown in the thermocouple example in Figure 57).
With higher source impedance, using two equal resistors provides a balanced input with possible advantages of
lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
Microphone,
Hydrophone,
etc.
Device
47 kW
47 kW
Thermocouple
Device
10 kW
Device
Center tap provides
bias current return.
Figure 57. Providing an Input Common-Mode Current Path
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REFERENCE TERMINAL
The INA827 output voltage is developed with respect to the voltage on the reference terminal. Often, in dualsupply operation, the reference pin (pin 6) is connected to the low-impedance system ground. Offsetting the
output signal to a precise mid-supply level (for example, 2.5 V in a 5-V supply environment) can be useful in
single-supply operation. The signal can be shifted by applying a voltage to the device REF pin, which can be
useful when driving a single-supply ADC.
For best performance, any source impedance to the REF terminal should be kept below 5 Ω. Referring to
Figure 54, the reference resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to
this 50-kΩ resistor. The imbalance in resistor ratios results in degraded common-mode rejection ratio (CMRR).
Figure 58 shows two different methods of driving the reference pin with low impedance. The OPA330 is a lowpower, chopper-stabilized amplifier and therefore offers excellent stability over temperature. The OPA330 is
available in the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference
in a small SOT23-6 package.
+5 V
VIN-
+5 V
RG
VOUT
INA827
VIN-
REF
VIN+
+5 V
RG
VOUT
INA827
REF
+5 V
VIN+
+2.5 V
OPA330
a) Level shifting using the OPA330 as a low-impedance buffer
REF3225
+5 V
b) Level shifting using the low-impedance output of the REF3225
Figure 58. Options for Low-Impedance Level Shifting
DYNAMIC PERFORMANCE
Figure 19 illustrates that, despite having low quiescent current of only 200 µA, the INA827 achieves much wider
bandwidth than other instrumentation amplifiers (INAs) in its class. This achievement is a result of using TI’s
proprietary high-speed precision bipolar process technology. The current-feedback topology provides the INA827
with wide bandwidth even at high gains. Settling time also remains excellent at high gain because of a 1.5-V/µs
high slew rate.
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OPERATING VOLTAGE
The INA827 operates over a power-supply range of +2.7 V to +36 V (±1.35 V to ±18 V). Supply voltages higher
than 40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature
are shown in the Typical Characteristics section.
Low-Voltage Operation
The INA827 can operate on power supplies as low as ±1.35 V. Most parameters vary only slightly throughout this
supply voltage range; see the Typical Characteristics section. Operation at very low supply voltage requires
careful attention to assure that the input voltages remain within the linear range. Voltage swing requirements of
the internal nodes limit the input common-mode range with low power-supply voltage. Figure 7 to Figure 13 and
Figure 35 to Figure 38 describe the linear operation range for various supply voltages, reference connections,
and gains.
ERROR SOURCES
Most modern signal-conditioning systems calibrate errors at room temperature. However, calibration of errors
that result from a change in temperature is normally difficult and costly. Therefore, it is important to minimize
these errors by choosing high-precision components such as the INA827 that have improved specifications in
critical areas that impact overall system precision. Figure 59 shows an example application.
+15 V
RS+ = 10 kW
VDIFF = 1 V
16 kW
VOUT
Device
REF
VCM = 10 V
RS- = 9.9 kW
Signal Bandwidth: 5 kHz
-15 V
Figure 59. Example Application with G = 10 V/V and 1-V Differential Voltage
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Resistor-adjustable INAs such as the INA827 yield the lowest gain error at G = 5 because of the inherently wellmatched drift of the internal resistors of the differential amplifier. At gains greater than 5 (for instance, G = 10 V/V
or G = 100 V/V) gain error becomes a significant error source because of the resistor drift contribution of the
feedback resistors in conjunction with the external gain resistor. Except for very high gain applications, gain drift
is by far the largest error contributor compared to other drift errors (such as offset drift). The INA827 offers the
lowest gain error over temperature in the marketplace for both G > 5 and G = 5 (no external gain resistor).
Table 2 summarizes the major error sources in common INA applications and compares the two cases of G = 5
(no external resistor) and G = 10 (with a 16-kΩ external resistor). As can be seen in Table 2, while the static
errors (absolute accuracy errors) in G = 5 are almost twice as great as compared to G = 10, there is a great
reduction in drift errors because of the significantly lower gain error drift. In most applications, these static errors
can readily be removed during calibration in production. All calculations refer the error to the input for easy
comparison and system evaluation.
Table 2. Error Calculation
INA827
ERROR SOURCE
ERROR CALCULATION
SPECIFICATION
G = 10 ERROR
(ppm)
G = 1 ERROR
(ppm)
ABSOLUTE ACCURACY AT +25°C
Input offset voltage (µV)
VOSI / VDIFF
150
150
150
Output offset voltage (µV)
VOSO / (G × VDIFF)
2000
200
400
Input offset current (nA)
IOS × maximum (RS+, RS–) / VDIFF
5
50
50
94 (G = 10),
88 (G = 5)
200
398
600
998
25 (G = 10),
1 (G = 5)
2000
80
200
200
CMRR (dB)
VCM / (10CMRR / 20 × VDIFF)
Total absolute accuracy error (ppm)
DRIFT TO +105°C
Gain drift (ppm/°C)
GTC × (TA – 25)
Input offset voltage drift (μV/°C)
(VOSI_TC / VDIFF) × (TA – 25)
5
Output offset voltage drift (μV/°C)
[VOSO_TC / ( G × VDIFF)] × (TA – 25)
30
240
240
2440
760
5
5
5
eNI = 17
eNO = 250
6
6
11
11
3051
1769
Total drift error (ppm)
RESOLUTION
Gain nonlinearity (ppm of FS)
Voltage noise (1 kHz)
BW ´
(eNI2 +
eNO
G
2
6
´
VDIFF
Total resolution error (ppm)
TOTAL ERROR
Total error
Total error = sum of all error sources
LAYOUT GUIDELINES
Attention to good layout practices is always recommended. Keep traces short and, when possible, use a printed
circuit board (PCB) ground plane with surface-mount components placed as close to the device pins as possible.
Place 0.1-μF bypass capacitors close to the supply pins. These guidelines should be applied throughout the
analog circuit to improve performance and provide benefits such as reducing the electromagnetic-interference
(EMI) susceptibility.
CMRR vs Frequency
The INA827 pinout has been optimized for achieving maximum CMRR performance over a wide range of
frequencies. However, care must be taken to ensure that both input paths are well-matched for source
impedance and capacitance to avoid converting common-mode signals into differential signals. In addition,
parasitic capacitance at the gain-setting pins can also affect CMRR over frequency. For example, in applications
that implement gain switching using switches or PhotoMOS® relays to change the value of RG, the component
should be chosen so that the switch capacitance is as small as possible.
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Product Folder Link(s): INA827
23
INA827
SBOS631 – JUNE 2012
www.ti.com
APPLICATION EXAMPLE
Programmable Logic Controller (PLC) Input
An example programmable logic controller (PLC) input application using an INA827 is shown in Figure 60.
±10 V
100 kW
+15 V
4.87 kW
4 mA to 20 mA
±20 mA
12.4 kW
VOUT = 2.5 V ± 2.3 V
Device
20 W
REF
-15 V
+2.5 V
REF3225
+5 V
Figure 60. ±10-V, 4-mA to 20-mA PLC Input
24
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): INA827
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
INA827AIDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
INA827AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
INA827AIDGKR
Package Package Pins
Type Drawing
VSSOP
DGK
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
3.4
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA827AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
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