PD - 95553B
IRLR3105PbF
IRLU3105PbF
®
HEXFET Power MOSFET
Features
l
l
l
l
l
l
l
Logic-Level Gate Drive
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
D
VDSS = 55V
RDS(on) = 0.037Ω
G
ID = 25A
S
Description
This HEXFET® Power MOSFET utilizes the latest processing
techniques to achieve extremely low on-resistance per silicon
area. Additional features of this design are a 175°C junction
operating temperature, fast switching speed and improved
repetitive avalanche rating. These features combine to make this
design an extremely efficient and reliable device for use in a wide
variety of applications.
The D-Pak is designed for surface mounting using vapor phase,
infrared, or wave soldering techniques. The straight lead version
(IRLU series) is for through-hole mounting applications. Power
dissipation levels up to 1.5 watts are possible in typical surface
mount applications.
D-Pak
IRLR3105PbF
I-Pak
IRLU3105PbF
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
EAS (tested)
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
25
18
100
57
0.38
± 16
61
94
See Fig.12a, 12b, 15, 16
3.4
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
–––
2.65
50
110
°C/W
1
10/01/10
IRLR/U3105PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
I GSS
Min. Typ. Max. Units
Conditions
55
––– –––
V
VGS = 0V, ID = 250µA
––– 0.056 ––– V/°C Reference to 25°C, ID = 1mA
–––
30
37
VGS = 10V, ID = 15A
mΩ
–––
35
43
VGS = 5.0V, ID = 13A
1.0
––– 3.0
V
VDS = VGS, ID = 250µA
15
––– –––
S
VDS = 25V, ID = 15A
––– ––– 20
VDS = 55V, VGS = 0V
µA
––– ––– 250
VDS = 44V, VGS = 0V, TJ = 150°C
––– ––– 200
VGS = 16V
nA
––– ––– -200
VGS = -16V
––– ––– 20
ID = 15A
––– ––– 5.6
nC
VDS = 44V
––– ––– 9.0
VGS = 5.0V, See Fig. 6 and 13
–––
8.0 –––
VDD = 28V
–––
57 –––
ID = 15A
–––
25 –––
RG = 24Ω
–––
37 –––
VGS = 5.0V, See Fig. 10
D
Between lead,
––– 4.5 –––
6mm (0.25in.)
nH
G
from package
––– 7.5 –––
and center of die contact
S
––– 710 –––
VGS = 0V
––– 150 –––
VDS = 25V
–––
28 –––
pF
ƒ = 1.0MHz, See Fig. 5
––– 890 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
––– 110 –––
VGS = 0V, VDS = 44V, ƒ = 1.0MHz
––– 210 –––
VGS = 0V, VDS = 0V to 44V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
25
––– –––
showing the
A
G
integral reverse
––– ––– 100
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 15A, VGS = 0V
––– 52
78
ns
TJ = 25°C, IF = 15A, VDD = 28V
––– 82 120
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
* When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to application note #AN-994
Notes through are on page 11
2
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IRLR/U3105PbF
1000
100
VGS
15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
BOTTOM 2.0V
VGS
15V
10V
5.0V
3.0V
2.7V
2.5V
2.25V
BOTTOM 2.0V
TOP
100
10
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
1
0.1
2.0V
0.01
0.1
1
20µs PULSE WIDTH
Tj = 25°C
10
10
2.0V
1
20µs PULSE WIDTH
Tj = 175°C
0.1
0.1
100
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
30
1000.00
T J = 25°C
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (A)
1
VDS, Drain-to-Source Voltage (V)
100.00
T J = 175°C
10.00
1.00
0.10
VDS = 25V
20µs PULSE WIDTH
0.01
2.0
4.0
6.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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T J = 175°C
25
20
T J = 25°C
15
10
5
VDS = 25V
20µs PULSE WIDTH
0
8.0
0
10
20
30
40
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
IRLR/U3105PbF
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds
ID= 15A
SHORTED
Crss = C gd
Coss = Cds + Cgd
1200
C, Capacitance (pF)
20
VGS , Gate-to-Source Voltage (V)
1600
Ciss
800
Coss
400
Crss
VDS= 44V
VDS= 28V
VDS= 11V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
1
10
0
100
VDS, Drain-to-Source Voltage (V)
1000
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100.0
10.0
1.0
TJ = 25°C
VGS = 0V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
20
30
40
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
4
10
Q G Total Gate Charge (nC)
100
10
100µsec
1msec
1
0.1
1.8
OPERATION IN THIS AREA
LIMITED BY RDS(on)
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLR/U3105PbF
3.0
25
2.5
ID , Drain Current (A)
20
15
10
5
0
25
50
75
100
125
150
I D = 25A
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
30
1.5
1.0
0.5
V GS = 10V
0.0
-60
175
-40
TC , Case Temperature ( °C)
-20
0
20
40
60
80
100 120 140 160 180
( ° C)
TJ , Junction Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
(Z thJC )
10
D = 0.50
1
Thermal Response
0.20
0.10
0.05
0.1
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P DM
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
t1/ t
2
J = P DM x Z thJC
+T C
0.01
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U3105PbF
100
TOP
ID
6.1A
11A
BOTTOM
15A
15V
20V
VGS
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
80
DRIVER
L
VDS
60
40
20
0
25
50
75
100
125
Starting Tj, Junction Temperature
I AS
150
175
( ° C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
2.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
10 V
ID = 250µA
1.5
1.0
0.5
0.0
-75
VGS
-50
-25
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRLR/U3105PbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.01
10
0.05
0.10
1
0.1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
70
T OP
Single Pulse
BOTT OM 50% Duty Cycle
ID = 15A
EAR , Avalanche Energy (mJ)
60
50
40
30
20
10
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRLR/U3105PbF
D.U.T
Driver Gate Drive
+
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
VDS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRLR/U3105PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120
WIT H AS SEMBLY
LOT CODE 1234
AS SEMBLED ON WW 16, 2001
IN T HE ASS EMBLY LINE "A"
PART NUMBER
INT ERNAT IONAL
RECT IFIER
LOGO
Note: "P" in assembly line position
indicates "Lead-Free"
IRF R120
116A
12
34
ASS EMBLY
LOT CODE
DAT E CODE
YEAR 1 = 2001
WEEK 16
LINE A
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRF R120
12
ASS EMBLY
LOT CODE
34
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
P = DES IGNAT ES LEAD-FREE
PRODUCT QUALIFIED T O T HE
CONSUMER LEVEL (OPT IONAL)
YEAR 1 = 2001
WEEK 16
A = AS SEMBLY SIT E CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRLR/U3105PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE : T HIS IS AN IRF U120
WIT H ASS EMBLY
LOT CODE 5678
ASS EMBLED ON WW 19, 2001
IN T HE AS SEMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBER
IRF U120
119A
56
78
ASS EMBLY
LOT CODE
Note: "P" in as s embly line pos ition
indicates Lead-Free"
DAT E CODE
YEAR 1 = 2001
WEE K 19
LINE A
OR
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMBE R
IRFU120
56
ASS EMBLY
LOT CODE
78
DAT E CODE
P = DES IGNAT E S LEAD-F REE
PRODUCT (OPT IONAL)
YEAR 1 = 2001
WEE K 19
A = ASSEMBLY S ITE CODE
Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRLR/U3105PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature.
as Coss while VDS is rising from 0 to 80% VDSS .
Limited by TJmax, starting TJ = 25°C, L = 0.55mH
Limited by TJmax ' see Fig 12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 15A, VGS =10V
avalanche performance.
ISD ≤ 25A, di/dt ≤ 290A/µs, VDD ≤ V(BR)DSS,
This value determined from sample failure population. 100%
TJ ≤ 175°C
tested to this value in production.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2010
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