Cypress CY2X013LXI156T Lvds crystal oscillator (xo) low jitter crystal oscillato Datasheet

CY2X013
LVDS Crystal Oscillator (XO)
Features
Functional Description
■
Low jitter crystal oscillator (XO)
■
Less than 1 ps typical root mean square (RMS) phase jitter
The CY2X013 is a high-performance and high-frequency XO.
The device uses a Cypress proprietary low-noise PLL to
synthesize the frequency from an integrated crystal.
■
Low-voltage differential signaling (LVDS) output
■
Output frequency from 50 MHz to 690 MHz
■
Factory-configured or field-programmable
■
Integrated phase-locked loop (PLL)
■
Output enable (OE) or power-down (PD#) function
■
Supply voltage: 3.3 V or 2.5 V
■
Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
■
Commercial and industrial temperature ranges
The CY2X013 is available as a factory-configured device or as
a field-programmable device. Factory-configured devices are
configured for general use (see Standard and Application-Specific Factory Configurations) or they can be
customer-specific.
Logic Block Diagram
4
CRYSTAL
OSCILLATOR
LOW- NOISE
PLL
CLK
OUTPUT
DIVIDER
5
CLK#
PROGRAMMABLE
CONFIGURATION
1
OE/PD#
Cypress Semiconductor Corporation
Document Number: 001-10261 Rev. *G
•
6
3
VDD
VSS
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 25, 2011
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CY2X013
Pinouts
Figure 1. Pin Diagram – 6-Pin Ceramic LCC
OE/PD# 1
DNU 2
VSS 3
6 VDD
5 CLK#
4 CLK
Table 1. Pin Definitions - 6-Pin Ceramic LCC
Pin
1
Name
OE/PD#
4, 5
2
6
3
CLK, CLK#
DNU
VDD
VSS
I/O Type
Description
CMOS input Output enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power-down pin: Active LOW. If PD# = 0, the device is powered down and the clock is disabled.
The functionality of this pin is programmable
LVDS output Differential output clock
–
Do not use: DNU pins are electrically connected, but perform no function
Power
Supply voltage: 2.5 V or 3.3 V
Power
Ground
Standard and Application-Specific Factory Configurations
Part Number
RMS Phase Jitter (Random)
Output Frequency
Pin 1 Function
Offset Range
Jitter (Typical)
CY2X013LXI062T
62.50 MHz
OE
1.875 MHz to 20 MHz
12 kHz to 20 MHz
0.36 ps
0.96 ps
CY2X013LXI100T
100.00 MHz
OE
637 kHz to 10 MHz
900 kHz to 7.5 MHz
0.52 ps
0.39 ps
CY2X013LXI122T
122.88 MHz
OE
12 kHz to 20 MHz
0.81 ps
CY2X013LXI125T
125.00 MHz
OE
1.875 MHz to 20 MHz
12 kHz to 20 MHz
0.34 ps
0.84 ps
CY2X013LXI156T
156.25 MHz
OE
1.875 MHz to 20 MHz
0.31 ps
CY2X013LXI200T
200.00 MHz
OE
12 kHz to 20 MHz
0.74 ps
Document Number: 001-10261 Rev. *G
Page 2 of 10
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CY2X013
Programming Description
Programming Variables
The CY2X013 is a programmable device. Prior to being used in
an application, it must be programmed with the output frequency
and other variables described in Programming Variables. Two
different device types are available, each with its own
programming flow. They are described in the following sections.
Output Frequency
Field Programmable CY2X013F
The CY2X013 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2X013 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz and
596 MHz to 617 MHz.
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a PCB.
Customers use CyClockWizard™ software to specify the device
configuration and generate a joint electron devices engineering
council
(JEDEC - extension .jed)
programming
file.
Programming of samples and prototype quantities is available
using the CyClockWizard software along with a
CY3675-CLKMAKER1 CyClockMaker Clock Programmer Kit
with a CY3675-LCC6A socket adapter. Cypress’s value-added
distribution
partners
also
provide
programming
services. Field-programmable devices are designated with an ‘F’
in the part number. They are intended for quick prototyping and
inventory reduction.
You can download the software and programmer kit hardware
from www.cypress.com by clicking the hyperlinks in the previous
paragraph.
Factory Configured CY2X013
For ready-to-use devices, the CY2X013 is available with no field
programming required. Pre-configured devices (see Standard
and Application-Specific Factory Configurations) are available
for samples or orders, or a request for a custom configuration
can be made. All requests are submitted to the local Cypress
field application engineer (FAE) or sales representative. After the
request is processed, the user receives a new part number,
samples, and datasheet with the programmed values. This part
number is used for additional sample requests and production
orders. The CY2X013 is one-time programmable (OTP).
Document Number: 001-10261 Rev. *G
The CY2X013 can synthesize a frequency to a resolution of one
part per million (ppm), but the actual accuracy of the output
frequency is limited by the accuracy of the integrated reference
crystal.
Pin 1: Output Enable (OE) or Power-Down (PD#)
Pin 1 is programmed as either OE or PD#. The OE function is
used to enable or disable the CLK output quickly, but it does not
reduce core power consumption. The PD# function puts the
device into a low-power state, but the wake-up takes longer
because the PLL must reacquire the lock.
Industrial versus Commercial Device Performance
Industrial and commercial devices have different internal
crystals. They have a potentially significant impact on
performance levels for applications requiring the lowest possible
phase noise. CyClockWIzard software allows the user to select
between and view the expected performance of both options.
Table 2. Device Programming Variables
Variable
Output frequency
Pin 1 function (OE or PD#)
Temperature range (commercial or industrial)
Page 3 of 10
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CY2X013
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply voltage
–0.5
4.4
V
VIN[1]
Input voltage, DC
Relative to VSS
–0.5
VDD + 0.5
V
TS
Temperature, storage
Non operating
–55
135
°C
TJ
Temperature, junction
–40
135
°C
ESDHBM
Electrostatic discharge (ESD) protection
human body model (HBM)
JEDEC Std 22-A114-B
2000
–
V
ΘJA[2]
Thermal resistance, junction to ambient
0 m/s airflow
64
°C / W
Operating Conditions
Parameter
VDD
Min
Typ
Max
Unit
3.3 V supply voltage range
Description
3.0
3.3
3.6
V
2.5 V supply voltage range
2.375
2.5
2.625
V
TPU
Power-up time for VDD to reach minimum specified voltage (power ramp is
monotonic)
0.05
–
500
ms
TA
Ambient temperature (commercial)
0
–
70
°C
–40
–
85
°C
Ambient temperature (industrial)
DC Electrical Characteristics
Parameter
IDD[3]
Description
Operating supply current
Min
Typ
Max
Unit
VDD = 3.6 V, OE/PD# = VDD,
output terminated
Condition
–
–
125
mA
VDD = 2.625 V, OE/PD# = VDD,
output terminated
–
–
120
mA
–
–
200
μA
ISB
Standby supply current
PD# = VSS
VOD
LVDS differential output voltage
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between CLK and
CLK#
247
–
454
mV
ΔVOD
Change in VOD between complementary
output states
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between CLK and
CLK#
–
–
50
mV
VOS
LVDS offset output voltage
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between CLK and
CLK#
1.125
–
1.375
V
ΔVOS
Change in VOS between complementary
output states
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between CLK and
CLK#
–
–
50
mV
IOZ
LVDS output leakage current
Tri-state output, unterminated,
measured on one pin while floating
the other pin, PD#/OE = VSS
–35
–
35
μA
VIH
Input high voltage
0.7 × VDD
–
–
V
VIL
Input low voltage
–
–
0.3 × VDD
V
IIH
Input high current
Input = VDD
–
–
115
μA
IIL
Input low current
Input = VSS
–
–
50
μA
CIN[3]
Input capacitance, OE/PD# pin
–
15
–
pF
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors.
Document Number: 001-10261 Rev. *G
Page 4 of 10
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CY2X013
AC Electrical Characteristics
The following table lists the AC electrical specifications for this device.[4]
Parameter
Description
Condition
[5]
Min
Typ
Max
Unit
50
–
690
MHz
FOUT
Output frequency
FSC
Frequency stability, commercial
devices[6]
VDD = min to max, TA = 0 °C to 70 °C
–
–
±35
ppm
FSI
Frequency stability, industrial
devices[6]
VDD = min to max, TA = –40 °C to 85 °C
–
–
±55
ppm
AG
Aging, 10 years
–
–
±15
ppm
TDC
Output duty cycle
F <= 450 MHz, measured at zero crossing
45
50
55
%
F > 450 MHz, measured at zero crossing
40
50
60
%
TR, TF
Output rise and fall time
20% and 80% of full output swing
–
0.35
1.0
ns
TOHZ
Output disable time
Time from falling edge on OE to stopped
outputs (asynchronous)
–
–
100
ns
TOE
Output enable time
Time from rising edge on OE to outputs at
a valid frequency (asynchronous)
–
–
120
ns
TLOCK
Startup time
Time for CLK to reach valid frequency
measured from the time
VDD = VDD(min) or from PD# rising edge
–
–
5
ms
TJitter(φ)
RMS phase jitter (random)
FOUT = 106.25 MHz (12 kHz to 20 MHz)
–
1
–
ps
Pre-defined factory configurations[7]
See Note 7
ps
Switching Waveforms
Figure 2. Output Voltage Swing
CLK#
VOD1
VOD2
CLK
ΔVOD = VOD1 - VOD2
Figure 3. Output Offset Voltage
CLK
CLK#
50 Ω
50 Ω
VOS
Notes
4. Not 100% tested, guaranteed by design and characterization.
5. This parameter is specified in the CyClockWizard software.
6. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, and variation from temperature and supply voltage.
7. Typical phase noise specs for factory programmed devices are listed in the Standard and Application-Specific Factory Configurations table on page 2.
Document Number: 001-10261 Rev. *G
Page 5 of 10
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CY2X013
Figure 4. Duty Cycle Timing
CLK
TDC =
TPW
TPERIOD
CLK#
TPW
TPERIOD
Figure 5. Output Rise and Fall Time
CLK#
CLK
80%
80%
20%
20%
TR
TF
Figure 6. Output Enable and Disable Timing
OE
VIH
VIL
TOHZ
TOE
CLK
High-Impedance
CLK#
Termination Circuits
Figure 7. LVDS Termination
CLK
100 Ω
CLK#
Document Number: 001-10261 Rev. *G
Page 6 of 10
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CY2X013
Ordering Information
Part Number
Configuration
Package Description
Product Flow
Pb-free
CY2X013FLXCT
CY2X013FLXIT
Field-programmable
6-pin ceramic LCC SMD - tape and reel
Commercial, 0 °C to 70 °C
Field-programmable
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
CY2X013LXI062T
[8]
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
CY2X013LXI100T
[8]
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
CY2X013LXI122T[8]
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
CY2X013LXI125T
[8]
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
CY2X013LXI156T
[8]
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
CY2X013LXI200T
[8]
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales
representative for more information.
Possible Configurations
Part Number[9]
Configuration
Package Description
Product Flow
Pb-free
CY2X013LXCxxxT
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Commercial, 0 °C to 70 °C
CY2X013LXIxxxT
Factory-configured
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2X013 F LX C/I XXX T
Tape and reel
Custom part configuration code
C = Commercial
I = Industrial
6-pin LCC package
Field programmable device
Base part number
Company ID : CY = Cypress
Notes
8. Device configuration details are described in the Standard and Application-Specific Factory Configurations table on page 2.
9. “xxx” indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or a sales representative.
Document Number: 001-10261 Rev. *G
Page 7 of 10
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CY2X013
Package Diagram
Figure 8. 6-Pin 5.0 × 3.2 mm Ceramic LCC
001-10044 *A
Acronyms
Document Conventions
Acronym
Description
Units of Measure
ESD
electrostatic discharge
FAE
field application engineer
°C
degrees Celsius
HBM
human body model
mA
milliampere
JEDEC
joint electron devices engineering council
mV
millivolts
LCC
leadless chip carrier
MHz
megahertz
ms
millisecond
LVDS
Low-voltage differential signaling
OE
output enable
PCB
printed circuit board
PLL
phase-locked loop
RMS
root mean square
XO
crystal oscillator
OTP
one-time programmable
Document Number: 001-10261 Rev. *G
Symbol
Unit of Measure
ns
nanoseconds
pF
picofarads
μA
microamperes
ppm
parts per million
ps
picoseconds
V
volts
Ω
ohms
W
watts
Page 8 of 10
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CY2X013
.
Document History Page
Document Title: CY2X013 LVDS Crystal Oscillator (XO)
Document Number: 001-10261
Revision
ECN
Orig. of
Change
Submission
Date
**
504518
RGL
09/21/06
New data sheet
*A
2705638
KVM/AESA
05/13/09
Removed pull up resistor on pin 1, Pin 2 changed from NC to DNU
Added description of frequency range gaps, Removed frequency stability as a
programming option; added phase noise / jitter optimization, Max storage
temperature changed from 150 to 135°C, Max junction temperature changed from
125 to 135°C, Removed flammability and moisture sensitivity specs, Added
thermal resistance data, IDD increased (100mA to 120 mA), conditions changed,
and separate spec added for 2.5V supply, Changed IDD values and conditions,
Standby current changed from 1mA to 250μA, Changes to IIL and IIH, Added CIN
spec, Changed frequency stability and aging specs, Relaxed duty cycle spec
added for >450 MHz, Removed period jitter spec, and Revised switching
waveform figures
*B
2718898
WWZ
06/15/09
Minor ECN to post data sheet to external web
*C
2768029
KVM
09/18/09
Change VOD limits from 250/450 mV to 247/454 mV
Change ISB max from 250 μA to 200 μA
Add clause to IOZ Condition column
Add max limit for TR, TF: 1.0 ns
Change TOE max from 100 ns to 120 ns
Change TLOCK max from 10 ms to 5 ms
*D
2897691
KVM
03/23/10
Updated data sheet status from Preliminary to Final
Updated Ordering Information
Added Possible Configurations
Updated Package Diagram
*E
2973338
CXQ
07/08/10
Added Standard and Application-Specific Factory Configurations table on page 2.
Added phase jitter specs for pre-defined configurations in AC Electrical
Characteristics (note 7 refers users to the new table on page 2 for typical specs).
Added CY2X013LXI100T, CY2X013LXI122T, CY2X013LXI125T, and
CY2X013LXI156T devices to Ordering Information and added note 8 to reference
the configuration descriptions for each new device.
Changed all references to CyberClocksOnline software to CyClockWizard.
Removed section on phase noise versus jitter SW optimization.
*F
3047226
BASH
10/08/10
Added CY2X013LXI062T to Standard and Application-Specific Factory Configurations table on page 2 and to Ordering Information table.
Added Acronym and Units of Measure table
Updated datasheet as per template
*G
3205939
BASH
03/25/11
Added CY2X013LXI200T to Standard and Application-Specific Factory Configurations table on page 2 and to Ordering Information table.
Document Number: 001-10261 Rev. *G
Description of Change
Page 9 of 10
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CY2X013
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
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© Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-10261 Rev. *G
Revised March 25, 2011
Page 10 of 10
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