ML145106 PLL Frequency Synthesizer CMOS INTERFACES WITH DUAL–MODULUS PRESCALERS Legacy Device: Motorola MC145106 The ML145106 is a phase–locked loop (PLL) frequency synthesizer constructed in CMOS on a single monolithic structure. This synthesizer finds applications in such areas as AM radio, shortwave, amateur radio, CB and FM transceivers. The device contains an oscillator/amplifier, a 210 or 211 divider chain for the oscillator signal, a programmable divider chain for the input signal, and a phase detector. The ML145106 has circuitry for a 10.24 MHz oscillator or may operate with an external signal. The circuit provides a 5.12 MHz output signal, which can be used for frequency tripling. A 29 programmable divider divides the input signal frequency for channel selection. The inputs to the programmable divider are standard ground–to–supply binary signals. Pull–down resistors on these inputs normally set these inputs to ground enabling these programmable inputs to be controlled from a mechanical switch or electronic circuitry. The phase detector may control a VCO and yields a high level signal when input frequency is low, and a low level signal when input frequency is high. An out–of–lock signal is provided from the on–chip lock detector with a “0” level for the out–of–lock condition. • • • • • • • • • • P DIP 18 = VP PLASTIC DIP CASE 707 18 1 SOG 20W = -6P SOG PACKAGE CASE 751D 20 1 CROSS REFERENCE/ORDERING INFORMATION LANSDALE MOTOROLA PACKAGE P DIP 18 MC145106P ML145106VP SOG 20W MC145106DW ML145106-6P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. Single Power Supply Wide Supply Range: 4.5 to 12 V Provision for 10.24 MHz Crystal Oscillator 5.12 MHz Output Programmable Division Binary Input Selects up to 29 On–Chip Pull–Down Resistors on Programmable Divider Inputs Selectable Reference Divider, 210 or 211 (Including ÷ 2) Three–State Phase Detector See Application Note AN535 and Article Reprint AR254 Chip Complexity: 880 FETs or 220 Equivalent Gates BLOCK DIAGRAM OSCout ÷ 2out OSCin FS REFERENCE DIVIDE 29 OR 210 ÷2 φDetout PHASE DETECTOR fin DIVIDE–BY–N COUNTER 29 – 1 P0 P1 Page 1 of 8 P2 P3 P4 P5 P6 LD P7 P8 www.lansdale.com Issue bBC ML145106 LANSDALE Semiconductor, Inc. PIN ASSIGNMENTS PLASTIC DIP VDD 1 18 VSS fin 2 17 P0 OSCin 3 16 P1 OSCout 4 15 P2 ÷2 out 5 14 P3 FS 6 13 P4 φDetout 7 12 P5 LD 8 11 P6 P8 9 10 P7 SOG PACKAGE VDD 1 20 VSS fin 2 19 P0 OSCin 3 18 NC OSCout 4 17 P1 ÷2 out 5 16 P2 FS 6 15 P3 φDetout 7 14 P4 LD 8 13 NC P8 9 12 P5 P7 10 11 P6 NC = NO CONNECTION MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter DC Supply Voltage Input Voltage, All Inputs DC Input Current, per Pin Operating Temperature Range Storage Temperature Range Page 2 of 8 Symbol Value Unit VDD – 0.5 to + 12 V Vin – 0.5 to VDD + 0.5 V I ± 10 mA TA – 40 to + 85 °C Tstg – 65 to + 150 °C www.lansdale.com This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS°≤ (Vin or Vout)°≤ VDD. Issue b B B ML145106 LANSDALE Semiconductor, Inc. ELECTRICAL CHARACTERISTICS (TA = 25°C Unless Otherwise Stated, Voltages Referenced to VSS) All Types Symbol VDD Vdc Min Typ* Max Unit Power Supply Voltage Range VDD – 4.5 – 12 V Supply Current IDD 5.0 10 12 – – – 6 20 28 10 35 50 mA “0” Level VIL 5.0 10 12 – – – – – – 1.5 3.0 3.6 V “1” Level VIH 5.0 10 12 3.5 7.0 8.4 – – – – – – “0” Level Iin 5.0 10 12 – 5.0 – 15 – 20 – 20 – 60 – 80 – 50 – 150 – 200 5.0 10 12 – – – – – – – 0.3 – 0.3 – 0.3 5.0 10 12 – – – – – – 0.3 0.3 0.3 5.0 10 12 7.5 22.5 30 30 90 120 75 225 300 Characteristic Input Voltage Input Current FS, Pull–Up Resistor Source Current) (P0 – P8) (FS) “1” Level (P0 – P8, Pull–Down Resistor Sink Current) (OSCin, fin) “0” Level 5.0 10 12 – 2.0 – 6.0 – 9.0 – 6.0 – 25 – 37 – 15 – 62 – 92 (OSCin, fin) “1” Level 5.0 10 12 2.0 6.0 9.0 6.0 25 37 15 62 92 5.0 10 12 – 0.7 – 1.1 – 1.5 – 1.4 – 2.2 – 3.0 – – – 5.0 10 12 0.9 1.4 2.0 1.8 2.8 4.0 – – – – – 1.0 1.5 0.2 0.3 – – 5.0 10 12 – – – 1.0 0.5 – – – – Output Drive Current (VO = 4.5 V) (VO = 9.5 V) (VO = 11.5 V) (VO = 0.5 V) (VO = 0.5 V) (VO = 0.5 V) IOH Source Sink IOL µA mA Input Amplitude (fin @ 4.0 MHz) (OSCin @ 10.24 MHz) – Input Resistance (OSCin, fin) Rin Input Capacitance (OSCin, fin) Cin – – 6.0 – pF Three–State Leakage Current (φDetout) IOZ 5.0 10 12 – – – – – – 1.0 1.0 1.0 µA fin 4.5 12 0 0 – – 4.0 4.0 MHz OSCin 4.5 12 0.1 0.1 – – 10.24 10.24 MHz Input Frequency (– 40 to + 85°C) Oscillator Frequency (– 40 to + 85°C) V p–p Sine MΩ *Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC's potential performance. Page 3 of 8 www.lansdale.com Issue b B ML145106 LANSDALE Semiconductor, Inc. 25 25 20 20 V DD , SUPPLY VOLTAGE (V) V DD , POSITIVE POWER SUPPLY (V) TYPICAL CHARACTERISTICS* + 25°C 15 + 85°C – 40°C 10 5.0 0 0 10 20 30 fin, MAXIMUM FREQUENCY (MHz) 40 50 Figure 1. Maximum Divider Input Frequency versus Supply Voltage + 25°C 15 + 85°C – 40°C 10 5.0 0 0 10 20 30 40 OSCin, MAXIMUM FREQUENCY (MHz) 50 Figure 2. Maximum Oscillator Input Frequency versus Supply Voltage * Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC's potential performance. TRUTH TABLE Selection P8 P7 P6 P5 P4 P3 P2 P1 P0 Divide by N 0 0 0 0 0 • • • 0 • • • 1 0 0 0 0 0 • • • 1 • • • 1 0 0 0 0 0 • • • 1 • • • 1 0 0 0 0 0 • • • 1 • • • 1 0 0 0 0 0 • • • 1 • • • 1 0 0 0 0 0 • • • 1 • • • 1 0 0 0 0 1 • • • 1 • • • 1 0 0 1 1 0 • • • 1 • • • 1 0 1 0 1 0 • • • 1 • • • 1 2* 3* 2 3 4 • • • 255 • • • 511 LD Lock Detector (PDIP, SOG – Pin 8) LD is high when loop is locked, pulses low when out–of–lock. φDetout (PDIP, SOG – Pin 7) Signal for control of external VCO, output high when f in/N is less than the reference frequency; output low when f in/N is greater than the reference frequency. Reference frequency is the divided down oscillator–input frequency typically 5.0 or 10 kHz. NOTE Phase Detector Gain = VDD/4π. 1: Voltage level = VDD. 0: Voltage level = 0 or open circuit input. * The binary setting of 00000000 and 00000001 on P8 to P0 results in a 2 and 3 division which is not in the 2N – 1 sequence. When pin is not connected the logic signal on that pin can be treated as a “0”. PIN DESCRIPTIONS FS Reference Oscillator Frequency Division Select (PDIP,SOG – Pin 6) When using 10.24 MHz OSC frequency, this control selects 10 kHz, a “0” selects 5.0 kHz. P0 – P8 Programmable Inputs (PDIP – Pins 17 – 9; SOG – Pins 19, 17 – 14, 12 – 9) Programmable divider inputs (binary). ÷2out (PDIP, SOG – Pin 5) Reference OSC frequency divided by 2 output; when using 10.24 MHz OSC frequency, this output is 5.12 MHz for frequency tripling applications. fin Frequency Input (PDIP, SOG – Pin 2) Frequency input to programmable divider (derived fromVCO). VDD Positive Power Supply (PDIP, SOG – Pin 1) OSCin, OSCout Oscillator Input and Oscillator Output (PDIP, SOG – Pins 3, 4) Oscillator/amplifier input and output terminals. Page 4 of 8 VSS Ground (PDIP – Pin 18, SOG – Pin 20) www.lansdale.com Issue b ML145106 LANSDALE Semiconductor, Inc. Legacy Applications Information PLL SYNTHESIZER APPLICATIONS The ML145106 is well suited for applications in CB radios because of the channelized frequency requirements. A typical 40 channel CB transceiver synthesizer, using a single crystal reference, is shown in Figure 3 for receiver IF values of 10.695 MHz and 455 kHz. In addition to applications in CB radios, the MC145106 can be used as a synthesizer for several other systems. Various frequency spectrums can be achieved through the use of proper offset, prescaling, and loop programming techniques. In general, 300 – 400 channels can be synthesized using a single loop, with many additional channels available when multiple loop approaches are employed. Figures 4 and 5 are examples of some possibilities. In the aircraft synthesizer of Figure 5, the VHF loop (top) will provide a 50 kHz, 360 channel system with 10.7 MHz R/T offset when only the 11.0500 MHz (transmit) and 12.1200 LD 29/210 OSC 10.24 MHz MHz (receive) frequencies are provided to mixer #1. When these signals are provided with crystal oscillators, the result is a three crystal 360 channel, 50 kHz step synthesizer. When using the offset loop (bottom) in Figure 5 to provide the indicated injection frequencies for mixer #1 (two for transmit and two for receive) 360 additional channels are possible. This results in a 720–channel, 25 kHz step synthesizer which requires only two crystals and provides R/T offset capability. The receive offset value is determined by the 11.31 MHz crystal frequency and is 10.7 MHz for the example. The VHF marine synthesizer in Figure 4 depicts a single loop approach for FM transceivers. The VCO operates on frequency during transmit and is offset downward during receive. The offset corresponds to the receive IF (10.7 MHz) for channels having identical receive/transmit frequencies (simplex), and is (10.7 – 4.6 = 6.1) MHz for duplex channels. Carrier modulation is introduced in the loop during transmit. 2 ML145106 5.0 kHz PHASE DETECTOR LOOP FILTER VCO BUFFER PROGRAMMABLE DIVIDER VDD 26.965 – 27.405 MHz (TRANSMIT) 26.510 – 26.950 MHz (RECEIVE) GND SWITCH WAFERS R/T BUFFER 1.365 – 1.805 MHz (TRANSMIT) 0.91 – 1.35 MHz (RECEIVE) X5 25.6 MHz MIXER 10.24 MHz TO RECEIVER 2ND MIXER 16.270 – 16.710 MHz RECEIVER 1ST LOCAL OSC SIGNAL MIXER Figure 3. Single Crystal CB Synthesizer Featuring On–Frequency VCO During Transmit Page 5 of 8 www.lansdale.com Issue b ML145106 LANSDALE Semiconductor, Inc. Legacy Applications Information GND REF OSC LOCK DETECT VDD 2 5.12 MHz (10.24 MHz) 29, 210 DIVIDER PHASE DETECTOR 2.5 kHz (5.0 kHz) LOOP FILTER VCO AND BUFFER ML145106 RECEIVER L.O. RANGE 145.575 – 152.575 MHz *151.3 N 29 – 1 PROGRAMMABLE INPUTS N = 97 TO 153 *152 BUFFER FILTER TRIPLER TRANSMIT RANGE 156.025 – 157.425 MHz *157.4 MODULATION 0.2425 – 0.3825 (0.4850 – 0.7650) *0.3800 TRANSMIT MODULATION CIRCUIT 10 ( 5) MIXER 15.36 (30.72) TRANSMIT RECEIVE RECEIVE OFFSET OSCILLATOR NOTES: • Receiver IF = 10.7 MHz. • Low Side Injection. • Duplex Offset = 4.6 MHz. • Step Size = 25 kHz. • Frequencies in MHz unless noted. • Values in parentheses are for a 5.0 kHz reference frequency. • Example frequencies for Channel 28 shown by *. #Can be eliminated by adding 184 to N for Duplex Channels. SIMPLEX 14.29 (28.58) DUPLEX 14.75# (29.50) Figure 4. VHF Marine Transceiver Synthesizer Page 6 of 8 www.lansdale.com Issue b ML145106 LANSDALE Semiconductor, Inc. Legacy Applications Information LOCK DETECT REF OSC ÷2 29, 210 DIVIDER 10.24 MHz 5.0 kHz MC145106 PHASE DETECTOR LOOP FILTER VCO AND BUFFER MIXER #1 ÷ 10 TRANSMIT 118.000 – 135.975 MHz (25 kHz STEPS) RECEIVE 128.700 – 146.675 MHz ÷ N 29 – 1 VHF LOOP PROGRAMMING 750 kHz – 2545 kHz N = 150 – 509 VDD GND TRANSMIT 11.0500 MHz 11.0525 MHz LOCK DETECT 5.12 MHz REF OSC AND ÷ 2 RECEIVE 12.1200 MHz 12.1225 MHz 29, 210 DIVIDER 2.5 kHz PHASE DETECTOR MC145106 LOOP FILTER VCO AND BUFFER MIXER #2 AMP OSC ÷ N 29 – 1 1 0 1 0 0 0 1 0 OFFSET LOOP PROGRAMMING 810 kHz – 812.5 kHz N = 324 – 325 VDD GND TRANSMIT 10.24 MHz RECEIVE 11.31 MHz (SELECT FREQUENCY TO GIVE DESIRED R/T OFFSET) Figure 5. VHF Aircraft 720 Channel Two Crystal Frequency Synthesizer Page 7 of 8 www.lansdale.com Issue b ML145106 LANSDALE Semiconductor, Inc. OUTLINE DIMENSIONS P DIP 18 = VP (ML145106VP) CASE 707–02 18 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 10 B 1 9 A L C K N F H D J M SEATING PLANE G DIM A B C D F G H J K L M N SOG 20W = -6P (ML145106-6P) CASE 751D–04 11 –B– 10X P 0.010 (0.25) 1 M B M 10 20X D 0.010 (0.25) M T A B S J S F R C –T– 18X G K SEATING PLANE INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0° 15° 0.020 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 20 MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0° 15° 0.51 1.02 X 45° DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0° 7° 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0° 7° 0.395 0.415 0.010 0.029 M Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc. Page 8 of 8 www.lansdale.com Issue b