CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 1/12 2-Wire Serial EEPROMs 1K/2K/4K/8K/16K CTK24BC01-16P8 Description The CTK24BC family provides 1K, 2K, 4K, 8K and 16K of serial electrically erasable and programmable read-only memory (EEPROM). The wide Vdd range allows for low-voltage operation down to 1.8V. The device, fabricated using traditional CMOS EEPROM technology, is optimized for many industrial and commercial applications where low-voltage and low-power operation is essential. The device is accessed via a 2-wire serial interface. Features • Internally organized as 128×8(1K), 256×8(2K) 512×8(4K), 1024×8(8K), 2048×8(16K) • Low-voltage and standard-voltage operation : 1.8~5.5V • 2-wire serial interface bus • Date retention : 100 years • High endurance : 1,000,000 write cycles • 100kHz(1.8V)& 400kHz(5V) compatibility • Bi-directional data transfer protocol • Self-timed write cycle (5ms max) • Write protect pin for hardware data protection • 8-byte page (1K, 2K) and 16-byte page (4K, 8K, 16K) write modes • Allows for partial page write Absolute Maximum Ratings Parameter Voltage on any pin with respect to ground Maximum operating voltage DC output current Operating temperature range Storage temperature range Ratings -0.8 to VCC+1.5 6.25 5.0 -55 ~ +125 -65 ~ +150 Unit V V mA ℃ ℃ Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of these specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 2/12 Pin Configurations Pin Name A0-A2 SDA SCL WP Gnd VCC Function Address inputs Serial data Serial clock input Write protect Ground Power supply Block Diagram CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 3/12 Pin Descriptions Serial Data(SDA): The SDA pin used for sending and receiving data bits in serial mode. Since the SDA pin is defined as an open-drain connection, a pull-up resistor is needed. Serial Clock(SCL): The SCL input is used to synchronize data input and output with clocked out on the falling edge of SCL. Device/Page Addresses(A2, A1, A0): The A2, A1, and A0 pins are used to address multiple devices on a single bus system and should be hard-wired. ● The CTK24BC01 and CTK24BC02 use the A2, A1 and A0 pins to provide the capability for addressing up to eight 1K/2K devices on a single bus system (please see the Device Addressing section for further details) ● The CTK24BC04 uses the A2 and A1 inputs and a total of for 4K device may be addressed on a single bus system. The A0 pin is not used, but should be grounded if possible. ● The CTK24BC08 only uses the A2 input hardware addressing. On a single bus system, a total of two 8K devices may be addressed. The A0 and A1 pins are not used, but should be grounded if possible. ● The CTK24BC16 does not use the device address pins, so only one device can be connected to a single bus system. Therefore, the A0, A1, and A2 pins are not used, but should be grounded if possible. Write Protect (WP): The CTK24BC01/02/04/08/16 has a Write Protect pin that provides hardware data protection. When connected to ground, the Write Protect pin allows for normal read/write operations. If the WP pin is connected to VCC, no data can be overwritten. Memory Organization The internal memory organization for the CTK24BC family is arranged differently for each of the densities. The CTK24BC01, for instance, is internally organized as 16 pages of 8 bytes each and requires a 7-bit data word address. The CTK24BC16, on the other hand, is organized as 128 pages of 16 bytes each with an 11-bit data word address. The table below summarizes these differences. Density # of pages Bytes per page Data word address length CTK24BC01 (1K) 16 pages 8 bytes 7 bits CTK24BC02 (2K) 32 pages 8 bytes 8 bits CTK24BC04 (4K) 32 pages 16 bytes 9 bits CTK24BC08 (8K) 64 pages 16 bytes 10 bits CTK24BC16 (16K) 128 pages 16 bytes 11 bits Pin Capacitance Applicable over recommended operating range :TA=25℃, f=1MHz, VCC=+1.8V Symbol Test Condition Max Unit CI/O Input/Output Capacitance (SDA) 8 pF CIN Input Capacitance (A0, A1,A2, SCL) 6 pF Condition VI/O=0V VIN=0V Note : These parameters are characterized and not 100% tested. CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 4/12 DC Characteristics Applicable over recommended operating range: TA=-40~+85℃, VCC=+1.8V~+5.0V(unless otherwise noted) Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current VCC=5.0V Supply Current VCC=5.0V Standby Current VCC=1.8V Standby Current VCC=2.5V Standby Current VCC=5.5V Input Leakage Current Output Leakage Current Input Low Level (Note 1) Input High Level (Note 1) Output Low Level VCC=3.0V Output Low Level VCC=3.0V Symbol VCC 1 VCC 2 VCC 3 ICC ICC ISB 1 ISB 2 ISB 3 ILI ILO VIL VIH VOL 2 VOL 1 Condition READ at 100KHz WRITE at 100KHz VIN=VCC or VSS VIN=VCC or VSS VIN=VCC or VSS VIN=VCC or VSS VOUT=VCC or VSS IOL =2.1mA IOL =0.15mA Min. 1.8 2.7 4.5 -0.6 VCC×0.7 - Typ. 0.4 2.0 0.6 1.4 5.0 0.2 0.1 - Max. 5.5 5.5 5.5 1.0 3.0 3.0 4.0 18 5.0 5.0 VCC×0.3 VCC+0.5 0.4 0.2 Unit V V V mA mA μA μA μA μA μA V V V V Note : VIL and VIH Max are reference only and are not tested. AC Characteristics Applicable over recommended operating range: TA=-40~+85℃, VCC=+1.8V~+5.0V, CL=1 TTL Gate & 100pF(unless otherwise noted) Parameter Symbol Clock Frequency, SCL fSCL Clock Pulse Width Low tLOW Clock Pulse Width High tHIGH Noise Suppression Time (Note 1) tI Clock Low to Data Out Valid tAA Time the bus must be free before A new transmission can start (Note 1) tBUF Start Hold Time tHD.STA Start Setup Time tSU.STA Data in Hold Time tHD.DAT Data in Setup Time tSU.DAT Input Rise Time (Note 1) tR Input Fall Time (Note 1) tF CTK24BC01-16P8 Condition VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V Min. Typ. - - 4.7 1.2 4.0 0.6 0.1 0.1 4.7 1.2 4.0 0.6 4.7 0.6 0 0 200 100 Max. 100 400 Unit - - μs - - μs - 100 50 4.5 0.9 KHz ns μs - - μs - - μs - - μs - - μs - - ns - - - - 1.0 0.3 300 300 μs ns CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 5/12 AC Characteristics(Cont.) Applicable over recommended operating range: TA=-40~+85℃, VCC=+1.8V~+5.0V, CL=1TTL Gate & 100pF(unless otherwise noted) Parameter Stop Setup Time Symbol tSU.STO Data out Hold Time tDH Write Cycle Time tWR 5.0V, 25℃, Byte Mode Endurance (Note 1) Note: 1. This parameter is characterized and not 100% tested. Condition VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V VCC=1.8V VCC=2.7~5.5V Min. 4.7 0.6 100 50 Typ. Max. Unit - - μs - - ns - - 5 5 ms 1M 1M - - Write Cycles Device Operation Clock and Data Transitions: Transitions on the SDA pin should only occur when SCL is low(refer to the Data Validity timing diagram in Figure 3). If the SDA pin changes when SCL is high, then the transition will be interpreted as a START or STOP condition. START Condition: A START condition occurs when the SDA transitions from high to low when SCL is high. The START signal is usually used to initiate a command(refer to the START and STOP definition timing diagram in Fig 4) STOP Condition: A STOP condition occurs when the SDA transitions from low to high when SCL is high. (refer to the START and STOP definition timing diagram in Fig 4) The STOP command will put the device into standby mode after no acknowledgement is issued during the read sequence. Acknowledge: An acknowledgement is sent by pulling the SDA low to confirm that a word has been successfully received. All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words, so acknowledgements are usually issued during the 9th clock cycle. Standby Mode: Standby mode is entered when the chip is initially powered-on or after a STOP command has been issued and any internal operations have been completed. Memory Reset: In the event of unexpected power or connection loss, a START condition can be issued to restart the input command sequence. If the device is currently in write cycle mode, this command will be ignored. CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 6/12 Bus Timing Figure 1. SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing Figure 2. SCL: Serial Clock, SDA: Serial Data I/O Note : 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 7/12 Figure 3. Data Validity Figure 4. START and STOP Definition Figure 5. OUTPUT Acknowledge CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 8/12 Device Addressing To enable the chip for a read or write operation, an 8-bit device address word followed by a START condition must be issued. The 1st four bits of the device address word consist of a mandatory ‘1010’ pattern, while the 2nd four bits depend on the particular density being used(refer to Figure 6): ●In the 1K/2K chip, the next 3 bits should correspond to the hard-wired input A2, A1, and A0 device address bits. ●In the 4K chip, the next 3 bits are the A2 and A1 device address bits and a memory page address bit. The two device address bits must compare to their corresponding hard-wired input pins. ●In the 8K chip, the next 3 bits include the A2 device address bit with the next 2 bits used for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. ●The 16K chip does not use any device address bits but instead the 3 bits are used for memory page addressing. Figure 6. Device address The memory page address bits , P2, P1, and P0 are used to select the page in the array. P2 represents the most significant bit, while P1 and P0 are considered the next most significant bits. The eight bit of the device address determines read or write operation. If the R/W bit is high, then a read operation is initiated. Otherwise, if the R/W bit is low, then a write operation is started. After comparing the device address and finding a match, the EEPROM device will issue an acknowledgement by pulling SDA low. If the comparison fails, the chip will return to standby mode. Figure 7. Byte Write CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 9/12 Figure 8. Page Write Write Operation Byte/Page Write: If a write operation is entered (R/W=0) and an acknowledgement is sent, then the next sequence requires an 8-bit data word address. After an acknowledgement is received from this word address, the 1st byte of data can be loaded. The device will send an acknowledgement after each byte to confirm the transmission. To being the write cycle, a STOP condition must be issued ( refer to Figure 7). Both byte and page write operations are supported, so the STOP condition can be issued after the 1st byte or the last byte in the page. When the STOP condition occurs, an internal time is started, all inputs are disabled, and the EEPROM will not respond to any more commands until the write cycle is completed. Note: The number of bytes in a page depends on the density used. If 1K density is used, then the page size is 8 bytes. In contrast, if the 16K density is used, then the page size is 16 bytes. Refer to the Memory Organization section for more details. The internal page counter is incremented after each byte received, but the row location of the memory page will always remain the same. Therefore the device will wrap around to the 1st byte in the page after the last byte in the page is received. Any further data loaded into the page buffer will overwrite the previous data loaded. Acknowledge Polling: After the STOP condition is issued, the write cycle begins. Acknowledge polling can be initiated by sending a START condition followed by the device address word. If the EEPROM has completed the internal write cycle and returned to standby mode, the device will respond by sending back an acknowledgement by pulling the SDA pin low. Otherwise, the sequence will be ignored and no acknowledgement will be sent. Read Operations There are three types of read operations: current address read, random address read, and sequence read. A random address read can be considered a current address read operation with an additional sequence in the beginning to load a different address into the internal counter. A sequential read occurs when subsequent bytes are clocked out after a current address read or random address read occurs. CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 10/12 Current Address Read : A current address read operation is initiated by issuing R/W=1 in the device address word(refer to Figure 9). Since the internal address counter maintains the last address incremented by one accessed during the last read or write operation, the internal address counter will always retain the last address incremented by one. Random Read : To access a different address location that the one currently stored in the internal counter, a random read operation is provided. The random read is actually a combination of a “dummy” byte write sequence with a current address read command (refer to Figure 10). The “dummy” byte write loads a different address into the internal counter, and the data can then be accessed using the current address read. Sequential Read : In order to access subsequent data word after a current address read or random read has been initiated, the user should send an acknowledgement to the EEPROM chip after each data byte received. If an acknowledgement is not received, then the chip will not send any more data and expect a STOP condition on the next cycle to reset back to standby mode(refer to Figure 11). Sequential reads can be used to perform an entire chip read. Unlike the page write operation, the internal counter will increment to the next row after the last byte of the page has been reached. When the address reaches the last byte of the last memory page, the next address will increment to the 1st byte of the 1st memory page. Once the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. When the microcontroller does not respond with a zero but does generate a following stop condition, the sequential read operation is terminated. Figure 9. Current Address Read CTK24BC01-16P8 CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 11/12 Figure 10. Random Read Figure 11. Sequential Read Ordering Information Ordering Code CTK24BC01P8 CTK24BC02P8 CTK24BC04P8 CTK24BC08P8 CTK24BC16P8 CTK24BC01-16P8 Package DIP-8 Device Function 1K bit(128×8) 2K bit(256×8) 4K bit(512×8) 8K bit(1024×8) 16K bit(2048×8) Operating Ranges Industrial (-40~+85℃) CYStek Product Specification CYStech Electronics Corp. Spec. No. : C705P8 Issued Date : 2007.08.23 Revised Date : Page No. : 12/12 DIP-8P Dimension Marking: Date Code 24BC □□ □□□□ Memory: 1K: 01 2K: 02 4K: 04 8K:08 16K:16 DIP-8P Plastic Package CYStek Package Code : P8 Inches Min. Max. 0.021 0.015 0.115 0.195 0.014 0.022 0.014 0.020 0.045 0.046 0.030 0.045 0.008 0.014 DIM A A1 A2 b b1 b2 b3 c Millimeters Min. Max. 0.5334 0.381 2.921 4.953 0.356 0.559 0.356 0.508 1.143 1.778 0.762 1.143 0.203 0.356 DIM c1 D E E1 e HE L Inches Min. Max. 0.008 0.011 0.355 0.400 0.240 0.280 0.300 0.325 0.100 BSC 0.430 0.115 0.150 Millimeters Min. Max. 0.203 0.279 9.017 10.16 6.096 7.112 7.620 8.255 2.540BSC 10.92 2.921 3.810 Notes : 1.Controlling dimension : millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material : • Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0 Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. CTK24BC01-16P8 CYStek Product Specification