FUNCTIONAL BLOCK DIAGRAM FEATURES 2 pF off capacitance 1 pC charge injection 33 V supply range 150 Ω on resistance Fully specified at +12 V, ±15 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead LFCSP packages Typical power consumption: <0.03 µW S1 IN1 IN1 D1 D1 S2 S2 IN2 IN2 ADG1211 D2 ADG1212 S2 D2 D2 ADG1213 S3 IN3 S3 IN3 D3 D3 S4 S4 IN4 IN4 D1 IN2 S3 IN3 S1 S1 IN1 D3 S4 IN4 D4 D4 D4 SWITCHES SHOWN FOR A LOGIC 1 INPUT APPLICATIONS Automatic test equipment Data aquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communication systems GENERAL DESCRIPTION The ADG1211/ADG1212/ADG1213 are monolithic CMOS devices containing four independently selectable switches designed on an iCMOS process. iCMOS (industrial-CMOS) is a modular manufacturing process combining high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 30 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages, while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. Figure 1. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. The ADG1211/ADG1212/ADG1213 contain four independent single-pole/single-throw (SPST) switches. The ADG1211 and ADG1212 differ only in that the digital control logic is inverted. The ADG1211 switches are turned on with Logic 0 on the appropriate control input, while Logic 1 is required for the ADG1212. The ADG1213 has two switches with digital control logic similar to that of the ADG1211; the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on, and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. The ADG1213 exhibits break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 2 pF off capacitance (±15 V supply). 1 pC charge injection. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <0.03 µW. 16-lead TSSOP and 4 mm × 4 mm LFCSP packages. Rev. PrE Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 04778-0-001 Preliminary Technical Data 1 pF Off Capacitance, 1 pC Charge Injection, ±15 V/12 V iCMOS™ Quad SPST Switches ADG1211/ADG1212/ADG1213 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADG1211/ADG1212/ADG1213 Preliminary Technical Data TABLE OF CONTENTS Specifications..................................................................................... 3 Terminology .......................................................................................8 Single Supply ................................................................................. 3 Typical Performance Characteristics ..............................................9 Absolute Maximum Ratings............................................................ 6 Test Circuits..................................................................................... 12 ESD Caution.................................................................................. 6 Outline Dimensions ....................................................................... 14 Pin Configurations and Function Descriptions ........................... 7 Ordering Guide .......................................................................... 14 REVISION HISTORY 11/04—Revision PrE: Preliminary Version Rev. PrE | Page 2 of 16 Preliminary Technical Data ADADG1211/ADG1212/ADG1213 SPECIFICATIONS SINGLE SUPPLY VDD = 15 V ± 10%, VSS = −15 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 25°C 85°C Y Version1 Unit 120 160 VDD to VSS 180 V Ω typ Ω max Ω typ On Resistance Match between Channels (∆RON) 5 On Resistance Flatness (RFLAT(ON)) 25 50 LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) ±0.01 ±0.5 ±0.01 ±1 ±0.5 ±1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON ±5 ±0.04 ±1 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±5 0.005 ±2 Break-before-Make Time Delay, tD 15 nA max 2.0 0.8 ±2.5 ±0.5 V min V max µA typ µA max pF typ 1 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise −3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD 1 75 85 0.002 700 2 2 4 0.001 5.0 IDD 0.001 5.0 ISS 0.001 5.0 Rev. PrE | Page 3 of 16 VS = ±10 V, IS = −10 mA; Figure 20 VS = ±10 V , IS = −10 mA VS = −5 V/0 V/+5 V; IS = −10 mA VDD = +10 V, VSS = −10 V VS = 0 V/10 V, VD = 10 V/0 V; Figure 21 VS = 0 V/10 V, VD = 10 V/0 V; Figure 21 nA max ±5 50 15 nA typ nA max nA typ nA typ 5 tOFF Ω max Ω typ Ω max Test Conditions/Comments ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF typ pF typ µA typ µA max µA typ µA max µA typ µA max VS = VD = 0 V or 10 V; Figure 22 VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = ±10 V; Figure 23 RL = 300 Ω, CL = 35 pF VS = ±10 V; Figure 23 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V; Figure 24 VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27 RL = 600 Ω, 5 V rms, f = 20 Hz to 20 kHz RL = 50 Ω, CL = 5 pF; Figure 28 VDD = +16.5 V, VSS = −16.5 V Digital Inputs = 0 V or VDD Digital Inputs = 5 V Digital Inputs = 0 V or VDD ADG1211/ADG1212/ADG1213 Parameter IGND 25°C 0.001 Preliminary Technical Data Y Version1 85°C Test Conditions/Comments Digital Inputs = 0 V or VDD 5.0 Unit µA typ µA max µA typ µA max Y Version1 Unit Test Conditions/Comments 0 V to VDD 5.0 IGND 1 2 0.001 Digital Inputs = 5 V Temperature range for Y Version is −40°C to +125°C. Guaranteed by design, not subject to production test. VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 25°C 85°C 220 250 On Resistance Match between Channels (∆RON) 1 V Ω typ Ω max Ω typ On -Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) 12 Ω max Ω typ Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINLor IINH ±0.01 ±0.5 ±0.01 ±0.5 ±0.04 ±1 ±2.5 ±2.5 ±5 2.0 0.8 0.001 ±0.5 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 tON 5 50 tOFF 15 Break-before-Make Time Delay, tD 15 Charge Injection Off Isolation Channel-to-Channel Crosstalk −3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) 5 75 85 100 2 2 4 1 Rev. PrE | Page 4 of 16 nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ pF typ pF typ pF typ VS = +10 V, IS = −10 mA; Figure 20 VS = +10 V, IS = −10 mA VS = −5 V/0 V/+5 V, IS = −10 mA VDD = 12 V VS = 1 V/10 V, VD = 10 V/0 V; Figure 21 VS = 1 V/10 V, VD = 10 V/0 V; Figure 21 VS = VD = 1 V or 10 V; Figure 22 VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = 8 V; Figure 23 RL = 300 Ω, CL = 35 pF VS = 8 V; Figure 23 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; Figure 24 VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 267 RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27 RL = 50 Ω, CL = 5 pF; Figure 28 Preliminary Technical Data Parameter POWER REQUIREMENTS IDD 25°C ADADG1211/ADG1212/ADG1213 85°C Y Version1 0.001 5.0 IDD 0.001 5.0 1 2 Temperature range for Y Version is −40°C to +125°C. Guaranteed by design, not subject to production test. Rev. PrE | Page 5 of 16 Unit µA typ µA max µA typ µA max Test Conditions/Comments VDD = 13.2 V Digital Inputs = 0 V or VDD Digital Inputs = 5 V ADG1211/ADG1212/ADG1213 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D Operating Temperature Range Industrial (B Version) Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance 16-Lead LFCSP, θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) 1 Rating 35 V −0.3 V to +25 V +0.3 V to −25 V VSS – 0.3 V to VDD + 0.3 V GND – 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle max) 30 mA −40°C to +85°C −40°C to +125°C −65°C to +150°C 150°C 150.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Table 4. ADG1211/ADG1212 Truth Table ADG1211 In 0 1 ADG1212 In 1 0 Switch Condition On Off Table 5. ADG1213 Truth Table Logic 0 1 Switch 1, 4 Off On 30.4°C/W 215°C 220°C Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrE | Page 6 of 16 Switch 2, 3 On Off Preliminary Technical Data ADADG1211/ADG1212/ADG1213 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS S2 GND 5 S4 13 VDD 12 NC 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 TOP VIEW NC = NO CONNECT GND 3 S4 4 Mnemonic IN1 D1 S1 VSS GND S4 D4 IN4 IN3 D3 S3 NC VDD S2 D2 IN2 9 S3 Figure 3. LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. LFCSP 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 10 NC NC = NO CONNECT Figure 2. TSSOP Pin Configuration TSSOP 1 2 3 4 5 6 7 8 0 10 11 12 13 14 15 16 12 S2 11 VDD TOP VIEW (Not to Scale) D4 5 4 VSS 2 04788-0-002 VSS ADG1211/ ADG1212/ ADG1213 PIN 1 INDICATOR S1 1 Function Logic Control Input. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Logic Control Input. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. No Connection. Most Positive Power Supply Potential. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Logic Control Input. Rev. PrE | Page 7 of 16 04778-0-003 14 13 D2 3 14 IN2 D2 S1 D3 8 IN2 15 IN3 7 16 2 16 D1 1 D1 IN4 6 IN1 15 IN1 ADG1211/ADG1212/ADG1213 ADG1211/ADG1212/ADG1213 Preliminary Technical Data TERMINOLOGY IDD The positive supply current. CD (Off) The off switch drain capacitance, measured with reference to ground. ISS The negative supply current. CD, CS (On) The on switch capacitance, measured with reference to ground. VD (VS) The analog voltage on Terminals D and S. CIN The digital input capacitance. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. tON The delay between applying the digital control input and the output switching on. See Figure 23. tOFF The delay between applying the digital control input and the output switching off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. ID (Off) The drain leakage current with the switch off. Off Isolation A measure of unwanted signal coupling through an off switch. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. VINH The minimum input voltage for Logic 1. Bandwidth The frequency at which the output is attenuated by 3 dB. IINL (IINH) The input current of the digital input. On Response The frequency response of the on switch. CS (Off) The off switch source capacitance, measured with reference to ground. Insertion Loss The loss due to the on resistance of the switch. Rev. PrE | Page 8 of 16 Preliminary Technical Data ADADG1211/ADG1212/ADG1213 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4. On Resistance as a Function of VD (VS) for Single Supply Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply Figure 5. On Resistance as a Function of VD (VS) for Dual Supply Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply Figure 9. Leakage Currents as a Function of VD (VS) Rev. PrE | Page 9 of 16 ADG1211/ADG1212/ADG1213 Preliminary Technical Data Figure 10. Leakage Currents as a Function of VD (VS) Figure 13. Leakage Currents as a Function of Temperature Figure 11. Leakage Currents as a Function of VD (VS) Figure 14. Supply Current vs. Input Switching Frequency Figure 12. Leakage Currents as a Function of Temperature Figure 15. Charge Injection vs. Source Voltage Rev. PrE | Page 10 of 16 Preliminary Technical Data ADADG1211/ADG1212/ADG1213 Figure 16. TON/TOFF Times vs. Temperature Figure 18. Crosstalk vs. Frequency Figure 17. Off Isolation vs. Frequency Figure 19. On Response vs. Frequency Rev. PrE | Page 11 of 16 ADG1211/ADG1212/ADG1213 Preliminary Technical Data TEST CIRCUITS IDS V1 D NC = No Connect A VD Figure 22. Test Circuit 3 —On Leakage VSS 0.1µF 0.1µF VDD VSS S VIN ADG1211 50% 50% VIN ADG1212 50% 50% VOUT D CL 35pF RL 300V IN 90% VOUT 90% GND tOFF tON Figure 23. Test Circuit 4—Switching Times VDD VSS VSS S1 D1 S2 D2 CL 35pF RL 300V IN1, IN2 RL 300V VOUT2 CL 35pF VOUT1 VOUT1 50% 90% 90% 0V 90% VOUT2 90% 0V ADG1213 tD GND tD Figure 24. Test Circuit 5—Break Before Make Time Delay RS VS VDD VSS VDD VSS S D VIN CL 1nF IN GND ADG1212 ON VOUT VIN OFF ADG1211 VOUT QINJ = CL3 DVOUT Figure 25. Test Circuit 6—Charge Injection Rev. PrE | Page 12 of 16 DVOUT 04778-0-025 VS2 50% 0V 04778-0-024 VDD VS1 VIN 0.1µF 0.1µF 04778-0-022 VD Figure 21. Test Circuit 2—Off Leakage VDD S NC A VS Figure 20. Test Circuit 1—On Resistance VS D 04778-0-023 RON = V1/IDS ID (ON) ID (OFF) S A 04778-0-021 VS IS (OFF) D 04778-0-020 S Preliminary Technical Data VSS VDD 0.1µF 0.1µF VDD NETWORK ANALYZER VSS S S D RL 50Ω GND VOUT 50Ω VS VIN RL 50Ω 04778-0-026 GND OFF ISOLATION = 20 LOG VOUT VS Figure 26. Test Circuit 7—Off Isolation VDD 0.1µF VDD VSS S1 D S2 R 50Ω VS VOUT VS 04778-0-027 GND CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG INSERTION LOSS = 20 LOG Figure 27. Test Circuit 8—Channel-to-Channel Crosstalk Rev. PrE | Page 13 of 16 VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 28. Test Circuit 9—Bandwidth VSS 0.1µF RL 50Ω NETWORK ANALYZER D VIN VOUT VSS IN VS NETWORK ANALYZER 0.1µF VDD 50Ω 50Ω IN VSS 0.1µF 04778-0-028 VDD ADADG1211/ADG1212/ADG1213 ADG1211/ADG1212/ADG1213 Preliminary Technical Data OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153AB Figure 29. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ PIN 1 INDICATOR 0.65 BSC TOP VIEW 12° MAX 1.00 0.85 0.80 0.60 MAX PIN 1 INDICATOR 0.60 MAX 13 12 16 1 EXPOSED PAD 3.75 BSC SQ 0.75 0.60 0.50 (BOTTOM VIEW) 2.25 2.10 SQ 1.95 4 9 8 5 0.25 MIN 1.95 BSC 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC Figure 30. 16-Lead Lead Frame Chip Scale Package [VQ_LFCSP] 4 mm × 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters ORDERING GUIDE Model ADG1211YRU ADG1211YCP ADG1212YRU ADG1212YCP ADG1213YRU ADG1213YCP Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Thin Shrink Small Outline Package (TSSOP) Lead Frame Chip Scale Package (LFCSP) Rev. PrE | Page 14 of 16 Package Option RU-16 CP-16-4 RU-16 CP-16-4 RU-16 CP-16-4 Preliminary Technical Data ADADG1211/ADG1212/ADG1213 NOTES Rev. PrE | Page 15 of 16 ADG1211/ADG1212/ADG1213 Preliminary Technical Data NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04778–0–11/04(PrE) Rev. PrE | Page 16 of 16