Freescale MPXN2010VLQ80R Pxs20 microcontroller Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: PXS20
Rev. 1, 09/2011
PXS20
PXS20 Microcontroller Data
Sheet
• High-performance e200z4d dual core
– 32-bit Power Architecture® technology CPU
– Core frequency as high as 120 MHz
– Dual issue five-stage pipeline core
– Variable Length Encoding (VLE)
– Memory Management Unit (MMU)
– 4 KB instruction cache with error detection code
– Signal processing engine (SPE)
• Memory available
– 1 MB flash memory with ECC
– 128 KB on-chip SRAM with ECC
– Built-in RWW capabilities for EEPROM emulation
• SIL3/ASILD innovative safety concept: LockStep mode
and Fail-safe protection
– Sphere of replication (SoR) for key components (such as
CPU core, eDMA, crossbar switch)
– Fault collection and control unit (FCCU)
– Redundancy control and checker unit (RCCU) on
outputs of the SoR connected to FCCU
– Boot-time Built-In Self-Test for Memory (MBIST) and
Logic (LBIST) triggered by hardware
– Boot-time Built-In Self-Test for ADC and flash memory
triggered by software
– Replicated safety enhanced watchdog
– Replicated junction temperature sensor
– Non-maskable interrupt (NMI)
– 16-region memory protection unit (MPU)
– Clock monitoring units (CMU)
– Power management unit (PMU)
– Cyclic redundancy check (CRC) unit
• Decoupled Parallel mode for high-performance use of
replicated cores
• Nexus Class 3+ interface
• Interrupts
– Replicated 16-priority controller
– Replicated 16-channel eDMA controller
MAPBGA–225
15 mm x 15 mm
QFN12
##_mm_x_##mm
SOT-343R
##_mm_x_##mm
PKG-TBD
## mm x ## mm
144 LQFP
(20 x 20 x 1.4 mm)
Preliminary—Subject to Change Without Notice
257 MAPBGA
(14 x 14 x 0.8 mm)
• GPIOs individually programmable as input, output or
special function
• Three 6-channel general-purpose eTimer units
• 2 FlexPWM units
– Four 16-bit channels per module
• Communications interfaces
– 2 LINFlexD channels
– 3 DSPI channels with automatic chip select generation
– 2 FlexCAN interfaces (2.0B Active) with 32 message
objects
– FlexRay module (V2.1 Rev. A) with 2 channels, 64
message buffers and data rates up to 10 Mbit/s
• Two 12-bit analog-to-digital converters (ADCs)
– 16 input channels
– Programmable cross triggering unit (CTU) to
synchronize ADCs conversion with timer and PWM
• Sine wave generator (D/A with low pass filter)
• On-chip CAN/UART bootstrap loader
• Single 3.0 V to 3.6 V voltage supply
• Ambient temperature range –40 °C to 125 °C
• Junction temperature range –40 °C to 150 °C
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
TBD
Table of Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High-Performance e200z4d Core . . . . . . . . . . . .7
1.5.2 Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Memory Protection Unit (MPU) . . . . . . . . . . . . . .8
1.5.4 Enhanced Direct Memory Access (eDMA) . . . . .9
1.5.5 On-Chip Flash Memory with ECC . . . . . . . . . . . .9
1.5.6 On-Chip SRAM with ECC . . . . . . . . . . . . . . . . . .9
1.5.7 Platform Flash Memory Controller. . . . . . . . . . .10
1.5.8 Platform Static RAM Controller (SRAMC) . . . . .10
1.5.9 Memory Subsystem Access Time . . . . . . . . . . .11
1.5.10 Error Correction Status Module (ECSM) . . . . . .11
1.5.11 Peripheral Bridge (PBRIDGE) . . . . . . . . . . . . . .11
1.5.12 Interrupt Controller (INTC). . . . . . . . . . . . . . . . .11
1.5.13 System Clocks and Clock Generation . . . . . . . .12
1.5.14 Frequency-Modulated Phase-Locked Loop
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.5.15 Main Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.16 Internal Reference Clock (RC) Oscillator. . . . . .13
1.5.17 Clock, Reset, Power Mode, and Test Control
Modules (MC_CGM, MC_RGM, MC_PCU, and
MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.5.18 Periodic Interrupt Timer Module (PIT) . . . . . . . .13
1.5.19 System Timer Module (STM). . . . . . . . . . . . . . .14
1.5.20 Software Watchdog Timer (SWT) . . . . . . . . . . .14
1.5.21 Fault Collection and Control Unit (FCCU) . . . . .14
1.5.22 System Integration Unit Lite (SIUL) . . . . . . . . . .14
1.5.23 Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . .15
1.5.24 Boot Assist Module (BAM). . . . . . . . . . . . . . . . .15
1.5.25 System Status and Configuration Module (SSCM) 15
1.5.26 Controller Area Network Module (CAN) . . . . . .15
1.5.27 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.28 Serial Communication Interface Module (UART)16
1.5.29 Serial Peripheral Interface (SPI) . . . . . . . . . . . .17
1.5.30 Pulse Width Modulator (PWM) . . . . . . . . . . . . .17
1.5.31 eTimer Module. . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.32 Sine Wave Generator (SWG) . . . . . . . . . . . . . .19
1.5.33 Analog-to-Digital Converter Module (ADC) . . . .19
1.5.34 Junction Temperature Sensor . . . . . . . . . . . . . .20
1.5.35 Cross Triggering Unit (CTU) . . . . . . . . . . . . . . .20
1.5.36 Cyclic Redundancy Checker (CRC) Unit . . . . . .20
1.5.37 Redundancy Control and Checker Unit (RCCU)21
1.5.38 Voltage Regulator / Power Management Unit (PMU)21
1.5.39 Built-In Self-Test (BIST) Capability . . . . . . . . . .21
2
3
4
5
6
1.5.40 IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . 21
1.5.41 Nexus Port Controller (NPC) . . . . . . . . . . . . . . 22
Package pinouts and signal descriptions . . . . . . . . . . . . . . . 23
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.3 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4 Pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 73
3.3 Recommended operating conditions . . . . . . . . . . . . . . 74
3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 75
3.4.1 General notes for specifications at maximum
junction temperature. . . . . . . . . . . . . . . . . . . . . 76
3.5 Electromagnetic Interference (EMI) characteristics (cut1) 77
3.6 Electrostatic discharge (ESD) characteristics . . . . . . . 78
3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.8 Voltage regulator electrical characteristics . . . . . . . . . 79
3.9 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 82
3.10 Supply current characteristics (cut2) . . . . . . . . . . . . . . 83
3.11 Temperature sensor electrical characteristics . . . . . . . 84
3.12 Main oscillator electrical characteristics . . . . . . . . . . . 84
3.13 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 86
3.14 16 MHz RC oscillator electrical characteristics . . . . . . 88
3.15 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 88
3.15.1 Input Impedance and ADC Accuracy . . . . . . . . 88
3.16 Flash memory electrical characteristics . . . . . . . . . . . 93
3.17 SWG electrical characteristics. . . . . . . . . . . . . . . . . . . 94
3.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.18.1 Pad AC specifications. . . . . . . . . . . . . . . . . . . . 94
3.19 Reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.19.1 Reset sequence duration . . . . . . . . . . . . . . . . . 96
3.19.2 Reset sequence description. . . . . . . . . . . . . . . 96
3.19.3 Reset sequence trigger mapping . . . . . . . . . . . 98
3.19.4 Reset sequence — start condition . . . . . . . . . 100
3.19.5 External watchdog window. . . . . . . . . . . . . . . 101
3.20 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . 101
3.20.1 RESET pin characteristics . . . . . . . . . . . . . . . 102
3.20.2 WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . 103
3.20.3 IEEE 1149.1 JTAG interface timing . . . . . . . . 103
3.20.4 Nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.20.5 External interrupt timing (IRQ pin) . . . . . . . . . 107
3.20.6 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 113
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 118
PXS20 Microcontroller Data Sheet, Rev. 1
2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
1
Introduction
1.1
Document overview
This document describes the features of the family and options available within the family members, and highlights important
electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams for the PXS20 series of
microcontroller units (MCUs). For functional characteristics, see the PXS20 Microcontroller Reference Manual. For use of the
PXS20 in a fail-safe system according to safety standard IEC 61508, see the Safety Application Guide for MPC5643L.
The PXS20 MCU series is available in two silicon versions, or “cuts”. These are referred to as “cut1” and “cut2” throughout
this document. Functional differences between the two cuts are clearly identified with the labels “cut1” and “cut2”.
1.2
Description
The PXS20 series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain
enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital
signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital
converter, Controller Area Network, and an enhanced modular input-output system.
The PXS20 family of 32-bit microcontrollers is the latest achievement in integrated safety controllers. The advanced and
cost-efficient host processor core of the PXS20 family complies with the Power Architecture embedded category. It operates at
speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the
available development infrastructure of current Power Architecture devices and is supported with software drivers, operating
systems and configuration code to assist with users’ implementations.
1.3
Device comparison
Table 1. PXS20 Family Feature Set
Feature
CPU
Type
PXS20
2 × e200z4
(in lock-step or decoupled operation)
Architecture
Harvard
Execution speed
0 – 120 MHz (+2% FM)
DMIPS intrinsic performance
> 240 MIPS
SIMD (DSP + FPU)
Yes
MMU
16 entry
Instruction set PPC
Yes
Instruction set VLE
Yes
Instruction cache
4 KB, EDC
MPU-16 regions
Yes, replicated module
Semaphore unit (SEMA4)
Buses
Core bus
Yes
AHB, 32-bit address, 64-bit data
Internal periphery bus
32-bit address, 32-bit data
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
3
Preliminary—Subject to Change Without Notice
Introduction
Table 1. PXS20 Family Feature Set (continued)
Feature
Crossbar
Master × slave ports
Memory
Code/data flash
PXS20
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3
1 MB, ECC, RWW
Static RAM (SRAM)
Modules
Interrupt controller (INTC)
128 KB, ECC
16 interrupt levels, replicated module
Periodic Interrupt Timer (PIT)
1 × 4 channels
System timer module (STM)
1 × 4 channels, replicated module
Software watchdog timer (SWT)
eDMA
Yes, replicated module
16 channels, replicated module
FlexRay
1 × 64 message buffers, dual channel
CAN
2 × 32 message buffers
UART with DMA support
2
Clock out
Yes
Fault control & collection unit (FCCU)
Yes
Cross triggering unit (CTU)
Yes
eTimer
3 × 6 channels
PWM
2 Module 4 × (2 + 1) channels
Analog-to-digital converter (ADC)
Modules
(cont.)
2 × 12-bit ADC, 16 channels per ADC
(3 internal, 4 shared and 9 external)
Sine-wave generator (SWG)
Serial peripheral interface (SPI)
32 point
3 × SPI
as many as 8 chip selects
Cyclic redundancy checker (CRC) unit
Yes
Junction temperature sensor (TSENS)
Yes, replicated module
 16
Digital I/Os
Supply
Device power supply
Analog reference voltage
Clocking
3.3 V with integrated bypassable ballast transistor
External ballast transistor not needed for bare die
3.0 V – 3.6 V and 4.5 V – 5.5 V
Frequency-modulated phase-locked loop (FMPLL)
Internal RC oscillator
External crystal oscillator
Debug
Nexus
Packages
Type
2
16 MHz
4 – 40 MHz
Level 3+
144 LQFP
257 MAPBGA
PXS20 Microcontroller Data Sheet, Rev. 1
4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
Table 1. PXS20 Family Feature Set (continued)
Feature
Temperature
PXS20
Temperature range (junction)
–40 to 150 °C
Ambient temperature range using external ballast
transistor (LQFP)
–40 to 125 °C
Ambient temperature range using external ballast
transistor (BGA)
TBD
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
5
Preliminary—Subject to Change Without Notice
Introduction
1.4
Block diagram
Figure 1 shows a top-level block diagram of the PXS20 device.
PXS20 Block Diagram
Debug
PMU
PMU
e200z4
JTAG
FPU
Nexus
e200z4
SWT
SWT
ECSM
SPE2
VLE
STM
VLE
FlexRay™
MMU
INTC
STM
MMU
Redundancy
Checker
I-Cache
eDMA
ECSM
INTC
Cache
eDMA
Crossbar Switch (XBAR)
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
Memory Protection Unit (MPU)
PBRIDGE
Redundancy Checker
Redundancy Checker
1 MB Flash (ECC)
128 KB SRAM (ECC)
PBRIDGE
PIT
FCCU
PIT
SPI
SPI
SPI
UART/LIN
UART/LIN
CRC
TSENS
CAN
TSENS
CAN
eTIMER
eTIMER
eTIMER
CMU
PWM
CMU
PWM
CTU
CMU
IRCOSC
ADC
FMPLL
ADC
WKPU
FMPLL
SIU
SSCM
XOSC
BAM
BAM
Redundancy Checker
Figure 1. PXS20 block diagram
PXS20 Microcontroller Data Sheet, Rev. 1
6
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
ADC
BAM
CAN
CMU
CRC
CTU
ECC
ECSM
eDMA
FCCU
FMPLL
INTC
IRCOSC
JTAG
MC
PBRIDGE
PIT
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Clock monitoring unit
– Cyclic redundancy check unit
– Cross Triggering Unit
– Error correction code
– Error correction status module
– Enhanced direct memory access controller
– Fault collection and control unit
– Frequency modulated phase locked loop
– Interrupt controller
– Internal RC oscillator
– Joint Test Action Group interface
– Mode entry, clock, reset, & power
– Peripheral I/O bridge
– Periodic interrupt timer
PMU
PWM
RC
RTC
SEMA4
SIUL
SPI
SSCM
STM
SWG
SWT
TSENS
UART/LIN
WKPU
XOSC
– Power management unit
– Pulse width modulator module
– Redundancy checker
– Real time clock
– Semaphore unit
– System integration unit lite
– Serial peripherals interface controller
– System status and configuration module
– System timer module
– Sine wave generator
– Software watchdog timer
– Temperature sensor
– Universal asynchronous receiver/transmitter/
local interconnect network
– Wakeup unit
– Crystal oscillator
Figure 2. PXS20 block diagram (continued)
1.5
1.5.1
Feature details
High-Performance e200z4d Core
The e200z4d Power Architecture® core provides the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
2 independent execution units, both supporting fixed-point and floating-point operations
Dual issue 32-bit Power Architecture® technology compliant
— 5-stage pipeline (IF, DEC, EX1, EX2, WB)
— In-order execution and instruction retirement
Full support for Power Architecture® instruction set and Variable Length Encoding (VLE)
— Mix of classic 32-bit and 16-bit instruction allowed
— Optimization of code size possible
Thirty-two 64-bit general purpose registers (GPRs)
Harvard bus (32-bit address, 64-bit data)
— I-Bus interface capable of one outstanding transaction plus one piped with no wait-on-data return
— D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
— 4 KB, 256-bit cache line (programmable for 2- or 4-way)
No data cache
16-entry MMU
8-entry branch table buffer
Branch look-ahead instruction buffer to accelerate branching
Dedicated branch address calculator
3 cycles worst case for missed branch
Load/store unit
— Fully pipelined
— Single-cycle load latency
— Big- and little-endian modes supported
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
7
Preliminary—Subject to Change Without Notice
Introduction
•
•
•
•
•
•
•
1.5.2
— Misaligned access support
— Single stall cycle on load to use
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine cycles)
Single precision floating-point unit
— 1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
— Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 × 32 division
— Special square root and min/max function implemented
Signal processing support: APU-SPE 1.1
— Support for vectorized mode: as many as two floating-point instructions per clock
Vectored interrupt support
Reservation instruction to support read-modify-write constructs
Extensive system development and tracing support via Nexus debug port
Crossbar Switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave port, although one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting
that slave port are stalled until the higher priority master completes its transactions.
The crossbar provides the following features:
•
•
•
•
4 masters and 3 slaves supported per each replicated crossbar
— Masters allocation for each crossbar: e200z4d core with two independent bus interface units (BIU) for I and D
access (2 masters), one eDMA, one FlexRay
— Slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum
flexibility to handle Instruction and Data array, one redundant SRAM controller with 1 slave port each and 1
redundant peripheral bus bridge
32-bit address bus and 64-bit data bus
Programmable arbitration priority
— Requesting masters can be treated with equal priority and are granted access to a slave port in round-robin method,
based upon the ID of the last master to be granted access or a priority order can be assigned by software at
application run time
Temporary dynamic priority elevation of masters
The XBAR is replicated for each processor.
1.5.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each master (eDMA, FlexRay, CPU) can be
assigned different access rights to each region.
•
•
16-region MPU with concurrent checks against each master access
32-byte granularity for protected address region
The memory protection unit is replicated for each processor.
PXS20 Microcontroller Data Sheet, Rev. 1
8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
1.5.4
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware microarchitecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is used to minimize the overall block size.
The eDMA module provides the following features:
•
•
•
•
•
•
•
•
•
16 channels supporting 8-, 16-, and 32-bit value single or block transfers
Support variable sized queues and circular buffered queue
Source and destination address registers independently configured to post-increment or stay constant
Support major and minor loop offset
Support minor and major loop done signals
DMA task initiated either by hardware requestor or by software
Each DMA task can optionally generate an interrupt at completion and retirement of the task
Signal to indicate closure of last minor loop
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processor.
1.5.5
On-Chip Flash Memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory (NVM) can be used for instruction
storage or data storage, or both. The flash memory module interfaces with the system bus through a dedicated flash memory
array controller. It supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow no-wait responses. Buffer misses incur a 3 wait
state response at 120 MHz.
The flash memory module provides the following features
•
•
•
•
•
•
•
•
1.5.6
1 MB of flash memory in unique multi-partitioned hard macro
Sectorization: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
EEPROM emulation (in software) within same module but on different partition
16 KB test sector and 16 KB shadow sector for test, censorship device and user option bits
Wait states:
— 3 wait states at 120 MHz
— 2 wait states at 80 MHz
— 1 wait state at 60 MHz
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
1-bit error correction, 2-bit error detection
On-Chip SRAM with ECC
The PXS20 SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to have the highest possible diagnostic
coverage including the array internal address decoder.
The SRAM module provides the following features:
•
System SRAM: 128 KB
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
9
Preliminary—Subject to Change Without Notice
Introduction
•
•
•
1.5.7
ECC on 32-bit word (syndrome of 7 bits)
— ECC covers SRAM bus address
1-bit error correction, 2-bit error detection
Wait states:
— 1 wait state at 120 MHz
— 0 wait states at 80 MHz and 60 MHz
Platform Flash Memory Controller
The following list summarizes the key features of the flash memory controller:
•
•
•
•
•
•
•
•
•
•
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned reads within the 32-bit container
are supported. Only aligned word writes are supported.
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each bank.
Code flash (bank0) interface provides configurable read buffering and page prefetch support.
— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized
flash access.
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a
least-recently-used replacement algorithm to maximize performance.
Data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash page. This logic supports
single-cycle read responses (0 AHB data-phase wait states) for accesses that hit in the holding register.
— No prefetch support is provided for this bank.
Programmable response for read-while-write sequences including support for stall-while-write, optional stall
notification interrupt, optional flash operation abort , and optional abort notification interrupt.
Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of
platforms and frequencies.
Support of address-based read access timing for emulation of other memory types.
Support for reporting of single- and multi-bit error events.
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
•
•
•
XBAR Slave Port (64-bit data path)
ECSM (ECC Error Reporting, error injection and configuration)
SRAM array
The following functions are implemented:
•
•
•
ECC encoding (32-bit boundary for data and complete address bus)
ECC decoding (32-bit boundary and entire address)
Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
PXS20 Microcontroller Data Sheet, Rev. 1
10
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
1.5.9
Memory Subsystem Access Time
Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower
memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the
slave being accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of memory accesses.
Table 2. Platform Memory Access Time Summary
AHB transfer
Data phase
wait states
Description
e200z4d instruction fetch
0
Flash memory prefetch buffer hit (page hit)
e200z4d instruction fetch
3
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
e200z4d data read
0–1
SRAM read
e200z4d data write
0
SRAM 32-bit write
e200z4d data write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
e200z4d data write
0–2
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d flash memory read
0
Flash memory prefetch buffer hit (page hit)
e200z4d flash memory read
3
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
1.5.10
Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform memories (flash memory and SRAM).
It does not implement the actual ECC calculation. A detected error (double error for flash memory or SRAM) is also reported
to the FCCU. The following errors and indications are reported into the ECSM dedicated registers:
•
•
•
•
ECC error status and configuration for flash memory and SRAM
ECC error reporting for flash memory
ECC error reporting for SRAM
ECC error injection for SRAM
1.5.11
Peripheral Bridge (PBRIDGE)
The PBRIDGE implements the following features:
•
•
•
•
•
Duplicated periphery
Master access right per peripheral (per master: read access enable; write access enable)
Write buffering for peripherals
Checker applied on PBRIDGE output toward periphery
Byte endianess swap capability
1.5.12
Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time
systems.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
11
Preliminary—Subject to Change Without Notice
Introduction
For high-priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can
be raised temporarily so that all tasks which share the resource can not preempt each other.
The INTC provides the following features:
•
•
•
•
Duplicated periphery
Unique 9-bit vector per interrupt source
16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
Priority elevation for shared resource
The INTC is replicated for each processor.
1.5.13
System Clocks and Clock Generation
The following list summarizes the system clock and clock generation on this device:
•
•
•
•
•
•
•
•
Lock status continuously monitored by lock detect circuitry
Loss-of-clock (LOC) detection for reference and feedback clocks
On-chip loop filter (for improved electromagnetic interference performance and fewer external components required)
Programmable output clock divider of system clock (1, 2, 4, 8)
PWM module and as many as three eTimer modules running on an auxiliary clock independent from system clock
(with max frequency 120 MHz)
On-chip crystal oscillator with automatic level control
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
— Supports automated frequency trimming by hardware during device startup and by user application
Auxiliary clock domain for motor control periphery (PWM, eTimer, CTU, ADC, and SWG)
1.5.14
Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL multiplication factor,
output clock divider ratio are all software configurable. The FMPLLs have the following major features:
•
•
•
•
•
•
•
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
Voltage controlled oscillator (VCO) range: 256–512 MHz
Frequency modulation via software control to reduce and control emission peaks
— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register
— Modulation frequency: triangular modulation with 25 kHz nominal rate
Option to switch modulation on and off via software interface
Reduced frequency divider (RFD) for reduced frequency operation without re-lock
3 modes of operation
— Bypass mode
— Normal FMPLL mode with crystal reference (default)
— Normal FMPLL mode with external reference
Lock monitor circuitry with lock status
PXS20 Microcontroller Data Sheet, Rev. 1
12
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
•
•
•
•
Loss-of-lock detection for reference and feedback clocks
Self-clocked mode (SCM) operation
On-chip loop filter
Auxiliary FMPLL
— Used for FlexRay due to precise symbol rate requirement by the protocol
— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies
of operation for PWM and timers and jitter-free control
— Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in
electric motor control loop
— Allows to run motor control periphery at different (precisely lower, equal or higher as required) frequency than
the system to ensure higher resolution
1.5.15
Main Oscillator
The main oscillator provides these features:
•
•
•
•
Input frequency range 4–40 MHz
Crystal input mode
External reference clock (3.3 V) input mode
FMPLL reference
1.5.16
Internal Reference Clock (RC) Oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor is compared to the stable bandgap
reference voltage. The RC oscillator is the device safe clock.
The RC oscillator provides these features:
•
•
•
•
Nominal frequency 16 MHz
±5% variation over voltage and temperature after process trim
Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the
FMPLL
RC oscillator is used as the default system clock during startup and can be used as back-up input source of FMPLL(s)
in case XOSC fails
1.5.17
Clock, Reset, Power Mode, and Test Control Modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
•
•
•
•
Clock gating and clock distribution control
Halt, stop mode control
Flexible configurable system and auxiliary clock dividers
Various execution modes
— Reset, Idle, Test, Safe
— Various RUN modes with software selectable powered modules
— No stand-by mode implemented (no internal switchable power domains)
1.5.18
Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features:
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
13
Preliminary—Subject to Change Without Notice
Introduction
•
•
•
4 general purpose interrupt timers
32-bit counter resolution
Can be used for software tick or DMA trigger operation
1.5.19
System Timer Module (STM)
The STM implements the following features:
•
Up-counter with 4 output compare registers
The STM is replicated for each processor.
1.5.20
Software Watchdog Timer (SWT)
This module implements the following features:
•
•
•
•
•
Fault tolerant output
Safe internal RC oscillator as reference clock
Windowed watchdog
Program flow control monitor with 16-bit pseudorandom key generation
Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21
Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
•
•
•
•
Redundant collection of hardware checker results
Redundant collection of error information and latch of faults from critical modules on the device
Collection of self-test results
Configurable and graded fault control
— Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset, or Safe mode entered)
— External reaction (failure is reported to the external/surrounding system via configurable output pins)
1.5.22
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal
peripheral multiplexing, and system reset operation. The reset configuration block contains the external pin boot configuration
logic. The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform
and discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
•
•
Centralized pad control on a per-pin basis
— Pin function selection
— Configurable weak pull-up/down
— Configurable slew rate control (slow/medium/fast)
— Hysteresis on GPIO pins
— Configurable automatic safe mode pad control
Input filtering for external interrupts
PXS20 Microcontroller Data Sheet, Rev. 1
14
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
1.5.23
Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
1.5.24
Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is executed only if serial booting mode
is selected via boot configuration pins.
The BAM provides the following features:
•
•
•
•
Enables booting via serial mode (CAN or LIN/UART)
Supports programmable 64-bit password protection for serial boot mode
Supports serial bootloading of either classic PowerPC Book E code (default) or Freescale VLE code
Automatic switch to serial boot mode if internal flash memory is blank or invalid
1.5.25
System Status and Configuration Module (SSCM)
The SSCM on this device features the following:
•
•
•
•
•
System configuration and status
Debug port status and debug port enable
Multiple boot code starting locations out of reset through implementation of search for valid Reset Configuration Half
Word
Sets up the MMU to allow user boot code to execute as either classic PowerPC Book E code (default) or as Freescale
VLE code out of flash memory
Triggering of device self-tests during reset phase of device boot
1.5.26
Controller Area Network Module (CAN)
The CAN module is a communication controller implementing the CAN protocol according to Bosch Specification version
2.0B. Although the CAN interface was designed to be used primarily as a vehicle networking bus, it is widely used in industrial
and other transport applications due to its robust operation, time determinism, cost effectiveness, and optional redundant
physical layer implementation.
The CAN module provides the following features:
•
•
•
•
•
•
•
•
•
•
•
Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— 0 to 8 bytes data length
— Programmable bit rate as fast as 1Mbit/s
32 message buffers of 0 to 8 bytes data length
Each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages
Programmable loop-back mode supporting self-test operation
3 programmable mask registers
Programmable transmit-first scheme: lowest ID or lowest buffer number
Time stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Independent of the transmission medium (an external transceiver is assumed)
High immunity to EMI
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
15
Preliminary—Subject to Change Without Notice
Introduction
•
•
•
•
Short latency time due to an arbitration scheme for high-priority messages
Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
Receive features
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a 6-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
Programmable clock source
— System clock
— Direct oscillator clock to avoid FMPLL jitter
1.5.27
FlexRay
The FlexRay module provides the following features:
•
•
•
•
•
•
•
•
•
Full implementation of FlexRay Protocol Specification 2.1 Rev. A
64 configurable message buffers can be handled
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
Message buffers configurable as transmit or receive
Message buffer size configurable
Message filtering for all message buffers based on Frame ID, cycle count, and message ID
Programmable acceptance filters for receive FIFO
Message buffer header, status, and payload data stored in system memory (SRAM)
Internal FlexRay memories have error detection and correction
1.5.28
Serial Communication Interface Module (UART)
The UART module with DMA support on this device features the following:
•
•
UART features:
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
– Parity, noise and framing errors
— Interrupt driven operation with 4 interrupts sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— 2 receiver wake-up methods
LIN features:
— Autonomous LIN frame handling
— Message buffer to store identifier and up to eight data bytes
— Supports message length of up to 64 bytes
— Detection and flagging of LIN errors
PXS20 Microcontroller Data Sheet, Rev. 1
16
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
—
—
—
—
—
Sync field; Delimiter; ID parity; Bit, Framing; Checksum and Timeout errors
Classic or extended checksum calculation
Configurable Break duration of up to 36-bit times
Programmable Baud rate prescalers (13-bit mantissa, 4-bit fractional)
Diagnostic features
– Loop back
– Self Test
– LIN bus stuck dominant detection
— Interrupt driven operation with 16 interrupt sources
— LIN slave mode features
– Autonomous LIN header handling
– Autonomous LIN response handling
– Discarding of irrelevant LIN responses using up to 16 ID filters
1.5.29
Serial Peripheral Interface (SPI)
The SPI modules provide a synchronous serial interface for communication between the PXS20 and external devices.
A SPI module provides these features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
As many as 8 chip select lines available, depending on package and pin multiplexing
4 clock and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for de-glitching
FIFOs for buffering as many as 5 transfers on the transmit and receive side
Queueing operation possible through use of the eDMA
General purpose I/O functionality on pins when not used for SPI
1.5.30
Pulse Width Modulator (PWM)
The PWM module contains four PWM channels, each of which is configured to control a single half-bridge power stage. Two
modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is present. Additionally, four
fault input channels are provided per PWM module.
This PWM is capable of controlling most motor types, including:
•
•
•
•
•
AC induction motors (ACIM)
Permanent Magnet AC motors (PMAC)
Brushless (BLDC) and brush DC motors (BDC)
Switched (SRM) and variable reluctance motors (VRM)
Stepper motors
A PWM module implements the following features:
•
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
17
Preliminary—Subject to Change Without Notice
Introduction
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum operating frequency as high as 120 MHz
— Clock source not modulated and independent from system clock (generated via secondary FMPLL)
Fine granularity control for enhanced resolution of the PWM period
PWM outputs can operate as complementary pairs or independent channels
Ability to accept signed numbers for PWM generation
Independent control of both edges of each PWM output
Synchronization to external hardware or other PWM supported
Double buffered PWM registers
— Integral reload rates from 1 to 16
— Half cycle reload capability
Multiple ADC trigger events can be generated per PWM cycle via hardware
Fault inputs can be assigned to control multiple PWM outputs
Programmable filters for fault inputs
Independently programmable PWM output polarity
Independent top and bottom deadtime insertion
Each complementary pair can operate with its own PWM frequency and deadtime values
Individual software control for each PWM output
All outputs can be forced to a value simultaneously
PWMX pin can optionally output a third signal from each channel
Channels not used for PWM generation can be used for buffered output compare functions
Channels not used for PWM generation can be used for input capture functions
Enhanced dual edge capture functionality
Option to supply the source for each complementary PWM signal pair from any of the following:
— External digital pin
— Internal timer channel
— External ADC input, taking into account values set in ADC high- and low-limit registers
DMA support
1.5.31
eTimer Module
The PXS20 provides three eTimer modules on the 257 MAPBGA device, and two eTimer modules on the 144 LQFP package.
Six 16-bit general purpose up/down timer/counters per module are implemented with the following features:
•
•
•
•
•
Maximum clock frequency of 120 MHz
Individual channel capability
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
Maximum count rate
— Equals peripheral clock divided by 2 for external event counting
— Equals peripheral clock for internal clock counting
Cascadeable counters
Programmable count modulo
PXS20 Microcontroller Data Sheet, Rev. 1
18
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
•
•
•
•
•
•
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Preloadable counters
Pins available as GPIO when timer functionality not in use
DMA support
1.5.32
Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).
•
•
Frequency range from 1 kHz to 50 kHz
Sine wave amplitude from 0.47 V to 2.26 V
1.5.33
Analog-to-Digital Converter Module (ADC)
The ADC module features include:
Analog part:
•
2 on-chip ADCs
— 12-bit resolution SAR architecture
— A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels)
— One channel dedicated to each T-sensor to enable temperature reading during application
— Separated reference for each ADC
— Shared analog supply voltage for both ADCs
— One sample and hold unit per ADC
— Adjustable sampling and conversion time
Digital part:
•
•
•
•
•
4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location
2 modes of operation: Motor Control Mode or Regular Mode
Regular mode features
— Register based interface with the CPU: one result register per channel
— ADC state machine managing three request flows: regular command, hardware injected command, software
injected command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
Motor control mode features
— Triggered mode only
— 4 independent result queues (1  16 entries, 2  8 entries, 1  4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit parts
— DMA compatible interfaces
Built-in self-test features triggered by software
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
19
Preliminary—Subject to Change Without Notice
Introduction
1.5.34
Junction Temperature Sensor
The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device
junction temperature.
The key parameters of the junction temperature sensor include:
•
•
Nominal temperature range from –40 to 150 °C
Software temperature alarm via analog ADC comparator possible
1.5.35
Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without
CPU load during the PWM period and with minimized CPU load for dynamic configuration.
The CTU implements the following features:
•
•
•
•
•
•
•
•
•
•
•
Cross triggering between ADC, PWM, eTimer, and external pins
Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers
Maximum operating frequency less than or equal to 120 MHz
Trigger generation unit configurable in sequential mode or in triggered mode
Trigger delay unit to compensate the delay of external low pass filter
Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
Double buffered ADC command list pointers to minimize ADC-trigger unit update
Double buffered ADC conversion command list with as many as 24 ADC commands
Each trigger capable of generating consecutive commands
ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
DMA support with safety features
1.5.36
Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register.
The CRC unit has the following features:
•
•
•
•
•
•
3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable
polynomial and seed
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register.
The following standard CRC polynomials are implemented:
— x16 + x12 + x5 + 1 [16-bit CRC-CCITT]
— x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
[32-bit CRC-ethernet(32)]
Key engine to be coupled with communication periphery where CRC application is added to allow implementation of
safe communication protocol
Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic
procedures
CRC unit connected as peripheral bus on internal peripheral bus
DMA support
1.5.37
Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:
PXS20 Microcontroller Data Sheet, Rev. 1
20
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Introduction
•
•
Duplicated module to guarantee highest possible diagnostic coverage (check of checker)
Multiple times replicated IPs are used as checkers on the SoR outputs
1.5.38
Voltage Regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features:
•
•
•
•
Single external rail required
Single high supply required: nominal 3.3 V for packaged option
— Packaged option requires external ballast transistor due to reduced dissipation capacity at high temperature but
can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower
frequency of operation)
All I/Os are at same voltage as external supply (3.3 V nominal)
Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages (reset, configuration, normal
operation) and, to maximize safety coverage, one LVD can be tested while the other operates (on-line self-testing
feature)
1.5.39
Built-In Self-Test (BIST) Capability
This device includes the following protection against latent faults:
•
•
•
•
Boot-time Memory Built-In Self-Test (MBIST)
Boot-time scan-based Logic Built-In Self-Test (LBIST)
Run-time ADC Built-In Self-Test (BIST)
Run-time Built-In Self Test of LVDs
1.5.40
IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while remaining transparent to system logic
when not in test mode. All data input to and output from the JTAGC block is communicated in serial format. The JTAGC block
is compliant with the IEEE standard.
The JTAG controller provides the following features:
•
•
•
•
•
IEEE Test Access Port (TAP) interface with 5 pins:
— TDI
— TMS
— TCK
— TDO
— JCOMP
Selectable modes of operation include JTAGC/debug or normal system operation
5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS
— IDCODE
— EXTEST
— SAMPLE
— SAMPLE/PRELOAD
3 test data registers: a bypass register, a boundary scan register, and a device identification register. The size of the
boundary scan register is parameterized to support a variety of boundary scan chain lengths.
TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
21
Preliminary—Subject to Change Without Notice
Introduction
1.5.41
Nexus Port Controller (NPC)
The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO
5001-2008 standard. This development support is supplied for MCUs without requiring external address and data pins for
internal visibility.
The NPC block interfaces to the host processor and internal buses to provide development support as per the IEEE-ISTO
5001-2008 Class 3+, including selected features from Class 4 standard.
The development support provided includes program trace, data trace, watchpoint trace, ownership trace, run-time access to the
MCUs internal memory map and access to the Power Architecture® internal registers during halt. The Nexus interface also
supports a JTAG only mode using only the JTAG pins. The following features are implemented:
•
Full and reduced port modes
•
MCKO (message clock out) pin
•
4 or 12 MDO (message data out) pins1
•
2 MSEO (message start/end out) pins
•
EVTO (event out) pin
— Auxiliary input port
•
EVTI (event in) pin
•
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
— Supports JTAG mode
•
Host processor (e200) development support features
— Data trace via data write messaging (DWM) and data read messaging (DRM). This allows the development tool
to trace reads or writes, or both, to selected internal memory resources.
— Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership trace by providing visibility
of which process ID or operating system task is activated. An ownership trace message is transmitted when a
new process/task is activated, allowing development tools to trace ownership flow.
— Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities
(direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what
transpires between the discontinuities. Thus, static code may be traced.
— Watchpoint messaging (WPM) via the auxiliary port
— Watchpoint trigger enable of program and/or data trace messaging
— Data tracing of instruction fetches via private opcodes
1. 4 MDO pins on 144 LQFP package, 12 MDO pins on 257 MAPBGA package.
PXS20 Microcontroller Data Sheet, Rev. 1
22
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 LQFP package
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
D[12]
G[6]
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
D[10]
G[11]
A[1]
A[0]
D[7]
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
C[1]
E[4]
B[7]
E[5]
C[2]
E[6]
B[8]
E[7]
E[2]
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
E[9]
B[15]
E[10]
B[14]
E[11]
C[0]
E[12]
E[0]
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NMI
A[6]
D[1]
F[4]
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
A[15]
A[14]
C[6]
FCCU_F[1]
D[2]
F[3]
B[6]
VSS_LV_COR
A[13]
VDD_LV_COR
A[9]
F[0]
VSS_LV_COR
VDD_LV_COR
VDD_HV_REG_2
D[4]
D[3]
VSS_HV_IO
VDD_HV_IO
D[0]
C[15]
JCOMP
A[12]
E[15]
A[11]
E[14]
A[10]
E[13]
B[3]
F[14]
B[2]
F[15]
F[13]
C[10]
B[1]
B[0]
Figure 3 shows the PXS20 in the 144 LQFP package.
Figure 3. PXS20 144 LQFP pinout (top view)
Figure 4 shows the PXS20 in the 257 MAPBGA package.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
23
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
1
2
3
A
VSS
VSS
VDD_HV
B
VSS
VSS
B[6]
C
VDD_HV
NC1
VSS
D
F[5]
F[4]
A[15]
6
7
8
9
10
11
12
13
14
15
16
17
H[0]
G[14]
D[3]
C[15]
VDD_HV
A[12]
H[10]
H[14]
A[10]
B[2]
C[10]
VSS
VSS
F[3]
A[9]
D[4]
D[0]
VSS
H[12]
E[15]
E[14]
B[3]
F[13]
B[0]
VDD_HV
VSS
FCCU_
F[1]
D[2]
A[13]
I[0]
JCOMP
H[11]
I[1]
F[14]
B[1]
VSS
A[4]
F[12]
C[6]
VSS
VDD_LV
VSS
A[11]
E[13]
F[15]
VDD_HV
VPP
NC
D[14]
G[3]
H[2]
A[14]
VDD_HV VDD_HV
F[0]
VDD_HV
MDO0
F[6]
D[1]
NMI
F
H[1]
G[12]
A[7]
A[8]
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
G
H[3]
VDD_HV
C[5]
A[6]
VDD_LV
VSS
VSS
VSS
VSS
VSS
H
G[13]
VSS
C[4]
A[5]
VDD_LV
VSS
VSS
VSS
VSS
J
F[7]
G[15]
VDD_LV
VSS
VSS
VSS
K
F[9]
F[8]
See
note2
C[7]
VDD_LV
VSS
VSS
L
F[10]
F[11]
D[9]
NC
VDD_LV
VSS
VSS
D[8]
NC
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
VSS
D[5]
VSS_LV_
VSS
RESET
D[6]
EXTAL
FCCU
_F[0]
VSS
D[7]
VSS
VDD_HV
NC
C[1]
VSS
VSS
NC
1
2
3
N
P
R
T
U
2
5
E
M
1
4
VDD_HV VDD_HV
XTAL
VDD_HV VDD_HV
_TEST
NC
C[14]
G[2]
I[3]
NC
C[13]
I[2]
G[4]
VDD_LV
D[12]
H[13]
H[9]
G[6]
VSS
VDD_LV
VSS
VSS
VSS
VDD_LV
VSS
VSS
VSS
VDD_LV
NC
VSS
VSS
VSS
VDD_LV
VDD_HV VDD_HV
VDD_LV VDD_HV
H[6]
VSS
H[15]
H[8]
H[7]
A[3]
NC
TCK
H[4]
B[4]
C[11]
B[5]
TMS
H[5]
NC
C[12]
A[2]
G[5]
PLL
VDD_LV_
PLL
VDD_LV
VSS
B[8]
NC
VSS
VDD_HV
B[14]
VDD_LV
VSS
VDD_HV
G[10]
G[8]
G[7]
B[7]
E[6]
VREFP_
B[10]
VREFP_
B[13]
B[15]
C[0]
BCTRL
A[1]
VSS
D[11]
G[9]
E[9]
E[10]
E[12]
E[0]
A[0]
D[10]
VDD_HV
VSS
HV_AD0
E[5]
E[7]
VREFN_
HV_AD1
B[11]
HV_AD0
VREFN_
HV_AD1
E[4]
C[2]
E[2]
B[9]
B[12]
VDD_HV
VSS
E[11]
NC
NC
VDD_HV
G[11]
VSS
VSS
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC = Not connected (the pin is physically not connected to anything on the device)
Pin K3 is NC on cut1 and RDY on cut2/3.
Figure 4. PXS20 257 MAPBGA pinout (top view)
Table 3 and Table 4 provide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the
signals multiplexed to each pin.
PXS20 Microcontroller Data Sheet, Rev. 1
24
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary
Pin #
Port/function
1
NMI
2
A[6]
3
4
5
Peripheral
Output function
—
D[1]
F[4]
F[5]
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
SIUL
GPIO[84]
GPIO[84]
NPC
MDO[3]
—
SIUL
GPIO[85]
GPIO[85]
NPC
MDO[2]
—
6
VDD_HV_IO
—
7
VSS_HV_IO
—
8
F[6]
9
MDO0
10
A[7]
11
12
13
C[4]
A[8]
C[5]
Input function
SIUL
GPIO[86]
GPIO[86]
NPC
MDO[1]
—
—
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
25
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
14
A[5]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
15
C[7]
16
VDD_HV_REG_0
—
17
VSS_LV_COR
—
18
VDD_LV_COR
—
19
F[7]
20
F[8]
SIUL
GPIO[87]
GPIO[87]
NPC
MCKO
—
SIUL
GPIO[88]
GPIO[88]
NPC
MSEO[1]
—
21
VDD_HV_IO
—
22
VSS_HV_IO
—
23
F[9]
24
25
26
F[10]
F[11]
D[9]
SIUL
GPIO[89]
GPIO[89]
NPC
MSEO[0]
—
SIUL
GPIO[90]
GPIO[90]
NPC
EVTO
—
SIUL
GPIO[91]
GPIO[91]
NPC
EVTI
—
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
27
VDD_HV_OSC
—
28
VSS_HV_OSC
—
29
XTALIN
—
30
XTALOUT
—
31
RESET
—
PXS20 Microcontroller Data Sheet, Rev. 1
26
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
32
D[8]
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
33
D[5]
34
D[6]
35
VSS_LV_PLL0_PLL1
—
36
VDD_LV_PLL0_PLL1
—
37
D[7]
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
analog output
—
FCCU
F[0]
F[0]
38
FCCU_F[0]
39
VDD_LV_COR
—
40
VSS_LV_COR
—
41
C[1]
42
43
44
45
46
E[4]
B[7]
E[5]
C[2]
E[6]
SIUL
—
GPIO[33]
ADC_0
—
AN[2]
SIUL
—
GPIO[68]
ADC_0
—
AN[7]
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[69]
ADC_0
—
AN[8]
SIUL
—
GPIO[34]
ADC_0
—
AN[3]
SIUL
—
GPIO[70]
ADC_0
—
AN[4]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
27
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
47
B[8]
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
SIUL
—
GPIO[71]
ADC_0
—
AN[6]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
48
49
E[7]
E[2]
50
VDD_HV_ADR0
—
51
VSS_HV_ADR0
—
52
B[9]
53
54
55
B[10]
B[11]
B[12]
SIUL
—
GPIO[25]
ADC_0
ADC_1
—
AN[11]
SIUL
—
GPIO[26]
ADC_0
ADC_1
—
AN[12]
SIUL
—
GPIO[27]
ADC_0
ADC_1
—
AN[13]
SIUL
—
GPIO[28]
ADC_0
ADC_1
—
AN[14]
56
VDD_HV_ADR1
—
57
VSS_HV_ADR1
—
58
VDD_HV_ADV
—
59
VSS_HV_ADV
—
60
B[13]
61
62
63
E[9]
B[15]
E[10]
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[73]
ADC_1
—
AN[7]
SIUL
—
GPIO[31]
SIUL
—
EIRQ[20]
ADC_1
—
AN[2]
SIUL
—
GPIO[74]
ADC_1
—
AN[8]
PXS20 Microcontroller Data Sheet, Rev. 1
28
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
64
B[14]
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
SIUL
—
GPIO[75]
ADC_1
—
AN[4]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
SIUL
—
GPIO[76]
ADC_1
—
AN[6]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
65
66
67
68
E[11]
C[0]
E[12]
E[0]
69
BCTRL
—
70
VDD_LV_COR
—
71
VSS_LV_COR
—
72
VDD_HV_PMU
—
73
A[0]
74
75
76
77
A[1]
G[11]
D[10]
G[10]
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
SIUL
GPIO[107]
GPIO[107]
FlexRay
DBG3
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
SIUL
GPIO[106]
GPIO[106]
FlexRay
DBG2
—
DSPI_2
CS3
—
FlexPWM_0
—
FAULT[2]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
29
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
78
D[11]
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[105]
GPIO[105]
FlexRay
DBG1
—
DSPI_1
CS1
—
FlexPWM_0
—
FAULT[1]
SIUL
—
EIRQ[29]
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[104]
GPIO[104]
FlexRay
DBG0
—
DSPI_0
CS1
—
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[21]
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[103]
GPIO[103]
FlexPWM_0
B[3]
B[3]
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
SIUL
GPIO[101]
GPIO[101]
FlexPWM_0
X[3]
X[3]
DSPI_2
CS3
—
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
79
80
81
82
83
84
85
86
G[9]
C[11]
G[8]
C[12]
G[7]
A[2]
G[5]
B[5]
87
TMS
—
88
TCK
—
PXS20 Microcontroller Data Sheet, Rev. 1
30
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
89
B[4]
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
90
VSS_HV_IO
—
91
VDD_HV_IO
—
92
A[3]
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
93
VDD_LV_COR
—
94
VSS_LV_COR
—
95
VDD_HV_REG_1
—
96
VSS_HV_FLA
—
97
VDD_HV_FLA
—
98
G[6]
99
100
101
102
103
D[12]
G[4]
C[13]
G[2]
C[14]
SIUL
GPIO[102]
GPIO[102]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[100]
GPIO[100]
FlexPWM_0
B[2]
B[2]
eTimer_0
—
ETC[5]
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[98]
GPIO[98]
FlexPWM_0
X[2]
X[2]
DSPI_1
CS1
—
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
31
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
104
G[3]
SIUL
GPIO[99]
GPIO[99]
FlexPWM_0
A[2]
A[2]
eTimer_0
—
ETC[4]
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
SIUL
GPIO[92]
GPIO[92]
eTimer_1
ETC[3]
ETC[3]
SIUL
—
EIRQ[30]
105
106
D[14]
F[12]
107
VPP_TEST
108
A[4]
109
110
111
112
B[0]
B[1]
C[10]
F[13]
1
—
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
SIUL
GPIO[93]
GPIO[93]
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[31]
PXS20 Microcontroller Data Sheet, Rev. 1
32
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
113
F[15]
SIUL
GPIO[95]
GPIO[95]
LINFlexD_1
—
RXD
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
—
SIUL
—
EIRQ[17]
SIUL
GPIO[94]
GPIO[94]
LINFlexD_1
TXD
—
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
—
LINFlexD_0
—
RXD
SIUL
GPIO[77]
GPIO[77]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
—
EIRQ[25]
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[78]
GPIO[78]
eTimer_1
ETC[5]
ETC[5]
SIUL
—
EIRQ[26]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
SIUL
GPIO[79]
GPIO[79]
DSPI_0
CS1
—
SIUL
—
EIRQ[27]
114
115
116
117
118
119
120
121
B[2]
F[14]
B[3]
E[13]
A[10]
E[14]
A[11]
E[15]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
33
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
122
A[12]
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
123
JCOMP
—
—
JCOMP
124
C[15]
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
125
D[0]
126
VDD_HV_IO
—
127
VSS_HV_IO
—
128
D[3]
129
D[4]
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
130
VDD_HV_REG_2
—
131
VDD_LV_COR
—
132
VSS_LV_COR
—
133
F[0]
SIUL
GPIO[80]
GPIO[80]
FlexPWM_0
A[1]
A[1]
eTimer_0
—
ETC[2]
SIUL
—
EIRQ[28]
PXS20 Microcontroller Data Sheet, Rev. 1
34
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
134
A[9]
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
135
VDD_LV_COR
136
A[13]
137
VSS_LV_COR
138
B[6]
139
140
F[3]
D[2]
—
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
—
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
SIUL
GPIO[83]
GPIO[83]
DSPI_0
CS6
—
SIUL
GPIO[50]
GPIO[50]
eTimer_1
ETC[3]
ETC[3]
FlexPWM_0
X[3]
X[3]
FlexRay
—
CB_RX
141
FCCU_F[1]
FCCU
F[1]
F[1]
142
C[6]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
143
A[14]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
35
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 3. 144 LQFP pin function summary (continued)
1
Pin #
Port/function
Peripheral
Output function
Input function
144
A[15]
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4. 257 MAPBGA pin function summary
Pin #
Port/function
A1
VSS_HV_IO_RING
—
A2
VSS_HV_IO_RING
—
A3
VDD_HV_IO_RING
—
A4
H[2]
A5
A6
A7
A8
Peripheral
H[0]
G[14]
D[3]
C[15]
A9
VDD_HV_IO_RING
A10
A[12]
Output function
Input function
SIUL
GPIO[114]
GPIO[114]
NPC
MDO[5]
—
SIUL
GPIO[112]
GPIO[112]
NPC
MDO[7]
—
SIUL
GPIO[110]
GPIO[110]
NPC
MDO[9]
—
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
—
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
PXS20 Microcontroller Data Sheet, Rev. 1
36
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
A11
H[10]
SIUL
GPIO[122]
GPIO[122]
FlexPWM_1
X[2]
X[2]
eTimer_2
ETC[2]
ETC[2]
SIUL
GPIO[126]
GPIO[126]
FlexPWM_1
A[3]
A[3]
eTimer_2
ETC[4]
ETC[4]
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
—
SIUL
—
EIRQ[17]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
A12
A13
A14
A15
H[14]
A[10]
B[2]
C[10]
A16
VSS_HV_IO_RING
—
A17
VSS_HV_IO_RING
—
B1
VSS_HV_IO_RING
—
B2
VSS_HV_IO_RING
—
B3
B[6]
B4
B5
A[14]
F[3]
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
SIUL
GPIO[83]
GPIO[83]
DSPI_0
CS6
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
37
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
B6
A[9]
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
B7
B8
D[4]
D[0]
B9
VSS_HV_IO_RING
B10
H[12]
B11
B12
B13
B14
B15
E[15]
E[14]
B[3]
F[13]
B[0]
—
SIUL
GPIO[124]
GPIO[124]
FlexPWM_1
B[2]
B[2]
SIUL
GPIO[79]
GPIO[79]
DSPI_0
CS1
—
SIUL
—
EIRQ[27]
SIUL
GPIO[78]
GPIO[78]
eTimer_1
ETC[5]
ETC[5]
SIUL
—
EIRQ[26]
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
—
LINFlexD_0
—
RXD
SIUL
GPIO[93]
GPIO[93]
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[31]
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
B16
VDD_HV_IO_RING
—
B17
VSS_HV_IO_RING
—
C1
VDD_HV_IO_RING
—
PXS20 Microcontroller Data Sheet, Rev. 1
38
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
C2
Not connected
—
C3
VSS_HV_IO_RING
—
C4
FCCU_F[1]
FCCU
F[1]
F[1]
C5
D[2]
SIUL
GPIO[50]
GPIO[50]
eTimer_1
ETC[3]
ETC[3]
FlexPWM_0
X[3]
X[3]
FlexRay
—
CB_RX
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
C6
Peripheral
A[13]
Output function
C7
VDD_HV_REG_2
—
C8
VDD_HV_REG_2
—
C9
I[0]
Input function
SIUL
GPIO[128]
GPIO[128]
eTimer_2
ETC[0]
ETC[0]
DSPI_0
CS4
—
FlexPWM_1
—
FAULT[0]
C10
JCOMP
—
—
JCOMP
C11
H[11]
SIUL
GPIO[123]
GPIO[123]
FlexPWM_1
A[2]
A[2]
SIUL
GPIO[129]
GPIO[129]
eTimer_2
ETC[1]
ETC[1]
DSPI_0
CS5
—
FlexPWM_1
—
FAULT[1]
SIUL
GPIO[94]
GPIO[94]
LINFlexD_1
TXD
—
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
C12
C13
C14
C15
I[1]
F[14]
B[1]
VSS_HV_IO_RING
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
39
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
C16
A[4]
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
SIUL
GPIO[92]
GPIO[92]
eTimer_1
ETC[3]
ETC[3]
SIUL
—
EIRQ[30]
SIUL
GPIO[85]
GPIO[85]
NPC
MDO[2]
—
SIUL
GPIO[84]
GPIO[84]
NPC
MDO[3]
—
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
C17
D1
D2
D3
D4
F[12]
F[5]
F[4]
A[15]
C[6]
D5
VSS_LV_CORE_RING
—
D6
VDD_LV_CORE_RING
—
D7
F[0]
SIUL
GPIO[80]
GPIO[80]
FlexPWM_0
A[1]
A[1]
eTimer_0
—
ETC[2]
SIUL
—
EIRQ[28]
D8
VDD_HV_IO_RING
—
D9
VSS_HV_IO_RING
—
D10
Not connected
—
PXS20 Microcontroller Data Sheet, Rev. 1
40
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
D11
A[11]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
SIUL
GPIO[77]
GPIO[77]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
—
EIRQ[25]
SIUL
GPIO[95]
GPIO[95]
LINFlexD_1
—
RXD
D12
D13
D14
E[13]
F[15]
D15
VPP_TEST
D16
D[14]
D17
1
G[3]
E1
MDO0
E2
F[6]
E3
—
VDD_HV_IO_RING
—
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
SIUL
GPIO[99]
GPIO[99]
FlexPWM_0
A[2]
A[2]
eTimer_0
—
ETC[4]
—
D[1]
SIUL
GPIO[86]
GPIO[86]
NPC
MDO[1]
—
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
E4
NMI
—
E14
Not connected
—
E15
C[14]
E16
G[2]
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
SIUL
GPIO[98]
GPIO[98]
FlexPWM_0
X[2]
X[2]
DSPI_1
CS1
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
41
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
E17
I[3]
SIUL
GPIO[131]
GPIO[131]
eTimer_2
ETC[3]
ETC[3]
DSPI_0
CS7
—
CTU_0
EXT_TGR
—
FlexPWM_1
—
FAULT[3]
SIUL
GPIO[113]
GPIO[113]
NPC
MDO[6]
—
SIUL
GPIO[108]
GPIO[108]
NPC
MDO[11]
—
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
F1
F2
F3
F4
H[1]
G[12]
A[7]
A[8]
F6
VDD_LV_CORE_RING
—
F7
VDD_LV_CORE_RING
—
F8
VDD_LV_CORE_RING
—
F9
VDD_LV_CORE_RING
—
F10
VDD_LV_CORE_RING
—
F11
VDD_LV_CORE_RING
—
F12
VDD_LV_CORE_RING
—
F14
Not connected
—
F15
C[13]
F16
F17
I[2]
G[4]
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[130]
GPIO[130]
eTimer_2
ETC[2]
ETC[2]
DSPI_0
CS6
—
FlexPWM_1
—
FAULT[2]
SIUL
GPIO[100]
GPIO[100]
FlexPWM_0
B[2]
B[2]
eTimer_0
—
ETC[5]
PXS20 Microcontroller Data Sheet, Rev. 1
42
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
G1
H[3]
SIUL
GPIO[115]
GPIO[115]
NPC
MDO[4]
—
G2
VDD_HV_IO_RING
G3
C[5]
G4
A[6]
—
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
G6
VDD_LV_CORE_RING
—
G7
VSS_LV_CORE_RING
—
G8
VSS_LV_CORE_RING
—
G9
VSS_LV_CORE_RING
—
G10
VSS_LV_CORE_RING
—
G11
VSS_LV_CORE_RING
—
G12
VDD_LV_CORE_RING
—
G14
D[12]
G15
G16
G17
H1
H2
H[13]
H[9]
G[6]
G[13]
VSS_HV_IO_RING
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[125]
GPIO[125]
FlexPWM_1
X[3]
X[3]
eTimer_2
ETC[3]
ETC[3]
SIUL
GPIO[121]
GPIO[121]
FlexPWM_1
B[1]
B[1]
DSPI_0
CS7
—
SIUL
GPIO[102]
GPIO[102]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[109]
GPIO[109]
NPC
MDO[10]
—
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
43
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
H3
C[4]
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
H4
A[5]
H6
VDD_LV
—
H7
VSS_LV
—
H8
VSS_LV
—
H9
VSS_LV
—
H10
VSS_LV
—
H11
VSS_LV
—
H12
VDD_LV
—
H14
VSS_LV
—
H15
VDD_HV_REG_1
—
H16
VDD_HV_FLA
—
H17
H[6]
J1
J2
F[7]
G[15]
SIUL
GPIO[118]
GPIO[118]
FlexPWM_1
B[0]
B[0]
DSPI_0
CS5
—
SIUL
GPIO[87]
GPIO[87]
NPC
MCKO
—
SIUL
GPIO[111]
GPIO[111]
NPC
MDO[8]
—
J3
VDD_HV_REG_0
—
J4
VDD_HV_REG_0
—
J6
VDD_LV
—
J7
VSS_LV
—
J8
VSS_LV
—
J9
VSS_LV
—
J10
VSS_LV
—
J11
VSS_LV
—
PXS20 Microcontroller Data Sheet, Rev. 1
44
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
J12
VDD_LV
—
J14
VDD_LV
—
J15
VDD_HV_REG_1
—
J16
VSS_HV_FLA
—
J17
H[15]
K1
K2
F[9]
F[8]
K3
(cut1)
Not connected
K3
(cut2)
RDY
K4
C[7]
Peripheral
Output function
SIUL
GPIO[127]
GPIO[127]
FlexPWM_1
B[3]
B[3]
eTimer_2
ETC[5]
ETC[5]
SIUL
GPIO[89]
GPIO[89]
NPC
MSEO[0]
—
SIUL
GPIO[88]
GPIO[88]
NPC
MSEO[1]
—
—
NPC
RDY
—
SIUL
GPIO[132]
GPIO[132]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
K6
VDD_LV
—
K7
VSS_LV
—
K8
VSS_LV
—
K9
VSS_LV
—
K10
VSS_LV
—
K11
VSS_LV
—
K12
VDD_LV
—
K14
Not connected
—
K15
H[8]
K16
H[7]
Input function
SIUL
GPIO[120]
GPIO[120]
FlexPWM_1
A[1]
A[1]
DSPI_0
CS6
—
SIUL
GPIO[119]
GPIO[119]
FlexPWM_1
X[1]
X[1]
eTimer_2
ETC[1]
ETC[1]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
45
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
K17
A[3]
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
SIUL
GPIO[90]
GPIO[90]
NPC
EVTO
—
SIUL
GPIO[91]
GPIO[91]
NPC
EVTI
—
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
L1
L2
L3
F[10]
F[11]
D[9]
L4
Not connected
—
L6
VDD_LV
—
L7
VSS_LV
—
L8
VSS_LV
—
L9
VSS_LV
—
L10
VSS_LV
—
L11
VSS_LV
—
L12
VDD_LV
—
L14
Not connected
—
L15
TCK
—
L16
H[4]
L17
B[4]
SIUL
GPIO[116]
GPIO[116]
FlexPWM_1
X[0]
X[0]
eTimer_2
ETC[0]
ETC[0]
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
M1
VDD_HV_OSC
—
M2
VDD_HV_IO_RING
—
M3
D[8]
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
PXS20 Microcontroller Data Sheet, Rev. 1
46
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
M4
Not connected
—
M6
VDD_LV
—
M7
VDD_LV
—
M8
VDD_LV
—
M9
VDD_LV
—
M10
VDD_LV
—
M11
VDD_LV
—
M12
VDD_LV
—
M14
C[11]
M15
Peripheral
B[5]
M16
TMS
M17
H[5]
Output function
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
—
SIUL
GPIO[117]
GPIO[117]
FlexPWM_1
A[0]
A[0]
DSPI_0
CS4
—
N1
XTALIN
—
N2
VSS_HV_IO_RING
—
N3
D[5]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
N4
VSS_LV_PLL0_PLL1
—
N14
Not connected
—
N15
C[12]
N16
A[2]
Input function
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
47
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
N17
G[5]
SIUL
GPIO[101]
GPIO[101]
FlexPWM_0
X[3]
X[3]
DSPI_2
CS3
—
P1
VSS_HV_OSC
—
P2
RESET
—
P3
D[6]
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
P4
VDD_LV_PLL0_PLL1
—
P5
VDD_LV_CORE_RING
—
P6
VSS_LV_CORE_RING
—
P7
B[8]
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
P8
Not connected
—
P9
VSS_HV_IO_RING
—
P10
VDD_HV_IO_RING
—
P11
B[14]
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
P12
VDD_LV_CORE_RING
—
P13
VSS_LV_CORE_RING
—
P14
VDD_HV_IO_RING
—
P15
G[10]
P16
G[8]
SIUL
GPIO[106]
GPIO[106]
FlexRay
DBG2
—
DSPI_2
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[104]
GPIO[104]
FlexRay
DBG0
—
DSPI_0
CS1
—
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[21]
PXS20 Microcontroller Data Sheet, Rev. 1
48
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
P17
G[7]
SIUL
GPIO[103]
GPIO[103]
FlexPWM_0
B[3]
B[3]
R1
XTALOUT
R2
FCCU_F[0]
R3
VSS_HV_IO_RING
R4
D[7]
R5
R6
E[6]
VDD_HV_ADR0
R8
B[10]
R9
VDD_HV_ADR1
R10
B[13]
R12
R14
A[1]
F[0]
—
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
analog output
—
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[70]
ADC_0
—
AN[4]
SIUL
—
GPIO[26]
ADC_0
ADC_1
—
AN[12]
—
C[0]
BCTRL
F[0]
—
B[15]
R13
R15
FCCU
B[7]
R7
R11
—
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[31]
SIUL
—
EIRQ[20]
ADC_1
—
AN[2]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
—
VSS_HV_IO_RING
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
—
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
49
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
R16
D[11]
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[105]
GPIO[105]
FlexRay
DBG1
—
DSPI_1
CS1
—
FlexPWM_0
—
FAULT[1]
SIUL
—
EIRQ[29]
R17
G[9]
T1
VSS_HV_IO_RING
—
T2
VDD_HV_IO_RING
—
T3
Not connected
—
T4
C[1]
T5
T6
E[5]
E[7]
T7
VSS_HV_ADR0
T8
B[11]
T9
VSS_HV_ADR1
T10
E[9]
T11
T12
T13
T14
E[10]
E[12]
E[0]
A[0]
SIUL
—
GPIO[33]
ADC_0
—
AN[2]
SIUL
—
GPIO[69]
ADC_0
—
AN[8]
SIUL
—
GPIO[71]
ADC_0
—
AN[6]
—
SIUL
—
GPIO[27]
ADC_0
ADC_1
—
AN[13]
—
SIUL
—
GPIO[73]
ADC_1
—
AN[7]
SIUL
—
GPIO[74]
ADC_1
—
AN[8]
SIUL
—
GPIO[76]
ADC_1
—
AN[6]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
PXS20 Microcontroller Data Sheet, Rev. 1
50
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 4. 257 MAPBGA pin function summary (continued)
Pin #
Port/function
Peripheral
Output function
Input function
T15
D[10]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
T16
VDD_HV_IO_RING
—
T17
VSS_HV_IO_RING
—
U1
VSS_HV_IO_RING
—
U2
VSS_HV_IO_RING
—
U3
Not connected
—
U4
E[4]
U5
U6
U7
U8
1
C[2]
E[2]
B[9]
B[12]
SIUL
—
GPIO[68]
ADC_0
—
AN[7]
SIUL
—
GPIO[34]
ADC_0
—
AN[3]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
SIUL
—
GPIO[25]
ADC_0
ADC_1
—
AN[11]
SIUL
—
GPIO[28]
ADC_0
ADC_1
—
AN[14]
U9
VDD_HV_ADV
—
U10
VSS_HV_ADV
—
U11
E[11]
SIUL
—
GPIO[75]
ADC_1
—
AN[4]
U12
Not connected
—
U13
Not connected
—
U14
VDD_HV_PMU
—
U15
G[11]
SIUL
GPIO[107]
GPIO[107]
FlexRay
DBG3
—
FlexPWM_0
—
FAULT[3]
U16
VSS_HV_IO_RING
—
U17
VSS_HV_IO_RING
—
VPP_TEST should always be tied to ground (VSS) for normal operations.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
51
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
2.2
Supply pins
Table 5. Supply pins
Supply
Pin #
144
pkg
257
pkg
Voltage regulator external NPN ballast base control pin
69
R13
VDD_LV_COR
Core logic supply
70
VDD_LV1
VSS_LV_COR
Core regulator ground
71
VSS_LV2
VDD_HV_PMU
Voltage regulator supply
72
U14
Symbol
Description
VREG control and power supply pins
BCTRL
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADR0
ADC_0 high reference voltage
50
R7
VSS_HV_ADR0
ADC_0 low reference voltage
51
T7
VDD_HV_ADR1
ADC_1 high reference voltage
56
R9
VSS_HV_ADR1
ADC_1 low reference voltage
57
T9
VDD_HV_ADV
ADC voltage supply for ADC_0 and ADC_1
58
U9
VSS_HV_ADV
ADC ground for ADC_0 and ADC_1
59
U10
Power supply pins (3.3 V)
VDD_HV_IO
3.3 V Input/Output supply voltage
6
VDD_HV3
VSS_HV_IO
3.3 V Input/Output ground
7
VSS_HV4
16
J3
VDD_HV_REG_0 VDD_HV_REG_0
VDD_HV_IO
3.3 V Input/Output supply voltage
21
VDD_HV3
VSS_HV_IO
3.3 V Input/Output ground
22
VSS_HV4
VDD_HV_OSC
Crystal oscillator amplifier supply voltage
27
M1
VSS_HV_OSC
Crystal oscillator amplifier ground
28
P1
VSS_HV_IO
3.3 V Input/Output ground
90
VSS_HV4
VDD_HV_IO
3.3 V Input/Output supply voltage
91
VDD_HV3
95
H15
VDD_HV_REG_1 VDD_HV_REG_1
VSS_HV_FLA
VSS_HV_FLA
96
J16
VDD_HV_FLA
VDD_HV_FLA
97
H16
VDD_HV_IO
VDD_HV_IO
126
VDD_HV3
VSS_HV_IO
VSS_HV_IO
127
VSS_HV4
130
C7
17
VSS_HV2
VDD_HV_REG_2 VDD_HV_REG_2
Power supply pins (1.2 V)
VSS_LV_COR
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
PXS20 Microcontroller Data Sheet, Rev. 1
52
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
Table 5. Supply pins (continued)
Supply
Pin #
144
pkg
257
pkg
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
18
VDD_LV1
VSS 1V2
VSS_LV_PLL0_PLL1 /
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling capacitor
must be connected between this pin and VDD_LV_PLL.
35
N4
VDD 1V2
VDD_LV_PLL0_PLL1
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must
be connected between this pin and VSS_LV_PLL.
36
P4
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
39
VDD_LV1
VSS_LV_COR
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
40
VSS_LV2
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VSS_LV_REGCOR.
70
VDD_LV1
VSS_LV_COR
VSS_LV_REGCOR0
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VDD_LV_REGCOR.
71
VSS_LV2
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
93
VDD_LV1
VSS_LV_COR
VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin.
94
VSS_LV2
VDD 1V2
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
131
VDD_LV1
VSS 1V2
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
132
VSS_LV2
VDD 1V2
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
135
VDD_LV1
VSS 1V2
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
137
VSS_LV2
Symbol
Description
VDD_LV_COR
1
VDD_LV balls are tied together on the 257 MAPBGA substrate.
VSS_LV balls are tied together on the 257 MAPBGA substrate.
3
VDD_HV balls are tied together on the 257 MAPBGA substrate.
4 VSS_HV balls are tied together on the 257 MAPBGA substrate.
2
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
53
Preliminary—Subject to Change Without Notice
Package pinouts and signal descriptions
2.3
System pins
Table 6. System pins
Pin #
Symbol
Description
Direction
144
pkg
257
pkg
Output only
9
E1
Dedicated pins
1
Nexus Message Data Output — line 0
MDO0
2
NMI
Non Maskable Interrupt
Input only
1
E4
XTAL
Input for oscillator amplifier circuit and internal clock generator
Input only
29
N1
EXTAL
Oscillator amplifier output
Output only
30
R1
2
TMS
JTAG state machine control
Input only
87
M16
TCK2
JTAG clock
Input only
88
L15
JTAG compliance select
Input only
123
C10
31
P2
107
D15
JCOMP3
Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and noise filter. Bidirectional
This pin has medium drive strength.
Test pin
VPP TEST
Pin for testing purpose only. To be tied to ground in normal
operating mode.
1
This pad is configured for Fast (F) pad speed.
This pad contains a weak pull-up.
3 This pad contains a weak pull-down.
2
2.4
Pin muxing
Table 7 defines the pin list and muxing for this device.
Each entry of Table 7 shows all the possible configurations for each pin, via the alternate functions. The default function
assigned to each pin after reset is indicated by ALT0.
NOTE
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable
device behavior.
PXS20 Microcontroller Data Sheet, Rev. 1
54
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Table 7. Pin muxing
Port
name
PCR
Peripheral
Alternate
output
function
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Port A
A[0]
A[2]
A[3]
PCR[1]
PCR[2]
PCR[3]
SIUL
GPIO[0]
ALT0
GPIO[0]
—
eTimer_0
ETC[0]
ALT1
ETC[0]
PSMI[35]; PADSEL=0
DSPI_2
SCK
ALT2
SCK
PSMI[1]; PADSEL=0
SIUL
—
—
EIRQ[0]
—
SIUL
GPIO[1]
ALT0
GPIO[1]
—
eTimer_0
ETC[1]
ALT1
ETC[1]
PSMI[36]; PADSEL=0
DSPI_2
SOUT
ALT2
—
—
SIUL
—
—
EIRQ[1]
—
SIUL
GPIO[2]
ALT0
GPIO[2]
—
eTimer_0
ETC[2]
ALT1
ETC[2]
PSMI[37]; PADSEL=0
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23]; PADSEL=0
DSPI_2
—
—
SIN
PSMI[2]; PADSEL=0
MC_RGM
—
—
ABS[0]
—
SIUL
—
—
EIRQ[2]
—
SIUL
GPIO[3]
ALT0
GPIO[3]
—
eTimer_0
ETC[3]
ALT1
ETC[3]
PSMI[38]; PADSEL=0
DSPI_2
CS0
ALT2
CS0
PSMI[3]; PADSEL=0
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27]; PADSEL=0
MC_RGM
—
—
ABS[2]
—
SIUL
—
—
EIRQ[3]
—
Pull down
M
S
73
T14
Pull down
M
S
74
R14
Pull down
M
S
84
N16
Pull down
M
S
92
K17
55
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
A[1]
PCR[0]
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Port
name
PCR
Peripheral
Alternate
output
function
A[4]
PCR[4]
SIUL
GPIO[4]
ALT0
GPIO[4]
—
eTimer_1
ETC[0]
ALT1
ETC[0]
PSMI[9]; PADSEL=0
DSPI_2
CS1
ALT2
—
—
eTimer_0
ETC[4]
ALT3
ETC[4]
PSMI[7]; PADSEL=0
MC_RGM
—
—
FAB
—
SIUL
—
—
EIRQ[4]
—
SIUL
GPIO[5]
ALT0
GPIO[5]
—
DSPI_1
CS0
ALT1
CS0
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14]; PADSEL=0
DSPI_0
CS7
ALT3
—
—
SIUL
—
—
EIRQ[5]
—
SIUL
GPIO[6]
ALT0
GPIO[6]
—
DSPI_1
SCK
ALT1
SCK
—
SIUL
—
—
EIRQ[6]
—
SIUL
GPIO[7]
ALT0
GPIO[7]
—
DSPI_1
SOUT
ALT1
—
—
SIUL
—
—
EIRQ[7]
—
SIUL
GPIO[8]
ALT0
GPIO[8]
—
DSPI_1
—
—
SIN
—
SIUL
—
—
EIRQ[8]
—
SIUL
GPIO[9]
ALT0
GPIO[9]
—
DSPI_2
CS1
ALT1
—
—
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27]; PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16]; PADSEL=0
A[5]
A[6]
A[7]
A[8]
Freescale Semiconductor
A[9]
PCR[5]
PCR[6]
PCR[7]
PCR[8]
PCR[9]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
108
C16
Pull down
M
S
14
H4
Pull down
M
S
2
G4
Pull down
M
S
10
F3
Pull down
M
S
12
F4
Pull down
M
S
134
B6
Package pinouts and signal descriptions
56
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
PCR
Peripheral
A[10]
PCR[10]
SIUL
GPIO[10]
ALT0
GPIO[10]
—
DSPI_2
CS0
ALT1
CS0
PSMI[3]; PADSEL=1
FlexPWM_0
B[0]
ALT2
B[0]
PSMI[24]; PADSEL=0
FlexPWM_0
X[2]
ALT3
X[2]
PSMI[29]; PADSEL=0
SIUL
—
—
EIRQ[9]
—
SIUL
GPIO[11]
ALT0
GPIO[11]
—
DSPI_2
SCK
ALT1
SCK
PSMI[1]; PADSEL=1
FlexPWM_0
A[0]
ALT2
A[0]
PSMI[20]; PADSEL=0
FlexPWM_0
A[2]
ALT3
A[2]
PSMI[22]; PADSEL=0
SIUL
—
—
EIRQ[10]
—
SIUL
GPIO[12]
ALT0
GPIO[12]
—
DSPI_2
SOUT
ALT1
—
—
FlexPWM_0
A[2]
ALT2
A[2]
PSMI[22]; PADSEL=1
FlexPWM_0
B[2]
ALT3
B[2]
PSMI[26]; PADSEL=0
SIUL
—
—
EIRQ[11]
—
SIUL
GPIO[13]
ALT0
GPIO[13]
—
FlexPWM_0
B[2]
ALT2
B[2]
PSMI[26]; PADSEL=1
DSPI_2
—
—
SIN
PSMI[2]; PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16]; PADSEL=1
SIUL
—
—
EIRQ[12]
—
SIUL
GPIO[14]
ALT0
GPIO[14]
—
FlexCAN_1
TXD
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13]; PADSEL=0
SIUL
—
—
EIRQ[13]
—
A[11]
A[12]
A[13]
A[14]
PCR[11]
PCR[12]
PCR[13]
PCR[14]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
118
A13
Pull down
M
S
120
D11
Pull down
M
S
122
A10
Pull down
M
S
136
C6
Pull down
M
S
143
B4
57
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Port
name
Alternate
output
function
Port
name
PCR
Peripheral
Alternate
output
function
A[15]
PCR[15]
SIUL
GPIO[15]
ALT0
GPIO[15]
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14]; PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34]; PADSEL=0
FlexCAN_0
—
—
RXD
PSMI[33]; PADSEL=0
SIUL
—
—
EIRQ[14]
—
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
M
S
144
D3
Pull down
M
S
109
B15
Pull down
M
S
110
C14
Pull down
M
S
114
A14
Pull down
M
S
116
B13
Port B
B[0]
B[1]
B[2]
Freescale Semiconductor
Pull down
B[3]
PCR[16]
PCR[17]
PCR[18]
PCR[19]
SIUL
GPIO[16]
ALT0
GPIO[16]
—
FlexCAN_0
TXD
ALT1
—
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11]; PADSEL=0
SSCM
DEBUG[0]
ALT3
—
—
SIUL
—
—
EIRQ[15]
—
SIUL
GPIO[17]
ALT0
GPIO[17]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12]; PADSEL=0
SSCM
DEBUG[1]
ALT3
—
—
FlexCAN_0
—
—
RXD
PSMI[33]; PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34]; PADSEL=1
SIUL
—
—
EIRQ[16]
—
SIUL
GPIO[18]
ALT0
GPIO[18]
—
LINFlex_0
TXD
ALT1
—
—
SSCM
DEBUG[2]
ALT3
—
—
SIUL
—
—
EIRQ[17]
—
SIUL
GPIO[19]
ALT0
GPIO[19]
—
SSCM
DEBUG[3]
ALT3
—
—
LINFlex_0
—
—
RXD
PSMI[31]; PADSEL=0
Package pinouts and signal descriptions
58
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
B[4]2
PCR[20]
SIUL
GPIO[20]
ALT0
GPIO[20]
—
JTAGC
TDO
ALT1
—
—
SIUL
GPIO[21]
ALT0
GPIO[21]
—
JTAGC
—
—
TDI
—
SIUL
GPIO[22]
ALT0
GPIO[22]
—
MC_CGM
clk_out
ALT1
—
—
DSPI_2
CS2
ALT2
—
—
SIUL
—
EIRQ[18]
—
SIUL
—
ALT0
GPI[23]
—
LINFlex_0
—
—
RXD
PSMI[31]; PADSEL=1
B[5]
B[6]
B[8]
B[9]
B[10]
B[11]
B[12]
PCR[22]
PCR[23]
PCR[24]
PCR[25]
PCR[26]
PCR[27]
PCR[28]
Input
functions
Input mux select
3
—
ADC_0
—
—
AN[0]
SIUL
—
ALT0
GPI[24]
—
eTimer_0
—
—
ETC[5]
PSMI[8]; PADSEL=2
3
—
ADC_0
—
—
AN[1]
SIUL
—
ALT0
GPI[25]
—
ADC_0
ADC_1
—
—
AN[11]3
—
SIUL
—
ALT0
GPI[26]
—
ADC_0
ADC_1
—
—
AN[12]3
—
SIUL
—
ALT0
GPI[27]
—
—
ADC_0
ADC_1
—
—
AN[13]3
SIUL
—
ALT0
GPI[28]
—
3
—
ADC_0
ADC_1
—
—
AN[14]
Pin #
144
pkg
257
pkg
Pull down
F
S
89
L17
Pull up
M
S
86
M15
Pull down
F
S
138
B3
—
—
—
43
R5
—
—
—
47
P7
—
—
—
52
U7
—
—
—
53
R8
—
—
—
54
T8
—
—
—
55
U8
59
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
B[7]
PCR[21]
Output
mux sel
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Port
name
PCR
Peripheral
Alternate
output
function
B[13]
PCR[29]
SIUL
—
ALT0
GPI[29]
—
LINFlex_1
—
—
RXD
PSMI[32]; PADSEL=0
B[14]
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
B[15]
PCR[30]
PCR[31]
Output
mux sel
Input
functions
Input mux select
3
—
ADC_1
—
—
AN[0]
SIUL
—
ALT0
GPI[30]
—
eTimer_0
—
—
ETC[4]
PSMI[7]; PADSEL=2
SIUL
—
—
EIRQ[19]
—
3
—
ADC_1
—
—
AN[1]
SIUL
—
ALT0
GPI[31]
—
SIUL
—
—
EIRQ[20]
—
ADC_1
—
—
AN[2]
3
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
—
—
—
60
R10
—
—
—
64
P11
—
—
—
62
R11
—
—
—
66
R12
—
—
—
41
T4
—
—
—
45
U5
Pull down
M
S
11
H3
—
Port C
C[0]
C[1]
C[2]
C[4]
PCR[32]
PCR[33]
PCR[34]
PCR[36]
SIUL
—
ALT0
GPI[32]
—
ADC_1
—
—
AN[3]3
—
SIUL
—
ALT0
GPI[33]
—
3
—
ADC_0
—
—
AN[2]
SIUL
—
ALT0
GPI[34]
—
—
Freescale Semiconductor
ADC_0
—
—
AN[3]3
SIUL
GPIO[36]
ALT0
GPIO[36]
—
DSPI_0
CS0
ALT1
CS0
—
FlexPWM_0
X[1]
ALT2
X[1]
PSMI[28]; PADSEL=0
SSCM
DEBUG[4]
ALT3
—
—
SIUL
—
—
EIRQ[22]
—
Package pinouts and signal descriptions
60
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
PCR
Peripheral
C[5]
PCR[37]
SIUL
GPIO[37]
ALT0
GPIO[37]
—
DSPI_0
SCK
ALT1
SCK
—
SSCM
DEBUG[5]
ALT3
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19]; PADSEL=0
SIUL
—
—
EIRQ[23]
—
SIUL
GPIO[38]
ALT0
GPIO[38]
—
DSPI_0
SOUT
ALT1
—
—
FlexPWM_0
B[1]
ALT2
B[1]
PSMI[25]; PADSEL=0
SSCM
DEBUG[6]
ALT3
—
—
SIUL
—
—
EIRQ[24]
—
SIUL
GPIO[39]
ALT0
GPIO[39]
—
FlexPWM_0
A[1]
ALT2
A[1]
PSMI[21]; PADSEL=0
SSCM
DEBUG[7]
ALT3
—
—
DSPI_0
—
—
SIN
—
SIUL
GPIO[42]
ALT0
GPIO[42]
—
DSPI_2
CS2
ALT1
—
—
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23]; PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17]; PADSEL=0
SIUL
GPIO[43]
ALT0
GPIO[43]
—
eTimer_0
ETC[4]
ALT1
ETC[4]
PSMI[7]; PADSEL=1
DSPI_2
CS2
ALT2
—
—
SIUL
GPIO[44]
ALT0
GPIO[44]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8]; PADSEL=0
DSPI_2
CS3
ALT2
—
—
C[6]
C[7]
C[10]
C[11]
C[12]
PCR[38]
PCR[39]
PCR[42]
PCR[43]
PCR[44]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
13
G3
Pull down
M
S
142
D4
Pull down
M
S
15
K4
Pull down
M
S
111
A15
Pull down
M
S
80
M14
Pull down
M
S
82
N15
61
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Port
name
Alternate
output
function
Port
name
PCR
Peripheral
Alternate
output
function
C[13]
PCR[45]
SIUL
GPIO[45]
ALT0
GPIO[45]
—
eTimer_1
ETC[1]
ALT1
ETC[1]
PSMI[10]; PADSEL=0
CTU_0
—
—
EXT_IN
PSMI[0]; PADSEL=0
FlexPWM_0
—
—
EXT_SYNC
PSMI[15]; PADSEL=0
SIUL
GPIO[46]
ALT0
GPIO[46]
—
eTimer_1
ETC[2]
ALT1
ETC[2]
PSMI[11]; PADSEL=1
CTU_0
EXT_TGR
ALT2
—
—
SIUL
GPIO[47]
ALT0
GPIO[47]
—
FlexRay
CA_TR_EN
ALT1
—
—
eTimer_1
ETC[0]
ALT2
ETC[0]
PSMI[9]; PADSEL=1
FlexPWM_0
A[1]
ALT3
A[1]
PSMI[21]; PADSEL=1
CTU_0
—
—
EXT_IN
PSMI[0]; PADSEL=1
FlexPWM_0
—
—
EXT_SYNC
PSMI[15]; PADSEL=1
C[14]
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
C[15]
PCR[46]
PCR[47]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
101
F15
Pull down
M
S
103
E15
Pull down
SYM
S
124
A8
Pull down
SYM
S
125
B8
Pull down
M
S
3
E3
Port D
D[0]
D[1]
PCR[48]
PCR[49]
Freescale Semiconductor
SIUL
GPIO[48]
ALT0
GPIO[48]
—
FlexRay
CA_TX
ALT1
—
—
eTimer_1
ETC[1]
ALT2
ETC[1]
PSMI[10]; PADSEL=1
FlexPWM_0
B[1]
ALT3
B[1]
PSMI[25]; PADSEL=1
SIUL
GPIO[49]
ALT0
GPIO[49]
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11]; PADSEL=2
CTU_0
EXT_TGR
ALT3
—
—
FlexRay
—
—
CA_RX
—
Package pinouts and signal descriptions
62
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
PCR
Peripheral
D[2]
PCR[50]
SIUL
GPIO[50]
ALT0
GPIO[50]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12]; PADSEL=1
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30]; PADSEL=0
FlexRay
—
—
CB_RX
—
SIUL
GPIO[51]
ALT0
GPIO[51]
—
FlexRay
CB_TX
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13]; PADSEL=1
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23]; PADSEL=2
SIUL
GPIO[52]
ALT0
GPIO[52]
—
FlexRay
CB_TR_EN
ALT1
—
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14]; PADSEL=2
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27]; PADSEL=2
SIUL
GPIO[53]
ALT0
GPIO[53]
—
DSPI_0
CS3
ALT1
—
—
FlexPWM_0
—
—
FAULT[2]
PSMI[18]; PADSEL=0
SIUL
GPIO[54]
ALT0
GPIO[54]
—
DSPI_0
CS2
ALT1
—
—
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30]; PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17]; PADSEL=1
SIUL
GPIO[55]
ALT0
GPIO[55]
—
DSPI_1
CS3
ALT1
—
—
DSPI_0
CS4
ALT3
—
—
SWG
analog output
—
—
—
D[3]
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
D[4]
D[5]
D[6]
D[7]
PCR[51]
PCR[52]
PCR[53]
PCR[54]
PCR[55]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
140
C5
Pull down
SYM
S
128
A7
Pull down
SYM
S
129
B7
Pull down
M
S
33
N3
Pull down
M
S
34
P3
Pull down
M
S
37
R4
63
Package pinouts and signal descriptions
Port
name
Alternate
output
function
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Port
name
PCR
Peripheral
Alternate
output
function
D[8]
PCR[56]
SIUL
GPIO[56]
ALT0
GPIO[56]
—
DSPI_1
CS2
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13]; PADSEL=2
DSPI_0
CS5
ALT3
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19]; PADSEL=1
SIUL
GPIO[57]
ALT0
GPIO[57]
—
FlexPWM_0
X[0]
ALT1
X[0]
—
LINFlexD_1
TXD
ALT2
—
—
SIUL
GPIO[58]
ALT0
GPIO[58]
—
FlexPWM_0
A[0]
ALT1
A[0]
PSMI[20]; PADSEL=1
eTimer_0
—
—
ETC[0]
PSMI[35]; PADSEL=1
SIUL
GPIO[59]
ALT0
GPIO[59]
—
FlexPWM_0
B[0]
ALT1
B[0]
PSMI[24]; PADSEL=1
eTimer_0
—
—
ETC[1]
PSMI[36]; PADSEL=1
SIUL
GPIO[60]
ALT0
GPIO[60]
FlexPWM_0
X[1]
ALT1
X[1]
PSMI[28]; PADSEL=1
LINFlexD_1
—
—
RXD
PSMI[32]; PADSEL=1
SIUL
GPIO[62]
ALT0
GPIO[62]
—
FlexPWM_0
B[1]
ALT1
B[1]
PSMI[25]; PADSEL=2
eTimer_0
—
—
ETC[3]
PSMI[38]; PADSEL=1
D[9]
D[10]
D[11]
D[12]
D[14]
PCR[57]
PCR[58]
PCR[59]
PCR[60]
PCR[62]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Freescale Semiconductor
Pull down
M
S
32
M3
Pull down
M
S
26
L3
Pull down
M
S
76
T15
Pull down
M
S
78
R16
Pull down
M
S
99
G14
Pull down
M
S
105
D16
—
—
—
68
T13
—
—
—
49
U6
Port E
E[0]
E[2]
PCR[64]
PCR[66]
SIUL
—
ALT0
GPI[64]
—
—
ADC_1
—
—
AN[5]3
SIUL
—
ALT0
GPI[66]
—
ADC_0
—
—
AN[5]3
—
Package pinouts and signal descriptions
64
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
E[4]
PCR[68]
SIUL
—
E[5]
E[6]
E[9]
E[10]
E[11]
E[12]
E[13]
E[14]
PCR[70]
PCR[71]
PCR[73]
PCR[74]
PCR[75]
PCR[76]
PCR[77]
PCR[78]
Input
functions
Input mux select
ALT0
GPI[68]
—
3
—
ADC_0
—
—
AN[7]
SIUL
—
ALT0
GPI[69]
—
ADC_0
—
—
AN[8]3
—
SIUL
—
ALT0
GPI[70]
—
3
—
ADC_0
—
—
AN[4]
SIUL
—
ALT0
GPI[71]
—
ADC_0
—
—
AN[6]3
—
SIUL
—
ALT0
GPI[73]
—
—
ADC_1
—
—
AN[7]3
SIUL
—
ALT0
GPI[74]
—
ADC_1
—
—
AN[8]3
—
SIUL
—
ALT0
GPI[75]
—
—
ADC_1
—
—
AN[4]3
SIUL
—
ALT0
GPI[76]
—
ADC_1
—
—
AN[6]3
—
SIUL
GPIO[77]
ALT0
GPIO[77]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8]; PADSEL=1
DSPI_2
CS3
ALT2
—
—
SIUL
—
—
EIRQ[25]
—
SIUL
GPIO[78]
ALT0
GPIO[78]
—
eTimer_1
ETC[5]
ALT1
ETC[5]
PSMI[14]; PADSEL=3
SIUL
—
—
EIRQ[26]
—
Pin #
144
pkg
257
pkg
—
—
—
42
U4
—
—
—
44
T5
—
—
—
46
R6
—
—
—
48
T6
—
—
—
61
T10
—
—
—
63
T11
—
—
—
65
U11
—
—
—
67
T12
Pull down
M
S
117
D12
Pull down
M
S
119
B12
65
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
E[7]
PCR[69]
Output
mux sel
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Port
name
PCR
Peripheral
Alternate
output
function
E[15]
PCR[79]
SIUL
GPIO[79]
ALT0
GPIO[79]
—
DSPI_0
CS1
ALT1
—
—
SIUL
—
—
EIRQ[27]
—
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
121
B11
Pull down
M
S
133
D7
Pull down
M
S
139
B5
Pull down
F
S
4
D2
Pull down
F
S
5
D1
Pull down
F
S
8
E2
Pull down
F
S
19
J1
Pull down
F
S
20
K2
Pull down
F
S
23
K1
Pull down
F
S
24
L1
Port F
F[0]
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
F[3]
F[4]
F[5]
F[6]
F[7]
F[8]
Freescale Semiconductor
F[9]
F[10]
PCR[80]
PCR[83]
PCR[84]
PCR[85]
PCR[86]
PCR[87]
PCR[88]
PCR[89]
PCR[90]
SIUL
GPIO[80]
ALT0
GPIO[80]
—
FlexPWM_0
A[1]
ALT1
A[1]
PSMI[21]; PADSEL=2
eTimer_0
—
—
ETC[2]
PSMI[37]; PADSEL=1
SIUL
—
—
EIRQ[28]
—
SIUL
GPIO[83]
ALT0
GPIO[83]
—
DSPI_0
CS6
ALT1
—
—
SIUL
GPIO[84]
ALT0
GPIO[84]
—
NPC
MDO[3]
ALT2
—
—
SIUL
GPIO[85]
ALT0
GPIO[85]
—
NPC
MDO[2]
ALT2
—
—
SIUL
GPIO[86]
ALT0
GPIO[86]
—
NPC
MDO[1]
ALT2
—
—
SIUL
GPIO[87]
ALT0
GPIO[87]
—
NPC
MCKO
ALT2
—
—
SIUL
GPIO[88]
ALT0
GPIO[88]
—
NPC
MSEO[1]
ALT2
—
—
SIUL
GPIO[89]
ALT0
GPIO[89]
—
NPC
MSEO[0]
ALT2
—
—
SIUL
GPIO[90]
ALT0
GPIO[90]
—
NPC
EVTO
ALT2
—
—
Package pinouts and signal descriptions
66
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
F[11]
PCR[91]
SIUL
GPIO[91]
ALT0
GPIO[91]
—
NPC
EVTI
ALT2
—
—
SIUL
GPIO[92]
ALT0
GPIO[92]
—
eTimer_1
ETC[3]
ALT1
ETC[3]
PSMI[12]; PADSEL=2
SIUL
—
—
EIRQ[30]
—
SIUL
GPIO[93]
ALT0
GPIO[93]
—
eTimer_1
ETC[4]
ALT1
ETC[4]
PSMI[13]; PADSEL=3
SIUL
—
—
EIRQ[31]
—
SIUL
GPIO[94]
ALT0
GPIO[94]
—
LINFlexD_1
TXD
ALT1
—
—
SIUL
GPIO[95]
ALT0
GPIO[95]
—
LINFlexD_1
—
—
RXD
PSMI[32]; PADSEL=2
F[12]
F[14]
F[15]
PCR[93]
PCR[94]
PCR[95]
Input
functions
Input mux select
Pin #
144
pkg
257
pkg
Pull down
M
S
25
L2
Pull down
M
S
106
C17
Pull down
M
S
112
B14
Pull down
M
S
115
C13
Pull down
M
S
113
D13
FCCU
FCCU_
F[0]
—
FCCU
F[0]
ALT0
F[0]
—
—
S
S
38
R2
FCCU_
F[1]
—
FCCU
F[1]
ALT0
F[1]
—
—
S
S
141
C4
Pull down
M
S
102
E16
Pull down
M
S
104
D17
Port G
G[2]
G[3]
PCR[98]
PCR[99]
SIUL
GPIO[98]
ALT0
GPIO[98]
—
FlexPWM_0
X[2]
ALT1
X[2]
PSMI[29]; PADSEL=1
DSPI_1
CS1
ALT2
—
—
SIUL
GPIO[99]
ALT0
GPIO[99]
—
FlexPWM_0
A[2]
ALT1
A[2]
PSMI[22]; PADSEL=2
eTimer_0
—
—
ETC[4]
PSMI[7]; PADSEL=3
67
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
F[13]
PCR[92]
Output
mux sel
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Port
name
PCR
Peripheral
Alternate
output
function
G[4]
PCR[100]
SIUL
GPIO[100]
ALT0
GPIO[100]
—
FlexPWM_0
B[2]
ALT1
B[2]
PSMI[26]; PADSEL=2
eTimer_0
—
—
ETC[5]
PSMI[8]; PADSEL=3
SIUL
GPIO[101]
ALT0
GPIO[101]
—
FlexPWM_0
X[3]
ALT1
X[3]
PSMI[30]; PADSEL=2
DSPI_2
CS3
ALT2
—
—
SIUL
GPIO[102]
ALT0
GPIO[102]
—
FlexPWM_0
A[3]
ALT1
A[3]
PSMI[23]; PADSEL=3
SIUL
GPIO[103]
ALT0
GPIO[103]
FlexPWM_0
B[3]
ALT1
B[3]
PSMI[27]; PADSEL=3
SIUL
GPIO[104]
ALT0
GPIO[104]
—
FlexRay
DBG0
ALT1
—
—
DSPI_0
CS1
ALT2
—
—
FlexPWM_0
—
—
FAULT[0]
PSMI[16]; PADSEL=2
SIUL
—
—
EIRQ[21]
—
SIUL
GPIO[105]
ALT0
GPIO[105]
—
FlexRay
DBG1
ALT1
—
—
DSPI_1
CS1
ALT2
—
—
FlexPWM_0
—
—
FAULT[1]
PSMI[17]; PADSEL=2
SIUL
—
—
EIRQ[29]
—
SIUL
GPIO[106]
ALT0
GPIO[106]
—
FlexRay
DBG2
ALT1
—
—
DSPI_2
CS3
ALT2
—
—
FlexPWM_0
—
—
FAULT[2]
PSMI[18]; PADSEL=1
G[5]
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
G[6]
G[7]
G[8]
G[9]
Freescale Semiconductor
G[10]
PCR[101]
PCR[102]
PCR[103]
PCR[104]
PCR[105]
PCR[106]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
100
F17
Pull down
M
S
85
N17
Pull down
M
S
98
G17
Pull down
M
S
83
P17
Pull down
M
S
81
P16
Pull down
M
S
79
R17
Pull down
M
S
77
P15
Package pinouts and signal descriptions
68
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
G[11]
PCR[107]
SIUL
GPIO[107]
ALT0
GPIO[107]
—
FlexRay
DBG3
ALT1
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19]; PADSEL=2
SIUL
GPIO[108]
ALT0
GPIO[108]
—
NPC
MDO[11]
ALT2
—
—
SIUL
GPIO[109]
ALT0
GPIO[109]
—
NPC
MDO[10]
ALT2
—
—
SIUL
GPIO[110]
ALT0
GPIO[110]
—
NPC
MDO[9]
ALT2
—
—
SIUL
GPIO[111]
ALT0
GPIO[111]
—
NPC
MDO[8]
ALT2
—
—
G[12]
G[14]
G[15]
PCR[109]
PCR[110]
PCR[111]
Input
functions
Input mux select
Pin #
144
pkg
257
pkg
Pull down
M
S
75
U15
Pull down
F
S
—
F2
Pull down
F
S
—
H1
Pull down
F
S
—
A6
Pull down
F
S
—
J2
Pull down
F
S
—
A5
Pull down
F
S
—
F1
Pull down
F
S
—
A4
Pull down
F
S
—
G1
Pull down
M
S
—
L16
Port H
H[0]
H[1]
H[2]
H[3]
H[4]
PCR[112]
PCR[113]
PCR[114]
PCR[115]
PCR[116]
SIUL
GPIO[112]
ALT0
GPIO[112]
—
NPC
MDO[7]
ALT2
—
—
SIUL
GPIO[113]
ALT0
GPIO[113]
—
NPC
MDO[6]
ALT2
—
—
SIUL
GPIO[114]
ALT0
GPIO[114]
—
NPC
MDO[5]
ALT2
—
—
SIUL
GPIO[115]
ALT0
GPIO[115]
—
NPC
MDO[4]
ALT2
—
—
SIUL
GPIO[116]
ALT0
GPIO[116]
—
FlexPWM_1
X[0]
ALT1
X[0]
—
eTimer_2
ETC[0]
ALT2
ETC[0]
PSMI[39]; PADSEL=0
69
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
G[13]
PCR[108]
Output
mux sel
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Port
name
PCR
Peripheral
Alternate
output
function
H[5]
PCR[117]
SIUL
GPIO[117]
ALT0
GPIO[117]
—
FlexPWM_1
A[0]
ALT1
A[0]
—
DSPI_0
CS4
ALT3
—
—
SIUL
GPIO[118]
ALT0
GPIO[118]
—
FlexPWM_1
B[0]
ALT1
B[0]
—
DSPI_0
CS5
ALT3
—
—
SIUL
GPIO[119]
ALT0
GPIO[119]
—
FlexPWM_1
X[1]
ALT1
X[1]
—
eTimer_2
ETC[1]
ALT2
ETC[1]
PSMI[40]; PADSEL=0
SIUL
GPIO[120]
ALT0
GPIO[120]
—
FlexPWM_1
A[1]
ALT1
A[1]
—
DSPI_0
CS6
ALT3
—
—
SIUL
GPIO[121]
ALT0
GPIO[121]
—
FlexPWM_1
B[1]
ALT1
B[1]
—
DSPI_0
CS7
ALT3
—
—
SIUL
GPIO[122]
ALT0
GPIO[122]
—
FlexPWM_1
X[2]
ALT1
X[2]
—
eTimer_2
ETC[2]
ALT2
ETC[2]
—
SIUL
GPIO[123]
ALT0
GPIO[123]
—
FlexPWM_1
A[2]
ALT1
A[2]
—
SIUL
GPIO[124]
ALT0
GPIO[124]
—
FlexPWM_1
B[2]
ALT1
B[2]
—
SIUL
GPIO[125]
ALT0
GPIO[125]
—
FlexPWM_1
X[3]
ALT1
X[3]
—
eTimer_2
ETC[3]
ALT2
ETC[3]
PSMI[42]; PADSEL=0
H[6]
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
H[7]
H[8]
H[9]
H[10]
H[11]
Freescale Semiconductor
H[12]
H[13]
PCR[118]
PCR[119]
PCR[120]
PCR[121]
PCR[122]
PCR[123]
PCR[124]
PCR[125]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
—
M17
Pull down
M
S
—
H17
Pull down
M
S
—
K16
Pull down
M
S
—
K15
Pull down
M
S
—
G16
Pull down
M
S
—
A11
Pull down
M
S
—
C11
Pull down
M
S
—
B10
Pull down
M
S
—
G15
Package pinouts and signal descriptions
70
Table 7. Pin muxing (continued)
Freescale Semiconductor
Table 7. Pin muxing (continued)
Port
name
PCR
Peripheral
Alternate
output
function
H[14]
PCR[126]
SIUL
GPIO[126]
ALT0
GPIO[126]
—
FlexPWM_1
A[3]
ALT1
A[3]
—
eTimer_2
ETC[4]
ALT2
ETC[4]
—
SIUL
GPIO[127]
ALT0
GPIO[127]
—
FlexPWM_1
B[3]
ALT1
B[3]
—
eTimer_2
ETC[5]
ALT2
ETC[5]
—
H[15]
PCR[127]
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
M
S
—
A12
Pull down
M
S
—
J17
Pull down
M
S
—
C9
Pull down
M
S
—
C12
Pull down
M
S
—
F16
Port I
I[0]
I[1]
I[2]
PCR[128]
PCR[129]
PCR[130]
SIUL
GPIO[128]
ALT0
GPIO[128]
—
eTimer_2
ETC[0]
ALT1
ETC[0]
PSMI[39]; PADSEL=1
DSPI_0
CS4
ALT2
—
—
FlexPWM_1
—
—
FAULT[0]
—
SIUL
GPIO[129]
ALT0
GPIO[129]
—
eTimer_2
ETC[1]
ALT1
ETC[1]
PSMI[40]; PADSEL=1
DSPI_0
CS5
ALT2
—
—
FlexPWM_1
—
—
FAULT[1]
—
SIUL
GPIO[130]
ALT0
GPIO[130]
—
eTimer_2
ETC[2]
ALT1
ETC[2]
PSMI[41]; PADSEL=1
DSPI_0
CS6
ALT2
—
—
FlexPWM_1
—
—
FAULT[2]
—
71
Package pinouts and signal descriptions
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Pull down
PXS20 Microcontroller Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Port
name
PCR
Peripheral
Alternate
output
function
I[3]
PCR[131]
SIUL
GPIO[131]
ALT0
GPIO[131]
—
eTimer_2
ETC[3]
ALT1
ETC[3]
PSMI[42]; PADSEL=1
DSPI_0
CS7
ALT2
—
—
CTU_0
EXT_TGR
ALT3
—
—
FlexPWM_1
—
—
FAULT[3]
—
SIUL
GPIO[132]
ALT0
GPIO[132]
—
NPC
RDY
ALT2
—
—
RDY
(cut2
only)
1
PCR[132]
(cut2 only)
Output
mux sel
Input
functions
Input mux select
Pad speed1
Weak pull
config during
SRC SRC
reset
=1
=0
Pin #
144
pkg
257
pkg
Pull down
M
S
—
E17
Pull down
F
S
—
K3
(cut2
only)
Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM = Symmetric (for
FlexRay)
2 The default function of this pin out of reset is ALT1 (TDO).
3 Analog
Package pinouts and signal descriptions
72
Table 7. Pin muxing (continued)
Freescale Semiconductor
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary and are from previous designs,
design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the
product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been
completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional column containing “SR”, “CC”, “P”,
“C”, “T”, or “D”.
•
•
•
3.2
“SR” identifies system requirements—conditions that must be provided to ensure normal device operation. An
example is the input voltage of a voltage regulator.
“CC” identifies controller characteristics—indicating the characteristics and timing of the signals that the chip
provides.
“P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define normal device operation.
They specify how each characteristic is guaranteed.
— P: parameter is guaranteed by production testing of each individual device.
— C: parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant
sample size across process variations.
— T: parameter is guaranteed by design characterization on a small sample size from typical devices under typical
conditions unless otherwise noted. All values are shown in the typical (“typ”) column are within this category.
— D: parameters are derived mainly from simulations.
Absolute maximum ratings
Table 8. Absolute maximum ratings1
Symbol
Parameter
Conditions
Min
Max2
Unit
VDD_HV_REG
SR
3.3 V voltage regulator supply voltage
—
–0.3
4.03, 4
V
VSS_HV_REG
SR
3.3 V voltage regulator reference voltage
—
–0.1
0.1
V
VDD_HV_IOx
SR
3.3 V input/output supply voltage
—
–0.3
3.63, 4
V
VSS_HV_IOx
SR
Input/output ground voltage
—
–0.1
0.1
V
V
VDD_HV_FLA
SR
3.3 V flash supply voltage
—
–0.3
3.63, 4
VSS_HV_FLA
SR
Flash memory ground
—
–0.1
0.1
V
VDD_HV_OSC
SR
3.3 V crystal oscillator amplifier supply
voltage
—
–0.3
4.03, 4
V
VSS_HV_OSC
SR
3.3 V crystal oscillator amplifier reference
voltage
—
–0.1
0.1
V
VDD_HV_ADR05 SR
VDD_HV_ADR1
3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
—
–0.3
6.0
V
VSS_HV_ADR0
VSS_HV_ADR1
SR
ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
—
–0.1
0.1
V
VDD_HV_ADV
SR
3.3 V ADC supply voltage
—
–0.3
4.03, 4
V
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
73
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 8. Absolute maximum ratings1 (continued)
Symbol
VSS_HV_ADV
1
2
3
4
5
6
3.3
Parameter
SR
Conditions
Min
Max2
Unit
—
–0.1
0.1
V
3.3 V ADC supply ground
106
TVDD
SR
Slope characteristics on all VDD during
power up
—
0.5
VIN
SR
Voltage on any pin with respect to ground
(VSS_HV_IOx)
—
–0.3
6.0
–0.3
VDD + 0.36
Relative to VDD
3.0 ×
V/µs
(3.0 V/sec)
V
IINJPAD
SR
Injected input current on any pin during
overload condition
—
–10
10
mA
IINJSUM
SR
Absolute sum of all injected input currents
during overload condition
—
–50
50
mA
TSTG
SR
Storage temperature
—
–55
150
°C
Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device
stress have not yet been determined.
5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining.
Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by
the same voltage source.
Only when VDD < 5.2 V.
Recommended operating conditions
Table 9. Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Min
Max1
Unit
VDD_HV_REG
SR 3.3 V voltage regulator supply voltage
—
3.0
3.6
V
VSS_HV_REG
SR 3.3 V voltage regulator reference voltage
—
0
0
V
VDD_HV_IOx
SR 3.3 V input/output supply voltage
—
3.0
3.6
V
VSS_HV_IOx
SR Input/output ground voltage
—
0
0
V
VDD_HV_FLA
SR 3.3 V flash supply voltage
—
3.0
3.6
V
VSS_HV_FLA
SR Flash memory ground
—
0
0
V
VDD_HV_OSC
SR 3.3 V crystal oscillator amplifier supply voltage
—
3.0
3.6
V
VSS_HV_OSC
SR 3.3 V crystal oscillator amplifier reference voltage
—
0
0
V
SR 3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
—
4.5 to 5.5 or
3.0 to 3.6
V
VDD_HV_ADV
SR 3.3 V ADC supply voltage
—
3.0
3.6
V
VSS_HV_AD0
VSS_HV_AD1
SR ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
—
0
0
V
VSS_HV_ADV
SR 3.3 V ADC supply ground
—
0
0
V
SR Internal supply voltage
—
—
—
V
VDD_HV_ADR02
VDD_HV_ADR1
VDD_LV_REGCOR3
PXS20 Microcontroller Data Sheet, Rev. 1
74
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
VSS_LV_REGCOR4 SR Internal reference voltage
2
Conditions
Min
Max1
Unit
—
0
0
V
VDD_LV_CORx
SR Internal supply voltage
—
—
—
V
VSS_LV_CORx3
SR Internal reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
VDD_LV_PLL2
VSS_LV_PLL
3
TA
SR Ambient temperature under bias
fCPU  120 MHz
–40
125
°C
TJ
SR Junction temperature under bias
—
–40
150
°C
1
Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics
and I/Os DC electrical specification may not be guaranteed.
2 V
DD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same
voltage source.
3 Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced
by an on-chip voltage regulator.
4 For the device to function properly, the low voltage grounds (V
SS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one
is used.
3.4
Thermal characteristics
Table 10. Thermal characteristics for 144 LQFP package1
Symbol
RJA
RJMA
RJB
RJC
JT
D
D
D
D
D
Parameter
Conditions
Value Unit
Thermal resistance, junction-to-ambient natural Single layer board – 1s
convection2
Four layer board – 2s2p
42
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
34
Thermal resistance junction-to-board3
—
22
°C/W
—
8
°C/W
—
3
°C/W
4
Thermal resistance junction-to-case
Junction-to-package-top natural
convection5
°C/W
34
°C/W
28
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
2
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
75
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 11. Thermal characteristics for 257 MAPBGA package1
Symbol
RJA
RJMA
D
D
Parameter
46
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
37
—
13
°C/W
—
8
°C/W
—
2
°C/W
D
Thermal resistance junction-to-board3
RJC
D
Thermal resistance junction-to-case4
D
Value Unit
Thermal resistance junction-to-ambient natural Single layer board – 1s
convection2
Four layer board – 2s2p
RJB
JT
Conditions
Junction-to-package-top natural convection
5
°C/W
26
°C/W
22
1
Thermal characteristics are targets based on simulation that are subject to change per device characterization.
Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board
meets JEDEC specification for this package.
3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC
specification for the specified package.
4 Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate
temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5
Thermal characterization parameter indicating the temperature difference between the package top and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JT.
2
3.4.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
TJ = TA + (RJA × PD)
Eqn. 1
where:
TA
= ambient temperature for the package (oC)
RJA
= junction to ambient thermal resistance (oC/W)
PD
= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
RJA = RJC + RCA
Eqn. 2
where:
RJA
= junction to ambient thermal resistance (°C/W)
RJC
= junction to case thermal resistance (°C/W)
RCA = case to ambient thermal resistance (°C/W)
PXS20 Microcontroller Data Sheet, Rev. 1
76
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using Equation 3:
TJ = TT + (JT × PD)
Eqn. 3
where:
TT
= thermocouple temperature on top of the package (°C)
JT
= thermal characterization parameter (°C/W)
PD
= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
3.4.1.1
References
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or
303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1.
2.
3.
3.5
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine
Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic
Packaging and Production, pp. 53–58, March 1998.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application
in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
Electromagnetic Interference (EMI) characteristics (cut1)
The characteristics in Table 13 were measured using:
•
•
•
Device configuration, tet conditions, and EM testing per standard IEC61967-2
Supply voltage of 3.3 V DC
Ambient temperature of 25 C
The configuration information referenced in Table 13 is explained in Table 12.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
77
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 12. EMI configuration summary
Configuration name
Description
Configuration A
•
•
•
•
•
High emission = all pads have max slew rate, LVDS pads running at 40 MHz
Oscillator frequency = 40 MHz
System bus frequency = 80 MHz
No PLL frequency modulation
IEC level I ( 36 dBV)
Configuration B
•
•
•
•
•
Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
Oscillator frequency = 40 MHz
System bus frequency = 80 MHz
2% PLL frequency modulation
IEC level K( 30 dBV)
Table 13. EMI emission testing specifications
Symbol
VEME
3.6
Parameter
CC Radiated emissions
Conditions
Min
Typ
Max
Unit
Configuration A; frequency range
150 kHz–50 MHz
—
16
—
dBV
Configuration A; frequency range
50–150 MHz
—
16
—
Configuration A; frequency range
150–500 MHz
—
32
—
Configuration A; frequency range
500–1000 MHz
—
25
—
Configuration B; frequency range
50–150 MHz
—
15
—
Configuration B; frequency range
50–150 MHz
—
21
—
Configuration B; frequency range
150–500 MHz
—
30
—
Configuration B; frequency range
500–1000 MHz
—
24
—
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according
to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n + 1) supply pin).
This test conforms to the AEC-Q100-002/-003/-011 standard.
PXS20 Microcontroller Data Sheet, Rev. 1
78
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 14. ESD ratings1, 2
No.
Symbol
Parameter
Conditions
Class
Max value3
Unit
1
VESD(HBM)
SR Electrostatic discharge
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
2
VESD(MM)
SR Electrostatic discharge
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
V
3
VESD(CDM)
SR Electrostatic discharge TA = 25 °C
(Charged Device Model) conforming to AEC-Q100-011
C3A
500
V
750 (corners)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
3
Data based on characterization results, not tested in production.
3.7
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up performance:
•
•
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 15. Latch-up results
No.
1
3.8
Symbol
LU
Parameter
SR
Static latch-up class
Conditions
Class
TA = 125 °C conforming to JESD 78
II level A
Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
•
•
•
•
•
•
•
•
•
•
High power regulator HPREG1 (internal ballast to support core current)
High power regulator HPREG2 (external NPN to support core current)
Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO)
Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG)
Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH)
Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD)
Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD)
High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when external NPN transistor is present on
board to supply core current. The PXS20 always powers up using HPREG1 if an external NPN transistor is present. Then the
PXS20 makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is fully operational, the
controller part of HPREG1 is switched off. The following bipolar transistors are supported:
•
BCP68 from ON Semiconductor
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
79
Preliminary—Subject to Change Without Notice
Electrical characteristics
•
BCX68 from Infineon
Table 16. Voltage regulator electrical specifications
Symbol
CV1V2
Parameter
Conditions
Min
Typ
Max
Unit
Min, max values shall be
granted with respect to
tolerance, voltage,
temperature, and aging
variations.
12
—
40
µF
SR
External decoupling/
stability capacitor
SR
Combined ESR of
external capacitor
—
0.01
—
0.10

SR
Number of pins for
external decoupling/
stability capacitor
—
5
—
—
—
SR
Total capacitance on
1.2 V pins
Ceramic capacitors,
taking into account
tolerance, aging, voltage
and temperature variation
300
—
900
nF
Cload = 10 µF × 4
—
—
2.5
ms
tSU
Start-up time after main
supply stabilization
—
Main High Voltage Power Low Voltage Detection,
upper threshold
—
—
—
2.9
V
—
D
Main supply low voltage
detector, lower threshold
—
2.6
—
—
V
—
D
Digital supply high voltage
detector upper threshold
Before a destructive reset
initialization phase
completion
Cut2: 1.355
—
Cut1: 1.5
Cut2: 1.495
V
After a destructive reset
initialization phase
completion
Cut1: 1.32
Cut2: 1.43
—
Cut1: 1.4
Cut2: 1.47
Before a destructive reset
initialization phase
completion
Cut1: 1.330
Cut2: 1.315
—
Cut1: 1.4
Cut2: 1.455
After a destructive reset
initialization phase
completion
Cut2: 1.39
—
Cut2: 1.43
—
D
Digital supply high voltage
detector lower threshold
V
—
D
Digital supply low voltage
detector lower threshold
After a destructive reset
initialization phase
completion
1.080
—
Cut1: 1.110
Cut2: 1.12
V
—
D
Digital supply low voltage
detector upper threshold
After a destructive reset
initialization phase
completion
Cut1: 1.17
Cut2: 1.16
—
Cut1: 1.19
Cut2: 1.20
V
—
D
POR rising/ falling supply
threshold voltage
—
1.6
—
2.6
V
PXS20 Microcontroller Data Sheet, Rev. 1
80
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 16. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
3
—
0.5 ×106
V/s
—
SR
Supply ramp rate
—
D
LVD_MAIN: Time
constant of RC filter at
LVD input
3.3V noise rejection at the
input of
LVD comparator
1.1
—
—
µs
—
D
HVD_DIG: Time constant
of RC filter at LVD input
1.2V noise rejection at the
input of
LVD comparator
0.1
—
—
µs
—
D
LVD_DIG: Time constant
of RC filter at LVD input
1.2V noise rejection at the
input of
LVD comparator
0.1
—
—
µs
VDD
BCP68
BCRTL
V1V2 ring on board
Rb
Rs
Lb
ESR
Cv1v2
Cext
Cint
V1V2 pin
PXS20
Figure 5. BCP68 board schematic example
NOTE
The combined ESR of the capacitors used on 1.2 V pins (V1V2 in the picture) shall be in
the range of 30 m to 150 m. The minimum value of the ESR is constrained by the
resonance caused by the external components, bonding inductance, and internal
decoupling. The minimum ESR is required to avoid the resonance and make the regulator
stable.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
81
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.9
DC electrical characteristics
Table 17 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V).
Table 17. DC electrical characteristics1
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
D Minimum low level input voltage
—
–0.12
—
—
V
VIL
P Maximum level input voltage
—
—
—
0.35 VDD_HV_IOx
V
VIH
P Minimum high level input voltage
—
0.65 VDD_HV_IOx
—
—
V
D Maximum high level input voltage
—
—
—
VDD_HV_IOx + 0.1
V
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
—
V
VOL_S
P Slow, low level output voltage
IOL = 1.5 mA
—
—
0.5
V
VOH_S
P Slow, high level output voltage
—
—
V
VOL_M
P Medium, low level output voltage
IOL = 2 mA
—
—
0.5
V
VOH_M
P Medium, high level output voltage
IOH = –2 mA
VDD_HV_IOx – 0.8
—
—
V
VOL_F
P Fast, high level output voltage
IOL = 1.5 mA
—
—
0.5
V
VOH_F
P Fast, high level output voltage
—
—
V
—
0.5
V
—
—
V
VIH
VOL_SYM
P Symmetric, high level output voltage
VOH_SYM
P Symmetric, high level output voltage
IINJ
T DC injection current per pin
IPU
P Equivalent pull-up current
IPD
IIL
P Equivalent pull-down current
P Input leakage current
(all bidirectional ports)
IOH = –1.5 mA VDD_HV_IOx – 0.8
IOH = –1.5 mA VDD_HV_IOx – 0.8
IOL = 1.5 mA
—
–1
—
1
mA
VIN = VIL
–130
—
—
µA
VIN = VIH
—
—
–10
VIN = VIL
10
—
—
VIN = VIH
—
—
130
TJ = –40 to
+150 °C
-1
—
1
-0.5
—
0.5
-1
—
1
Input leakage current
(shared ADC input-only ports)
µA
A
VILR
P RESET, low level input voltage
—
–0.12
—
0.35 VDD_HV_IOx
V
VIHR
P RESET, high level input voltage
—
0.65 VDD_HV_IOx
—
VDD_HV_IOx+0.12
V
D RESET, Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
—
V
IOL = 2 mA
—
—
0.5
V
VIN = VIL
10
—
—
µA
VIN = VIH
—
—
130
VHYSR
VOLR
IPD
1
—
IOH = –1.5 mA VDD_HV_IOx – 0.8
Input leakage current
(all ADC input-only ports)
2
2
D RESET, low level output voltage
D RESET, equivalent pull-down current
These specifications are design targets and subject to change per device characterization.
“SR” parameter values must not exceed the absolute maximum ratings shown in Table 8.
PXS20 Microcontroller Data Sheet, Rev. 1
82
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.10
Supply current characteristics (cut2)
Current consumption data is given in Table 18. These specifications are design targets and are subject to change per device
characterization.
Table 18. Current consumption characteristics
Symbol
IDD_LV_FULL
+ IDD_LV_PLL
IDD_LV_TYP
+ IDD_LV_PLL
IDD_LV_TYP
+ IDD_LV_PLL1
IDD_LV_BIST
+ IDD_LV_PLL
IDD_LV_STOP
IDD_LV_HALT
Parameter
Conditions
Min
Typ
Max
Unit
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
50 mA+
2.18 mA*fCPU[MHz]
mA
1.2 V supplies
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
80 mA+
2.50 mA*fCPU[MHz]
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
26 mA+
2.10 mA*fCPU[MHz]
1.2 V supplies
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
41 mA+
2.30 mA*fCPU[MHz]
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
279 mA
1.2 V supplies
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
318 mA
1.2 V supplies during
LBIST (full LBIST
configuration)
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
TBD
1.2 V supplies
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
TBD
T Operating current in
VDD STOP mode
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
50
T
TJ = 55 C
VDD_LV_COR = 1.32 V
—
—
57
P
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
80
T Operating current in
VDD HALT mode
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
58
T
TJ = 55 C
VDD_LV_COR = 1.32 V
—
—
64
P
TJ = 150 C
VDD_LV_COR = 1.32 V
—
—
72
T Operating current
T Operating current
P Operating current
T Operating current
mA
mA
mA
mA
mA
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
83
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 18. Current consumption characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IDD_HV_ADC2,3
T Operating current
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_ADC = 3.6 V
—
—
10
mA
IDD_HV_AREF3
T Operating current
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF = 3.6 V
—
—
3
mA
TJ = 150 C
120 MHz
ADC operating at 60 MHz
VDD_HV_REF = 5.5 V
—
—
5
IDD_HV_OSC
T Operating current
TJ = 150 C
3.3 V supplies
120 MHz
—
—
900
A
IDD_HV_FLASH4
T Operating current
TJ = 150 C
3.3 V supplies
120 MHz
—
—
4
mA
1
Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1, PIT,
CRC, PLL0/1, I/O supply current excluded
2 Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum
injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.
3 This value is the total current for both ADCs.
4 VFLASH is only available in the calibration package.
3.11
Temperature sensor electrical characteristics
Table 19. Temperature sensor electrical characteristics
Symbol
—
TS
3.12
P
D
Parameter
Accuracy
Minimum sampling period
Conditions
Min
Max
Unit
TJ = –40 °C to TA = 25 °C
–10
10
°C
TJ = TA to 125 °C
–7
7
°C
4
—
µs
—
Main oscillator electrical characteristics
The device provides an oscillator/resonator driver. Figure 6 describes a simple model of the internal oscillator driver and
provides an example of a connection for an oscillator or a resonator.
PXS20 Microcontroller Data Sheet, Rev. 1
84
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
EXTAL
Crystal
CL
EXTAL
RP
XTAL
CL
DEVICE
VDD
I
EXTAL
Resonator
R
XTAL
DEVICE
XTAL
DEVICE
Figure 6. Crystal oscillator and resonator connection scheme
NOTE
XTAL/EXTAL must not be directly used to drive external circuits.
MTRANS
1
0
VXTAL
1/fXOSCHS
VXOSCHS
90%
VXOSCHSOP
10%
TXOSCHSSU
valid internal clock
Figure 7. Main oscillator electrical characteristics
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
85
Preliminary—Subject to Change Without Notice
Electrical characteristics
×
Table 20. Main oscillator electrical characteristics
Symbol
Value
Conditions1
Parameter
Unit
Typ
Max
4.0
—
40.0
MHz
fXOSCHS
SR Oscillator frequency
gmXOSCHS
P Oscillator
transconductance
VDD = 3.3 V ±10%
4.5
—
13.25
mA/V
VXOSCHS
D Oscillation amplitude
fOSC = 4, 8, 10, 12, 16 MHz
1.3
—
—
V
fOSC = 40 MHz
1.1
—
—
D Oscillation operating
point
—
—
0.82
—
V
IXOSCHS
D Oscillator consumption
—
—
—
3.5
mA
TXOSCHSSU
T Oscillator start-up time
—
—
6
ms
—
—
2
VXOSCHSOP
—
Min
fOSC = 4, 8, 10, 12 MHz2
fOSC = 16, 40
1
2
3.13
MHz2
VIH
SR Input high level CMOS
Schmitt Trigger
Oscillator bypass mode
0.65 × VDD
—
VDD + 0.4
V
VIL
SR Input low level CMOS
Schmitt Trigger
Oscillator bypass mode
–0.4
—
0.35 × VDD
V
VDD = 3.3 V ±10%, TJ = –40 to +150 °C, unless otherwise specified.
The recommended configuration for maximizing the oscillator margin are:
XOSC_MARGIN = 0 for 4 MHz quartz
XOSC_MARGIN = 1 for 8/16/40 MHz quartz
FMPLL electrical characteristics
Table 21. FMPLL electrical characteristics
Symbol
Parameter
Conditions
fREF_CRYSTAL D FMPLL reference frequency
fREF_EXT
range1
fPLL_IN
Typ
Max
Unit
4
—
40
MHz
—
4
—
16
MHz
—
4
—
1202
MHz
20
—
150
MHz
Crystal reference
D Phase detector input frequency
range (after pre-divider)
fFMPLLOUT D Clock frequency range in normal
mode
fFREE
Min
P Free running frequency
Measured using clock division
(typically 16)
fsys
D On-chip FMPLL frequency2
—
16
—
120
MHz
tCYC
D System clock period
—
—
—
1 / fsys
ns
fLORL
fLORH
D Loss of reference frequency
window3
Lower limit
1.6
—
3.7
MHz
Upper limit
24
—
56
—
20
—
TBD
MHz
Stable oscillator (fPLLIN = 4 MHz),
stable VDD
—
—
200
µs
4,5
fSCM
D Self-clocked mode frequency
tLOCK
P Lock time
PXS20 Microcontroller Data Sheet, Rev. 1
86
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 21. FMPLL electrical characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
—
—
200
s
—
40
—
60
%
–6
—
6
ns
T Single period jitter (peak to peak) PHI @ 120 MHz,
Input clock @ 4 MHz
—
—
175
ps
PHI @ 100 MHz,
Input clock @ 4 MHz
—
—
185
ps
PHI @ 80 MHz,
Input clock @ 4 MHz
—
—
200
ps
PHI @ 16 MHz,
Input clock @ 4 MHz
—
—
±6
ns
tlpll
D FMPLL lock time 6, 7
tdc
D Duty cycle of reference
CJITTER
tPKJIT
tLTJIT
T CLKOUT period jitter
8,9,10,11
T Long term jitter
Long-term jitter (avg. over 2 ms
interval), fSYS maximum
fLCK
D Frequency LOCK range
—
–6
—
6
%
fsys
fUL
D Frequency un-LOCK range
—
–18
—
18
%
fsys
fCS
fDS
D Modulation Depth
Center spread
±0.25
—
±2.012
Down Spread
–0.5
—
-8.0
%
fsys
—
—
100
kHz
fMOD
D Modulation
frequency13
—
1
Considering operation with FMPLL not bypassed.
With FM; the value does not include a possible +2% modulation
3 “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self
clocked mode.
4 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls
outside the fLOR window.
5 f
VCO is the frequency at the output of the VCO; its range is 256–512 MHz.
fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
fSYS = fVCOODF
6 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this FMPLL, load capacitors should not exceed these limits.
7 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control
bits in the synthesizer control register (SYNCR).
8 This value is determined by the crystal manufacturer and board design.
9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
10 Proper PC board layout procedures must be followed to achieve specifications.
11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C
JITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12 This value is true when operating at frequencies above 60 MHz, otherwise f
CS is 2% (above 64 MHz).
13
Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.
2
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
87
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.14
16 MHz RC oscillator electrical characteristics
Table 22. RC oscillator electrical characteristics
Symbol
Conditions
P RC oscillator frequency
fRC
RCMVAR
3.15
Parameter
TJ = 25 °C
P Fast internal RC oscillator variation with
respect to fRC.
—
Min
Typ
Max
Unit
—
16
—
MHz
—
—
±5
%
ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter.
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
( 2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out
7
( 1)
6
5
(5)
4
(4)
3
(3)
2
1
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
1 LSB (ideal)
0
1
2
3
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Offset Error OSE
Figure 8. ADC characteristics and error definitions
3.15.1
Input Impedance and ADC Accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to
PXS20 Microcontroller Data Sheet, Rev. 1
88
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being
substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained
(REQ = 1 / (fC  CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the
voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external
circuit must be designed to respect the Equation 4:
R S + R F + R L + R SW + R AD
1
V A  ---------------------------------------------------------------------------  --- LSB
R EQ
2
Eqn. 4
Equation 4 generates a constraint for external network design, in particular on resistive path. Internal switch resistances (RSW
and RAD) can be neglected with respect to external resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
VA
Filter
RF
Current Limiter
Channel
Selection
Sampling
RSW1
RAD
RL
CF
CP1
CP2
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
Current Limiter Resistance
RL
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 9. Input Equivalent Circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 9): A charge sharing phenomenon is
installed when the sampling phase is started (A/D switch close).
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
89
Preliminary—Subject to Change Without Notice
Electrical characteristics
Voltage Transient on CS
VCS
VA
VA2
V <0.5 LSB
1
2
1 < (RSW + RAD) CS << TS
2 = RL (CS + CP1 + CP2)
VA1
TS
t
Figure 10. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
•
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
CP  CS
 1 =  R SW + R AD   --------------------CP + CS
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
 1   R SW + R AD   C S « T S
Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 
•
Eqn. 7
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
 2  R L   C S + C P1 + C P2 
Eqn. 8
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
10   2 = 10  R L   C S + C P1 + C P2   TS
Eqn. 9
PXS20 Microcontroller Data Sheet, Rev. 1
90
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 
Eqn. 10
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Analog Source Bandwidth (VA)
TC 2 RFCF (Conversion Rate vs. Filter Pole)
fF  f0 (Anti-aliasing Filtering Condition)
Noise
2 f0 fC (Nyquist)
f0
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
f
Sampled Signal Spectrum (fC = conversion Rate)
f0
fC
f
Figure 11. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
Eqn. 11
VA
C P1 + C P2 + C F
------------ = -------------------------------------------------------V A2
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 12
C F  2048  C S
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
91
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 23. ADC conversion characteristics
Conditions1
Min
SR ADC Clock frequency (depends on ADC
configuration)
(The duty cycle depends on AD_CK2
frequency)
—
3
—
60
MHz
SR Sampling frequency
—
—
—
1.003
MHz
60 MHz
383
—
—
ns
TBD
625
—
—
ns
Symbol
fCK
fs
tsample
Parameter
D Sample time4
5
Typ Max
Unit
tconv
D Conversion time
CS6
D ADC input sampling capacitance
—
—
—
7.32
pF
CP16
D ADC input pin capacitance 1
—
—
—
5(7)
pF
CP26
D ADC input pin capacitance 2
—
—
—
0.8
pF
VREF range = 4.5 to 5.5 V
—
—
0.3
k
VREF range = 3.0 to 3.6 V
—
—
875

D Internal resistance of analog source
—
—
—
825

P Integral non linearity
—
–2
—
2
LSB
—
–1
—
2
LSB
RSW16
RAD6
INL
D Internal resistance of analog source
linearity8
DNL
P Differential non
OFS
T Offset error
—
–6
—
6
LSB
GNE
T Gain error
—
–6
—
6
LSB
—
—
250
nA
–3
—
3
mA
150C
—
—
300
nA
|Vref_ad0 - Vref_ad1| <
150mV
–3.6
—
3.6
mA
IS1WINJ
(cut2 only)
(single ADC channel)
Max leakage
150C
Max positive/negative injection
IS1WWINJ
(cut2 only)
(double ADC channel)
Max leakage
Max positive/negative injection
SNR
T Signal-to-noise ratio
—
67
—
—
dB
THD
T Total harmonic distortion
—
TBD
—
—
dB
SINAD
T Signal-to-noise and distortion
—
65
—
—
dB
ENOB
T Effective number of bits
—
10.5
—
—
bits
Without current injection
–6
—
6
LSB
With current injection
–8
—
8
LSB
Without current injection
–8
—
8
LSB
With current injection
–10
—
10
LSB
TUEIS1WINJ
(cut2 only)
P Total unadjusted error for IS1WINJ
T
TUEIS1WWINJ P Total unadjusted error for IS1WWINJ
(cut2 only)
T
1
VDD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF.
AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3 This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is not
possible.
2
PXS20 Microcontroller Data Sheet, Rev. 1
92
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
4
5
6
7
8
During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance
of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time
tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample
depend on programming.
This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
See Figure 9.
For the 144-pin package.
No missing codes.
3.16
Flash memory electrical characteristics
Table 24. Flash memory program and erase electrical specifications
No.
5
6
Factory Initial Lifetime
Unit
Avg2 Max3 Max4
—
—
500
µs
—
48
53
100
500
µs
16 KB block pre-program and erase time
—
TBD
TBD
500
5000
ms
4
T48KPPERASE *5 48 KB block pre-program and erase time
—
TBD
TBD
750
5000
ms
5
T64KPPERASE *5 64 KB block pre-program and erase time
—
TBD
TBD
900
5000
ms
TPPROGRAM
Page(128 bits) program
3
T16KPPERASE
*5
7
4
Min Typ1
39
6
3
TDWPROGRAM *5 Double word (64 bits) program time6
*5
2
2
Parameter
—
1
1
Symbol
time6
T128KPPERASE
*5
128 KB block pre-program and erase time
—
TBD
TBD
1300
7500
ms
T256KPPERASE
*5
256 KB block pre-program and erase time
—
TBD
TBD
2600 15000
ms
Typical program and erase times assume nominal supply values and operation at TJ = 25 °C. These values are
characterized, but not tested.
Factory Average program and erase times represent the effective performance averaged over > 1024 pages or blocks,
and are provided for factory throughput estimation assuming < 100 program/erase cycles, nominal supply values and
operation at TJ = 25 °C. These values are characterized, but not tested.
Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100
program/erase cycles, nominal supply values and operation at TJ = 25 °C. These values are verified at production test.
Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These
values are characterized, but not tested.
See Notes for individual specifications, as shown in column headings.
Actual hardware programming times. These do not include software overhead.
Table 25. Flash memory timing
Value
Symbol
TRES
TDONE
Parameter
Unit
Min
Typ
Max
D Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low
—
—
100
ns
D Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared
—
—
5
ns
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
93
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 26. Flash memory module life
Value
No.
Symbol
Parameter
Unit
Min
Typ
Max
—
—
1000
1000002
—
20
10
5
—
—
—
—
—
—
1
P/E
C Number of program/erase cycles per block for 16 KB, 48 KB, 100000
and 64 KB blocks over the operating temperature range1
2
P/E
C Number of program/erase cycles per block for 128 KB and
256 KB blocks over the operating temperature range1
3
Retention C Minimum data retention at 85 °C average ambient temperature3
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
cycles
cycles
years
Operating temperature range is TJ from –40 °C to 150 °C. Typical endurance is evaluated at 25 C. Product
qualification is performed to the minimum specification. For additional information on the Freescale definition of
Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
2 Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks. For additional information on the Freescale
definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
3 Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
1
3.17
SWG electrical characteristics
Table 27. SWG electrical characteristics
Symbol
SINAD
3.18
3.18.1
Parameter
D
Signal-to-noise ratio plus distortion
Min
Max
Unit
50
—
dB
AC specifications
Pad AC specifications
Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 )1
No.
1
Tswitchon1
(ns)
Pad
Slow
T
Rise/Fall2
(ns)
Current slew3
(mA/ns)
Frequency
(MHz)
Load drive
(pF)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
3
—
40
—
—
40
—
—
4
0.01
—
2
25
3
—
40
—
—
50
—
—
2
0.01
—
2
50
3
—
40
—
—
75
—
—
2
0.01
—
2
100
3
—
40
—
—
100
—
—
2
0.01
—
2
200
PXS20 Microcontroller Data Sheet, Rev. 1
94
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 28. Pad AC specifications (3.3 V , IPP_HVE = 0 )1 (continued)
No.
2
3
Tswitchon1
(ns)
Pad
Medium
Fast
T
T
Rise/Fall2
(ns)
Current slew3
(mA/ns)
Frequency
(MHz)
Load drive
(pF)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
1
—
15
—
—
12
—
—
40
2.5
—
7
25
1
—
15
—
—
25
—
—
20
2.5
—
7
50
1
—
15
—
—
40
—
—
13
2.5
—
7
100
1
—
15
—
—
70
—
—
7
2.5
—
7
200
1
—
6
—
—
4
—
—
72
3
—
40
25
1
—
6
—
—
7
—
—
55
7
—
40
50
1
—
6
—
—
12
—
—
40
7
—
40
100
1
—
6
—
—
18
—
—
25
7
—
40
200
4
Symmetric
T
1
—
8
—
—
5
—
—
50
3
—
25
25
5
Pull Up/Down
(3.6 V max)
D
—
—
—
—
—
TBD
—
—
—
—
—
—
50
1
Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition.
Slope at rising/falling edge.
3 Data based on characterization results, not tested in production.
2
VDDE/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
VOH
Pad
Output
VOL
Figure 12. Pad output delay
3.19
Reset sequence
This section shows the duration for different reset sequences. It describes the different reset sequences and it specifies the start
conditions and the end indication for the reset sequences.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
95
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.19.1
Reset sequence duration
Table 29 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in
Section 3.19.2, Reset sequence description.
Table 29. RESET sequences
TReset
No.
1
1
Symbol
TDRB
Parameter
CC
Conditions
Destructive Reset Sequence, BIST enabled
2
TDR
CC
Destructive Reset Sequence, BIST disabled
3
TERLB
CC
External Reset Sequence Long, BIST enabled
Unit
Min
Typ
Max1
cut1
52
60
65
ms
cut2
40
47
51
ms
—
500
4200
5000
s
cut1
52
57
65
ms
cut2
41
45
49
ms
4
TFRL
CC
Functional Reset Sequence Long
—
35
150
400
s
5
TFRS
CC
Functional Reset Sequence Short
—
1
4
10
s
The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
3.19.2
Reset sequence description
The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the
figures indicate the starting point and the end point for which the duration is specified in Table 29. The start point and end point
conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3, Reset sequence
trigger mapping.
With the beginning of DRUN mode the first instruction is fetched and executed. At this point application execution starts and
the internal reset sequence is finished.
The figures below show the internal states of the chip during the execution of the reset sequence and the possible states of the
signal pin RESET.
NOTE
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an
external reset generator or by the chip internal reset circuitry. A high level on this pin can
only be generated by an external pull up resistor which is strong enough to overdrive the
weak internal pull down resistor. The rising edge on RESET in the following figures
indicates the time when the device stops driving it low. The reset sequence durations given
in table Table 29 are applicable only if the internal reset sequence is not prolonged by an
external reset generator keeping RESET asserted low beyond the last PHASE3.
PXS20 Microcontroller Data Sheet, Rev. 1
96
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
RESET_B
PHASE0
PHASE1,2
Establish IRC
and PWR
Flash init
PHASE3
BIST
Device
Self Test
Config
Setup
MBIST
PHASE1,2
LBIST
PHASE3
Flash init
DRUN
Device
Application
Config
Execution
TDRB, min < TReset < TDRB, max
Figure 13. Destructive Reset Sequence, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE0
PHASE1,2
Establish IRC
and PWR
Flash init
PHASE3
DRUN
Device
Application
Config
Execution
TDR, min < TReset < TDR, max
Figure 14. Destructive Reset Sequence, BIST disabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
RESET_B
PHASE1,2
Flash init
PHASE3
BIST
Device
Self Test
Config
Setup
MBIST
PHASE1,2
LBIST
Flash init
PHASE3
DRUN
Device
Application
Config
Execution
TERLB, min < TReset < TERLB, max
Figure 15. External Reset Sequence Long, BIST enabled
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
97
Preliminary—Subject to Change Without Notice
Electrical characteristics
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE1,2
Flash init
PHASE3
DRUN
Device
Application
Config
Execution
TFRL, min < TReset < TFRL, max
Figure 16. Functional Reset Sequence Long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE3
DRUN
Application
Execution
TFRS, min < TReset < TFRS, max
Figure 17. Functional Reset Sequence Short
The reset sequences shown in Figure 16 and Figure 17 are triggered by functional reset events. RESET is driven low during
these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to
drive RESET low for the duration of the internal reset sequence1.
3.19.3
Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It specifies the reset sequence start
conditions as well as the reset sequence end indications that are the basis for the timing data provided in Table 29.
1.See RGM_FBRE register for more details.
PXS20 Microcontroller Data Sheet, Rev. 1
98
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 30. Reset sequence trigger — reset sequence
Reset Sequence
Reset
Sequence
Start
Condition
Reset
Sequence
End
Indication
All internal
destructive reset
sources
(LVDs or internal
HVD during
power-up and
during
operation)
Section 3.1
9.4.1,
Destructive
reset
Release of
RESET2
Assertion of
RESET3
Section 3.1
9.4.2,
External
reset via
RESET
All internal
functional reset
sources
configured for
long reset
Sequence
starts with
internal
reset
trigger
Reset
Sequence
Trigger
All internal
functional reset
sources
configured for
short reset
1
2
3
4
5
6
7
Release of
RESET7
Destructiv
e Reset
Sequence,
BIST
disabled1
External
Reset
Sequenc
e Long,
BIST
enabled
Functiona
l Reset
Sequenc
e Long
Functiona
l Reset
Sequenc
e Short
triggers
cannot
trigger
cannot
trigger
cannot
trigger
cannot trigger
triggers4
triggers5
triggers6
cannot trigger
cannot
trigger
triggers
cannot
trigger
cannot trigger
cannot
trigger
cannot
trigger
triggers
Destructiv
e Reset
Sequence,
BIST
enabled1
Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.
End of the internal reset sequence (as specified in Table 29) can only be observed by release of RESET if it is not
held low externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till
RESET is released externally.
The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before.
RESET does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST
disabled. However, it can prolong these sequences if RESET is held low externally beyond the end of the internal
sequence (beyond PHASE3).
If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the
shadow sector of the NVM.
If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the
shadow sector of the NVM.
If RESET is configured for short reset
Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for
the functional reset source which triggered the reset sequence.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
99
Preliminary—Subject to Change Without Notice
Electrical characteristics
3.19.4
Reset sequence — start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage
rails / signals ramp up with a very slow slew rate compared to the overall reset sequence duration.
3.19.4.1
Destructive reset
Figure 18 shows the voltage threshold that determines the start of the Destructive Reset Sequence, BIST enabled and the start
for the Destructive Reset Sequence, BIST disabled.
V
Supply Rail
Vmax
Vmin
TReset, max starts here
t
TReset, min starts here
Figure 18. Reset sequence start for Destructive Resets
Table 31. Voltage Thresholds
3.19.4.2
Variable name
Value
Vmin
Refer to Table 16
Vmax
Refer to Table 16
Supply Rail
VDD_HV_PMU
External reset via RESET
Figure 19 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of RESET as
specified in Table 30.
PXS20 Microcontroller Data Sheet, Rev. 1
100
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
V
RESET_B
RESET
0.65 * VDD_HV_IO
0.35 * VDD_HV_IO
t
TReset, max starts here
TReset, min starts here
Figure 19. Reset sequence start via RESET assertion
3.19.5
External watchdog window
If the application design requires the use of an external watchdog the data provided in Section 3.19, Reset sequence can be used
to determine the correct positioning of the trigger window for the external watchdog. Figure 20 shows the relationships between
the minimum and the maximum duration of a given reset sequence and the position of an external watchdog trigger window.
Watchdog needs to be triggered within this window
TWDStart, min
External Watchdog Window Closed
External Watchdog Window Open
TWDStart, max
External Watchdog Window Closed
External Watchdog Window Open
Watchdog trigger
Basic Application Init
TReset, min
Application Running
TReset, max
Earliest
Application
Start
Basic Application Init
Application Running
Latest
Application
Start
Application time required to
prepare watchdog trigger
Internal Reset Sequence
Start condition (signal or voltage rail)
Figure 20. Reset sequence - External watchdog trigger window position
3.20
AC timing characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows:
• TJ = –40 to 150 C
• Supply voltages as specified in Table 9
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
101
Preliminary—Subject to Change Without Notice
Electrical characteristics
• Input conditions: All Inputs: tr, tf = 1 ns
• Output Loading: All Outputs: 50 pF
3.20.1
RESET pin characteristics
The PXS20 implements a dedicated bidirectional RESET pin.
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
Figure 21. Start-up reset requirements
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
Figure 22. Noise filtering on reset signal
PXS20 Microcontroller Data Sheet, Rev. 1
102
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 32. RESET electrical characteristics
No.
1
1
2
Symbol
Parameter
D Output transition time output pin
Ttr
2
2
WFRST
3
WNFRST P nRESET input not filtered pulse
Conditions1
Min
Typ
Max
Unit
CL = 25pF
—
—
12
ns
CL = 50pF
—
—
25
CL = 100pF
—
—
40
—
—
—
40
ns
—
500
—
—
ns
P nRESET input filtered pulse
VDD = 3.3 V ± 10%, TJ = –40 to +150 °C, unless otherwise specified
CL includes device and package capacitance (CPKG < 5 pF).
3.20.2
WKUP/NMI timing
Table 33. WKUP/NMI glitch filter
No.
3.20.3
Symbol
Parameter
1
WFNMI
2
WNFNMI D NMI pulse width that is passed
Min
Typ
Max
Unit
—
—
45
ns
205
—
—
ns
D NMI pulse width that is rejected
IEEE 1149.1 JTAG interface timing
Table 34. JTAG pin AC electrical characteristics
No.
Symbol
Parameter
Conditions
Min Max Unit
1
tJCYC
D TCK cycle time
—
62.5
—
ns
2
tJDC
D TCK clock pulse width (measured at VDDE/2)
—
40
60
%
3
tTCKRISE
D TCK rise and fall times (40%–70%)
—
—
3
ns
4
tTMSS, tTDIS
D TMS, TDI data setup time
—
5
—
ns
5
tTMSH, tTDIH D TMS, TDI data hold time
—
25
—
ns
6
tTDOV
D TCK low to TDO data valid
—
—
20
ns
7
tTDOI
D TCK low to TDO data invalid
—
0
—
ns
8
tTDOHZ
D TCK low to TDO high impedance
—
—
20
ns
11
tBSDV
D TCK falling edge to output valid
—
—
50
ns
12
tBSDVZ
D TCK falling edge to output valid out of high impedance
—
—
50
ns
13
tBSDHZ
D TCK falling edge to output high impedance
—
—
50
ns
14
tBSDST
D Boundary scan input valid to TCK rising edge
—
50
—
ns
15
tBSDHT
D TCK rising edge to boundary scan input invalid
—
50
—
ns
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
103
Preliminary—Subject to Change Without Notice
Electrical characteristics
TCK
2
3
2
1
3
Figure 23. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 24. JTAG test access port timing
PXS20 Microcontroller Data Sheet, Rev. 1
104
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 25. JTAG boundary scan timing
3.20.4
Nexus timing
Table 35. Nexus debug port timing1
No.
Symbol
Parameter
1
tMCYC
D MCKO Cycle Time
2
tMDC
D MCKO Duty Cycle
D MCKO Low to MDO, MSEO, EVTO Data
Conditions Min
Valid2
Max
Unit
—
15.6
—
ns
—
40
60
%
—
–0.1
0.25 tMCYC
3
tMDOV
4
tEVTIPW
D EVTI Pulse Width
—
4.0
5
tEVTOPW
D EVTO Pulse Width
—
1
—
62.5
—
ns
—
40
60
%
—
8
—
ns
5
—
ns
0
25
ns
6
tTCYC
D TCK Cycle Time
7
tTDC
D TCK Duty Cycle
3
8
tNTDIS, tNTMSS D TDI, TMS Data Setup Time
9
tNTDIH, tNTMSH D TDI, TMS Data Hold Time
10
tJOV
D TCK Low to TDO/RDY Data Valid
—
tTCYC
tMCYC
1
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is
measured from 50% of MCKO and 50% of the respective signal.
2 For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
105
Preliminary—Subject to Change Without Notice
Electrical characteristics
3
The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
EVTI
4
Figure 26. Nexus output timing
MCKO
MDO, MSEO
MDO/MSEO data are valid during MCKO rising and falling edge
Figure 27. Nexus Double Data Rate (DDR) Mode output timing
PXS20 Microcontroller Data Sheet, Rev. 1
106
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
6
7
TCK
8
9
TMS, TDI
10
TDO/RDY
Figure 28. Nexus TDI, TMS, TDO timing
3.20.5
External interrupt timing (IRQ pin)
Table 36. External interrupt timing
No.
Parameter
Conditions
Min Max Unit
1
tIPWL
D IRQ pulse width low
—
3
—
tCYC
2
tIPWH
D IRQ pulse width high
—
3
—
tCYC
—
6
—
tCYC
3
1
Symbol
tICYC
D IRQ edge to edge
time1
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
107
Preliminary—Subject to Change Without Notice
Electrical characteristics
IRQ
1
2
3
Figure 29. External interrupt timing
3.20.6
DSPI timing
Table 37. DSPI timing
No.
1
Symbol
tSCK
D
Parameter
DSPI cycle time
Conditions
Master (MTFE = 0)
D
Slave (MTFE = 0)
D
Slave Receive Only
Mode1
Min
Max
Unit
62
—
ns
62
—
16
—
2
tCSC
D
PCS to SCK delay
—
16
—
ns
3
tASC
D
After SCK delay
—
16
—
ns
4
tSDC
D
SCK duty cycle
—
5
tA
D
Slave access time
SS active to SOUT valid
—
40
ns
6
tDIS
D
Slave SOUT disable time
SS inactive to SOUT High-Z or invalid
—
10
ns
7
tPCSC
D
PCSx to PCSS time
—
13
—
ns
8
tPASC
D
PCSS to PCSx time
—
13
—
ns
9
tSUI
D
Data setup time for inputs
Master (MTFE = 0)
20
—
ns
Slave
2
—
Master (MTFE = 1, CPHA = 0)
5
—
Master (MTFE = 1, CPHA = 1)
20
—
Master (MTFE = 0)
–5
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
11
—
Master (MTFE = 1, CPHA = 1)
–5
—
Master (MTFE = 0)
—
4
Slave
—
23
Master (MTFE = 1, CPHA = 0)
—
12
Master (MTFE = 1, CPHA = 1)
—
4
10
11
tHI
tSUO
D
D
Data hold time for inputs
Data valid (after SCK edge)
tSCK/2 - 10 tSCK/2 + 10
ns
ns
ns
PXS20 Microcontroller Data Sheet, Rev. 1
108
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
Table 37. DSPI timing (continued)
No.
Symbol
12
tHO
1
D
Parameter
Conditions
Data hold time for outputs
Min
Max
Unit
Master (MTFE = 0)
–2
—
ns
Slave
6
—
Master (MTFE = 1, CPHA = 0)
6
—
Master (MTFE = 1, CPHA = 1)
–2
—
Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data
on SIN, but no valid data is transmitted on SOUT.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Note: The numbers shown are referenced in Table 37.
Figure 30. DSPI classic SPI timing — master, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
109
Preliminary—Subject to Change Without Notice
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
11
Data
First Data
Last Data
Note: The numbers shown are referenced in Table 37.
Figure 31. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Note: The numbers shown are referenced in Table 37.
Figure 32. DSPI classic SPI timing — slave, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
110
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Note: The numbers shown are referenced in Table 37.
Figure 33. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
First Data
Last Data
Data
11
Data
Last Data
Note: The numbers shown are referenced in Table 37.
Figure 34. DSPI modified transfer format timing — master, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
111
Preliminary—Subject to Change Without Notice
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Note: The numbers shown are referenced in Table 37.
Figure 35. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Note: The numbers shown are referenced in Table 37.
Figure 36. DSPI modified transfer format timing – slave, CPHA = 0
PXS20 Microcontroller Data Sheet, Rev. 1
112
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Note: The numbers shown are referenced in Table 37.
Figure 37. DSPI modified transfer format timing — slave, CPHA = 1
7
8
PCSS
PCSx
Note: The numbers shown are referenced in Table 37.
Figure 38. DSPI PCS strobe (PCSS) timing
4
Package characteristics
4.1
Package mechanical data
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
113
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 39. 144 LQFP package mechanical drawing (1 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
114
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 40. 144 LQFP package mechanical drawing (2 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
115
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 41. 257 MAPBGA package mechanical drawing (1 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
116
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Package characteristics
Figure 42. 257 MAPBGA package mechanical drawing (2 of 2)
PXS20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
117
Preliminary—Subject to Change Without Notice
Ordering information
5
Ordering information
M PX S 20 10 V MM 120 R
Qualification status
Brand
Family
Class
Flash memory size
Temperature range
Package identifier
Operating frequency
Tape and reel indicator
Qualification status
P = Pre-qualification (engineering samples)
M = Fully spec. qualified, general market flow
S = Fully spec. qualified, automotive flow
Temperature range
V = –40 °C to 105 °C
(ambient)
Family
D = Display Graphics
N = Connectivity/Network
R = Performance/Real Time Control
S = Safety
Package identifier
LQ = 144 LQFP
MM = 257 MAPBGA
Operating frequency
80 = 80 MHz
120 = 120 MHz
Flash Memory Size
05 = 512 KB
10 = 1 MB
Tape and reel status
R = Tape and reel
(blank) = Trays
Note: Not all options are available on all devices. See Table 38 for more information.
Figure 43. PXS20 orderable part number description
Table 38. PXS20 orderable part number summary
6
Part number
Flash/SRAM
Package
Speed
(MHz)
MPXS2005VLQ80
512 KB / 128 KB
144 LQFP (20 mm x 20 mm)
80
MPXS2010VLQ80
1 MB / 128 KB
144 LQFP (20 mm x 20 mm)
80
MPXS2010VMM80
1 MB / 128 KB
257 MAPBGA (14 mm x 14 mm)
80
MPXS2010VLQ120
1 MB / 128 KB
144 LQFP (20 mm x 20 mm)
120
MPXS2010VMM120
1 MB / 128 KB
257 MAPBGA (14 mm x 14 mm)
120
Document revision history
Table 39 summarizes revisions to this document.
Table 39. Revision history
Revision
1
Date
Description of Changes
30 Sep 2011 Initial release.
PXS20 Microcontroller Data Sheet, Rev. 1
118
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd. Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
[email protected]
Freescale Semiconductor Literature Distribution Center
1-800-441-2447 or +1-303-675-2140
Fax: +1-303-675-2150
[email protected]
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. The described product contains a PowerPC processor
core. The PowerPC name is a trademark of IBM Corp. and used under license.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2011. All rights reserved.
PXS20
Rev. 1
09/2011