AD DAC08AQ 8-bit, high-speed, multiplying d/a converter (universal digital logic interface) Datasheet

a
8-Bit, High-Speed, Multiplying D/A Converter
(Universal Digital Logic Interface)
DAC08
FEATURES
Fast Settling Output Current: 85 ns
Full-Scale Current Prematched to ⴞ1 LSB
Direct Interface to TTL, CMOS, ECL, HTL, PMOS
Nonlinearity to 0.1% Maximum over
Temperature Range
High Output Impedance and Compliance:
–10 V to +18 V
Complementary Current Outputs
Wide Range Multiplying Capability: 1 MHz Bandwidth
Low FS Current Drift: ⴞ10 ppm/ⴗC
Wide Power Supply Range: ⴞ4.5 V to ⴞ18 V
Low Power Consumption: 33 mW @ ⴞ5 V
Low Cost
Available in Die Form
full-scale currents eliminates the need for full-scale trimming in
most applications. Direct interface to all popular logic families
with full noise immunity is provided by the high swing, adjustable threshold logic input.
High voltage compliance complementary current outputs are
provided, increasing versatility and enabling differential operation to effectively double the peak-to-peak output swing. In
many applications, the outputs can be directly converted to
voltage without the need for an external op amp.
All DAC08 series models guarantee full 8-bit monotonicity,
and nonlinearities as tight as ± 0.1% over the entire operating
temperature range are available. Device performance is essentially unchanged over the ± 4.5 V to ± 18 V power supply range,
with 33 mW power consumption attainable at ± 5 V supplies.
The compact size and low power consumption make the DAC08
attractive for portable and military/aerospace applications;
devices processed to MIL-STD-883, Level B are available.
GENERAL DESCRIPTION
The DAC08 series of 8-bit monolithic digital-to-analog converters provide very high-speed performance coupled with low cost
and outstanding applications flexibility.
Advanced circuit design achieves 85 ns settling times with very
low “glitch” energy and at low power consumption. Monotonic
multiplying performance is attained over a wide 20-to-1 reference
current range. Matching to within 1 LSB between reference and
DAC08 applications include 8-bit, 1 µs A/D converters, servo
motor and pen drivers, waveform generators, audio encoders
and attenuators, analog meter drivers, programmable power
supplies, CRT display drivers, high-speed modems and other
applications where low cost, high speed and complete input/
output versatility are required.
FUNCTIONAL BLOCK DIAGRAM
V+
13
VLC
MSB
B1
1
5
B2
B3
6
B4
7
B5
8
9
B6
10
B7
11
LSB
B8
12
DAC08
VREF (+)
VREF (–)
BIAS
NETWORK
CURRENT
SWITCHES
14
4
2
IOUT
IOUT
15
REFERENCE
AMPLIFIER
16
COMP
3
V–
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
DAC08–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ VS = ⴞ15 V, IREF = 2.0 mA, –55ⴗC TA +125ⴗC for DAC08/08A, 0ⴗC TA +70ⴗC
for DAC08E and DAC08H, –40ⴗC to +85ⴗC for DAC08C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT .)
Parameter
Symbol Conditions
Resolution
Monotonicity
Nonlinearity
Settling Time
NL
tS
Propagation Delay
Each Bit
All Bits Switched
Full-Scale Tempco1
tPLH
tPHL
TCIFS
Min
DAC08A/H
Typ
Max
8
8
Min
DAC08E
Typ
8
8
VOC
To ± 1/2 LSB,
All Bits Switched ON
or OFF, TA = 25°C1
85
± 0.1
135
85
TA = 25°C1
35
35
± 10
60
60
± 50
35
35
± 10
Full Range Current
IFR4
Full Range Symmetry
Zero-Scale Current
Output Current Range
IFRS
IZS
IOR1
IOR2
Output Current Noise
Logic Input Levels
Logic “0”
Logic Input “1”
Logic Input Current
Logic “0”
Logic Input “1”
Logic Input Swing
Logic Threshold Range
Reference Bias Current
Reference Input
Slew Rate
VIL
VIL
IIL
IIH
VIS
VTHR
I15
dI/dt
Power Supply Sensitivity
PSSIFS+
PSSIFS–
Power Supply Current
I+
I–
I+
I–
I+
I–
Power Dissipation
PD
Full-Scale Current
Change <1/2 LSB,
ROUT > 20 MΩ typ
VREF = 10.000 V
R14, R15 = 5.000 kΩ
TA = 25°C
IFR4 – IFR2
R14, R15 = 5.000 kΩ
VREF = +15.0 V,
V– = –10 V
VREF = +25.0 V,
V– = –12 V
IREF = 2 mA
–10
+18
–10
1.984 1.992
2.000
1.94
± 0.5
0.1
±4
1
± 5 V, IREF = 1.0 mA
+5 V, –15 V,
IREF = 2.0 mA
± 15 V, IREF = 2.0 mA
Unit
85
± 0.39
150
Bits
Bits
% FS
ns
± 0.19
150
60
60
± 80
± 50
35
35
± 10
60
60
± 80
ns
ns
ppm/°C
+18
–10
+18
V
1.99
2.04
1.94
1.99
2.04
mA
±1
0.2
±8
2
±2
0.2
± 16
4
2.1
2.1
4.2
4.2
4.2
mA
25
25
0.8
25
0.8
2
–2
0.002
–10
–10
–10
10
+18
+13.5
–3
nA
0.8
V
V
–10
10
+18
+13.5
–3
µA
µA
V
V
µA
mA/µs
2
–2
0.002
–10
–10
–1
REQ = 200 Ω
4
8
4
RL = 100 Ω
CC = 0 pF
See Fast Pulsed Ref. Info Following.1
V+ = 4.5 V to 18 V
± 0.0003 ± 0.01
V– = –4.5 V to –18 V
± 0.002 ± 0.01
IREF = 1.0 mA
VS = +5 V, –15 V,
IREF = 2.0 mA
VS = ± 15 V,
IREF = 2.0 mA
Max
2.1
2
VS = ± 5 V, IREF = 1.0 mA
DAC08C
Typ
µA
µA
mA
VLC = 0 V
VLC = 0 V
VIN = –10 V to +0.8 V
VIN = 2.0 V to 18 V
V– = –15 V
VS = ± 15 V1
Min
8
8
DAC08E
Output Voltage
Compliance
(True Compliance)
Max
–1
8
–10
10
+18
+13.5
–3
–2
0.002
–10
–10
4
–1
8
± 0.0003 ± 0.01
± 0.002 ± 0.01
± 0.0003 ± 0.01
± 0.002 ± 0.01
%∆IO/%∆V+
%∆IO/%∆V–
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
2.3
–4.3
2.4
–6.4
2.5
–6.5
3.8
–5.8
3.8
–7.8
3.8
–7.8
mA
mA
mA
mA
mA
mA
33
48
33
48
33
48
mW
108
135
136
174
103
135
136
174
108
135
136
174
mW
mW
NOTES
1
Guaranteed by design.
Specifications subject to change without notice.
–2–
REV. B
DAC08
TYPICAL ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Reference Input Slew Rate
Propagation Delay
Settling Time
dI/dt
tPLH, tPHL
tS
(@ VS = ⴞ15 V, and IREF = 2.0 mA, unless otherwise noted. Output
characteristics apply to both IOUT and IOUT .)
Conditions
TA = 25°C, Any Bit
To ± 1/2 LSB, All Bits
Switched ON or OFF,
TA = 25°C
All Grades
Typical
Unit
8
35
mA/µs
ns
85
ns
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS 1
Operating Temperature
DAC08AQ, Q . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
DAC08HQ, EQ, CQ, HP, EP . . . . . . . . . . . . 0°C to +70°C
DAC08CP, CS . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature (TJ) . . . . . . . . . . . . . –65°C to +150°C
Storage Temperature Q Package . . . . . . . . . –65°C to +150°C
Storage Temperature P Package . . . . . . . . . –65°C to +125°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
V+ Supply to V– Supply . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . V– to V– plus 36 V
VLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V– to V+
Analog Current Outputs (at VS– = 15 V) . . . . . . . . . . 4.25 mA
Reference Input (V14 to V15) . . . . . . . . . . . . . . . . . . . V– to V+
Reference Input Differential Voltage
(V14 to V15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Reference Input Current (I14) . . . . . . . . . . . . . . . . . . . 5.0 mA
Package Type
␪JA2
␪JC
Unit
16-Lead Cerdip (Q)
16-Lead Plastic DIP (P)
20-Terminal LCC (RC)
16-Lead SO (S)
100
82
76
111
16
39
36
35
°C/W
°C/W
°C/W
°C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for worst-case mounting conditions, i.e., θJA is specified for device
in socket for cerdip, Plastic DIP, and LCC packages; θJA is specified for device
soldered to printed circuit board for SO package.
ORDERING GUIDE1
Model
NL
Temperature
Range
Package
Description
Package
Option
# Parts Per
Container
DAC08AQ
DAC08AQ2/883C
DAC08HP
DAC08HQ
DAC08Q
DAC08Q2/883C
DAC08RC/883C
DAC08EP
DAC08EQ
DAC08ES
DAC08ES-REEL
DAC08CP
DAC08CQ
DAC08CS
DAC08CS-REEL
DAC08NBC
DAC08GBC
DAC08GRBC
± 0.10%
± 0.10%
± 0.10%
± 0.10%
± 0.19%
± 0.19%
± 0.19%
± 0.19%
± 0.19%
± 0.19%
± 0.19%
± 0.39%
± 0.39%
± 0.39%
± 0.39%
± 0.10%
± 0.19%
± 0.39%
–55°C to +125°C
–55°C to +125°C
0°C to 70°C
0°C to 70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
25°C
25°C
25°C
Cerdip-16
Cerdip-16
P-DIP-16
Cerdip-16
Cerdip-16
Cerdip-16
LCC-20
P-DIP-16
Cerdip-16
SO-16
SO-16
P-DIP-16
Cerdip-16
SO-16
SO-16
DICE
DICE
DICE
Q-16
Q-16
N-16
Q-16
Q-16
Q-16
E-20
N-16
Q-16
R-16A (Narrow Body)
R-16A (Narrow Body)
N-16
Q-16
R-16A (Narrow Body)
R-16A (Narrow Body)
25
25
25
25
25
25
55
25
25
47
2500
25
25
47
2500
NOTES
1
Devices processed in total compliance to MIL-STD-883. Consult factory for 883 data sheet.
2
For availability and burn-in information on SO and PLCC packages, contact your local sales office.
The DAC08 contains 84 transistors. Die size 63 mil x 87 mil = 5,481 square mils.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the DAC08 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
WARNING!
ESD SENSITIVE DEVICE
DAC08
PIN CONNECTIONS
V–
14 VREF (+)
VREF (–)
3
14 B6
COMP 4
13 B5
12 B8 LSB
VLC 5
12 B4
B2 6
11 B7
IOUT 6
11 B3
B3 7
10 B6
V– 7
10 B2
B4 8
9
B5
IOUT 8
MSB B1 5
13 V+
9
3
1
2
20 19
18
VREF (+)
5
17
V+
6
16
NC
7
15
B8 LSB
8
14
B7
V– 4
IOUT
NC
MSB B1
B2
9 10 11 12 13
B1 MSB
B3
IOUT 4
B6
15 B7
3
B5
IOUT
2
NC
COMP
16 B8 LSB
VREF (+)
NC
V+ 1
15 VREF (–)
IOUT
VLC
16 COMPENSATION
2
B4
VLC 1
DAC08RC/883 20-Lead LCC
(RC Suffix)
VREF (–)
16-Lead SO
(S Suffix)
16-Lead Dual-In-Line Package
(Q and P Suffix)
NC = NO CONNECT
DICE CHARACTERISTICS
(125°C Tested Dice Available)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
V LC
IOUT
V–
IOUT
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8 (LSB)
V+
V REF (+)
V REF (–)
COMP
DIE SIZE 0.087 ⴛ 0.063 inch, 5,270 sq. mils
(2.209 ⴛ 1.60 mm, 3.54 sq. mm)
–4–
REV. B
DAC08
WAFER TEST LIMITS
(@ VS = ⴞ15 V, IREF = 2.0 mA; TA = 25ⴗC, unless otherwise noted. Output characteristics apply to both
IOUT and IOUT .)
Parameter
Symbol
Resolution
Monotonicity
Nonlinearity
Output Voltage
Compliance
Full-Scale Current
Full-Scale Symmetry
Zero-Scale Current
Output Current Range
NL
VOC
IFS4 or
IFS2
IFSS
IZS
IFS1 or
IFS2
Logic Input “0”
Logic Input “1”
Logic Input Current
Logic “0”
Logic “1”
Logic Input Swing
IIL
IIH
VIS
Reference Bias Current
Power Supply
Sensitivity
I15
PSSIFS+
PSSIFS–
Power Supply Current
I+
Power Dissipation
PD
Conditions
Full-Scale Current
Change < 1/2 LSB
VREF = 10.000 V
R14, R15 = 5.000 kΩ
V– = –10 V,
VREF = +15 V
V– = –12 V,
VREF = +25 V
R14, R15 = 5.000 kΩ
VIL
VIH
VLC = 0 V
VIN = –10 V to +0.8 V
VIN = +2.0 V to +18 V
V– = –15 V
V+ = +4.5 V to +18 V
V– = –4.5 V to –18 V
IREF = 1.0 mA
VS = ± 15 V
IREF ≤ 2.0 mA
VS = ± 15 V
IREF ≤ 2.0 mA
DAC08N
Limit
DAC08G
Limit
DAC08GR
Limit
Unit
8
8
± 0.1
+18
–10
2.04
1.94
±8
2
8
8
± 0.19
+18
–10
2.04
1.94
±8
4
8
8
± 0.39
+18
–10
2.04
1.94
± 16
4
Bits min
Bits min
% FS max
V max
V min
mA max
mA min
µA max
µA max
2.1
2.1
2.1
mA min
4.2
4.2
4.2
mA min
0.8
2
0.8
2
0.8
2
V max
V min
± 10
± 10
+18
–10
–3
0.01
± 10
± 10
+18
–10
–3
0.01
± 10
± 10
+18
–10
–3
0.01
µA max
µA max
V max
V min
µA max
% FS/% V max
3.8
–7.8
174
3.8
–7.8
174
3.8
–7.8
174
mA max
µA max
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
REV. B
–5–
DAC08
+VREF
0mA
RREF OPTIONAL RESISTOR
FOR OFFSET INPUTS
RIN
14
REQ
200⍀
0V
RP
4
15
TYPICAL VALUES:
RIN = 5k⍀
+VIN = 10V
16
IOUT
RL
2
1.0mA
RL
2.0mA
IOUT
NO CAP
(0000|0000)
Figure 1. Pulsed Reference Operation
C2
(1111|1111)
Figure 4. True and Complementary Output Operation
R1 = 9k⍀
C1 = 0.001␮F
C2, C3 = 0.01␮F
+18V
C1
IREF = 2mA
5mV
R1
2V
2.4V
16 15 14 13 12
11 10 9
DAC08
1
2
3
4
5
6
7
0.4V
0V
8
8␮A
0
50ns
100mV
C3
50ns/DIVISION
–18V MIN
Figure 5. LSB Switching
Figure 2. Burn-in Circuit
ALL BITS SWITCHED ON
1V
2.4V
2.5V
LOGIC INPUT
0.5V
OUTPUT –1/2LSB
SETTLING
0V
+1/2LSB
1V
0.4V
–0.5mA
IOUT
–2.5mA
200ns
100mV
REQ 200⍀
RL = 100⍀
CC = 0
10mV
SETTLING TIME FIXTURE
IFS = 2mA, RL = 1k⍀
1/2LSB = 4␮A
200ns/DIVISION
Figure 3. Fast Pulsed Reference Operation
50ns
50ns/DIVISION
Figure 6. Full-Scale Settling Time
–6–
REV. B
Typical Performance Characteristics–DAC08
4.0
3.0
2.0
LIMIT FOR
V– = –5V
1.0
10
500
LIMIT FOR
V– = –15V
400
300
200
R14 = R15 = 1k⍀
8 RL 500⍀
ALL BITS “ON”
6
VR15 = 0V
4
RELATIVE OUTPUT – dB
TA = T MIN TO TMAX
ALL BITS “HIGH”
PROPAGATION DELAY – ns
IFS, OUTPUT CURRENT – mA
5.0
1LSB = 7.8␮A
2
–2
–4
1
–6 1. C = 15pF, V = 2.0V p–p
C
IN
CENTERED AT +1.0V
–8
LARGE SIGNAL
–10 2. C = 15pF, V = 50mV p–p
C
IN
CENTERED AT +200mV
–12
SMALL SIGNAL
–14
0.1
0.2
0.5
1.0
2.0
FREQUENCY – MHz
100
1LSB = 61nA
0.0
0.0
1.0
2.0
3.0
4.0
IREF , REFERENCE CURRENT – mA
5.0
TPC 1. Full-Scale Current vs.
Reference Current
4.0
TA = T MIN TO TMAX
0
10
0.05
0.02
0.1
0.5
2.0
0.01
0.05
0.2
1.0
5.0
IFS, OUTPUT FULL SCALE CURRENT – mA
TPC 2. LSB Propagation Delay vs. IFS
2
0
10
5.0
TPC 3. Reference Input Frequency
Response
10.0
2.0
8.0
1.6
ALL BITS ON
NOTE: POSITIVE COMMON-MODE
RANGE IS ALWAYS (V+) –1.5V
2.8
2.4
V– = –15V
V– = –5V
2.0
V+ = +15V
IREF = 2mA
1.6
IREF = 1mA
1.2
6.0
4.0
2.0
0.8
1.2
0.8
0.4
IREF = 0.2mA
0.4
0
0
4.0 8.0 12.0 16.0
–12.0 –8.0 –4.0
LOGIC INPUT VOLTAGE – V
0.0
18
–2
2
6
10
14
–14 –10 –6
V15, REFERENCE COMMON-MODE VOLTAGE – V
TPC 4. Reference Amp CommonMode Range
TPC 5. Logic Input Current vs. Input
Voltage
0
28
1.8
24
1.6
3.2
20
2.4
V– = –15V
V– = –5V
IREF = 2mA
1.6
1.2
IREF = 1mA
0.0
–14 –10
12
8
IREF = 0.2mA
0
14
FOR OTHER V– OR IREF.
SEE OUTPUT CURRENT VS. OUTPUT
VOLTAGE CURVE.
18
1.4
1.2
–50
0
50
100
TEMPERATURE – ⴗC
150
B1
1.0
IREF = 2.0mA
0.8
0.6
B2
0.4
0.2
8
12
–6
–2
2
6
10
OUTPUT VOLTAGE – V
SHADED AREA INDICATES
PERMISSIBLE OUTPUT VOLTAGE
RANGE FOR V– = –15V. I REF 2.0mA.
4
4
0.8
0.4
16
OUTPUT CURRENT – mA
2.8
2.0
150
ALL BITS ON
OUTPUT VOLTAGE – V
TA = T MIN TO TMAX
0
50
100
TEMPERATURE – ⴗC
–50
TPC 6. VTH – VLC vs. Temperature
3.6
4.0
OUTPUT CURRENT – mA
VTH – VLC – V
3.2
LOGIC INPUT – ␮A
OUTPUT CURRENT – mA
3.6
V– = –5V
B4
B5
B3
V– = –15V
0
–12
–8
–4
0
4
8
12
16
LOGIC INPUT VOLTAGE – V
NOTE: B1 THROUGH B8 HAVE IDENTICAL
TRANSFER CHARACTERISTICS. BITS ARE FULLY
SWITCHED WITH LESS THAN 1/2 LSB ERROR, AT
LESS THAN 100mV FROM ACTUAL THRESHOLD.
THESE SWITCHING POINTS ARE GUARANTEED
TO LIE BETWEEN 0.8V AND 2.0V OVER THE
OPERATING TEMPERATURE RANGE (VLC = 0.0V).
TPC 7. Output Current vs. Output
Voltage (Output Voltage Compliance)
REV. B
TPC 8. Output Voltage Compliance
vs. Temperature
–7–
TPC 9. Bit Transfer Characteristics
DAC08
10
10
7
I–
6
5
4
3
I+
2
1
ALL BITS “HIGH” OR “LOW”
9
POWER SUPPLY CURRENT – mA
8
0
10
BITS MAY BE “HIGH” OR “LOW”
POWER SUPPLY CURRENT – mA
POWER SUPPLY CURRENT – mA
ALL BITS “HIGH” OR “LOW”
9
8
7
I– WITH IREF = 2mA
6
5
I– WITH IREF = 1mA
4
I– WITH IREF = 0.2mA
3
2
I+
1
0
2
4
6
8
8
7
V– = –15V
6
5
4
3
I+
V+ = +15V
2
0
–50
0
50
100
TEMPERATURE – ⴗC
V–, NEGATIVE POWER SUPPLY – V dc
TPC 10. Power Supply Current vs. V+
I–
IREF = 2.0mA
1
0
–0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20
10 12 14 16 18 20
V+, POSITIVE POWER SUPPLY – V dc
9
TPC 11. Power Supply Current vs. V–
150
TPC 12. Power Supply Current vs.
Temperature
BASIC CONNECTIONS
+VREF
RREF
IIN
IREF
VIN
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
14
IREF
RIN
+VREF
15
IREF
RREF
VREF (+)
RREF
(R14)
R15 VREF (–)
PEAK NEGATIVE SWING OF IIN
14 5 6 7 8 9 10 11 12
15
R15 +VREF
2
3
16
14
R15
(OPTIONAL)
VIN
255 0.1␮F
+V
IFR = REF ⴛ
RREF
256
HIGH INPUT
IMPEDANCE
+VREF MUST BE ABOVE PEAK POSITIVE SWING OF V IN
FOR FIXED REFERENCE,
TTL OPERATION,
TYPICAL VALUES ARE:
VREF = 10.000V
RREF = 5.000k⍀
R15 = RREF
CC = 0.01␮F
VLC = 0V (GROUND)
V+
Figure 7. Accommodating Bipolar References
LSB
MSB
B1 B2 B3 B4 B5 B6 B7 B8
IO
4
14
IO
5.000k⍀
2
V–
V+
VLC
Figure 8. Basic Positive Reference Operation
EO
5.000k⍀
0.1␮F
IO + IO = IFR FOR
ALL LOGIC STATES
IO
1
COMP
15
IREF = 2.000mA
13
V–
CC
RREF
IO
4
FULL RANGE
HALF-SCALE +LSB
HALF-SCALE
HALF-SCALE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
B1
1
1
1
0
0
0
B2
1
0
0
1
0
0
B3
1
0
0
1
0
0
B4
1
0
0
1
0
0
B5
1
0
0
1
0
0
B6
1
0
0
1
0
0
B7
1
0
0
1
0
0
B8
1
1
0
1
1
0
IOmA
1.992
1.008
1.000
0.992
0.008
0.000
IOmA
0.000
0.984
0.992
1.000
1.984
1.992
EO
–9.960
–5.040
–5.000
–4.960
–0.040
0.000
EO
–0.000
–4.920
–4.960
–5.000
–9.920
–9.860
EO
Figure 9. Basic Unipolar Negative Operation
–8–
REV. B
DAC08
10.000V
LSB
MSB
B1 B2 B3 B4 B5 B6 B7 B8 10.000k⍀
IO
IREF(+) = 2.000mA
EO
4
14
IO
EO
2
B1
1
1
1
1
0
0
0
POS. FULL RANGE
10.000k⍀ POS. FULL RANGE –LSB
ZERO-SCALE +LSB
ZERO-SCALE
ZERO-SCALE –LSB
NEG. FULL-SCALE +LSB
NEG. FULL-SCALE
B2
1
1
0
0
1
0
0
B3
1
1
0
0
1
0
0
B4
1
1
0
0
1
0
0
B5
1
1
0
0
1
0
0
B6
1
1
0
0
1
0
0
B7
1
1
0
0
1
0
0
B8 EO
1 –9.920
0 –9.840
1 –0.080
0 0.000
1 +0.080
1 +9.920
0 +10.000
EO
+10.000
+9.920
+0.160
+0.080
0.000
–9.840
–9.920
Figure 10. Basic Bipolar Output Operation
LOW T.C.
4.5k⍀
VREF
10V
RREF
14
1V
10k⍀
POT
R15
–VREF
15
APPROX
5k⍀
IFS
Figure 11. Recommended Full-Scale Adjustment Circuit
IO
4
14
IREF(+) 2mA
39k⍀
IO
2
15
NOTE
RREF SETS IFS; R15 IS FOR
BIAS CURRENT CANCELLATION.
–VREF
RREF
Figure 12. Basic Negative Reference Operation
10k⍀
5.0k⍀
15V
MSB
LSB
B1 B2 B3 B4 B5 B6 B7 B8
+15V
2
10V
6
5.000k⍀
IO
VO
REF01*
B1
POS. FULL RANGE
1
1
EO ZERO-SCALE
NEG. FULL-SCALE +1 LSB 0
NEG. FULL-SCALE
0
4
5
OP711
5.0k⍀
V+
V–
CC
VLC
IO 2
B2
1
0
0
0
B3
1
0
0
0
B4
1
0
0
0
B5
1
0
0
0
B6
1
0
0
0
B7
1
0
0
0
B8 EO
1 +4.960
0 0.000
1 –4.960
0 –5.000
4
*OR ADR01
+15V –15V
–15V
Figure 13. Offset Binary Operation
RL
IO
4
IO
2
0 TO +IFR ⴛ RL
OP711
IO
4
EO
OP711
IO
2
RL
0 TO –IFR ⴛ RL
IFR =
255
IFR =
I
256 REF
Figure 14. Positive Low Impedance Output Operation
Figure 15. Negative Low Impedance Output Operation
CMOS, HTL, NMOS
VTH = V LC 1.4V
15V CMOS
VTH = 7.6V
15V
ECL
VLC
VLC
1
6.2k⍀
V+
13k⍀
9.1k⍀
20k⍀
2N3904
2N3904
“A”
2N3904
0.1␮F
3k⍀
39k⍀
TO PIN 1
VLC
“A”
–5.2V
TO PIN 1
VLC
R3
400␮A
TEMPERATURE COMPENSATING V LC CIRCUITS
Figure 16. Interfacing with Various Logic Families
–9–
2N3904
3k⍀
20k⍀
6.2k⍀
REV. B
255
I
256 REF
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT NONINVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4)
TO GROUND.
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC),
CONNECT INVERTING INPUT OF OP AMP TO IO (PIN 2); CONNECT IO (PIN 4) TO
GROUND.
TTL, DTL
VTH = 1.4V
EO
DAC08
APPLICATION INFORMATION
REFERENCE AMPLIFIER SETUP
The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input reference current. The reference current may be fixed or may vary
from nearly zero to 4.0 mA. The full-scale output current is a
linear function of the reference current and is given by:
IFR =
LOGIC INPUTS
255
× IREF , where IREF = I14
256
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal
(Pin 14) of the reference amplifier. Alternatively, a negative
reference may be applied to VREF(–) at Pin 15; reference current
flows from ground through R14 into VREF(+) as in the positive
reference case. This negative reference connection has the advantage of a very high impedance presented at Pin 15. The voltage
at Pin 14 is equal to and tracks the voltage at Pin 15 due to the
high gain of the internal reference amplifier. R15 (nominally equal
to R14) is used to cancel bias current errors; R15 may be eliminated with only a minor increase in error.
Bipolar references may be accommodated by offsetting VREF or
Pin 15. The negative common-mode range of the reference
amplifier is given by: VCM– = V– plus (IREF × 1 kΩ) plus 2.5 V.
The positive common-mode range is V+ less 1.5 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction bypassed to
ground with a 0.1 µF capacitor.
For most applications the tight relationship between IREF and IFS
will eliminate the need for trimming IREF. If required, full-scale
trimming may be accomplished by adjusting the value of R14, or
by using a potentiometer for R14. An improved method of
full-scale trimming which eliminates potentiometer T.C. effects
is shown in the recommended full-scale adjustment circuit.
The DAC08 design incorporates a unique logic input circuit
that enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made possible by the large input swing capability, 2 µA logic input
current and completely adjustable logic threshold voltage.
For V– = –15 V, the logic inputs may swing between –10 V
and +18 V. This enables direct interface with 15 V CMOS
logic, even when the DAC08 is powered from a 5 V supply.
Minimum input logic swing and minimum logic threshold
voltage are given by: V– plus (IREF × 1 kΩ) plus 2.5 V. The
logic threshold may be adjusted over a wide range by placing
an appropriate voltage at the logic threshold control pin (Pin 1,
VLC). The appropriate graph shows the relationship between
VLC and VTH over the temperature range, with VTH nominally
1.4 above VLC. For TTL and DTL interface, simply ground pin
1. When interfacing ECL, an IREF = 1 mA is recommended. For
interfacing other logic families, see preceding page. For general
set-up of the logic control circuit, it should be noted that Pin 1
will source 100 µA typical; external circuitry should be designed
to accommodate this current.
Fastest settling times are obtained when Pin 1 sees a low impedance. If Pin 1 is connected to a 1 kΩ divider, for example, it
should be bypassed to ground by a 0.01 µF capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO + IO = IFS. Current appears at the “true” (IO) output
when a “1” (logic high) is applied to each logic input. As the
binary count increases, the sink current at pin 4 increases proportionally, in the fashion of a “positive logic” D/A converter.
When a “0” is applied to any input bit, that current is turned
off at Pin 4 and turned on at Pin 2. A decreasing logic count
increases IO as in a negative or inverted logic D/A converter.
Both outputs may be used simultaneously. If one of the outputs
is not required, it must be connected to ground or to a point
capable of sourcing IFS; do not leave an unused output pin open.
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative common-mode range. The recommended range for operation with
a dc reference current is 0.2 mA to 4.0 mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier to
be compensated using a capacitor from Pin 16 to V–. The value
of this capacitor depends on the impedance presented to Pin 14:
for R14 values of 1.0, 2.5 and 5.0 kΩ, minimum values of CC
are 15, 37 and 75 pF. Larger values of R14 require proportionately increased values of CC for proper phase margin, so the
ratio of CC (pF) to R14 (kΩ) = 15.
For fastest response to a pulse, low values of R14 enabling
small CC values should be used. If Pin 14 is driven by a high
impedance such as a transistor current source, none of the
above values will suffice and the amplifier must be heavily
compensated which will decrease overall bandwidth and slew
rate. For R14 = 1 kΩ and CC = 15 pF, the reference amplifier
slews at 4 mA/µs enabling a transition from IREF = 0 to IREF =
2 mA in 500 ns.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 14 is
200 Ω and CC = 0. This yields a reference slew rate of 16 mA/µs,
which is relatively independent of RIN and VIN values.
Both outputs have an extremely wide voltage compliance enabling
fast direct current-to-voltage conversion through a resistor tied
to ground or other voltage source. Positive compliance is 36 V
above V– and is independent of the positive supply. Negative
compliance is given by V– plus (IREF × 1 kΩ) plus 2.5 V.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This
feature is especially useful in cable driving, CRT deflection and
in other balanced applications such as driving center-tapped
coils and transformers.
POWER SUPPLIES
The DAC08 operates over a wide range of power supply voltages
from a total supply of 9 V to 36 V. When operating at supplies
of ± 5 V or less, IREF ≤ 1 mA is recommended. Low reference
current operation decreases power consumption and increases
negative compliance, reference amplifier negative common-mode
–10–
REV. B
DAC08
SETTLING TIME
range, negative logic input range and negative logic threshold
range; consult the various figures for guidance. For example,
operation at –4.5 V with IREF = 2 mA is not recommended
because negative output compliance would be reduced to near
zero. Operation from lower supplies is possible; however, at
least 8 V total must be applied to ensure turn-on of the internal
bias network.
The DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful
board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 35 ns for each of the 8 bits.
Settling time to within 1/2 LSB of the LSB is therefore 35 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 85 ns, thus determining the overall settling time
of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08 including the package is
approximately 15 pF, therefore the output RC time constant
dominates settling time if RL > 500 Ω.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required: however, an artificial
ground may be used to ensure logic swings, etc., remain
between acceptable limits.
Power consumption may be calculated as follows:
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
PD = (I+) (V+) + (I–) (V–)
A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states; this is useful in
cryptographic applications and further serves to reduce the size
of the power supply bypass capacitors.
Measurement of settling time requires the ability to accurately
resolve ± 4 µA, therefore a 1 kΩ load is needed to provide
adequate drive for most oscilloscopes. The settling time fixture shown in schematic labelled “Settling Time Measurement”
uses a cascade design to permit driving a 1 kΩ load with less
than 5 pF of parasitic capacitance at the measurement node. At
IREF values of less than 1.0 mA, excessive RC damping of the
output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code change
does not require the normal 6.2 time constants to settle to
within ± 0.2% of the final value, and thus settling times may be
observed at lower values of IREF.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is low, typically ±10 ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approximately 10% at –55°C; at +125°C an increase of about 15%
is typical.
The reference amplifier must be compensated by using a capacitor
from pin 16 to V–. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see “Reference Amplifier Compensation for Multiplying Applications” section.
DAC08 switching transients or “glitches” are very low and may
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time.
Fastest operation can be obtained by using short leads, minimizing
output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capacitors
at the supply pins provide full transient protection.
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range
of 4 µA to 4 mA. Monotonic operation is maintained over a
typical range of IREF from 100 µA to 4.0 mA.
+5V
VL
FOR TURN-ON, VL = 2.7V
FOR TURN-OFF, VL = 0.7V
1k⍀
1␮F
50␮F
MINIMUM
CAPACITANCE
Q2
1k⍀
VCL
0.7V
RREF
+VREF
VIN
1␮F
14 5 6 7 8 9 10 11 12
100k⍀
4
DAC08
R15
15
VOUT 1X
PROBE
Q1
0.1␮F
2k⍀
2
13
3
16
0.1␮F
–15V
0.1␮F
+15V
–15V
Figure 17. Settling Time Measurement
–11–
–0.4V
0.1␮F
IOUT
0.01␮F
REV. B
15k⍀
+0.4V
0V
0V
DAC08
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Cerdip (Q-16)
0.005 (0.13) MIN
0.840 (21.34)
0.745 (18.92)
0.080 (2.03) MAX
16
16
9
1
8
PIN 1
0.060 (1.52)
0.015 (0.38)
1
0.325 (8.25)
0.300 (7.62)
0.210 (5.33)
MAX
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
SEATING
0.022 (0.558) 0.100 0.070 (1.77) PLANE
(2.54)
0.045 (1.15)
0.014 (0.356)
BSC
0.840 (21.34) MAX
0.195 (4.95)
0.115 (2.93)
PIN 1
9
1
8
0.015 (0.381)
0.008 (0.204)
0.050 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.015 (0.38)
0.008 (0.20)
15°
0°
20-Terminal Leadless Chip Carrier (E-20)
0.358 (9.09)
0.342 (8.69)
SQ
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.310 (7.87)
0.220 (5.59)
0.150
(3.81)
0.200 (5.08)
MIN
0.125 (3.18)
SEATING
0.023 (0.58) 0.100 0.070 (1.78)
PLANE
0.014 (0.36) (2.54) 0.030 (0.76)
BSC
0.3937 (10.00)
0.3859 (9.80)
16
8
0.200 (5.08)
MAX
16-Lead SO (R-16A)
0.1574 (4.00)
0.1497 (3.80)
9
PIN 1
0.280 (7.11)
0.240 (6.10)
C00268–0–2/02(B)
16-Lead Plastic DIP (N-16)
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.095 (2.41)
0.075 (1.90)
TOP
VIEW
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
8ⴗ
0ⴗ 0.0500 (1.27)
0.0192 (0.49) SEATING
0.0099 (0.25)
PLANE
0.0138 (0.35)
0.0160 (0.41)
0.0075 (0.19)
0.358
(9.09)
MAX
SQ
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.088 (2.24)
0.054 (1.37)
0.200 (5.08)
BSC
0.100 (2.54) BSC
19
18
3
4
20
1
BOTTOM
VIEW
14
13
0.055 (1.40)
0.045 (1.14)
0.015 (0.38)
MIN
0.028 (0.71)
0.022 (0.56)
0.050 (1.27)
BSC
8
9
45° TYP
0.150 (3.81)
BSC
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to Figures 14 and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Replacement of SO-16 with R-16A Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. B
PRINTED IN U.S.A.
Edit to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8