Dual Port, Xpressview, 225 MHz HDMI Receiver ADV7612 Data Sheet FEATURES Dedicated, flexible audio output port Super audio CD (SACD) with DSD output interface HBR audio Dolby® TrueHD DTS-HD Master Audio™ General Interrupt controller with two interrupt outputs Standard Identification (STDI) circuit Highly flexible 36-bit pixel output interface Internal EDID RAM Any-to-any 3 × 3 color space conversion (CSC) matrix 2-layer PCB design supported 100-lead LQFP_EP, 14 mm × 14 mm package Qualified for Automotive Applications High-Definition Multimedia Interface (HDMI®) 1.4a features supported All mandatory and additional 3D video formats supported Extended colorimetry, including sYCC601, Adobe RGB, Adobe YCC 601, xvYCC extended gamut color CEC 1.4-compatible HDMI receiver 225 MHz maximum TMDS clock frequency Xpressview fast switching of HDMI ports 36-/30-bit Deep Color and 24-bit color support High-bandwidth Digital Content Protection (HDCP) 1.4 support with internal HDCP keys HDCP repeater support Up to 127 KSVs supported Integrated CEC controller Programmable HDMI equalizer 5 V detect and Hot Plug assert for each HDMI port Audio support Audio support including high bit rate (HBR) and direct stream digital (DSD) S/PDIF (IEC 60958-compatible) digital audio support Supports up to four I2S outputs Advanced audio mute feature APPLICATIONS Projectors Automotive Video conferencing HDTVs AVR, HTiB Soundbars Video switches HS/VS HDCP KEYS FIELD/DE 36 COMPONENT PROCESSOR LLC DATA HDMI1 TMDS DDC HDMI2 DEEP COLOR HDMI Rx 4 I2S S/PDIF DSD HBR MCLK SCLK LRCLK TMDS DDC OUTPUT MUX FAST SWITCH OUTPUT MUX FUNCTIONAL BLOCK DIAGRAM HS VS/FIELD DE LLC 36-BIT YCbCr/RGB AUDIO OUTPUT 5 MCLK SCLK NOTES 1. LRCLK IS ACCESSIBLE THROUGH THE AP5 PIN. 09308-001 ADV7612 Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved. ADV7612 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up Sequence ................................................................... 11 Applications ....................................................................................... 1 Power-Down Sequence .............................................................. 11 Functional Block Diagram .............................................................. 1 Functional Overview...................................................................... 12 Revision History ............................................................................... 2 HDMI Receiver........................................................................... 12 General Description ......................................................................... 3 Component Processor ............................................................... 12 Detailed Functional Block Diagram .......................................... 3 Other Features ............................................................................ 12 Specifications..................................................................................... 4 Pixel Input/Output Formatting .................................................... 13 Electrical Characteristics ............................................................. 4 Pixel Data Output Modes Features .......................................... 13 Data and I C Timing Characteristics ......................................... 5 Outline Dimensions ....................................................................... 17 Absolute Maximum Ratings ............................................................ 7 Ordering Guide .......................................................................... 17 Package Thermal Performance ................................................... 7 Automotive Products ................................................................. 17 2 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Power Supply Sequencing .............................................................. 11 REVISION HISTORY 5/12—Rev. C to Rev. D Changes to Features Section............................................................ 1 Changes to General Description Section and Figure 2 ............... 3 Added Endnote 3 (Table 1) ............................................................. 4 Deleted TDM Serial Timing Parameter (Table 2) ........................ 5 Changes to Figure 5 .......................................................................... 6 Deleted Figure 6 ................................................................................ 7 Changed Pin 75 to AP1 in Figure 7 and Table 4........................... 9 Changed Pin 89 and Pin 90 Descriptions (Table 4) ................... 10 Changes to HDMI Receiver and Other Features Sections ........ 12 Deleted Time-Division Multiplexed (TDM) Mode Section and Figure 9 ..................................................................................... 13 Added Endnote 1 in Pixel Input/Output Formatting Section and Endnote 1 to Table 5 ....................................................................... 15 Changes to Ordering Guide .......................................................... 18 6/11—Rev. B to Rev. C Changes to Figure 7 .......................................................................... 9 Updated Outline Dimensions ....................................................... 19 6/11—Rev. A to Rev. B Changes to Data Output Transition Time (t11), Table 2 .............. 5 Changes to Pin 17 and Pin 18 Description, Table 4 ................... 10 Changes to Pin 87 and Pin 89 Description, Table 4 ................... 11 4/11—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Ordering Guide .......................................................... 19 Added Automotive Products Section........................................... 19 11/10—Revision 0: Initial Version Rev. D | Page 2 of 20 Data Sheet ADV7612 GENERAL DESCRIPTION The ADV7612 is offered in automotive, professional (no HDCP), and industrial versions. The operating temperature range is −40°C to +85°C. The UG-216 contains critical information that must be used in conjunction with the ADV7612. The ADV7612 is a high quality Xpressview™ fast switching HDMI®-capable receiver. It incorporates a dual input HDMIcapable receiver that supports all mandatory 3D TV formats defined in HDMI 1.4a specification, HDTV formats up to 1080p 36-bit Deep Color, and display resolutions up to UXGA (1600 × 1200 at 60 Hz). It integrates a CEC controller that supports the capability discovery and control (CDC) feature. The ADV7612 incorporates Xpressview fast switching on both input HDMI ports. Using Analog Devices, Inc., hardware-based HDCP engine that minimizes software overhead, Xpressview technology allows fast switching between both HDMI input ports in less than 1 second. Each HDMI port has dedicated 5 V detect and Hot Plug™ assert pins. The HDMI receiver also includes an integrated programmable equalizer that ensures robust operation of the interface with long cables. The ADV7612 offers a flexible audio output port for audio data extraction from the HDMI stream. HDMI audio formats, including SACD via DSD and HBR, are supported by ADV7612. The HDMI receiver has advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output. The ADV7612 contains one main component processor (CP) that processes the video signals from the HDMI receiver. It provides features such as contrast, brightness and saturation adjustments, STDI detection block, free run, and synchronization alignment controls. Fabricated in an advanced CMOS process, the ADV7612 is provided in a 14 mm × 14 mm, 100-lead surface-mount LQFP_EP, RoHS-compliant package, and is specified over the −40°C to +85°C temperature range. DETAILED FUNCTIONAL BLOCK DIAGRAM CS CEC RXA_5V RXB_5V HPA_A/INT2* HPA_B DDCA_SDA DDCA_SCL DDCB_SDA DDCB_SCL RXA_C± RXB_C± RXA_0± RXA_1± RXA_2± RXB_0± RXB_1± RXB_2± CEC CONTROLLER CONTROL INTERFACE I2C CONTROL AND DATA 5V DETECT AND HPD CONTROLLER EDID REPEATER CONTROLLER PLL EQUALIZER BACKEND COLOR SPACE CONVERSION INTERRUPT CONTROLLER (INT1, INT2) HDMI PROCESSOR HDCP EEPROM HDCP ENGINE SAMPLER COMPONENT PROCESSOR A B C DATA PREPROCESOR AND COLOR SPACE CONVERSION PACKET/ INFOFRAME MEMORY PACKET PROCESSOR EQUALIZER 12 12 12 SAMPLER MUTE AUDIO PROCESSOR AUDIO OUTPUT FORMATTER SCL SDA OUTPUT FORMATTER DPLL XPressView ™ FAST SWITCHING XTALP XTALN P0 TO P11 P12 TO P23 P24 TO P25 LLC HS VS/FIELD/ALSB DE INT1 INT2* AP1 AP2 AP3 AP4 AP5 SCLK/INT2* MCLK/INT2* AP0 *INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2. Figure 2. Detailed Functional Block Diagram Rev. D | Page 3 of 20 09308-002 ADV7612 ADV7612 Data Sheet SPECIFICATIONS At DVDD = 1.71 V to 1.89 V, DVDDIO = 3.14 V to 3.46 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.14 V to 3.46 V, CVDD = 1.71 V to 1.89 V, Operating temperature range, unless otherwise noted. ELECTRICAL CHARACTERISTICS Table 1. Parameter DIGITAL INPUTS 1 Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL INPUTS (5 V TOLERANT)1, 2 Input High Voltage Input Low Voltage Input Current DIGITAL OUTPUTS1 Output High Voltage Output Low Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 3,4 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Terminator Power Supply Comparator Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Terminator Supply Current Comparator Supply Current POWER-DOWN CURRENTS3,6 Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Terminator Supply Current Comparator Supply Current Power-Up Time Symbol Test Conditions/Comments Min VIH VIH VIL VIL IIN XTALN and XTALP Other digital inputs XTALN and XTALP Other digital inputs RESET pin CS pin Other digital inputs 1.2 2 Typ ±45 ±45 ±10 CIN VIH VIL IIN 2.6 VOH VOL ILEAK 2.4 −82 VS/FIELD/ALSB pin ±35 HPA_A/INT2, HPA_B pin Digital inputs other than XTALN and XTALP ±10 1.71 3.14 1.71 3.14 1.71 Dual 1080p60 12 bit with BG 5port Dual 1080p60 12 bit with BG5 port Dual 1080p60 12 bit with BG5 port Dual 1080p60 12 bit with BG5 port Dual 1080p60 12 bit with BG5 port IDVDD_PD IDVDDIO_PD IPVDD_PD ITVDD_PD ICVDD_PD tPWRUP Unit 0.4 0.8 ±60 ±60 10 V V V V µA µA µA pF 0.8 +82 V V µA 0.4 ±60 V V µA ±82 µA µA 20 pF 1.8 3.3 1.8 3.3 1.8 149.5 9.9 39.2 121.4 187.0 1.89 3.46 1.89 3.46 1.89 201.9 178.5 36.9 134.5 210.9 V V V V V mA mA mA mA mA 0.3 1.3 1.5 0.1 1.3 25 0.4 1.7 1.8 0.3 1.7 mA mA mA mA mA ms COUT DVDD DVDDIO PVDD TVDD CVDD IDVDD IDVDDIO IPVDD ITVDD ICVDD Max Data guaranteed by characterization. The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, RXA_5V, and RXB_5V. Data recorded during lab characterization 4 Maximum current consumption values are recorded with maximum rated voltage supply levels, MoireX video pattern, and at maximum rated temperature. 5 BG = background. 6 Power-Down Mode 0 (IO map, Register 0x0C = 0x62), ring oscillator powered down (HDMI map, Register 0x48 = 0x01), and DDC pads off (HDMI map, Register 0x73 = 0x03). 1 2 3 Rev. D | Page 4 of 20 Data Sheet ADV7612 DATA AND I2C TIMING CHARACTERISTICS Table 2. Parameter CLOCK AND CRYSTAL Crystal Frequency, XTALP Crystal Frequency Stability LLC Frequency Range I2C PORTS SCL Frequency SCL Minimum Pulse Width High 1 SCL Minimum Pulse Width Low1 Start Condition Hold Time1 Start Condition Setup Time1 SDA Setup Time1 SCL and SDA Rise Time1 SCL and SDA Fall Time1 Stop Condition Setup Time1 RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark-Space Ratio1 DATA AND CONTROL OUTPUTS 2 Data Output Transition Time1 I2S PORT, MASTER MODE SCLK Mark-Space Ratio1 LRCLK Data Transition Time1 I2S Data Transition Time1 1 2 Symbol Test Conditions/Comments Min Typ Max Unit ±50 170 MHz ppm MHz 28.63636 13.5 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 kHz ns µs ns ns ns ns ns µs 5 ms 600 1.3 600 600 100 300 300 t9:t10 45:55 t11 t12 End of valid data to negative clock edge Negative clock edge to start of valid data t15:t16 t17 t18 t19 t20 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 1.0 0.0 45:55 Data guaranteed by characterization. With the DLL block on output clock bypassed. Rev. D | Page 5 of 20 55:45 % duty cycle 2.2 0.3 ns ns 55:45 10 10 5 5 % duty cycle ns ns ns ns ADV7612 Data Sheet Timing Diagrams t3 t5 t3 SDA t6 t1 t2 t7 t4 9308-003 SCL t8 2 Figure 3. I C Timing t9 t10 LLC t11 9308-004 t12 P0 TO P23, HS, VS/FIELD/ALSB, DE Figure 4. Pixel Port and Control SDR Output Timing t15 SCLK t16 t17 LRCLK t18 t19 LEFT-JUSTIFIED MODE MSB MSB – 1 t20 I2S I2S MODE t19 MSB I2S RIGHT-JUSTIFIED MODE MSB – 1 t20 t19 MSB LSB t20 NOTES 1. LRCLK IS A SIGNAL ACCESSIBLE VIA AP5 PIN. 2. I2S SIGNALS ARE ACCESSIBLE VIA THE AP1 TO AP4 PINS. Figure 5. I2S Timing Rev. D | Page 6 of 20 09308-005 I2S Data Sheet ADV7612 ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE Table 3. Parameter DVDD to GND PVDD to GND DVDDIO to GND CVDD to GND TVDD to GND Digital Inputs Voltage to GND 5 V Tolerant Digital Inputs to GND1 Digital Outputs Voltage to GND XTALP, XTALN SCL/SDA Data Pins to DVDDIO Maximum Junction Temperature (TJ MAX) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 Rating 2.2 V 2.2 V 4.0 V 2.2 V 4.0 V GND − 0.3 V to DVDDIO + 0.3 V 5.3 V To reduce power consumption when using the ADV7612, the user is advised to turn off the unused sections of the part. Due to the printed circuit board (PCB) metal variation and, therefore, variation in PCB heat conductivity, the value of θJA may differ for various PCBs. The most efficient measurement solution is obtained using the package surface temperature to estimate the die temperature because this eliminates the variance associated with the θJA value. GND − 0.3 V to DVDDIO + 0.3 V −0.3 V to PVDD + 0.3 V DVDDIO − 0.3 V to DVDDIO + 3.6 V 125°C The maximum junction temperature (TJ MAX) of 125°C must not be exceeded. The following equation calculates the junction temperature using the measured package surface temperature and applies only when no heat sink is used on the device under test (DUT): −60°C to +150°C 260°C where: TS is the package surface temperature (°C). ΨJT = 0.3°C/W for the 100-lead LQFP_EP. The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, and DDCB_SDA. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( TJ = TS + Ψ JT × WTOTAL ) WTOTAL = ((PVDD × IPVDD) + (0.05 × TVDD × ITVDD) + (CVDD × ICVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO)) where 0.05 is 5% of the TVDD power that is dissipated on the part itself. ESD CAUTION Rev. D | Page 7 of 20 ADV7612 Data Sheet RXA_5V DDCA_SDA DDCA_SCL HPA_B RXB_5V DDCB_SDA DDCB_SCL CEC DVDD XTALN XTALP PVDD CS RESET INT1 SDA SCL DVDD MCLK/INT2 AP5 SCLK/INT2 AP4 AP3 AP2 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PIN 1 INDICATOR 18 58 P10 TVDD 19 57 P11 RXB_1– 20 56 P12 RXB_1+ 21 55 P13 TVDD 22 54 DVDDIO RXB_2– 23 53 P14 RXB_2+ 24 52 P15 CVDD 25 51 P16 50 P9 RXB_0+ NC 59 49 17 P17 P8 RXB_0– 48 60 P18 16 47 P7 TVDD P19 61 46 15 P20 DVDD RXB_C+ 45 62 P21 14 44 P6 RXB_C– P22 63 43 P5 13 P23 64 CVDD TOP VIEW (Not to Scale) 42 12 LLC P4 RXA_2+ 41 65 DVDD ADV7612 40 11 P24 P3 RXA_2– 39 66 P25 10 38 P2 TVDD P26 67 37 9 DVDDIO P1 RXA_1+ 36 68 P27 8 35 P0 RXA_1– P28 69 34 7 P29 DVDDIO TVDD 33 70 P30 6 32 DE RXA_0+ P31 71 31 5 P32 HS RXA_0– 30 72 P33 4 29 VS/FIELD/ALSB TVDD DVDDIO 73 28 3 P34 AP0 RXA_C+ 27 AP1 74 26 75 2 NC 1 P35 CVDD RXA_C– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT EXPOSED PAD (PIN0) TO GROUND (BOTTOM). Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic GND CVDD RXA_C− RXA_C+ TVDD RXA_0− RXA_0+ TVDD RXA_1− RXA_1+ TVDD RXA_2− RXA_2+ CVDD RXB_C− Type Ground Power HDMI input HDMI input Power HDMI input HDMI input Power HDMI input HDMI input Power HDMI input HDMI input Power HDMI input Description Ground. HDMI Analog Block Supply Voltage (1.8 V). Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. HDMI Analog Block Supply Voltage (1.8 V). Digital Input Clock Complement of Port B in the HDMI Interface. Rev. D | Page 8 of 20 09308-008 HPA_A/INT2 100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Data Sheet Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Mnemonic RXB_C+ TVDD RXB_0− RXB_0+ TVDD RXB_1− RXB_1+ TVDD RXB_2− RXB_2+ CVDD NC P35 P34 DVDDIO P33 P32 P31 P30 P29 P28 P27 DVDDIO P26 P25 P24 DVDD LLC P23 P22 P21 P20 P19 P18 P17 NC P16 P15 P14 DVDDIO P13 P12 P11 P10 P9 P8 P7 DVDD P6 P5 P4 ADV7612 Type HDMI input Power HDMI input HDMI input Power HDMI input HDMI input Power HDMI input HDMI input Power No connect Digital video output Digital video output Power Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Power Digital video output Digital video output Digital video output Power Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output No connect Digital video output Digital video output Digital video output Power Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Digital video output Power Digital video output Digital video output Digital video output Description Digital Input Clock True of Port B in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Terminator Supply Voltage (3.3 V). Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 2 True of Port B in the HDMI Interface. HDMI Analog Block Supply Voltage (1.8 V). No connect. Video Pixel Output Port. Video Pixel Output Port. Digital I/O Supply Voltage (3.3 V). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital I/O Supply Voltage (3.3 V). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital Core Supply Voltage (1.8 V). Line-Locked Output Clock for the Pixel Data (Range is 13.5 MHz to 170 MHz). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. No connect. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital I/O Supply Voltage (3.3 V). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital Core Supply Voltage (1.8 V). Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Rev. D | Page 9 of 20 ADV7612 Data Sheet Pin No. 66 67 68 69 70 71 72 73 Mnemonic P3 P2 P1 P0 DVDDIO DE HS VS/FIELD/ALSB Type Digital video output Digital video output Digital video output Digital video output Power Miscellaneous digital Digital video output Digital video output 74 AP0 Miscellaneous digital 75 AP1 Miscellaneous digital 76 AP2 Miscellaneous digital 77 AP3 Miscellaneous ditial 78 AP4 Miscellaneous ditial 79 SCLK/INT2 Miscellaneous digital 80 AP5 Miscellaneous 81 MCLK/INT2 Miscellaneous 82 83 84 85 DVDD SCL SDA INT1 Power Miscellaneous digital Miscellaneous digital Miscellaneous digital 86 RESET Miscellaneous digital 87 CS Miscellaneous digital 88 89 PVDD XTALP Power Miscellaneous analog 90 XTALN Miscellaneous analog 91 92 93 94 95 96 97 98 99 100 DVDD CEC DDCB_SCL DDCB_SDA RXB_5V HPA_B DDCA_SCL DDCA_SDA RXA_5V HPA_A/INT2 Power Digital input/output HDMI input HDMI input HDMI input Miscellaneous digital HDMI input HDMI input HDMI input Miscellaneous digital Description Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Video Pixel Output Port. Digital I/O Supply Voltage (3.3 V). DE (data enable) is a signal that indicates active pixel data. HS is a horizontal synchronization output signal. VS is a vertical synchronization output signal. FIELD is a field synchronization output signal in all interlaced video modes. VS or FIELD can be configured for this pin. ALSB allows selection of the I2C address. Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio output, HBR, DSD, DST, or I2S. Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio output, HBR, DSD, DST, or I2S. Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio output, HBR, DSD, DST, or I2S. Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio output, HBR, DSD, DST, or I2S. Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio output, HBR, DSD, DST, or I2S. A dual function pin that can be configured to output an audio serial clock or an Interrupt 2 signal. Audio Output Pin. Pin AP0 to Pin AP5 can be configured to output S/PDIF digital audio output, HBR, DSD, DST, or I2S. Additionally, Pin AP5 can be configured to provide LRCLK. A dual function pin that can be configured to output an audio master clock or an Interrupt 2 signal. Digital Core Supply Voltage (1.8 V). I2C Port Serial Clock Input. SCL is the clock line for the control port. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. Interrupt. This pin can be active low or active high. When status bits change, this pin is triggered. The events that trigger an interrupt are under user configuration. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7612 circuitry. Chip Select. This pin has an internal pull-down. Pulling this line up causes I2C state machine to ignore I2C transmission. PLL Supply Voltage (1.8 V). Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator Source to Clock the ADV7612. Crystal Input. Input pin for 28.63636 MHz crystal. This pin should be left unconnected if XTALP is driven with 1.8 V clock signal. Digital Core Supply Voltage (1.8 V). Consumer Electronic Control Channel. HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant. 5 V Detect Pin for Port B in the HDMI Interface. Hot Plug assert signal output for HDMI Port B. HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant. HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant. 5 V Detect Pin for Port A in the HDMI Interface. A dual function pin that can be configured to output Hot Plug assert signal (for HDMI Port A) or an Interrupt 2 signal. Rev. D | Page 10 of 20 Data Sheet ADV7612 POWER SUPPLY SEQUENCING The recommended power-up sequence of the ADV7612 is to power up the 3.3 V supplies first, followed by the 1.8 V supplies. Reset should be held low while the supplies are powered up. The ADV7612 supplies may be de-asserted simultaneously as long as a higher rated supply does not go below a lower rated supply. Alternatively, the ADV7612 may be powered up by asserting all supplies simultaneously. In this case, care must be taken while the supplies are being established to ensure that a lower rated supply does not go above a higher rated supply level. 3.3V 3.3V SUPPLIES 1.8V 1.8V SUPPLIES 3.3V SUPPLIES POWER-UP 1.8V SUPPLIES POWER-UP Figure 7. Recommended Power-Up Sequence Rev. D | Page 11 of 20 9308-007 POWER-DOWN SEQUENCE POWER SUPPLY (V) POWER-UP SEQUENCE ADV7612 Data Sheet FUNCTIONAL OVERVIEW HDMI RECEIVER The HDMI receiver supports all mandatory and many optional 3D formats, HDTV formats up to 1080p, and all display resolutions up to UXGA (1600 × 1200 at 60 Hz). With the inclusion of HDCP, displays can now receive encrypted video content. The HDMI interface of the ADV7612 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the HDCP 1.4 protocol. The HDMI-compatible receiver on the ADV7612 allows programmable equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance. The ADV7612 has a synchronization regeneration block used to regenerate the DE based on the measurement of the video format being displayed, and to filter the horizontal and vertical synchronization signals to prevent glitches. The HDMI receiver also supports TERC4 error detection, used for detection of corrupted HDMI packets following a cable disconnect. The HDMI receiver offers advanced audio functionality. The receiver contains an audio mute controller that can detect a variety of conditions, which may result in audible extraneous noise in the audio output. On detection of these conditions, the audio signal can be ramped to prevent audio clicks or pops. Audio output can be formatted to one of the following modes: • • • • LPCM and IEC 61937 S/PDIF DSD audio DST audio HBR audio Xpressview fast switching can be implemented with full HDCP authentication available on the background port. Synchronization measurement and status information are available for the background port. HDMI receiver features include: • • • • • • • • • • 2:1 multiplexed HDMI receiver 3D format support 225 MHz HDMI receiver Integrated equalizer for cable lengths up to 30 meters HDCP 1.4 also on background ports Internal HDCP keys 36-/30-bit Deep Color support PCM, HBR, DST, and DSD audio packet support Repeater support Internal EDID RAM • • Hot Plug assert output pin for each HDMI port CEC controller COMPONENT PROCESSOR The ADV7612 has an any-to-any 3 × 3 CSC matrix. The CSC block is placed at the back of the CP section. CSC enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color space converter. CP features include: • • • • • • • • 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats are supported Manual adjustments including gain (contrast) and offset (brightness), hue, and saturation Free run output mode that provides stable timing when no video input is present 170 MHz conversion rate, which supports RGB input resolutions up to 1600 × 1200 at 60 Hz Contrast, brightness, hue, and saturation controls Standard identification enabled by STDI block RGB that can be color space converted to YCrCb and decimated to a 4:2:2 format for video-centric back end IC interfacing DE output signal supplied for direct connection to HDMI/DVI transmitter OTHER FEATURES The ADV7612 has HS, VS, FIELD, and DE output signals with programmable position, polarity, and width. The ADV7612 has two programmable interrupt request output pins, including INT1 and INT2 (INT2 is accessible only via one of following pins: MCLK/INT2, SCLK/INT2, or HPA_A/INT2). It also features a low power-down mode. The I2C address of the main map is 0x98 after reset. This can be changed after reset to 0x9A if pullup is attached to VS/FIELD/ALSB pin and I2C command SAMPLE_ALSB is issued. Refer to the Register Access and Serial Ports Description section in the UG-216. The ADV7612 is provided in a 14 mm × 14 mm, RoHS-compliant LQFP_EP package, and is specified over the −40°C to +85°C temperature range. Rev. D | Page 12 of 20 Data Sheet ADV7612 PIXEL INPUT/OUTPUT FORMATTING The output section of the ADV7612 is highly flexible. The pixel output bus can support up to 36-bit 4:4:4 YCrCb or 36-bit 4:4:4 RGB. The pixel data supports both single and double data rates modes 1. In SDR mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit 4:4:4 output is possible. In DDR mode, the pixel output port can be configured in an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB. Bus rotation is supported. Table 5 to Table 8 outline the different output formats that are supported. All output modes are controlled via I2C. 1 DDR mode is only supported only up to 50 MHz (an equivalent to data rate clocked 100 MHz clock in SDR mode). PIXEL DATA OUTPUT MODES FEATURES The output pixel port features include the following: • 8-/10-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS, and FIELD output signals 16-/20-/24-bit YCrCb with embedded time codes and/or HS and VS/FIELD pin timing 24-/30-/36-bit YCrCb/RGB with embedded time codes and/or HS and VS/FIELD pin timing DDR 8-/10-/12-bit 4:2:2 YCrCb DDR 12-/24-/30-/36 bit 4:4:4 RGB • • • • Table 5. SDR 4:2:2 Output Modes OP_FORMAT_SEL[7:0] Pixel Output P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 0x0 1 8-Bit SDR ITU-R BT.656 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z 0x1 10-Bit SDR ITU-R BT.656 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z SDR 4:2:2 0x2 12-Bit SDR ITU-R BT.656 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y11, Cb11, Cr11 Y10, Cb10, Cr10 Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z 0x6 12-Bit SDR ITU-R BT.656 Mode 1 High-Z High-Z High-Z High-Z High-Z High-Z Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z Y11, Cb11, Cr11 Y10, Cb10, Cr10 Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 Y3, Cb3, Cr3 Y2, Cb2, Cr2 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Modes 0x00, 0x01, 0x02, 0x06 and 0x0A require additional writes to IO Map reg. 0x19[7:6]=2’b11 and IO Map reg.0x33[6]=1 Rev. D | Page 13 of 20 0x0A 12-Bit SDR ITU-R BT.656 Mode 2 Y3, Cb3, Cr3 Y2, Cb2, Cr2 Y1, Cb1, Cr1 Y0, Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y11, Cb11, Cr11 Y10, Cb10, Cr10 Y9, Cb9, Cr9 Y8, Cb8, Cr8 Y7, Cb7, Cr7 Y6, Cb6, Cr6 Y5, Cb5, Cr5 Y4, Cb4, Cr4 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z ADV7612 Data Sheet Table 6. SDR 4:2:2 and 4:4:4 Output Modes OP_FORMAT_SEL[7:0] 0x80 0x81 Pixel Output P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 16-Bit SDR ITU-R BT.656 4:2:2 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 High-Z High-Z High-Z High-Z Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 High-Z High-Z High-Z High-Z 20-Bit SDR ITU-R BT.656 4:2:2 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 High-Z High-Z Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 High-Z High-Z SDR 4:2:2 0x82 24-Bit SDR ITU-R BT.656 4:2:2 Mode 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb11, Cr11 Cb10, Cr10 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 0x86 24-Bit SDR ITU-R BT.656 4:2:2 Mode 1 High-Z High-Z Cb1, Cr1 Cb0, Cr0 High-Z High-Z Y1 Y0 High-Z High-Z High-Z High-Z Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 High-Z High-Z Cb11, Cr11 Cb10, Cr10 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 Cb3, Cr3 Cb2, Cr2 High-Z High-Z Rev. D | Page 14 of 20 0x8A 24-Bit SDR ITU-R BT.656 4:2:2 Mode 2 Y3 Y2 Y1 Y0 Cb3, Cr3 Cb2, Cr2 Cb1, Cr1 Cb0, Cr0 High-Z High-Z High-Z High-Z Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 High-Z High-Z High-Z High-Z Cb11, Cr11 Cb10, Cr10 Cb9, Cr9 Cb8, Cr8 Cb7, Cr7 Cb6, Cr6 Cb5, Cr5 Cb4, Cr4 High-Z High-Z High-Z High-Z 0x40 SDR 4:4:4 0x41 0x42 24-Bit SDR 4:4:4 Mode 0 R7 R6 R5 R4 R3 R2 R1 R0 High-Z High-Z High-Z High-Z G7 G6 G5 G4 G3 G2 G1 G0 High-Z High-Z High-Z High-Z B7 B6 B5 B4 B3 B2 B1 B0 High-Z High-Z High-Z High-Z 30-Bit SDR 4:4:4 Mode 0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 High-Z High-Z G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 High-Z High-Z B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 High-Z High-Z 36-Bit SDR 4:4:4 Mode 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0x46 36-Bit SDR 4:4:4 Mode 1 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B11 B10 B9 B8 G11 G10 B7 B6 B5 B4 B3 B2 B1 B0 R11 R10 G9 G8 Data Sheet ADV7612 Table 7. DDR 4:2:2 Output Modes OP_FORMAT_SEL[7:0] Pixel Output P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 0x20 8-Bit DDR ITU-656 (Clock/2 Output) 4:2:2 Mode 0 Clock Rise Clock Fall High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y7 Cb7, Cr7 Y6 Cb6, Cr6 Y5 Cb5, Cr5 Y4 Cb4, Cr4 Y3 Cb3, Cr3 Y2 Cb2, Cr2 Y1 Cb1, Cr1 Y0 Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DDR 4:2:2 Mode (Clock/2) 0x21 10-Bit DDR ITU-656 (Clock/2 Output) 4:2:2 Mode 0 Clock Rise Clock Fall High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y9 Cb9, Cr9 Y8 Cb8, Cr8 Y7 Cb7, Cr7 Y6 Cb6, Cr6 Y5 Cb5, Cr5 Y4 Cb4, Cr4 Y3 Cb3, Cr3 Y2 Cb2, Cr2 Y1 Cb1, Cr1 Y0 Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Rev. D | Page 15 of 20 0x22 12-Bit DDR ITU-656 (Clock/2 Output) 4:2:2 Mode 0 Clock Rise Clock Fall High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Y11 Cb11, Cr11 Y10 Cb10, Cr10 Y9 Cb9, Cr9 Y8 Cb8, Cr8 Y7 Cb7, Cr7 Y6 Cb6, Cr6 Y5 Cb5, Cr5 Y4 Cb4, Cr4 Y3 Cb3, Cr3 Y2 Cb2, Cr2 Y1 Cb1, Cr1 Y0 Cb0, Cr0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z ADV7612 Data Sheet Table 8. DDR 4:4:4 Output Modes OP_FORMAT_SEL[7:0] Pixel Output P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 1 2 0x60 24-Bit DDR RGB (Clock/2 Output) Clock Rise Clock Fall R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R0-0 R0-1 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DDR 4:4:4 Mode (Clock/2) 1, 2 0x61 30-Bit DDR RGB (Clock/2 Output) Clock Rise Clock Fall R9-0 R9-1 R8-0 R8-1 R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R0-0 R0-1 High-Z High-Z High-Z High-Z G9-0 G9-1 G8-0 G8-1 G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 High-Z High-Z High-Z High-Z B9-0 B9-1 B8-0 B8-1 B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 High-Z High-Z High-Z High-Z -0 = even samples. -1 = odd samples. Rev. D | Page 16 of 20 0x62 36-Bit DDR RGB (Clock/2 Output) Clock Rise Clock Fall R11-0 R11-1 R10-0 R10-1 R9-0 R9-1 R8-0 R8-1 R7-0 R7-1 R6-0 R6-1 R5-0 R5-1 R4-0 R4-1 R3-0 R3-1 R2-0 R2-1 R1-0 R1-1 R0-0 R0-1 G11-0 G11-1 G10-0 G10-1 G9-0 G9-1 G8-0 G8-1 G7-0 G7-1 G6-0 G6-1 G5-0 G5-1 G4-0 G4-1 G3-0 G3-1 G2-0 G2-1 G1-0 G1-1 G0-0 G0-1 B11-0 B11-1 B10-0 B10-1 B9-0 B9-1 B8-0 B8-1 B7-0 B7-1 B6-0 B6-1 B5-0 B5-1 B4-0 B4-1 B3-0 B3-1 B2-0 B2-1 B1-0 B1-1 B0-0 B0-1 Data Sheet ADV7612 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.00 REF 16.20 16.00 SQ 15.80 1.60 MAX 14.20 14.00 SQ 13.80 100 1 12.00 BSC 76 75 76 100 1 75 PIN 1 SEATING PLANE EXPOSED PAD TOP VIEW 0.20 0.09 (PINS DOWN) 25 26 VIEW A 0.15 0.05 0.50 BSC LEAD PITCH 7° 0° 0.08 COPLANARITY BOTTOM VIEW 51 50 (PINS UP) 51 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-BED-HD ROTATED 90° CCW 25 26 50 06-22-2011-A 1.45 1.40 1.35 6.00 REF SQ Figure 8. 100-Lead Low Profile Quad Flat Package [LQFP_EP] SW-100-2 Dimensions shown in millimeters ORDERING GUIDE Model1, 2, 3 ADV7612BSWZ ADV7612BSWZ-P ADV7612WBSWZ EVAL-ADV7612EB1Z Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C EVAL-ADV7612EB2Z EVAL-ADV7612-7511 EVAL-ADV7612-7511P 1 2 3 Package Description 100-Lead LQFP_EP 100-Lead LQFP_EP 100-Lead LQFP_EP Evaluation board with HDCP keys Package Option SW-100-2 SW-100-2 SW-100-2 Evaluation board without HDCP keys Low cost evaluation board with HDCP Low cost evaluation board without HDCP Z = RoHS Compliant Part. The ADV7612BSWZ-P is a non-HDCP version. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADV7612WBSWZ model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. Rev. D | Page 17 of 20 ADV7612 Data Sheet NOTES Rev. D | Page 18 of 20 Data Sheet ADV7612 NOTES Rev. D | Page 19 of 20 ADV7612 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09308-0-5/12(D) Rev. D | Page 20 of 20