LTC1414 14-Bit, 2.2Msps, Sampling A/D Converter U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 2.2Msps Outstanding Spectral Purity: 80dB S/(N + D) and 95dB SFDR at 100kHz 78dB S/(N + D) and 84dB SFDR at Nyquist Ultralow Distortion with Single-Ended or Differential Inputs ±2.5V Bipolar Input Range Eliminates Level Shifting and Rail-to-Rail Op Amp Requirements Easy Hookup for External or Internal Reference No Pipeline Delay Power Dissipation: 175mW on ±5V Supplies 28-Pin Narrow SSOP Package ■ ■ ■ ■ ■ The LTC1414’s high performance sample-and-hold has a full-scale input range of ±2.5V. Outstanding AC performance includes 80dB S/(N + D) and 95dB SFDR with a 100kHz input. The performance remains high at the Nyquist input frequency of 1.1MHz with 78dB S/(N + D) and 84dB SFDR. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 40MHz bandwidth. The 70dB common mode rejection can eliminate ground loops and common mode noise by measuring signal differentially from the source U APPLICATIO S ■ The LTC ®1414 is a 14-bit, 2.2Msps, sampling A/D converter which draws only 175mW from ±5V supplies. This high performance ADC includes a high dynamic range sample-and-hold, a precision reference and requires no external components. Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems The ADC has a microprocessor compatible, 14-bit parallel output port. There is no pipline delay in the conversion results. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO OPTIONAL 3V LOGIC SUPPLY 5V Effective Bits and Signal-to-Noise + Distortion vs Input Frequency 10µF AVDD DVDD OVDD 14 OUTPUT BUFFERS 14-BIT ADC S/H AIN – • • • D13 (MSB) D0 (LSB) 4.0625V COMP 80 12 74 11 68 10 9 8 7 6 5 BUFFER 10µF 86 13 S/(N + D) (dB) AIN + EFFECTIVE BITS LTC1414 14 4 2k VREF 2.5V REFERENCE TIMING AND LOGIC 1µF VSS 10µF AGND DGND BUSY 3 CONVST 2 OGND fSAMPLE = 2.2MHz 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1414 TA02 1414 TA01 – 5V 1 LTC1414 W U U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION AVDD = OVDD = DVDD = VDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................. 6V Negative Supply Voltage (VSS) ................................ – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ..........(VSS – 0.3V) to 10V Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V) Power Dissipation.............................................. 500mW Operating Temperature Range ..................... 0°C to 70°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C AIN+ AIN– 1 28 AVDD 2 27 AGND VREF 3 26 VSS REFCOMP 4 25 BUSY AGND 5 24 CONVST D13 (MSB) 6 23 DGND D12 7 22 DVDD D11 8 21 OVDD D10 9 20 D0 D9 10 19 D1 D8 11 18 D2 D7 12 17 D3 D6 13 16 D4 OGND 14 15 D5 LTC1414CGN GN PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 110°C, θJA = 110°C/ W Consult factory for Industrial, Military and A grade parts. U CO VERTER CHARACTERISTICS PARAMETER With internal reference (Notes 5, 6) LTC1414 TYP MAX UNITS ● ±0.75 ±2.0 LSB ● ±0.75 ± 1.75 LSB ±5 ±20 ±24 LSB LSB ±60 ±25 LSB LSB CONDITIONS MIN Resolution (No Missing Codes) Integral Linearity Error ● (Note 7) Differential Linearity Error Offset Error 13 (Note 8) Bits ● Full-Scale Error Internal Reference External Reference = 2.5V ±10 ±5 Full-Scale Tempco Internal Reference External Reference = 2.5V ±15 ±1 U U A ALOG I PUT (Note 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range 4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 4.75V ● IIN Analog Input Leakage Current Between Conversions ● CIN Analog Input Capacitance Between Conversions During Conversions tACQ Sample-and-Hold Acquisition Time tAP Sample-and-Hold Aperture Delay Time tjitter Sample-and-Hold Aperture Delay Time Jitter CMRR 2 ppm/°C ppm/°C Analog Input Common Mode Rejection Ratio MIN MAX ±2.5 40 UNITS V ±1 8 4 ● – 2.5V < (AIN– = AIN+) < 2.5V TYP µA pF pF 100 ns –1 ns 3 psRMS 70 dB LTC1414 W U DY A IC ACCURACY (Note 5) SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion Ratio 100kHz Input Signal 1.1MHz Input Signal THD Total Harmonic Distortion SFDR IMD MIN TYP MAX UNITS 80 78 dB dB 100kHz Input Signal, First 5 Harmonics 1.1MHz Input Signal, First 5 Harmonics – 95 – 83 dB dB Spurious Free Dynamic Range 100kHz Input Signal, First 5 Harmonics 1.1MHz Input Signal, First 5 Harmonics 95 84 dB dB Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz Full Power Bandwidth S/(N + D) ≥ 74dB Full Linear Bandwidth U U U I TER AL REFERE CE CHARACTERISTICS – 86 dB 40 MHz 3 MHz (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS VREF Output Voltage IOUT = 0 2.480 2.500 2.520 V VREF Output Tempco IOUT = 0 ±15 ppm/°C VREF Line Regulation 4.75V ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.01 0.01 LSB/ V LSB/ V VREF Output Resistance IOUT ≤ 0.1mA COMP Output Voltage IOUT = 0 U U DIGITAL I PUTS AND OUTPUTS SYMBOL PARAMETER 2 kΩ 4.06 V (Note 5) CONDITIONS MIN TYP MAX VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VOL Low Level Output Voltage VDD = 4.75V, IO = – 10µA VDD = 4.75V, IO = – 200µA ● VDD = 4.75V, IO = 160µA VDD = 4.75V, IO = 1.6mA ● 2.4 UNITS V 1.2 pF 4.74 V V 4.0 0.05 0.10 0.4 V V ISOURCE Output Source Current VOUT = 0V – 10 mA ISINK Output Sink Current VOUT = VDD 10 mA UW POWER REQUIRE E TS (Note 5) SYMBOL PARAMETER CONDITIONS MIN MAX UNITS VDD Positive Supply Voltage (Note 9) 4.75 TYP 5.25 V VSS Negative Supply Voltage (Note 9) – 4.75 – 5.25 V IDD Positive Supply Current CS High ● 12 16 mA ISS Negative Supply Current CS High ● 23 30 mA PD Power Dissipation 175 230 mW 3 LTC1414 WU TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX fSAMPLE(MAX) Maximum Sampling Frequency ● 2.2 tCONV Conversion Time ● 220 330 400 ns tACQ Acquisition Time ● 40 100 ns tTHROUGHPUT Throughput Time (Acquisition + Conversion) t1 CONVST to BUSY Delay ● 370 454 t2 Data Ready Before BUSY↑ t3 Delay Between Conversions (Note 9) ● 100 ns t4 CONVST Low Time (Note 10) ● 40 ns t5 CONVST High Time (Note 10) ● 40 ns t6 Aperture Delay of Sample-and-Hold CL = 25pF UNITS MHz ns 10 ns ±20 ns –1 The ● denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 2.2MHz and tr = tf = 5ns unless otherwise specified. ns Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN– grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Recommended operating conditions. Note 10: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best results ensure that CONVST returns high either within 225ns after the start of the conversion or after BUSY rises. U W TYPICAL PERFOR A CE CHARACTERISTICS Signal-to-Noise Ratio vs Input Frequency Distortion vs Input Frequency 86 90 0 13 80 80 –10 12 74 11 68 9 8 7 6 5 4 3 fSAMPLE = 2.2MHz 2 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1414 TA02 4 –20 70 DISTORTION (dB) 10 SIGNAL-TO-NOISE RATIO (dB) 14 S/(N + D) (dB) EFFECTIVE BITS S/(N + D) vs Input Frequency 60 50 40 30 –30 –40 –50 –70 20 –80 10 –90 0 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1414 G02 THD –60 –100 10k 3rd 2nd 100k 1M INPUT FREQUENCY (Hz) 10M 1414 G03 LTC1414 U W TYPICAL PERFOR A CE CHARACTERISTICS Spurious-Free Dynamic Range vs Input Frequency 0 2.0 0 fSAMPLE = 2.2MHz fIN1 = 80.566kHz fIN2 = 97.753kHz –10 –20 –20 –40 –50 –60 –70 1.0 –40 DNL (LSBs) –30 AMPLITUDE (dB) SPURIOUS-FREE DYNAMIC RANGE (dB) Differential Nonlinearity vs Output Code Intermodulation Distortion Plot –60 0 –80 –1.0 –80 –100 –90 –100 10k –120 100k 1M INPUT FREQUENCY (Hz) 10M –2.0 0 200 400 600 800 FREQUENCY (kHz) 0 1000 4096 8192 12288 OUTPUT CODE 16384 1414 G04 1414 G06 1414 F05a Integral Nonlinearity vs Output Code Power Supply Feedthrough vs Ripple Frequency 2.0 80 0 –1.0 VSS (VRIPPLE = 0.02V) VDD (VRIPPLE = 0.2V) OGND (VRIPPLE = 0.5V) OVDD (VRIPPLE = 0.5V) –20 COMMON MODE REJECTION (dB) AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) 0 1.0 INL (LSBs) Input Common Mode Rejection vs Input Frequency –40 –60 –80 –100 –2.0 0 4096 8192 12288 OUTPUT CODE 16384 70 60 50 40 30 20 10 0 –120 0 2M 4M 6M 8M RIPPLE FREQUENCY (Hz) 1414 G07 10M 1k 1M 10k 100k INPUT FREQUENCY (Hz) 1414 G08 10M LTC1414 • F12 U U U PIN FUNCTIONS A IN+ (Pin 1): Positive Analog Input. ±2.5V input range when AIN– is grounded. ±2.5V differential if AIN– is driven differentially with AIN+. AIN– (Pin 2): Negative Analog Input. Can be grounded or driven differentially with AIN+. VREF (Pin 3): 2.5V Reference Output. OGND (Pin 14): Digital Ground for the Output Drivers. Tie to AGND D5 to D0 (Pins 15 to 20): Data Outputs. OVDD (Pin 21): Positive Supply for the Output Drivers. Tie to Pin 28 when driving 5V logic. For 3V logic, tie to supply of the logic being driven. REFCOMP (Pin 4): 4.06V Reference Bypass Pin. Bypass to AGND with 10µF ceramic or 10µF tantalum in parallel with 0.1µF ceramic. DVDD (Pin 22): 5V Positive Supply. Tie to Pin 28. DGND (Pin 23): Digital Ground. Tie to AGND. AGND (Pin 5): Analog Ground. CONVST (Pin 24): Conversion Start Signal. This active low signal starts a conversion on its falling edge. D13 to D6 (Pins 6 to 13): Data Outputs. 5 LTC1414 U U U PIN FUNCTIONS BUSY (Pin 25): The BUSY Output Shows the Converter Status. It is low when a conversion is in progress. AGND (Pin 27): Analog Ground. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10µF ceramic or 10µF tantalum in parallel with 0.1µF ceramic. VSS (Pin 26): – 5V Negative Supply. Bypass to AGND with 10µF ceramic or 10µF tantalum in parallel with 0.1µF ceramic. W FUNCTIONAL BLOCK DIAGRA U U CSAMPLE AIN+ AVDD CSAMPLE DVDD AIN– 2k VREF VSS ZEROING SWITCHES 2.5V REF + REF AMP COMP 14-BIT CAPACITIVE DAC – REFCOMP (4.06V) OVDD 14 SUCCESSIVE APPROXIMATION REGISTER AGND OUTPUT LATCHES • • • D13 D0 OGND INTERNAL CLOCK DGND CONTROL LOGIC 1414 BD CONVST BUSY WU W TI I G DIAGRA tCONV t4 t5 CONVST t1 t3 BUSY t2 DATA 6 DATA (N – 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0 1414 TD LTC1414 U W U U APPLICATIONS INFORMATION CONVERSION DETAILS The LTC1414 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. The ADC is complete with a precision reference and an internal clock. The device is easy to interface with microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) AIN+ AIN– CSAMPLE+ SAMPLE CSAMPLE– SAMPLE HOLD HOLD HOLD CDAC+ + CDAC– VDAC+ Conversion start is controlled by the CONVST input. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. COMP – VDAC– 14 SAR OUTPUT LATCH D13 D0 1414 F01 Figure 1. Simplified Block Diagram Signal-to-Noise Ratio The signal-to-(noise + distortion) ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2a shows a typical spectral content with a 2.2MHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 1.1MHz. (See Figure 2b) 0 SINAD = 80dB SFDR = 96dB fSAMPLE = 2.2MHz fIN = 97.753kHz –20 AMPLITUDE (dB) During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase, and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 70ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 14-bit data word) which represents the difference of AIN+ and AIN– are loaded into the 14-bit output latches. ZEROING SWITCHES HOLD –40 –60 –80 DYNAMIC PERFORMANCE –100 The LTC1414 has excellent high speed sampling capability. FFT (Fast Four Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1414 FFT plot. –120 0 200 400 600 800 FREQUENCY (kHz) 1000 1414 F02a Figure 2a. LTC1414 Nonaveraged, 2048 Point FFT, Input Frequency = 100kHz 7 LTC1414 U U W U APPLICATIONS INFORMATION 0 –40 EFFECTIVE BITS AMPLITUDE (dB) –20 –60 –80 86 13 80 12 74 11 68 10 S/(N + D) (dB) SINAD = 78dB SFDR = 84dB fSAMPLE = 2.2MHz fIN = 997.949kHz 14 9 8 7 6 5 4 –100 3 fSAMPLE = 2.2MHz 2 –120 0 200 400 600 800 FREQUENCY (kHz) 1k 1000 10k 100k 1M INPUT FREQUENCY (Hz) 10M 1414 TA02 1414 F02b Figure 2b. LTC1414 2048 Point FFT, Input Frequency = 1MHz Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency 0 –10 Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOBS = [S/(N + D) – 1.76]/6.02 where S/(N + D) is expressed in dB. At the maximum sampling rate of 2.2MHz the LTC1414 maintains near ideal ENOBs up to the Nyquist input frequency of 1.1MHz. Refer to Figure 3. Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: 2 2 2 V + V3 + V4 + … VN THD = 20 log 2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1414 has good distortion performance up to the Nyquist frequency and beyond. 8 –30 –40 –50 THD –60 –70 –80 2nd –90 3rd –100 1 100k 1M 10k INPUT FREQUENCY (Hz) 10M 1414 F04 Figure 4. Distortion vs Input Frequency Total Harmonic Distortion 2 DISTORTION (dB) –20 Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to the THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3 etc. For example, the 2nd order IMD terms include (fa ± fb). If the two input sine waves are equal in magnitude, the value (in dB) of the 2nd order IMD products can be expressed by the following formula: LTC1414 U U W U APPLICATIONS INFORMATION ( amplitude at fa ± f b IMD f a ± fb = 20log amplitude at fa ( ) ) 0 fSAMPLE = 2.2MHz fIN1 = 80.566kHz fIN2 = 97.753kHz AMPLITUDE (dB) –20 –40 Driving the Analog Input –60 –80 –100 –120 0 200 400 600 800 FREQUENCY (kHz) 1000 1414 F05a Figure 5a. Intermodulation Distortion Plot with Inputs at 80kHz and 97kHz 0 fSAMPLE = 2.2MHz fIN1 = 970.019kHz fIN2 = 1.492MHz –20 AMPLITUDE (dB) The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 74dB (12 effective bits). The LTC1414 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. –40 –60 –80 –100 The differential analog inputs of the LTC1414 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN– input is grounded). The A IN+ and AIN– inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low then the LTC1414 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time, with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 70ns for full throughput rate). –120 0 200 400 600 800 FREQUENCY (kHz) 1000 10 Figure 5b. Intermodulation Distortion Plot with Input Signals of 1MHz and 1.5MHz Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dB relative to the RMS value of a fullscale input signal. ACQUISITION TIME (µs) 1414 F05b 1 0.1 0.01 10 Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. 100 1k 10k SOURCE RESISTANCE (Ω) 100k 1414 FO6 Figure 6. Acquisition Time vs Source Resistance 9 LTC1414 U W U U APPLICATIONS INFORMATION Choosing an Input Amplifier AC Coupled Inputs Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz must be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 40MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. In applications where only the AC component of the analog input is important, it may be desirable to AC couple the input. This is easily accomplished by DC biasing the LTC1414 analog input with a resistor to ground and using a coupling capacitor to the input. Figure 7 shows a simple AC coupled input circuit for the LTC1414 using only two additional components. C1 is a 10µF ceramic capacitor and R1 is a 1000Ω resistor to ground. R1 and C1 form a highpass filter with a lower cut off frequency of 1/2π(C1)R1 or 15.9Hz. C1 10µF ANALOG INPUT The best choice for an op amp to drive the LTC1414 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1414. More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM. LT®1223: 100MHz Video Current Feedback Amplifier. 6mA supply current. ±5V to ±15V supplies. Low noise. Good for AC applications. LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current. ±5V to ±15V supplies. Low noise. Best for AC applications. LT1229/LT1230: Dual and Quad 100MHz Current Feedback Amplifiers. ±2V to ±15V supplies. Low noise. Good AC specifications, 6mA supply current each amplifier. LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current. Good AC and DC specs. ±5V to ±15V supplies. 70ns settling to 0.5LSB. R1 1k 1 AIN+ 2 AIN – 3 1µF 4 LTC1414 VREF REFCOMP 10µF 5 AGND LTC1414 • F07 Figure 7. AC Coupled Input Differential Drive In some applications the ADC drive circuitry is differential. The differential drive can be applied directly to the LTC1414 without any special translation circuitry. Differential drive can be advantageous at high frequencies (>1MHz) since it provides improved THD and SFDR. Transformers can be used to provide AC coupling, input scaling and single ended to differential conversion as shown in Figure 8. The resistor RS across the secondary will determine the input impedance on the primary. The input impedance of the primary RP will be related to the secondary load resistor RS by the equation RP = RS/n2 LT1363: 70MHz, 1000V/µs Op Amps. 6.3mA supply current. Good AC and DC specifications. 60ns settling to 0.5LSB. For example, if a Minicircuits T4-6T transformer is used, the turns ratio is 2; if RS is 200Ω then RP is equal to 50Ω. LT1364/LT1365: Dual and Quad 70MHz, 1000V/µs Op Amps. 6.3mA supply current per amplifier. 60ns settling to 0.5LSB. The center tap of the secondary will set the common mode voltage and should be grounded for optimal AC performance. LinearView is a trademark of Linear Technology Corporation. 10 LTC1414 U U W U APPLICATIONS INFORMATION R1 50Ω 1:N RP ANALOG INPUT C1 500pF RS R2 50Ω Input Range 1 AIN+ 2 AIN – 3 1µF 4 LTC1414 VREF REFCOMP The ±2.5V input range of the LTC1414 is optimized for low noise and low distortion. Most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. 10µF 5 AGND LTC1414 • F08 Figure 8. If a Transformer Coupled Input is Required, this Circuit Provides a Simple Solution Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1414 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 40MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 9 shows a 500pF capacitor from AIN+ to ground and a 100Ω source resistor to limit the input bandwidth to 3.2MHz. The 500pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch-sensitive circuitry. High quality capacitors and resistors should be used since poor quality components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Some applications may require other input ranges. The LTC1414 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1414 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3), see Figure 10. A 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry. The reference amplifier multiplies the voltage at the VREF pin by 1.625 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin, REFCOMP (Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1µF or greater. For the best noise performance, a 10µF ceramic or 10µF tantalum in parallel with a 0.1µF ceramic is recommended. 2.500V R1 2k 3 VREF BANDGAP REFERENCE + 100Ω INPUT 500pF 1 AIN+ 2 AIN – 3 4.0625V 4 REFCOMP – LTC1414 R2 40k 10µF VREF 5 AGND 4 REFERENCE AMP R3 64k LTC1414 REFCOMP 10µF 1414 F10 5 AGND Figure 10. LTC1414 Reference Circuit LTC1414 • F09 Figure 9. An RC Filter Reduces the ADC’s 40MHz Bandwidth to 3.2MHz and Filters Out Wideband Noise Which May Be Present in the Input Signal 11 LTC1414 U U W U APPLICATIONS INFORMATION 1 ANALOG INPUT ±2V TO ±3V DIFFERENTIAL 80 COMMON MODE REJECTION (dB) The VREF pin can be driven with a DAC or other means shown in Figure 11. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1414 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed after a reference adjustment. AIN+ 50 40 30 20 10 1k 2 3 4 10M LTC1414 • F12 Figure 12. CMRR vs Input Frequency VREF The output is two’s complement binary with 1LSB = FS – (– FS)/16384 = 5V/16384 = 305.2µV. REFCOMP 10µF 5 1M 10k 100k INPUT FREQUENCY (Hz) AIN– AGND 1414 F11 Figure 11. Driving VREF with a DAC Differential Inputs The LTC1414 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of AIN+ – (AIN–) independent of the common mode voltage. The common mode rejection holds up to extremely high frequencies, see Figure 12. The only requirement is that neither input can exceed the AVDD or AVSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from –84dB with a common mode of 0V to –75dB with a common mode of 2.5V or –2.5V. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 14 shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN– input. For zero offset error apply – 152µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the AIN– input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.499544V (FS – 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. 011…111 011…110 011…101 OUTPUT CODE 2V TO 3V 60 0 LTC1414 LTC1450 70 000…000 111…111 100…010 100…001 Full-Scale and Offset Adjustment Figure 13 shows the ideal input/output characteristics for the LTC1414. The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). 12 100…000 –(FS – 1LSB) 0 FS – 1LSB INPUT RANGE LTC1414 • F13 Figure 13. LTC1414 Transfer Characteristics LTC1414 U U W U APPLICATIONS INFORMATION –5V R3 24k R1 50k ANALOG INPUT R4 100Ω 1 AIN+ 2 AIN – The LTC1414 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN– inputs will be reflected by the input CMRR. The AIN– input can be used as a ground sense for the AIN+ input; the LTC1414 will hold and convert the difference voltage between AIN+ and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN– traces should be run side by side to equalize coupling. LTC1414 R5 R2 47k 50k 3 R6 24k 4 VREF REFCOMP 10µF 5 AGND LTC1414 • F14 Figure 14. Offset and Full-Scale Adjust Circuit Board Layout and Bypassing To obtain the best performance from the LTC1414, a printed circuit board with a ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital line alongside an analog signal line or underneath the ADC. The analog input should be screened by AGND. High quality tantalum and ceramic bypass capacitors should be used at the VDD, VSS and VREF pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. 1 AIN+ AIN– ANALOG INPUT CIRCUITRY + – 2 A single point analog ground separate from the logic system ground should be established with an analog ground plane at AGND (Pin 5, 27) or as close as possible to the ADC (see Figure 8). The ADC’s DGND (Pin 23) and all other analog grounds should be connected to this single analog ground point. No other digital grounds should be connected to this analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and these traces should be as wide as possible. Excessive capacitive loading on the ADC’s data output lines can generate large transient currents on the ADC supplies which may affect conversion results. In these cases, the use of digital buffers is recommended to isolate the ADC from the excessive loading. EXAMPLE LAYOUT Figures 16a, 16b, 16c and 16d show the schematic and layout of an evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board. DIGITAL SYSTEM LTC1414 REFCOMP 4 AGND 10µF DVDD OVDD DGND OGND AVDD VSS 5, 27 26 10µF 28 22 21 23 14 10µF ANALOG GROUND PLANE 1414 F15 Figure 15. Power Supply Grounding Practice 13 LTC1414 U U W U APPLICATIONS INFORMATION VSS VCC J3 5V AGND + D2 SS12 DGND J1 –5V D1 SS12 C2 22µF 10V + J2 GND VCC VLOGIC R14 20Ω 0.125W C2 22µF 10V + C10 10µF 10V VCC C12 0.1µF C14 0.1µF C7 0.1µF DGND J9 JP3 JP2 J4 A+ R15 51Ω R17 10k R18 10k JP4 J5 A– C11 470pF C4 0.1µF VOUT V + 7 U3 LT1363 2 – 6 3 + 8 V– 4 1 SO-8 V + 7 U1 LT1363 2 – 6 3 + 8 V– 4 1 DIP-8 (OPTIONAL) R16 51Ω C3 0.1µF VSS J10 VREF C8 1µF 10V J8 J7 CLK C13 4.7µF 10V VCC VSS R19 51Ω DGND C5 1µF 10V C9 1µF 10V U5 74HC574 B[00:13] B00 B01 B02 B03 B04 B05 B08 U4 LTC1414CGN 1 2 3 4 25 24 23 22 21 28 26 27 5 14 AIN+ (MSB)D13 D12 AIN– D11 VREF REFCOMP D10 D9 BUSY D8 CONVST D7 DGND D6 OVDD D5 OVDD D4 AVDD D3 VSS D2 AGND D1 AGND D0 OGND 6 7 8 9 10 11 12 13 15 16 17 18 19 20 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 1 11 2 3 4 5 6 7 8 9 0E D0 D1 D2 D3 D4 D5 D6 D7 D[00:13] Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12 D00 D01 D02 D03 D04 D05 D08 19 18 17 16 15 14 13 12 D07 D06 D09 D10 D11 D12 D13 U6 74HC574 B07 B06 B09 B10 B11 B12 B13 1 11 2 3 4 5 6 7 8 9 0E D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D00 D01 D02 D03 D04 D05 D06 D07 D08 C15 1µF 10V D09 U7G, HC14 VLOGIC 14 PWR GND D13 7 U7E, HC14 D11 11 D12 10 D13 DGND DATA READY NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5% 2. ALL CAPACITOR VALUES IN µF, 25V, 20% AND IN pF, 50V, 10% 13 12 U7F, HC14 R21 1k C6 15pF D13 9 8 U7D, HC14 1414 F16a Figure 16a. Evaluation Circuit Schematic 14 D10 RDY J6-13 D00 J6-14 D01 J6-11 D02 J6-12 D03 J6-9 D04 J6-10 D05 J6-7 D06 J6-8 D07 J6-5 D08 J6-6 D09 J6-3 D10 J6-4 D11 J6-1 D12 J6-2 D13 J6-15 D13 J6-16 RDY J6-17 DGND J6-18 DGND HEADER 18-PIN LTC1414 U W U U APPLICATIONS INFORMATION Figure 16b. Evaluation Circuit Board Component Side Silkscreen 15 LTC1414 U W U U APPLICATIONS INFORMATION Figure 16c. Evaluation Circuit Board Component Side Layout 16 LTC1414 U W U U APPLICATIONS INFORMATION Figure 16d. Evaluation Circuit Board Solder Side Layout 17 LTC1414 U U W U APPLICATIONS INFORMATION Digital Interface The output data is updated at the end of the conversion as BUSY rises. Output data is updated coincident with the rising edge of BUSY. Data will be valid, and can be latched, 20ns after the rising edge of BUSY. Valid data can also be latched with the falling edge of BUSY or with the rising edge of CONVST. In the latter two cases the data latched will be for the previous conversion. The A/D converter has just one control input CONVST. Data is output on 14-bit parallel bus. An additional output BUSY indicates the converter status. DIGITAL OUTPUTS The parallel digital outputs of the LTC1414 are designed to interface to TTL and CMOS logic. The output data is two’s complement coded. CONVST Drive Considerations Timing jitter of the CONVST signal can adversely affect the noise performance of the LTC1414 when the input signal contains high slew rate components. The falling edge of CONVST determines the sampling instant. Any uncertainty in this sampling instant will translate to voltage noise when a fast changing input signal is being sampled. For a full amplitude sinusoidal input, the relationship between timing jitter (tjitter) and SNRj is The output drivers have a separate power pin (OVDD) and ground pin (OGND). This allows relatively noisy output ground and the output supply bypass ground to be separated from the other ADC grounds. Additionally, the OVDD pin may be driven by the supply of the logic that is being driven. For example, the OVDD supply may be 3V while LTC1414 DVDD and AVDD pins are 5V, allowing 3V logic to be driven directly. SNRj = 20log(1/2π • fIN • tjitter) Care should be taken to not load the digital outputs with excessive capacitance. Large capacitive loads result in large charging currents which can cause conversion errors. It is recommended that the capacitive loading is kept under 20pF. If it is not possible to keep the capacitance low, a buffer or latch may be used to isolate the LTC1414 from the capacitive load. where SNRj is the signal-to-jitter noise ratio. Timing and Control The internal clock is factory trimmed to achieve a typical conversion time of 330ns and a maximum conversion time over the full operating temperature range of 400ns. No external adjustments are required. The guaranteed maximum acquisition time is 100ns. In addition, a throughput time (acquisition + conversion) of 454ns and a minimum sampling rate of 2.2Msps is guaranteed. The internal circuitry of the LTC1414 has been optimized for ultralow jitter (typically 3ps RMS). The external clock drive circuitry is equally important and must also have low jitter to achieve low noise. Internal Clock The conversion start is controlled by the CONVST input. The falling edge of CONVST will start a conversion. Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. tCONV t4 t5 CONVST t1 t3 BUSY t2 DATA DATA (N – 1) DB13 TO DB0 DATA N DB13 TO DB0 Figure 17. Timing Diagram 18 DATA (N + 1) DB13 TO DB0 1414 F17 LTC1414 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. GN Package 28-Lead Plastic SSOP Narrow (0.150) (LTC DWG # 05-08-1641) 0.386 – 0.393* (9.804 – 9.982) 28 27 26 25 24 23 22 21 20 19 18 17 1615 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.0075 – 0.0098 (0.191 – 0.249) 0.033 (0.838) REF 2 3 4 5 6 7 8 9 10 11 12 13 14 0.053 – 0.069 (1.351 – 1.748) 0.004 – 0.009 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.008 – 0.012 (0.203 – 0.305) 0.025 (0.635) BSC * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. GN28 (SSOP) 0398 19 LTC1414 U TYPICAL APPLICATIO 2.2MHz, 14-Bit Sampling ADC 5V DIFFERENTIAL ANALOG INPUT –2.5V TO 2.5V 1 AIN+ AVDD 2 AIN– AGND 3 VREF OUT 2.5V 4 1µF 10µF 5 REFCOMP AGND VSS BUSY CONVST DGND 6 D13 (MSB) 7 D12 8 D11 9 D10 10 D9 11 D8 14-BIT PARALLEL BUS 12 D7 13 D6 14 OGND 27 –5V 10µF 10µF LTC1414 VREF 28 DVDD OVDD D0 D1 D2 D3 D4 D5 26 25 24 23 22 0.1µF 5V 21 20 19 18 17 16 15 1414 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1412 Low Power, 12-Bit ,3Msps, ADC Nyquist Sampling, 150mW, 72dB SINAD LTC1415 Single 5V, 12-Bit, 1.25Msps, ADC Single Supply, 55mW Dissipation LTC1416 Low Power, 14-Bit, 400ksps, ADC ±5V Supplies, 75mW Dissipation LTC1417 Very Low Power, 14-Bit, 400ksps, ADC 20mW, 5V or ±5V Supply, Serial I/O in 16-Pin SSOP LTC1418 Very Low Power, 14-Bit, 200ksps, ADC 15mW, 5V or ±5V Supply, Serial or Parallel I/O LTC1419 Low Power, 14-Bit, 800ksps, ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation LTC1604 High Speed, 16-Bit, 333ksps, ADC 90dB SINAD, –100dB THD, 220mW Dissipation LT1460 Micropower Precision Series Reference 0.075% Accuracy, 10ppm/°C Drift 20 Linear Technology Corporation 1414f LT/TP 0399 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998