TI1 MSP430X31X Mixed signal microcontroller Datasheet

MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
D Low Supply Voltage Range 2.5 V − 5.5 V
D Ultra Low-Power Consumption
D Low Operation Current, 400 μA at 1 MHz,
D
D
D
D
D
D
D
D
D
D
D
DL PACKAGE
(56-PIN TOP VIEW)
TDO/TDI
TDI/VPP
TMS
TCK
RST/NMI
XBUF
VSS
VCC
R23
R13
Xin
Xout/TCLK
P0.0
P0.1/RXD
P0.2/TXD
P0.3
P0.4
P0.5
P0.6
P0.7
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
CIN
NC
3V
Five Power Saving Modes: (Standby Mode:
1.3 μA, RAM Retention/Off Mode: 0.1 μA)
Wakeup From Standby Mode in 6 μs
Maximum
16-Bit RISC Architecture, 300 ns Instruction
Cycle Time
Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz
Integrated LCD Driver for up to 64 or 92
Segments
Slope A/D Converter With External
Components
Serial Onboard Programming
Program Code Protection by Security Fuse
Family Members Include:
MSP430C311S: 2k Byte ROM, 128 Byte RAM
MSP430C312: 4k Byte ROM, 256 Byte RAM
MSP430C313: 8k Byte ROM, 256 Byte RAM
MSP430C314: 12k Byte ROM, 512 Byte RAM
MSP430C315: 16k Byte ROM, 512 Byte RAM
MSP430P313: 8k Byte OTP, 256 Byte RAM†
MSP430P315: 16k Byte OTP, 512 Byte RAM
MSP430P315S: 16k Byte OTP, 512 Byte RAM
EPROM Version Available for Prototyping :
PMS430E313FZ†, PMS430E315FZ
Available in:
56-Pin Plastic Small-Outline Package
(SSOP),
48-Pin SSOP (MSP430C311S,
MSP430P315S),
68-Pin J-Leaded Ceramic Chip Carrier
(JLCC) Package (EPROM Only)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
COM3
COM2
COM1
COM0
S27/O27/CMPI
S26/O26
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
S2/O2
S1
S0
DL PACKAGE
(48-PIN TOP VIEW)
TDI/VPP
TMS
TCK
RST/NMI
XBUF
VSS
VCC
R23
R13
Xin
Xout/TCLK
P0.1/RXD
P0.2/TXD
P0.3
P0.4
P0.5
P0.6
NC
TP0.0
TP0.1
TP0.2
TP0.3
TP0.5
CIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TDO/TDI
COM3
COM2
COM1
COM0
S27/O27/CMPI
NC
VSS
NC
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
S2/O2
NC − No internal connection
description
The MSP430 is an ultralow-power mixed signal microcontroller family consisting of several devices that feature
different sets of modules targeted to various applications. The microcontroller is designed to be battery operated
for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated registers on the CPU, and
a constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled oscillator,
together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode to active mode in
less than 6 ms.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.
Copyright © 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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•
1
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
description (continued)
Typical applications include sensor systems that capture analog signals, converting them to digital values, and
then processes the data and displays them or transmits them to a host system. The timer/port module provides
single-slope A/D conversion capability for resistive sensors.
AVAILABLE OPTIONS
PACKAGED DEVICES
SSOP
48-Pin
(DL)
SSOP
56-Pin
(DL)
−40°C
40°C to 85°C
MSP430C311SIDL
MSP430P315SIDL
MSP430C312IDL
MSP430C313IDL
MSP430C314IDL
MSP430C315IDL
MSP430P313IDL†
MSP430P315IDL
25°C
—
—
TA
†
JLCC
68-Pin
(FZ)
PMS430E313FZ†
PMS430E315FZ
MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.
functional block diagram
MSP430C312,313,314,315 and MSP430P313†,315 and PMS430E313,315
XIN
Xout
Oscillator
FLL
System Clock
V CC
XBUF
4/8/12/16 kB
ROM
8/16 kB
ACLK
MCLK
TDI/VPP
OPT or EPROM
C: ROM
P: OTP
E: EPROM
V SS
RST/NMI
P0.0−7
8
256/512 B
Power-On-
RAM
Reset
8-Bit Timer/
Counter
I/O Port
TXD
Serial Protocol
Support
8 I/O’s, All With
Interr. Cap.
3 Int. Vectors
RXD
TDO/TDI
MAB, 16 Bit
CPU
Test
Incl. 16 Reg.
JTAG
MAB, 4 Bit
MCB
MDB, 16 Bit
MDB, 8 Bit
Bus
Conv
TMS
TCK
Watchdog
Timer
Applications:
Timer/Port
15/16 Bit
A/D Conv.
Timer, O/P
Basic
Timer1
f LCD
LCD
92 Segments
1, 2, 3, 4 MUX
Com0−3
S0−18,22,23,26/
O2−18,22,23,26
S27/O27/CMPI
5
TP0.5
2
•
TP0.0−4
CIN
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•
CMPI
R13
R23
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
Terminal Functions
MSP430C312, MSP430C313†, MSP430C314, MSP430C315, MSP430P313†, MSP430P315
56-pin SSOP package
TERMINAL
NAME
CIN
I/O
DESCRIPTION
27
I
Counter enable. CIN input enables counter (TPCNT1) (timer/port).
52 −55
O
Common output pins. COM0 −COM3 are used for LCD back planes.
P0.0
13
I/O
General-purpose digital I/O pin
P0.1/RXD
14
I/O
General-purpose digital I/O pin, receive data input port − 8-bit (timer/counter)
P0.2/TXD
15
I/O
General-purpose digital I/O pin, transmit data output port − 8-bit (timer/counter)
P0.3 −P0.7
Five general-purpose digital I/O pins, bit 3−7
COM0 −COM3
16 −20
I/O
R23
9
I
Input of second positive analog LCD level (V2) (LCD)
R13
10
I
Input of third positive analog LCD level (V3 of V4) (LCD)
RST/NMI
5
I
Reset input or nonmaskable interrupt input
S0
29
O
Segment line S0 (LCD)
S1
30
O
Segment line S1 (LCD)
S2/O2 −S5/O5
31 −34
O
Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
S6/O6 −S9/O9
35 −38
O
Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
S10/O10 −S13/O13
39 −42
O
Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
S14/O14 −S17/O17
43 −46
O
Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
47
O
Segment line (S18) or digital output port O18 , group 5 (LCD)
S18/O18
S22/O22 −S23/O23
†
NO.
48,49
O
Segment lines (S22 to S23) or digital output port O22 to O23, group 6 (LCD)
S26/O26
50
O
Segment line (S26) or digital output port O26, group 7 (LCD)
S27/O27/CMPI
51
I/O
Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI
(timer/port)
TCK
4
I
Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP
2
I
Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
TDO/TDI
1
I/O
Test data output port. TDO/TDI is used as a data output terminal or as a data input during
programming.
TMS
3
I
TP0.0
21
O/Z
General-purpose 3-state digital output port, bit 0 (timer/port)
TP0.1
22
O/Z
General-purpose 3-state digital output port, bit 1 (timer/port)
TP0.2
23
O/Z
General-purpose 3-state digital output port, bit 2 (timer/port)
TP0.3
24
O/Z
General-purpose 3-state digital output port, bit 3( timer/port)
TP0.4
25
O/Z
General-purpose 3-state digital output port, bit 4 (timer/port)
TP0.5
26
I/O/Z
General-purpose 3-state digital I/O pin, bit 5 (timer/port)
VCC
8
VSS
7
XBUF
6
Test mode select. TMS is an input terminal for device programming and test.
Supply voltage
Ground reference
O
Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Input terminal of crystal oscillator
Xin
11
I
Xout/TCLK
12
I/O
Output terminal of crystal oscillator or test clock input
MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.
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3
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
functional block diagram
MSP430C311S and MSP430P315S
XIN
Xout
XBUF
V CC
V SS
RST/NMI
P0.1−6
6
Oscillator
FLL
System Clock
ACLK
MCLK
TDI/VPP
2 kB
ROM
16 kB
128/512B
Power-On-
RAM
Reset
8-bit Timer/
Counter
OTP
C: ROM
P: OTP
I/O Port
TXD
Serial Protocol
Support
6 I/O’s, All With
Interr. Cap.
2 Int. Vectors
RXD
TDO/TDI
MAB, 16 Bit
CPU
Test
Incl. 16 Reg.
JTAG
MAB, 4 Bit
MCB
MDB, 16 Bit
MDB, 8 Bit
Bus
Conv
TMS
TCK
Watchdog
Timer
Applications:
Timer/Port
15/16 Bit
A/D Conv.
Timer, O/P
Basic
Timer1
f LCD
LCD
64 Segments
1, 2, 3, 4 MUX
CMPI
4
TP0.0−3
TP0.5
4
•
R13
CIN
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•
R23
COM0−3
S2−16/O2−16
S27/O27/CMPI
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
Terminal Functions
MSP430C311S, MSP430P315S
48-pin SSOP package
TERMINAL
NAME
CIN
NO.
I/O
DESCRIPTION
24
I
Counter enable. CIN input enables counter (TPCNT1) (timer/port).
44 −47
O
Common output pins, COM0 −COM3 are used for LCD back planes.
P0.1/RXD
12
I/O
General-purpose digital I/O pin, receive data input port − 8-Bit (timer/counter)
P0.2/TXD
13
I/O
General-purpose digital I/O pin, transmit data output port − 8-Bit (timer/counter)
P0.3
14
I/O
General-purpose digital I/O pins, bit 3
P0.4
15
I/O
General-purpose digital I/O pins, bit 4
P0.5
16
I/O
General-purpose digital I/O pins, bit 5
P0.6
17
I/O
General-purpose digital I/O pins, bit 6
R23
8
I
Input of second positive analog LCD level (V2) (LCD)
R13
9
I
Input of third positive analog LCD level (V3 of V4) (LCD)
COM0 −COM3
RST/NMI
4
I
Reset input or nonmaskable interrupt input
S2/O2 −S5/O5
25 −28
O
Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
S6/O6 −S9/O9
29 −32
O
Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
S10/O10 −S13/O13
33 −36
O
Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
S14/O14 −S16/O16
37 −39
O
Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
S27/O27/CMPI
43
I/O
Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI
(timer/port)
TCK
3
I
Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP
1
I
Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
TDO/TDI
48
I/O
Test data output port. TDO/TDI is used as a data output terminal or as a data input during
programming.
TMS
2
I
TP0.0
19
O/Z
General-purpose 3-state digital output port, bit 0 (timer/port)
TP0.1
20
O/Z
General-purpose 3-state digital output port, bit 1 (timer/port)
TP0.2
21
O/Z
General-purpose 3-state digital output port, bit 2 (timer/port)
TP0.3
22
O/Z
General-purpose 3-state digital output port, bit 3 (timer/port)
TP0.5
23
I/O/Z
General-purpose 3-state digital I/O pin, bit 5 (timer/port)
VCC
7
VSS
6, 41
Test mode select. TMS is an input terminal for device programming and test.
Supply voltage
Ground references
XBUF
5
O
Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Xin
10
I
Input terminal of crystal oscillator
Xout/TCLK
11
I/O
Output terminal of crystal oscillator or test clock input
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5
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
short-form description
processing unit
The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development and
distinguishable by the ease of programming. All operations other than program-flow instructions are
consequently performed as register operations in conjunction with seven addressing modes for source and four
modes for destination operand.
CPU
Sixteen registers located inside the CPU provide
reduced instruction execution time. This reduces
a register-register operation execution time to one
cycle of the processor frequency.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Four registers are reserved for special use as a
program counter, a stack pointer, a status register,
and a constant generator. The remaining ones are
available as general-purpose registers.
Constant Generator
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R14
Peripherals connected to the CPU using a data
address and control bus can be handled easily
with all instructions for memory manipulation.
instruction set
The instruction set for this register-register
R15
General-Purpose Register
architecture provides a powerful and easy-to-use
assembly language. The instruction set consists of 51 instructions with three formats and seven addressing
modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing
modes are listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4, R5
R4 + R5 → R5
Single operands, destination only
e.g. CALL R8
PC → (TOS), R8 → PC
Relative jump, un-/conditional
e.g. JNE
Jump-on equal bit = 0
Each instruction that operates on word and byte data is identified by the suffix B.
Examples:
6
Instructions for word operation
Instructions for byte operation
MOV
ADD
PUSH
SWPB
MOV.B
ADD.B
PUSH.B
—
EDE,TONI
#235h,&MEM
R5
R5
•
EDE,TONI
#35h,&MEM
R5
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MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
Table 2. Address Mode Descriptions
ADDRESS MODE
s
d
Register
√
√
MOV Rs, Rd
MOV R10, R11
R10 → R11
Indexed
√
√
MOV X(Rn), Y(Rm)
MOV 2(R5), 6(R6)
M(2 + R5) → M(6 + R6)
Symbolic (PC relative)
√
√
MOV EDE, TONI
Absolute
√
√
MOV &MEM, &TCDAT
Indirect
√
MOV @Rn, Y(Rm)
MOV @R10, Tab(R6)
M(R10) → M(Tab + R6)
Indirect autoincrement
√
MOV @Rn+, RM
MOV @R10+, R11
M(R10) → R11, R10 + 2 → R10
Immediate
√
MOV #X, TONI
MOV #45, TONI
#45 → M(TONI)
NOTE: s = source
SYNTAX
EXAMPLE
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
d = destination
Computed branches (BR) and subroutine call (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultra low-power and ultra-low energy
consumption. This is achieved by the management of the operations during the different module operation
modes and CPU states. The requirements are fully supported during interrupt event handling. An interrupt event
awakens the system from each of the various operating modes and returns with the RETI instruction to the mode
that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal
frequency and MCLK , a multiple of ACLK, is used as the system clock.
The software can configure five operating modes:
D Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
D Low-power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
D Low-power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
D Low-power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
D Low-power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(³MCLK generator) is switched off.
D Low-power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
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7
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
operation modes and interrupts (continued)
The most general bits that influence current consumption and support fast turn-on from low power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.
15
9
8
Reserved For Future
Enhancements
rw-0
7
0
V
SCG1
SCG0
OscOff
CPUOff
GIE
N
Z
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
rw-0
C
rw-0
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
WDTIFG (see Note 1)
Reset
0FFFEh
15, highest
NMI, oscillator fault
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 4)
Nonmaskable,
(Non)maskable
0FFFCh
14
Dedicated I/O P0.0
P0.0IFG
Maskable
0FFFAh
13
P0 1IFG
P0.1IFG
Maskable
0FFF8h
12
0FFF6h
11
0FFF4h
10
0FFF2h
9
Power-up, external reset, watchdog
Dedicated I/O P0.1
8-Bit Timer/Counter
Watchdog Timer
Basic Timer1
I/O Port 0.2 −7
8
Maskable
RC1FG, RC2FG, EN1FG
(see Note 2)
Timer/Port
NOTES: 1.
2.
3.
4.
WDTIFG
Maskable
0FFF0h
8
0FFEEh
7
0FFECh
6
0FFEAh
5
0FFE8h
4
0FFE6h
3
0FFE4h
2
BTIFG
Maskable
0FFE2h
1
P0.27IFG (see Note 1)
Maskable
0FFE0h
0, lowest
Multiple source flags
Timer/port interrupt flags are located in the timer/port registers
Non maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.
(Non) maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot.
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MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
Address
6
5
4
0h
3
2
1
P0IE.1
P0IE.0
OFIE
rw-0
WDTIE:
OFIE:
P0IE.0:
P0IE.1:
rw-0
rw-0
0
WDTIE
rw-0
Watchdog Timer enable signal
Oscillator fault enable signal
Dedicated I/O P0.0
P0.1 or 8-Bit Timer/Counter, RXD
7
Address
01h
6
5
4
3
2
BTIE
0
0
TPIE
rw-0
TPIE:
BTIE:
1
rw-0
Timer/Port enable signal
Basic Timer1 enable signal
interrupt flag register 1 and 2
7
Address
6
5
02h
4
3
2
1
NMIIFG
P0IFG.1
P0IFG.0
OFIFG
rw-0
WDTIFG:
rw-0
rw-0
rw-1
WDTIFG
rw-0
Set on overflow or security key violation
OR
Reset on VCC power-on or reset condition at RST/NMI-pin
Flag set on oscillator fault
Dedicated I/O P0.0
P0.1 or 8-Bit Timer/Counter, RXD
Signal at RST/NMI-pin
OFIFG:
P0.0IFG:
P0.1IFG:
NMIIFG:
7
Address
03h
6
5
4
3
2
1
0
BTIFG
rw
BTIFG:
Basic Timer1 flag
module enable register 1 and 2
Address
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
04h
Address
05h
Legend
rw:
rw-0:
Bit can be read and written.
Bit can be read and written. It is reset by PUC
SFR bit is not present in device.
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•
9
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
memory organization
MSP430C311S
FFFFh
FFE0h
FFDFh
Int. Vector
2 kB ROM
MSP430C313
MSP430C312
FFFFh
FFE0h
FFDFh
Int. Vector
FFFFh
FFE0h
FFDFh
Int. Vector
MSP430C315
MSP430C314
FFFFh
FFE0h
FFDFh
Int. Vector
FFFFh
FFE0h
FFDFh
Int. Vector
4 kB ROM
F800h
8 kB ROM
F000h
12 kB ROM
16 kB ROM
E000h
D000h
C000h
03FFh
0200h
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
128B RAM
16b Per.
8b Per.
SFR
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
FFE0h
FFDFh
Int. Vector
16b Per.
8b Per.
SFR
FFFFh
FFE0h
FFDFh
16b Per.
8b Per.
SFR
01FFh
0100h
00FFh
0010h
000Fh
0000h
Int. Vector
8 kB OTP
or
EPROM
16 kB
OTP
or
EPROM
E000h
C000h
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
†
10
256B RAM
16b Per.
8b Per.
SFR
03FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
512B RAM
16b Per.
8b Per.
SFR
MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.
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•
03FFh
0200h
512B RAM
256B RAM
MSP430P315
MSP430P315S
PMS430E315
MSP430P313†
PMS430E313†
FFFFh
256B RAM
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
512B RAM
16b Per.
8b Per.
SFR
01FFh
0100h
00FFh
0010h
000Fh
0000h
16b Per.
8b Per.
SFR
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
peripherals
Peripherals connected to the CPU through a data, address, and control busses can be handled easily with
instructions for memory manipulation.
oscillator and system clock
Two clocks are used in the system: the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency. The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without requiring any other external components.
The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.
The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:
•
•
•
•
High frequency in order to react quickly to system hardware requests or events
Low frequency in order to minimize current consumption, EMI, etc.
Stable frequency for timer applications e.g. real-time clock (RTC)
Enable start-stop operation with a minimum delay
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency, which is multiplied to achieve the desired
nominal operating range:
f(system) = (N+1) × f(crystal)
The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO), provides immediate start-up capability together with long-term crystal stability. The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 μs, the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used. This forces longer cycle times if
the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to
meet the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a power-up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
removal of the PUC condition. Correct operation of the FLL control logic requires the presence of a stable crystal
oscillator.
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•
11
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
peripherals (continued)
digital I/O
There is one eight-bit I/O port, Port0, that is implemented (MSP430C311S and MSP430P315S have six bits
available on external pins). Six control registers give maximum digital input/output flexibility to the application:
•
•
•
•
All individual I/O bits are programmable independently.
Any combination of input, output, and interrupt conditions is possible.
Interrupt processing of external events is fully implemented for all eight bits of port P0.
Provides read/write access to all registers with all instructions
The six registers are:
•
•
•
•
•
•
Input register
8 bits
contains information at the pins
Output register
8 bits
contains output information
Direction register
8 bits
controls direction
Interrupt flags
6 bits
indicates if interrupt(s) are pending
Interrupt edge select
8 bits
contains input signal change necessary for interrupt
Interrupt enable
6 bits
contains interrupt enable bits
All these registers contain eight bits except for the interrupt flag register and the interrupt enable register. The
two least significant bits (LSBs) of the interrupt flag and interrupt enable registers are located in the special
functions register (SFR). Three interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one
commonly used for any interrupt event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with
the 8-bit timer/counter.
LCD drive
Liquid crystal displays (LCDs) for static, 2-, 3-, and 4-MUX operations can be driven directly. The controller LCD
logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module
and not part of the data memory. Eight mode and control bits define the operation and current consumption of
the LCD drive. The information for the individual digits can be easily obtained using table programming
techniques combined with the correct addressing mode. The segment information is stored in LCD memory
using instructions for memory manipulation.
The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3-,
and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The
MSP430x31x has four common signals and 23 segment lines. The MSP430C311S and MSP430P315S have
four common lines and 16 segment lines.
Timer/Port
The Timer/Port module has two 8-bit counters, an input that triggers one counter, and six digital outputs in the
MSP430x31x (MSP430C311S, MSP430C315S have five digital outputs available on external pins) with
high-impedance state capability. Both counters have an independent clock-selector for selecting an external
signal or one of the internal clocks (ACLK or MCLK). One counter has an extended control capability to halt,
count continuously, or gate the counter by selecting one of two external signals. This gate signal sets the
interrupt flag, if an external signal is selected, and the gate stops the counter.
Both timers can be read from and written to by software. The two 8-bit counters can be cascaded to a 16-bit
counter. A common interrupt vector is implemented. The interrupt flag can be set from three events in the 8-bit
counter mode (gate signal, overflow from the counters) or from two events in the 16-bit counter mode (gate
signal, overflow from the MSB of the cascaded counter).
12
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MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
peripherals (continued)
slope A/D conversion
Slope A/D conversion is accomplished with the timer/port module using external resistor(s) for reference (Rref),
external resistor(s) to the measured (Rmeas), and an external capacitor. The external components are driven
by software in such a way that the internal counter measures the time that is needed to charge or discharge
the capacitor. The reference resistor’s (Rref) charge or discharge time is represented by Nref counts. The
unknown resistors (Rmeas) charge or discharge time is represented by Nmeas counts. The unknown resistor’s
value (Rmeas) is the value of Rref multiplied by the relative number of counts (Nmeas/Nref). This value determines
resistive sensor values that correspond to the physical data, for example temperature, when an NTC or PTC
resistor is used.
Basic Timer1
The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low
frequency control signals. This is done within the system by one central divider, the basic timer1, to support low
current applications. The BTCTL control register contains the flags which controls or selects the different
operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a
watchdog overflow, or a watchdog security key violation occurs, all bits in the register hold undefined or
unchanged status. The user software usually configures the operational conditions on the BT1 during
initialization.
The Basic Timer1 has two 8 bit timers which can be cascaded to a 16 bit timer. Both timers can be read and
written by software. Two bits in the SFR address range handle the system control interaction according to the
function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the
basic timer interrupt enable (BTIE) bit.
Watchdog Timer
The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software problem has occurred. If the selected time interval expires, a system reset is generated. If this
watchdog function is not needed in an application, the module can work as an interval timer, which generates
an interrupt after the selected time interval.
The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.
The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is a 16-bit read/write
register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.
If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When
the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In
addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL which configure the NMI
pin.
8-Bit Timer/Counter
The 8-bit interval timer supports three major functions for the application:
• Serial communication or data exchange
• Pulse counting or pulse accumulation
• Timer
The 8-bit Timer/Counter peripheral includes the following major blocks: an 8-bit up-counter with
preload-register, an 8-bit control register, an input clock selector, an edge detection (e.g. start bit detection for
asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-bit
counter.
The 8-bit counter counts up with an input clock, which is selected by two control bits from the control register.
The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from
the logical AND of MCLK and terminal P0.1.
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13
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
8-Bit Timer/Counter (continued)
Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A
write-access to the counter results in loading the content of the preload-register into the counter. The software
writes or reads the preload-register with all instructions. The preload-register acts as a buffer and can be written
immediately after the load of the counter is completed. The enable input enables the count operation. When
the enable signal is set to high, the counter will count up each time a positive clock edge is applied to the clock
input of the counter.
Serial protocols, like UART protocol, need start-bit edge-detection to determine, at the receiver, the start of a
data transmission. When this function is activated, the counter starts counting after start-bit condition is
detected. The first signal level is sampled into the RXD input data-latch after completing the first timing interval,
which is programmed into the counter. Two latches used for input and output data (RXD_FF and TXD_FF) are
clocked by the counter after the programmed timing interval has elapsed.
UART
The serial communication is realized by using software and the 8-bit timer/counter hardware. The hardware
supports the output of the serial data stream, bit-by-bit, with the timing determined by the counter. The
software/hardware interface connects the mixed signal controller to external devices, systems, or networks.
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
14
EPROM
EPROM control
EPCTL
054h
Crystal buffer
Crystal buffer control
CBCTL
053h
System clock
SCG frequency control
SCG frequency integrator
SCG frequency integrator
SCFQCTL
SCFI1
SCFI0
052h
051h
050h
Timer /Port
Timer/Port enable
Timer/Port data
Timer/Port counter2
Timer/Port counter1
Timer/Port control
TPE
TPD
TPCNT2
TPCNT1
TPCTL
04Fh
04Eh
04Dh
04Ch
04Bh
8-Bit Timer/Counter
8-Bit Timer/Counter data
8-Bit Timer/Counter preload
8-Bit Timer/Counter control
TCDAT
TCPLD
TCCTL
044h
043h
042h
Basic Timer1
Basic Timer/Counter2
Basic Timer/Counter1
Basic Timer control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
LCD
LCD memory 15
:
LCD memory1
LCD control & mode
LCDM15
03Fh
LCDM1
LCDCTL
031h
030h
Port P0
Port P0 interrupt enable
Port P0 interrupt edge select
Port P0 interrupt flag
Port P0 direction
Port P0 output
Port P0 input
P0IE
P0IES
P0IFG
P0DIR
P0OUT
P0IN
015h
014h
013h
012h
011h
010h
Special function
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
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•
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC +0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 2 mA
Storage temperature, Tstg (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS.
recommended operating conditions
MIN
Supply voltage, VCC
Supply voltage during programming
programming, VCC
NOM
MAX
UNIT
MSP430Cxxx
2.5
5.5
MSP430P313‡, PMS430E313‡
2.7
5.5
MSP430P315, PMS430E315
2.7
5.5
MSP430P313
2.7
5.5
V
MSP430P315
4.5
5.5
V
Supply voltage, VSS
0
V
V
MSP430C31x
40
−40
MSP430P31x
Operating free-air
free air temperature range, TA
85
PMS430E31x
XTAL frequency, f(XTAL)
32 768
DC
2.2
VCC = 5 V
DC
3.3
Low-level input voltage, VIL (excluding Xin, Xout)
VSS
VSS+0.8
High-level input voltage, VIH (excluding Xin, Xout)
0.7×VCC
VCC
VSS
0.2×VCC
0.8×VCC
VCC
Low-level input voltage, VIL(Xin, Xout)
VCC = 3 V/5 V
High-level input voltage, VIH(Xin, Xout)
MHz
V
V
MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.
f(system) − Maximum Processor
Frequency − MHz
‡
Hz
VCC = 3 V
Processor frequency f(system) (signal MCLK) fsystem
°C
C
25
f(MHz)
3.3
2.2
Minimum
3
2.5
5
5.5
VCC (V)
VCC − Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock.
Figure 1. Processor Frequency vs Supply Voltage, C Versions
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15
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
f(system) − Maximum Processor
Frequency − MHz
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
f(MHz)
3.3
2.2
1.5
Minimum
2.7
3
5
5.5
VCC (V)
VCC − Supply Voltage − V
NOTE: Minimum processor frequency is defined by system clock.
Figure 2. Processor Frequency vs Supply Voltage, P/E Versions
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
supply current (into VCC) excluding external current (f(system) = 1 MHz)
PARAMETER
I(AM)
I(CPUOff)
I(LPM2)
Active mode
Low power mode
Low-power
mode, (LPM0
(LPM0,1)
1)
Low power mode,
Low-power
mode (LPM2)
TEST CONDITIONS
C31x
TA = − 40°C + 85°C
P313†
TA = − 40°C + 85°C
P315(S)
TA = − 40°C + 85°C
C31x
TA = − 40°C + 85°C
P313†
TA = − 40°C + 85°C
P315(S)
TA = − 40°C + 85°C
NOM
MAX
VCC = 3 V
400
500
VCC = 5 V
730
850
VCC = 3 V
2100
2700
VCC = 5 V
7000
8600
VCC = 3 V
490
550
VCC = 5 V
960
1050
VCC = 3 V
50
70
VCC = 5 V
100
130
VCC = 3 V
70
85
VCC = 5 V
150
170
VCC = 3 V
50
70
VCC = 5 V
100
130
VCC = 3 V
6
12
VCC = 5 V
13
25
1.5
2.4
1.3
2
TA = 85°C
1.6
2.8
TA = − 40°C
5.2
7
4.2
6
TA = 85°C
4.8
5.4
TA = − 40°C
0.1
0.8
0.1
0.8
0.4
1.3
TA = − 40°C + 85°C
TA = − 40°C
TA = 25°C
I(LPM3)
Low power mode,
Low-power
mode (LPM3)
TA = 25°C
I(LPM4)
Low-power
p
mode,, (LPM4)
(
)
MIN
TA = 25°C
VCC = 3 V
VCC = 5 V
VCC = 3 V/5 V
TA = 85°C
UNIT
μA
μA
μA
μA
μA
μ
† MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.
NOTE: All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured
with active basic timer (ACLK selected) and LCD module. (fLCD = 1024 Hz, 4 mux)
16
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•
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
current consumption of active mode versus system frequency, C versions only
IAM = IAM[1 MHz] × fsystem [MHz]
current consumption of active mode versus supply voltage, C versions only
IAM = IAM[3 V] + 200 μA/V × (VCC −3 V)
schmitt-trigger inputs port 0, Timer/Port, CIN, TP0.5
PARAMETER
TEST CONDITIONS
VIT+
Positive going input threshold voltage
Positive-going
VIT−
Negative going input threshold voltage
Negative-going
Vhys
Input hysteresis (VIT+− VIT−)
MIN
NOM
MAX
VCC = 3 V
1.2
2.1
VCC = 5 V
2.3
3.4
VCC = 3 V
0.5
1.35
VCC = 5 V
1.4
2.3
VCC = 3 V
0.3
1
VCC = 5 V
0.6
1.4
UNIT
V
V
V
standard inputs TCK, TMS, TDI, RST/NMI
PARAMETER
VIL
Low-level input voltage
VIH
High-level input voltage
TEST CONDITIONS
MIN
VCC = 3 V/5 V
NOM
MAX
VSS
VSS+0.8
0.7VCC
VCC
UNIT
V
outputs port 0, P0.x, Timer/Port, TP0.0 − 5, LCD: S2/O2 to S26/O26 XBUF:XBUF, JTAG:TDO
PARAMETER
VOH
VOL
High level output voltage
High-level
Low level output voltage
Low-level
TEST CONDITIONS
MIN
NOM
MAX
IOH = − 1.2 mA,
VCC = 3 V,
See Note 5
VCC −0.4
VCC
IOH = − 3.5 mA,
VCC = 3 V,
See Note 6
VCC −1
VCC
IOH = − 1.5 mA,
VCC = 5 V,
See Note 5
VCC −0.4
VCC
IOH = − 4.5 mA,
VCC = 5 V,
See Note 6
VCC −1
VCC
IOL = 1.2 mA,
VCC = 3 V,
See Note 5
VSS
VSS+0.4
IOL = 3.5 mA,
VCC = 3 V,
See Note 6
VSS
VSS+1
IOL = 1.5 mA,
VCC = 5 V,
See Note 5
VSS
VSS+0.4
IOL = 4.5 mA,
VCC = 5 V,
See Note 6
VSS
VSS+1
UNIT
V
V
NOTES: 5. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ± 9.6 mA to hold the maximum voltage
drop specified.
6. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ± 20 mA to hold the maximum voltage
drop specified.
leakage current (see Note 7)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Ilkg(TP)
High-impedance leakage current, timer/port
Timer/port:VTP0.x,
VCC = 3 V/5 V,
CIN = VSS, VCC,
(see Note 8)
± 50
nA
Ilkg(S27)
High-impedance leakage current, S27
VS27 = VSS to VCC,
VCC = 3 V/5 V
± 50
nA
Leakage current, port 0
Port P0: P0.x, 0 ≤ × ≤ 7,
(see Note 9)
VCC = 3 V/5 V,
± 50
nA
Ilkg(P0x)
NOTES: 7. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
8. All timer/port pins TP0.0 to TP0.5 are Hi-Z. Pins CIN and TP.0 to TP0.5 are connected together during leakage current measurement.
In the leakage measurement the input CIN is included. The input voltage is VSS or VCC.
9. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.
•
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•
17
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
optional resistors, individually programmable with ROM code, P0.x, (see Note 10)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
R(opt1)
VCC = 3 V/5 V
2.1
4.1
6.2
kΩ
R(opt2)
VCC = 3 V/5 V
3.1
6.2
9.3
kΩ
R(opt3)
VCC = 3 V/5 V
6
12
18
kΩ
R(opt4)
VCC = 3 V/5 V
10
19
29
kΩ
R(opt5)
VCC = 3 V/5 V
19
37
56
kΩ
R(opt6)
Resistors, individually programmable with ROM code, all port pins,
values applicable for pulldown and pullup
VCC = 3 V/5 V
38
75
113
kΩ
R(opt7)
VCC = 3 V/5 V
56
112
168
kΩ
R(opt8)
VCC = 3 V/5 V
94
187
281
kΩ
R(opt9)
VCC = 3 V/5 V
131
261
392
kΩ
R(opt10)
VCC = 3 V/5 V
167
337
506
kΩ
NOTE 10: Optional resistors Roptx for pull-down or pull-up are not programmed in standard OTP/EPROM devices P/E313 (MSP430P313/E313
not recommended for new designs − replaced by MSP430P315/E315) and P/E315(s)
inputs P0.x, CIN, TP.5; output XBUF
PARAMETER
t(int)
External interrupt timing
f(IN)
Input frequency
t(H) or t(L)
TEST CONDITIONS
VCC
MIN
Port P0
External trigger signal for the
interrupt flag, (see Notes 11 and 12)
3 V/5 V
1.5
P0.x, CIN, TP.5
High level or low level time
t(H) or t(L)
f(XBUF)
Clock output frequency
XBUF, CL = 20 pF
XBUF, CL = 20 pF,
t(Xdc)
Duty cycle of clock output frequency
3 V/5 V
DC
3V
225
5V
150
NOM
MAX
cycle
f(system)
ns
f(system)
3V/5V
40%
f(XBUF) = f(ACLK)
3V/5V
35%
f(XBUF) = f(ACLK/n)
3V/5V
MHz
ns
3 V/5 V
f(MCLK)= 1.1 MHz
UNIT
MHz
60%
50%
65%
NOTES: 11. The external signal sets the interrupt flag every time tint is met. It may be set even with trigger signals shorter than tint. The conditions
to set the flag must be met independently from this timing constraint. Tint is defined in MCLK cycles.
12. The external interrupt signal cannot exceed the maximum inut frequency (f(in)).
crystal oscillator, Xin, Xout
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
C(Xin)
Integrated capacitance at input
VCC = 3 V/5 V
12
pF
C(Xout)
Integrated capacitance at output
VCC = 3 V/5 V
12
pF
18
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MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
electrical characteristics over recommended and operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
f(NOM)
TEST CONDITIONS
DCO
NDCO = 1A0h FN_4=FN_3=FN_2=0
fDCO3
NDCO = 00 0110 0000 FN
FN_4=FN_3=FN_2=0
4 FN 3 FN 2 0
fDCO26
4=FN 3=FN 2=0
NDCO = 11 0100 0000 FN
FN_4=FN_3=FN_2=0
MIN
VCC = 3 V/5 V
f(NOM)
fDCO3
NDCO = 00 0110 0000 FN
FN_4=FN_3=0,
4=FN 3=0 FN_2=1
FN 2=1
2xf(NOM)
fDC26
fDCO3
CO
NDCO = 11 0100 0000 FN
FN_4=FN_3=0,
4=FN 3=0 FN_2=1
FN 2=1
4=0 FN
3= 1,
1 FN_2=X
FN 2=X
NDCO
FN_4=0,
FN_3=
CO = 00 0110 0000 FN
3xf(NOM)
fDCO26
fDCO3
NDCO = 11 0100 0000 FN_4=
FN 4= 0,
0 FN_3=1,
FN 3=1 FN_2=X
FN 2=X
NDCO = 00 0110 0000 FN
FN_4
4 =1
=1, FN
FN_3=FN_2=X
3=FN 2=X
4xf(NOM)
fDCO26
CO
4=1 FN
3=FN 2=X
NDCO
FN_4=1,
FN_3=FN_2=X
CO = 11 0100 0000 FN
NOM
MAX
1
MHz
VCC = 3 V
0.15
0.6
VCC = 5 V
0.18
0.62
VCC = 3 V
1.25
4.7
VCC = 5 V
1.45
5.5
VCC = 3 V
0.36
1.05
VCC = 5 V
0.39
1.2
VCC = 3 V
2.5
8.1
VCC = 5 V
3
9.9
VCC = 3 V
0.5
1.5
VCC = 5 V
0.6
1.8
VCC = 3 V
3.7
11
VCC = 5 V
4.5
13.8
VCC = 3 V
0.7
1.85
VCC = 5 V
0.8
2.4
VCC = 3 V
4.8
13.3
VCC = 5 V
6
NDCO
fMCLK = fNOM FN_4=FN_3=FN_2=0
VCC = 3 V/5 V
A0h
S
fNDCO+1 = S × fNDCO
VCC = 3 V/5 V
1.07
UNIT
MHz
MHz
MHz
MHz
17.7
1A0h
340h
1.13
f(DCO26)
4xfNOM
f(DCO26)
f(DCO3)
3xfNOM
f(DCO26)
f(DCO3)
2xfNOM
DCO Frequency
Adjusted by Bits
2∧9−2∧5 in SCFI1
f(DCO3)
fNOM
Tolerance at Tap 3
f(DCO3)
FN_2 = 0
FN_3 = 0
FN_4 = 0
Legend
Tolerance at Tap 26
f(DCO26)
FN_2 = 1
FN_3 = 0
FN_4 = 0
FN_2 = X
FN_3 = 1
FN_4 = 0
FN_2 = X
FN_3 = X
FN_4 = 1
Figure 3
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19
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
LCD
PARAMETER
V23
TEST CONDITIONS
MIN
MAX
Voltage at R23
VCC = 3 V/5 V
Voltage at R13
VCC = 3 V/5 V
(VCC −VSS) ×
1/3+VSS
Analog voltage
V13
NOM
(VCC −VSS)×
2/3+VSS
UNIT
VO(HLCD)
Output 1 (HLCD)
I(HLCD) <= 10 nA
VCC −0.125
VCC
VO(LLCD)
Output 0 (LLCD)
I(LLCD) <= 10 nA
VSS
VSS+0.125
II(R13)
Input leakage
(see Note 13)
R13 = VCC /3
Output (SXX)
I(SXX) = − 3 μA
μA,
II(R23)
ro(R13) to S(XX)
ro(R23) to S(XX)
VCC = 3 V/5 V
V
V
V
± 20
nA
33
kΩ
NOM
MAX
UNIT
VCC = 3 V
250
350
VCC = 5 V
450
600
0.25×VCC
0.260×VCC
R23 = 2 VCC /3
VCC = 3 V/5 V
NOTE 13: I(IRxx) is measured with no load on the segment or common LCD I/O pins.
comparator (Timer/Port)
PARAMETER
TEST CONDITIONS
I(com)
Comparator (timer/port)
CPON = 1
Vref(com)
Internal reference voltage at (−) terminal
CPON = 1
Vhys(com)
Input hysteresis (comparator)
MIN
VCC = 3 V/5 V
0.230×VCC
VCC = 3 V
5
37
VCC = 5 V
10
42
TEST CONDITIONS
MIN
CPON = 1
μA
A
V
mV
RAM
PARAMETER
VRAMh
CPU halted (see Note 14)
NOM
MAX
1.8
UNIT
V
NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
PUC/POR
PARAMETER
TEST CONDITIONS
MIN
t(POR_delay)
V(POR)
POR
20
UNIT
250
μs
1.5
2.4
V
TA = 25°C
1.2
2.1
V
0.9
1.8
V
0
0.4
VCC = 3 V/5 V
V(min)
PUC/POR
MAX
150
TA = − 40°C
TA = 85°C
t(reset)
NOM
Reset is accepted internally
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2
V
μs
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
V
VCC
V
(POR)
No POR
POR
V
(min)
POR
t
Figure 4. Power-On Reset (POR) vs Supply Voltage
3
2.4
V POR [V]
2.5
2.1
1.8
2
1.5
1.5
1
1.2
0.9
0.5
25°C
0
−40
−20
0
20
40
60
80
Temperature [°C]
Figure 5. V(POR) vs Temperature
wakeup from LPM3
PARAMETER
TEST CONDITIONS
f = 1 MHz
t(LPM3)
Delay
y time
f = 2 MHz
f = 3 MHz
•
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 5 V
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MIN
NOM
MAX
UNIT
6
6
μs
μ
6
21
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
JTAG, program memory
PARAMETER
f(TCK)
TEST CONDITIONS
TCK frequency
JTAG/Test
R(TEST)
V(FB)
JTAG/Fuse (see Note 16)
5
VCC = 5 V
DC
10
25
Fuse blow voltage, C versions (see Note 15)
VCC = 3 V/ 5 V
5.5
6
Fuse blow voltage, E/P versions
(see Note 17)
VCC = 3 V/ 5 V
11
12
Supply current on TDI/VPP to blow fuse
Time to blow the fuse
90
MHz
kΩ
V
100
mA
1
ms
Programming voltage, applied to TDI/VPP
11
11.5
13
V
P315(S), E315
Programming voltage, applied to TDI/VPP
12
12.5
13
V
70
mA
Current from programming voltage source
EPROM (E) and OTP(P) −
versions only
(see Note 18)
Programming time, single pulse
Pulses for successful programming
t(erase)
Erase time wave length 2537 Å at 15 Ws/cm2
(UV lamp of 12 mW/ cm2)
EPROM (E)
Write/erase cycles
Data retention TJ < 55°C
NOTES: 15.
16.
17.
18.
5
Programming time, fast algorithm
Pn
22
60
UNIT
P313, E313
I(PP)
t(ppf)
MAX
VCC = 3 V/ 5 V
t(FB)
t(pps)
NOM
DC
Pullup resistors on TMS, TCK, TDI
(see Note 15)
I(FB)
V(PP)
MIN
VCC = 3 V
4
30
•
•
μs
100
Pulses
min
1000
cycles
10
years
The TMS and TCK pullup resistors are implemented in all ROM(C) and EPROM(E) versions.
Once the JTAG fuse is blown no further access to the MSP430 JTAG/test feature is possible.
The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired.
Refer to the Recommended Operating Conditions for the correct VCC during programing.
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100
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
TYPICAL CHARACTERISTICS
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin, after power up, or if the
TMS is being held low after power-up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
Time TMS Goes Low After POR
TMS
ITDI
ITF
Figure 6. Fuse Check Mode Current, MSP430P/E313,P/E315,C31x
Care must be taken to avoid accidentally activating the fuse check mode, including guarding against EMI/ESD
spikes that could cause signal edges on the TMS pin.
Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.
C3xx
P/E3xx
TDI
Open
68k, pulldown
TDO
Open
68k, pulldown
TMS
Open
Open
TCK
Open
Open
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23
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
TYPICAL CHARACTERISTICS
DIGITAL CONTROLLED OSCILLATOR FREQUENCY
vs
SUPPLY VOLTAGE
1.8
1.2
1.5
1
f (DCO) / f (DCO@ 3 V)
f (DCO) / f (DCO@ 25°C )
DIGITAL CONTROLLED OSCILLATOR FREQUENCY
vs
OPERATING FREE-AIR TEMPERATURE
1.2
0.9
0.6
0.6
0.4
0.2
0.3
0
−40
0.8
0
−20
0
20
40
60
80
T − Operating Free-Air Temperature − °C
0
90
Figure 7
24
2
4
VCC − Supply Voltage − V
Figure 8
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6
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
TYPICAL CHARACTERISTICS
typical input/output schematics
VCC
VCC
(see Note A)
(see Note A)
(see Note B)
(see Note B)
(see Note B)
(see Note B)
(see Note A)
(see Note A)
GND
GND
CMOS INPUT (RST/NMI)
CMOS SCHMITT-TRIGGER INPUT (CIN)
VCC
(see Note A)
(see Note B)
(see Note B)
(see Note A)
GND
I/O WITH SCHMITT-TRIGGER INPUT (P0.x,
TP0.5)
CMOS 3-STATE OUTPUT
(TP0.0−4, XBUF)
TDO_Internal
VCC
TDO_Control
60 k TYP
TDI_Control
TDI_Internal
MSP430C31x: TMS, TCK
MSP430P/E31x: TMS, TCK
MSP430C31x: TDO/TDI
MSP430P/E31x: TDO/TDI
NOTES: A. Optional selection of pull-up or pull-down resistors with ROM (masked) versions.
B. Fuses for the optional pull-up and pull-down resistors can only be programmed at the factory.
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25
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
TYPICAL CHARACTERISTICS
typical input/output schematics
VC
COM0 −3
VD
Control COM0 −3
VA
S0, S1
VB
Segment control
VA
S2/O2−Sn/On
VB
Segment control
LCDCTL (LCDM5,6,7)
Data (LCD RAM bits 0−3
or bits 4 −7)
LCD OUTPUT (COM0 −4, Sn, Sn/On)
NOTE: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator.
VPP_ Internal
TDI_ Internal
TDI/VPP
JTAG
Fuse
TDO/TDI_Control
TDO/TDI
TMS
TDO_ Internal
JTAG Fuse
Blow
Control
From/To JTAG_CBT_SIG_REG
NOTES: A. During programming activity and when blowing the JTAG enable fuse, the TDI/VPP terminal is used to apply the correct voltage
source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry.
B. The TDI/VPP terminal of the ’P31x and ’E31x does not have an internal pullup resistor. An external pulldown resistor is
recommended to avoid a floating node, which could increase the current consumption of the device.
C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P31x and ’E31x need a pullup or a pulldown resistor to avoid
floating a node, which could increase the current consumption of the device.
Figure 9. MSP430P313/E313/P315(S)/E315: TDI/VPP, TDO/TDI
26
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MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
PMS430E313†, PMS430E315 (FZ package)
NC
NC
VSS
XBUF
RST/NMI
TCK
TMS
TDI/VPP
TDO/TDI
COM3
COM2
COM1
COM0
S27/O27/CMPI
S26/O26
NC
NC
FZ PACKAGE
(TOP VIEW)
10
9
8 7
6
5 4 3 2
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/O7
NC
NC
NC
NC
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
Cin
S0
S1
S2/O2
S3/O3
S4/O4
S5/O5
S6/O6
NC
NC
NC
NC
VCC
R23
R13
Xin
Xout/TCLK
P0.0
P0.1/RXD
P0.2/TXD
P0.3
P0.4
P0.5
P0.6
P0.7
TP0.0
NC
NC − No internal connection
†
MSP430P313/E313 not recommended for new designs − replaced by MSP430P315/E315.
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27
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D − FEBRUARY 1998 − REVISED APRIL 2000
MECHANICAL DATA
FZ (S-CQCC-J**)
J-LEADED CERAMIC CHIP CARRIER
28 LEAD SHOWN
0.040 (1,02) 45°
Seating Plane
0.180 (4,57)
A
0.155 (3,94)
0.140 (3,55)
B
4
1
0.120 (3,05)
26
25
5
A
B
0.050 (1,27)
C
(at Seating
Plane)
0.032 (0,81)
0.026 (0,66)
0.020 (0,51)
0.014 (0,36)
19
11
18
12
0.025 (0,64) R TYP
0.040 (1,02) MIN
0.120 (3,05)
0.090 (2,29)
B
A
C
JEDEC
NO. OF
OUTLINE
PINS**
MIN
MAX
MIN
MAX
MIN
MAX
MO-087AA
28
0.485
(12,32)
0.495
(12,57)
0.430
(10,92)
0.455
(11,56)
0.410
(10,41)
0.430
(10,92)
MO-087AB
44
0.685
(17,40)
0.695
(17,65)
0.630
(16,00)
0.655
(16,64)
0.610
(15,49)
0.630
(16,00)
MO-087AC
52
0.785
(19,94)
0.795
(20,19)
0.730
(18,54)
0.765
(19,43)
0.680
(17,28)
0.740
(18,79)
MO-087AD
68
0.985
(25,02)
0.995
(25,27)
0.930
(23,62)
0.955
(24,26)
0.910
(23,11)
0.930
(23,62)
4040219 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
28
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430P313IDL
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
MSP430P315IDL
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
M430P313
MSP430P315IDLR
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
MSP430P315SIDL
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
MSP430P315SIDLR
OBSOLETE
SSOP
DL
48
TBD
Call TI
Call TI
M430P315S
PMS430E315FZ
OBSOLETE
JLCC
FZ
68
TBD
Call TI
Call TI
PMS430E315FZ
-40 to 85
M430P315
M430P315
-40 to 85
M430P315S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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